Memory and storage systems

Abstract

The present disclosure relates to the field of semiconductor circuit design, and particularly relates to a memory and a storage system. The memory comprises: n memory blocks, n being a positive integer; an activation control circuit configured to receive an address signal and an activation signal, count the activation signals corresponding to each memory block based on the address signal, and generate and output a row hammer refresh indication signal corresponding to the memory block when the number of the activation signals corresponding to any memory block meets a preset activation value; wherein the address signal indicates a memory block currently performing an activation operation; and a row hammer refresh control circuit coupled to the activation control circuit and configured to receive a refresh signal and the row hammer refresh indication signal, and generate a target memory block row hammer refresh signal corresponding to the memory block based on the refresh signal and the row hammer refresh indication signal, the target memory block row hammer refresh signal being used to instruct the corresponding memory block to perform a row hammer refresh operation, so as to reduce the power consumption of the memory.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular, to a memory and a storage system. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) stores data through a structure of one transistor connecting one storage area (1T1C), wherein the transistor is controlled by a word line (WL), and when the WL is turned on, the charge in the storage area is shared with the charge of a bit line (BL) to read out the data in the target storage area or write data into the target storage area.

[0003] However, frequent opening of the word line can cause the loss of charge in the adjacent storage area, which can cause errors in the data stored in the storage area, i.e., the Row Hammer phenomenon of the memory. Row Hammer is a vulnerability on a DRAM device, and its main performance is that when an attacker hammers a certain row of memory, the memory cells of other rows will correspondingly flip.

[0004] As the manufacturing precision of DRAM is getting higher and higher, the components are getting smaller and smaller in the physical layer. It is very difficult to integrate larger memory capacity on a chip and prevent electromagnetic interference between each memory cell. This situation makes the read and write of a single area of the memory possibly interfere with the adjacent area, thereby causing the Row Hammer phenomenon.

[0005] The idea of Row Hammer protection is simply to monitor the number of ACTs and addresses, then find out the potential attacked addresses, and then re-refresh the two rows near the attacked addresses to maintain data integrity.

[0006] However, the Row Hammer protection strategy is to operate all storage blocks (banks / bank groups) together, i.e., when a bank is attacked, all banks perform Row Hammer protection together, which greatly increases the power consumption of the memory. SUMMARY

[0007] The embodiments of the present disclosure provide a memory and a storage system to optimize the strategy of Row Hammer protection of the memory, thereby reducing the power consumption of the memory.

[0008] An embodiment of the present disclosure provides a memory, comprising: n memory blocks, n being a positive integer; an activation control circuit configured to receive an address signal and an activation signal, count the activation signal corresponding to each memory block based on the address signal, and generate and output a row hammer refresh indication signal corresponding to the memory block when the number of the activation signal corresponding to any memory block meets a preset activation value; wherein the address signal indicates a memory block currently performing an activation operation; a row hammer refresh control circuit coupled to the activation control circuit and configured to receive a refresh signal and the row hammer refresh indication signal, and generate a target memory block row hammer refresh signal corresponding to the memory block based on the refresh signal and the row hammer refresh indication signal, the target memory block row hammer refresh signal being used to instruct the corresponding memory block to perform a row hammer refresh operation.

[0009] The row hammer refresh indication signal is used to indicate the memory block whose number of activation signals meets the preset activation value, i.e., the memory block that may generate a Row Hammer phenomenon; the row hammer refresh control circuit generates the target memory block row hammer refresh signal based on the refresh signal and the row hammer refresh indication signal, i.e., the memory needs to be protected against Row Hammer, and the memory block whose number of activation signals meets the preset activation value generates the target memory block row hammer refresh signal for the memory block, so as to perform supplemental refresh only on the target memory block in the supplemental refresh process, i.e., the Row Hammer protection strategy in the embodiment of the present disclosure is to protect only the memory block that may generate a Row Hammer phenomenon, avoiding the supplemental refresh process for the memory block that will not generate a Row Hammer phenomenon, thereby reducing the power consumption of the memory.

[0010] Optionally, the activation control circuit comprises: n activation control modules, the activation control modules corresponding to the memory blocks one by one; an identification module configured to receive the address signal and the activation signal, and generate a target memory block activation signal corresponding to the address signal based on the address signal and the activation signal, the target memory block activation signal being used to drive the activation control module corresponding to the memory block corresponding to the address signal; each activation control module is configured to count based on the corresponding target memory block activation signal to generate an activation count value, and generate and output the row hammer refresh indication signal corresponding to the memory block when the activation count value meets the preset activation value.

[0011] Optionally, each activation control module comprises: a counting unit configured to count based on the corresponding target memory block activation signal to generate an activation count value; a comparison unit coupled to the counting unit and receiving the preset activation value, and configured to generate and output the row hammer refresh indication signal corresponding to the memory block when the activation count value meets the preset activation value.

[0012] Optionally, each activation control module comprises: a cascade of k-stage D flip-flops, an input end of each stage of D flip-flop is connected to an inverting output end, k is an integer greater than 1; a clock end of the first stage of D flip-flop is configured to receive the target memory block activation signal, a clock end of the jth stage of D flip-flop is connected to an inverting output end of the (j-1)th stage of D flip-flop, 2≤j≤k, and an output end of the last stage of D flip-flop is configured to output the row hammer refresh instruction signal.

[0013] Optionally, the activation control module is arranged in the corresponding memory block.

[0014] Optionally, the row hammer refresh control circuit comprises: a first control module coupled to the activation control circuit and configured to generate a row hammer refresh enable signal based on any row hammer refresh instruction signal; a second control module coupled to the first control module and configured to generate a row hammer refresh signal based on the refresh signal and the row hammer refresh enable signal; and n processing modules corresponding to the n memory blocks, each processing module being coupled to the second control module and the corresponding activation control circuit and configured to generate and output a target memory block row hammer refresh signal corresponding to the memory block based on the row hammer refresh signal and the row hammer refresh instruction signal corresponding to the memory block.

[0015] Optionally, the first control module comprises: an OR logic circuit comprising n input ends corresponding to receiving n row hammer refresh instruction signals corresponding to n memory blocks respectively, and an output end configured to output the row hammer refresh enable signal.

[0016] Optionally, the first control module comprises: an XOR logic circuit comprising n input ends corresponding to receiving n row hammer refresh instruction signals corresponding to n memory blocks respectively, and an output end configured to output the row hammer refresh enable signal.

[0017] Optionally, the processing module comprises: an AND logic circuit, a first input end of the AND logic circuit being configured to receive the row hammer refresh signal, a second input end of the AND logic circuit being configured to receive the row hammer refresh instruction signal corresponding to the corresponding memory block, and an output end of the AND logic circuit being configured to output the target memory block row hammer refresh signal.

[0018] Optionally, the processing module is arranged in the corresponding memory block.

[0019] Optionally, the memory further comprises: a decoding circuit configured to receive and decode a control command issued by the storage controller to generate at least one of the refresh signal, the activation signal, and the address signal.

[0020] Another embodiment of the present disclosure also provides a storage system comprising: a storage controller and a memory, the memory being responsive to a control command issued by the storage controller, and the memory being constituted based on the memory provided by the above-mentioned embodiments to optimize the strategy of the memory for Row Hammer protection, thereby reducing the power consumption of the memory. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram of the structure of a memory provided in an embodiment of this disclosure;

[0023] Figure 2 This is a schematic diagram of the structure of an activation control circuit provided in an embodiment of the present disclosure;

[0024] Figure 3 This is a schematic diagram of another activation control module provided in an embodiment of the present disclosure;

[0025] Figure 4 This is a schematic diagram of the structure of a line hammer refresh control circuit provided in an embodiment of the present disclosure;

[0026] Figure 5 A schematic diagram of the first control module and processing module provided in an embodiment of this disclosure;

[0027] Figure 6 This is a schematic diagram of the structure of a memory including a decoding circuit, provided as an embodiment of the present disclosure. Detailed Implementation

[0028] As the background technology shows, the Row Hammer protection approach can be simply described as monitoring the number of ACTs and their addresses, then identifying potentially vulnerable addresses, and finally refreshing the two rows near the vulnerable address to maintain data integrity.

[0029] Specifically, the number of activation signals (Action, ACT) received by the memory and their addresses are monitored. When the number of times the same address is activated by ACT reaches a preset value, it indicates that the current address may be experiencing a Row Hammer phenomenon. The Row Hammer phenomenon is avoided by supplementing and refreshing the adjacent rows of the current address.

[0030] For the above Row Hammer protection strategy, the number of activation signals (Action, ACT) and the address are monitored, and the specific bank / bank group information is not distinguished. When a bank may have Row Hammer phenomenon, the current address of all banks will be refreshed, which is an unnecessary step for banks that do not have Row Hammer phenomenon, increasing the power consumption of the memory.

[0031] In addition, using the number of ACTs as the standard for starting the Row Hammer protection strategy will cause the Row Hammer protection strategy to start too frequently, increasing the time for the memory to perform a refresh, i.e., increasing the refresh time of the memory, resulting in a decrease in the refresh efficiency of the memory.

[0032] An embodiment of the present disclosure provides a memory to optimize the Row Hammer protection strategy of the memory, thereby reducing the power consumption of the memory.

[0033] Those skilled in the art can understand that, in the embodiments of the present disclosure, many technical details are proposed in order to enable the reader to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the following embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation mode of the present disclosure. The embodiments can be combined with each other and mutually referenced without contradiction.

[0034] Figure 1 The structure schematic diagram of the memory provided for the present embodiment is as follows, Figure 2 The structure schematic diagram of the activation control circuit provided for the present embodiment is as follows, Figure 3 The structure schematic diagram of another activation control module provided for the present embodiment is as follows, Figure 4 The structure schematic diagram of the Row Hammer refresh control circuit provided for the present embodiment is as follows, Figure 5 The principle schematic diagram of the first control module and the processing module provided for the present embodiment is as follows, Figure 6 The structure schematic diagram of the memory including the decoding circuit provided for the present embodiment is as follows, and the memory provided for the present embodiment is described in detail below in combination with the drawings, as follows:

[0035] Reference Figure 1 The memory 100 includes:

[0036] n storage blocks 101, n is a positive integer; it should be noted that in the embodiment, each storage block 101 can refer to a single storage block bank or a storage block group bank in an actual setting. For each storage block 101, the storage block 101 includes a plurality of word lines WL and a plurality of bit lines BL and a plurality of storage units, wherein the corresponding storage unit is arranged at the intersection of the word line WL and the bit line BL, that is, each storage block corresponds to a word line WL and a bit line BL, and the memory selects the corresponding word line and bit line based on the corresponding address signal, so as to select the target storage unit in the plurality of storage units.

[0037] It should be noted that in the following description, the embodiment takes n = 4 storage blocks 101 (storage block a, storage block b, storage block c, and storage block d) corresponding to the memory 100 as an example for the purpose of understanding the Row Hammer protection strategy provided by the present disclosure by those skilled in the art, and does not constitute a limitation on the embodiment. In specific applications, the value of the specific storage block 101 is set based on the number of storage blocks in the applicable memory.

[0038] The activation control circuit 102 is configured to receive the address signal ADD and the activation signal ACT, count the activation signal ACT corresponding to each storage block 101 based on the address signal ADD, and generate and output the Row Hammer refresh instruction signal Flag corresponding to the storage block 101 when the number of activation signals corresponding to any one storage block 101 meets the activation preset value. The address signal ADD is used to indicate the storage block 101 currently performing the activation operation.

[0039] It should be noted that since the embodiment is mainly used for improving the Row Hammer protection strategy, the activation control circuit counts the activation signal ACT corresponding to each storage block 101 based on the address signal ADD within the interval between two adjacent refresh commands REF, so as to realize the regulation of the supplementary refresh target in the next refresh command REF.

[0040] The Row Hammer refresh control circuit 103 is coupled to the activation control circuit 102 and is configured to receive the refresh signal REF and the Row Hammer refresh instruction signal Flag, and generate the target storage block Row Hammer refresh signal Ref corresponding to the storage block 101 based on the refresh signal REF and the Row Hammer refresh instruction signal Flag. The target storage block Row Hammer refresh signal Ref is used to indicate that the corresponding storage block 101 performs the Row Hammer refresh operation.

[0041] It should be noted that the refresh signal REF mentioned in the embodiment is used to instruct the memory 100 to perform the supplementary refresh function, that is, to instruct the memory 100 to perform Row Hammer protection, and as the normal refresh function of the memory 100 is not closely related to the core content of the present disclosure, it is not described in detail in the embodiment.

[0042] For the activation control circuit 102, specifically, the count value of counting the activation signal ACT corresponding to the storage block a is count a, the count value of counting the activation signal ACT corresponding to the storage block b is count b, the count value of counting the activation signal ACT corresponding to the storage block c is count c, and the count value of counting the activation signal ACT corresponding to the storage block d is count d.

[0043] The count a is compared with the activation preset value a, when the count a is greater than or equal to the activation preset value a, the row hammer refresh instruction signal Flag<1> corresponding to the storage block a is generated and output; the count b is compared with the activation preset value b, when the count b is greater than or equal to the activation preset value b, the row hammer refresh instruction signal Flag<2> corresponding to the storage block b is generated and output; the count c is compared with the activation preset value c, when the count c is greater than or equal to the activation preset value c, the row hammer refresh instruction signal Flag<3> corresponding to the storage block c is generated and output; the count d is compared with the activation preset value d, when the count d is greater than or equal to the activation preset value d, the row hammer refresh instruction signal Flag<4> corresponding to the storage block d is generated and output; Flag<1>, Flag<2>, Flag<3> and Flag<4> jointly constitute Flag<4:1> that is Flag <n:1>.

[0044] In one example, if the row hammer refresh indication signal Flag <n:1>active high, when Flag <n:1>= "0100", it proves that the count c corresponding to the storage block c is greater than or equal to the activated preset value c; when Flag <n:1>If the value of the counter a corresponding to the memory block a is equal to "0011", it is proved that the counter a corresponding to the memory block a is greater than or equal to the activation preset value a and the counter b corresponding to the memory block b is greater than or equal to the activation preset value b. If the row hammer refresh instruction signal Flag <n:1>active low, when Flag <n:1>= "0111", it is proved that the count d corresponding to the storage block d is greater than or equal to the activation preset value d; when Flag <n:1>= "1001", it is proved that the count b corresponding to the storage block b is greater than or equal to the activation preset value b and the count c corresponding to the storage block c is greater than or equal to the activation preset value c. In addition, in the subsequent description of the present disclosure, the row hammer refresh indication signal Flag <n:1>The high level effective description is provided for the skilled in the art to understand the strategy of Row Hammer protection provided by the present disclosure, and does not constitute a limitation on the present embodiment.

[0045] For the row hammer refresh control circuit 103, when the refresh signal is received, the valid row hammer refresh indication signal Flag <n:1>corresponding to the generated valid target memory block row hammer refresh signal; specifically, if the target memory block row hammer refresh signal Ref <n:1>active high, when Flag <n:1>= "0100", then the generated Ref <n:1>= "0100", target memory block row hammer refresh signal Ref <n:1>for instructing the storage block c to perform a supplemental refresh; when Flag <n:1>= "0011", then the generated Ref <n:1>= "0011", target memory block row hammer refresh signal Ref <n:1>for instructing the storage block a and the storage block b to perform complementary refresh. If the target storage block row hammer refresh signal Ref <n:1>active low, when Flag <n:1>= "0100", then the generated Ref <n:1>= "1011", target memory block row hammer refresh signal Ref <n:1>for indicating the storage block c to perform a supplemental refresh; when Flag <n:1>= "0011", then the generated Ref <n:1>= "1100", target memory block row hammer refresh signal Ref <n:1>For indicating the storage block a and the storage block b to perform the supplementary refresh.

[0046] In summary, the row hammer refresh indication signal Flag is used to indicate the storage block 101 whose number of active signals meets the preset value, i.e., the storage block 101 that may have the Row Hammer phenomenon; the row hammer refresh control circuit 103 generates the target storage block row hammer refresh signal Ref based on the refresh signal REF and the row hammer refresh indication signal Flag, i.e., the memory needs to be protected against the Row Hammer, and the storage block 101 whose number of active signals meets the preset value, generates the target storage block row hammer refresh signal Ref for the storage block 101, so as to achieve the supplementary refresh of only the target storage block in the supplementary refresh process, i.e., the Row Hammer protection strategy in the embodiment of the present disclosure is to protect only the storage block 101 that may have the Row Hammer phenomenon, avoiding the supplementary refresh process of the storage block that will not have the Row Hammer phenomenon, thereby reducing the power consumption of the memory.

[0047] It should be noted that, for Figure 1 As shown in the circuit, the activation control circuit 102 is further configured to provide a memory bank control signal for the storage block 101, and the memory bank control signal is used for the storage block 101 to implement normal storage functions, and the storage functions of the storage block 101 are irrelevant to the core content of the present disclosure, and the embodiment will not be described in detail.

[0048] In some embodiments, with reference to Figure 2 The activation control circuit 102 comprises:

[0049] n activation control modules 201, and each of the activation control modules 201 corresponds to one of the storage blocks 101; i.e., the storage block a corresponds to the activation control module a, the storage block b corresponds to the activation control module b, the storage block c corresponds to the activation control module c, and the storage block d corresponds to the activation control module d.

[0050] The identification module 202 receives the address signal ADD and the active signal ACT, and is configured to generate a target storage block active signal corresponding to the address signal ADD based on the address signal ADD and the active signal ACT, and the target storage block active signal is used to drive the activation control module 201 corresponding to the storage block 101 corresponding to the address signal ADD.

[0051] Specifically, when the address signal ADD indicates an address in the storage block a, the target storage block activation signal generated by the identification module 202 is used to drive the activation control module a; when the address signal ADD indicates an address in the storage block b, the target storage block activation signal generated by the identification module 202 is used to drive the activation control module b; when the address signal ADD indicates an address in the storage block c, the target storage block activation signal generated by the identification module 202 is used to drive the activation control module c; when the address signal ADD indicates an address in the storage block d, the target storage block activation signal generated by the identification module 202 is used to drive the activation control module d.

[0052] In some embodiments, the target storage block activation signal is also used to drive other control logic circuits of the corresponding storage block, to generate other control signals for controlling the corresponding storage block to perform an activation operation.

[0053] Each activation control module 201 is configured to count based on the corresponding target storage block activation signal to generate an activation count value, and when the activation count value meets a preset activation value, generate and output a row hammer refresh indication signal Flag corresponding to the storage block 101.

[0054] For the activation row hammer refresh indication signal Flag <c>wherein c is any value greater than or equal to 1 and less than or equal to n, and the size of the specific value corresponds to the output of the activation control module 201, specifically, the activation control module 201 is configured to count the target storage block activation signal corresponding to the storage block a to generate the activation count value a, and when the activation preset value a is greater than or equal to the preset value a, the row hammer refresh indication signal Flag<1> corresponding to the storage block a is generated; the activation control module 201 is configured to count the target storage block activation signal corresponding to the storage block b to generate the activation count value b, and when the activation preset value b is greater than or equal to the preset value b, the row hammer refresh indication signal Flag<2> corresponding to the storage block b is generated; the activation control module 201 is configured to count the target storage block activation signal corresponding to the storage block c to generate the activation count value c, and when the activation preset value c is greater than or equal to the preset value c, the row hammer refresh indication signal Flag<3> corresponding to the storage block c is generated; the activation control module 201 is configured to count the target storage block activation signal corresponding to the storage block d to generate the activation count value d, and when the activation preset value d is greater than or equal to the preset value d, the row hammer refresh indication signal Flag<4> corresponding to the storage block d is generated.

[0055] For the activation control module 201, in one example, continuing to refer to Figure 2 Each activation control module 201 includes: a counting unit 210 configured to count the corresponding target storage block activation signal to generate an activation count value; a comparison unit 220 coupled to the counting unit 210 and receiving an activation preset value, configured to generate and output the row hammer refresh indication signal Flag <c>.

[0056] For the comparison unit 220, in some embodiments, the activation preset value can be in the form of a fixed value set in the comparison unit 220; in other embodiments, the activation preset value can be configured by a mode register, can also be adjusted in the test mode of the memory, and can be set differently for each memory block 101 according to the performance of each memory block 101, such as the number of weak addresses.

[0057] In another example, referring to Figure 3 Each activation control module 201 includes a cascade of k-stage D flip-flops 230, the input end D of each D flip-flop 230 is connected to the inverting output end Q-, and k is an integer greater than 1; the clock end Ck of the first-stage D flip-flop 230 is used to receive the target memory block activation signal, the clock end Ck of the j-stage D flip-flop 230 is connected to the inverting output end Q- of the j-1-stage D flip-flop 230, 2≤j≤k, and the output end Q of the last-stage D flip-flop 230 is used to output the row hammer refresh instruction signal Flag <c>.

[0058] Specifically, when the first-stage D flip-flop 230 receives the target memory block activation signal, the data Q output from the output terminal... <0> Inverting, the corresponding inverted output terminal outputs data QN <0> Invert the phase, and QN <0> As the input of the clock terminal Ck of the second-stage D flip-flop 230, when QN <0> Valid, the data Q output from the output terminal of the second-stage D flip-flop 230 is valid. <1> Inverting, the corresponding inverted output terminal outputs data QN <1> Inverting phase...and QN <k-1>as an input to the clock terminal Ck of the kth D flip-flop 230, when QN <k-1>effective, the output of the kth stage D flip-flop 230 outputs data Flag <c>inverted; in summary, every 2 k-1 target memory block activation signal, the row hammer refresh indication signal Flag <c>inverted, i.e. when the activation control module 201 is initially inactive, the row hammer refresh indication signal Flag <c>, and the activation control module 201 receives 2 k-1 target memory block activation signals, the activation control module 201 generates a row hammer refresh instruction signal Flag <c>The flip-flop is effective, and thus, by setting the value of k, the size of the activation count value can be adjusted based on the cascade D flip-flop 230.

[0059] In some embodiments, k can be set in the form of a fixed value, i.e., the number of cascaded D flip-flops in the activation control module 201 is fixed, and the activation preset value is fixedly set; in other embodiments, the number of cascaded D flip-flops in the activation control module 201 can be configured by a mode register, can also be adjusted in the test mode of the memory, and can be set with different k values for each memory block 101 according to the performance of each memory block 101, such as the number of weak addresses.

[0060] It should be noted that in other embodiments, the input end D of the D flip-flop can also be connected to the inverting output end Q-, and the output end Q can be connected to the input end of an inverter, and the output end of the inverter is connected to the input end D; correspondingly, the input end D of the next stage D flip-flop can be connected to the inverting output end Q- of the previous stage D flip-flop, and the input end D of the next stage D flip-flop can be connected to the output end of the inverter.

[0061] It should be noted that in some embodiments, the reset end RN of each stage D flip-flop is also used to receive a reset signal, so as to reset the row hammer refresh indication signal Flag corresponding to the activation control module 201 in the initial power-on stage of the memory. <c>Thus, the error count of activating the control module 201 is prevented.

[0062] In some embodiments, the activation control module 201 is disposed in the corresponding memory block 101, that is, the activation control module a corresponding to the memory block a is disposed in the memory block a, the activation control module b corresponding to the memory block b is disposed in the memory block b, the activation control module c corresponding to the memory block c is disposed in the memory block c, and the activation control module d corresponding to the memory block d is disposed in the memory block d, so as to simplify the length of the data transmission line between the n activation control modules 201 and the n memory blocks 101.

[0063] In some embodiments, with reference to Figure 4 , the row hammer refresh control circuit 103 comprises:

[0064] The first control module 301 is coupled to the activation control circuit 102 and is configured to, based on any row hammer refresh indication signal Flag <n:1>generate a row hammer refresh enable signal; specifically, when any one of the row hammer refresh indication signals Flag<1>, Flag<2>, Flag<3> and Flag<4> is a valid signal, the first control module 301 generates the row hammer refresh enable signal, which is used to indicate that there is a storage block 101 in the memory 100 with a number of opening times greater than a preset value.

[0065] The second control module 302 is coupled to the first control module 301 and is configured to generate a row hammer refresh signal based on the refresh signal REF and the row hammer refresh enable signal; specifically, when the refresh signal REF and the row hammer refresh enable signal are both valid signals, the second control module 302 generates the row hammer refresh signal, which is used to instruct the memory 100 to perform a supplementary refresh, i.e., to perform Row Hammer protection.

[0066] The n processing modules 303 correspond to the n storage blocks 101 one by one, and each processing module 303 is coupled to the second control module 302 and the corresponding activation control circuit 102 and is configured to generate a row hammer refresh signal based on the row hammer refresh signal and the row hammer refresh indication signal Flag <c>, generate and output a target memory block row hammer refresh signal Ref corresponding to the memory block <n:1>.

[0067] In particular, when the row hammer refresh signal and the row hammer refresh indication signal Flag <n:1>For the effective signal, the processing module a generates a target storage block Row Hammer refresh signal Ref<1> corresponding to the storage block a based on the Row Hammer refresh signal and a Row Hammer refresh indication signal Flag<1> corresponding to the storage block a, the target storage block Row Hammer refresh signal Ref<1> being used to instruct the storage block a to perform a supplementary refresh in the next refresh process, i.e., to perform Row Hammer protection in the next refresh process; the processing module b generates a target storage block Row Hammer refresh signal Ref<2> corresponding to the storage block b based on the Row Hammer refresh signal and a Row Hammer refresh indication signal Flag<2> corresponding to the storage block b, the target storage block Row Hammer refresh signal Ref<2> being used to instruct the storage block b to perform a supplementary refresh in the next refresh process, i.e., to perform Row Hammer protection in the next refresh process; the processing module c generates a target storage block Row Hammer refresh signal Ref<3> corresponding to the storage block c based on the Row Hammer refresh signal and a Row Hammer refresh indication signal Flag<3> corresponding to the storage block c, the target storage block Row Hammer refresh signal Ref<3> being used to instruct the storage block c to perform a supplementary refresh in the next refresh process, i.e., to perform Row Hammer protection in the next refresh process; and the processing module d generates a target storage block Row Hammer refresh signal Ref<4> corresponding to the storage block d based on the Row Hammer refresh signal and a Row Hammer refresh indication signal Flag<4> corresponding to the storage block d, the target storage block Row Hammer refresh signal Ref<4> being used to instruct the storage block d to perform a supplementary refresh in the next refresh process, i.e., to perform Row Hammer protection in the next refresh process. The processing module 303 corresponds to the Row Hammer refresh indication signal Flag <c>generating a target memory block row hammer refresh signal Ref <c>Thus, the storage block 101 needing Row Hammer protection is supplemented with refresh, and the refresh signal received by the storage block 101 not needing Row Hammer protection is shielded, so that the storage block 101 not needing Row Hammer protection is prevented from being supplemented with refresh.

[0068] In some embodiments, the processing module 303 is arranged in the corresponding storage block 101, that is, the processing module a corresponding to the storage block a is arranged in the storage block a, the processing module b corresponding to the storage block b is arranged in the storage block b, the processing module c corresponding to the storage block c is arranged in the storage block c, and the processing module d corresponding to the storage block d is arranged in the storage block d, so as to simplify the length of the data transmission line between the n processing modules 303 and the n storage blocks 101.

[0069] In some embodiments, referring to Figure 5 The first control module 301 includes an OR logic circuit 401, or the OR logic circuit 401 includes n input ends respectively corresponding to receiving n Row Hammer refresh indication signals Flag corresponding to n storage blocks 101, and an output end for outputting a Row Hammer refresh enable signal.

[0070] Specifically, the a input end corresponds to receiving a Row Hammer refresh indication signal Flag<1> corresponding to the storage block a, the b input end corresponds to receiving a Row Hammer refresh indication signal Flag<2> corresponding to the storage block b, the c input end corresponds to receiving a Row Hammer refresh indication signal Flag<3> corresponding to the storage block c, and the d input end corresponds to receiving a Row Hammer refresh indication signal Flag<4> corresponding to the storage block d, so that the OR logic circuit 401 is used to implement that when there is a valid Row Hammer refresh indication signal Flag <n:1>When the row hammer refresh indication signal Flag is 1, the output row hammer refresh enable signal is 1.

[0071] In some embodiments, the OR logic circuit 401 can be replaced by an XOR logic circuit, and accordingly, the XOR logic circuit includes n input terminals corresponding to receiving n row hammer refresh indication signals Flag corresponding to n storage blocks 101 respectively, and an output terminal for outputting a row hammer refresh enable signal.

[0072] Specifically, since the row hammer refresh indication signals Flag output by the n storage blocks are all 1, the output row hammer refresh enable signal is 1. <n:1>At the same time invalid, memory does not need to perform the supplementary refresh, at this time the exclusive or logic circuit output invalid level, meet the requirements; n memory block output row hammer refresh instruction signal Flag <n:1>There are valid and different for valid, target memory need to perform the supplementary refresh, at this time the exclusive or logic circuit output valid level, meet the requirements.

[0073] It should be noted that, based on the foregoing, the activation control circuit 102 statistics activation count value is between two refresh commands, and in this process, there can be a plurality of memory blocks 101 activation count value meets the activation preset value, and the resources of the supplementary refresh process in a single refresh command is limited, and the memory block 101 which meets the activation preset value of the activation count value cannot perform the supplementary refresh in the refresh command, and will be postponed to the next refresh command to perform the supplementary refresh.

[0074] In some embodiments, with reference to Figure 5 , the processing module 303, comprising and logic circuit 402, the first input end is used for receiving row hammer refresh signal, the second input end is used for receiving corresponding memory block 101 corresponding row hammer refresh instruction signal Flag <c>, and an output terminal for outputting a target memory block row hammer refresh signal Ref <c>.

[0075] Specifically, the processing module a includes an AND logic circuit a, the processing module b includes an AND logic circuit b, the processing module c includes an AND logic circuit c, and the processing module d includes an AND logic circuit d; the AND logic circuit a receives a row hammer refresh indication signal Flag<1> corresponding to the storage block a, and generates a target storage block row hammer refresh signal Ref<1> based on the row hammer refresh signal and the row hammer refresh indication signal Flag<1> when the row hammer refresh signal and the row hammer refresh indication signal Flag<1> are valid; the AND logic circuit b receives a row hammer refresh indication signal Flag<2> corresponding to the storage block b, and generates a target storage block row hammer refresh signal Ref<2> based on the row hammer refresh signal and the row hammer refresh indication signal Flag<2> when the row hammer refresh signal and the row hammer refresh indication signal Flag<2> are valid; the AND logic circuit c receives a row hammer refresh indication signal Flag<3> corresponding to the storage block c, and generates a target storage block row hammer refresh signal Ref<3> based on the row hammer refresh signal and the row hammer refresh indication signal Flag<3> when the row hammer refresh signal and the row hammer refresh indication signal Flag<3> are valid; the AND logic circuit d receives a row hammer refresh indication signal Flag<4> corresponding to the storage block d, and generates a target storage block row hammer refresh signal Ref<4> based on the row hammer refresh signal and the row hammer refresh indication signal Flag<4> when the row hammer refresh signal and the row hammer refresh indication signal Flag<4> are valid; the AND logic circuit is used to realize that when the row hammer refresh signal is valid, the target storage block row hammer refresh signal Ref<1>, Ref<2>, Ref<3>, and Ref<4> corresponding to the row hammer refresh indication signal Flag <c>generating a target memory block row hammer refresh signal Ref <c>.

[0076] In some embodiments, reference Figure 6 The memory 100 further includes a decoding circuit 105, which is used to receive and decode control commands issued by the memory controller to generate at least one of a refresh signal REF, an activation signal ACT, and an address signal ADD.

[0077] For the memory provided in this embodiment, the row hammer refresh indication signal Flag is used to indicate the memory block 101 whose number of activation signals corresponding to memory block 101 meets the activation preset value, that is, the memory block 101 that may generate the row hammer phenomenon; the row hammer refresh control circuit 103 generates the target memory block row hammer refresh signal Ref based on the refresh signal REF and the row hammer refresh indication signal Flag, that is, the memory needs to be protected against row hammer, and the memory block 101 whose number of activation signals corresponding to memory block 101 meets the activation preset value generates the target memory block row hammer refresh signal Ref for memory block 101, so that only the target memory block is refreshed during the supplementary refresh process. That is, the row hammer protection strategy in this embodiment is to only protect the memory block 101 that may generate the row hammer phenomenon, and avoid the supplementary refresh process of memory blocks that will not generate the row hammer phenomenon, thereby reducing the power consumption of the memory.

[0078] It should be noted that the features disclosed in the memory provided in the above embodiments can be arbitrarily combined without conflict to obtain new memory embodiments.

[0079] Another embodiment of this disclosure provides a storage system, including a storage controller and a memory, the memory responding to control commands issued by the storage controller, and the memory based on the memory configuration provided in the above embodiments to optimize the strategy for Row Hammer protection of the memory, thereby reducing the power consumption of the memory.

[0080] Specifically, the memory controller can provide various control signals to operate the memory. The memory controller can be integrated into various types of host devices, such as central processing units (CPUs), graphics processing units (GPUs), multimedia processors (MMPs), digital signal processors (DSPs), and application processors (APs). In some embodiments, the memory controller can be stacked together with the memory on the same substrate and configured as a single package.

[0081] The memory can be a memory unit or device based on semiconductor devices or components. For example, the memory device can be a volatile memory such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type two synchronous dynamic random access memory (DDR2 SDRAM), double data rate type three synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc., or can be a non-volatile memory such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0082] The connection between the memory controller and the memory is implemented through a plurality of buses, where the plurality of buses can be a signal transmission path, a link, or a channel for transmitting signals. The plurality of buses can include a command address bus and a data bus. The command address bus is usually a unidirectional bus for unidirectional transmission of command signals CMD and address signals to the memory. The data bus is usually a bidirectional bus for bidirectional transmission of data signals DQ between the memory controller and the memory.

[0083] Specifically, the memory controller transmits command signals CMD and address signals to the memory through the command address bus, which can be separately arranged as a command bus and an address bus in some embodiments. The memory controller is coupled to the memory through the data bus and receives data signals DQ from the memory or transmits data signals DQ to the memory through the data bus, which can be separately arranged as a digital sub-bus and a clock sub-bus in some embodiments, where the clock sub-bus is arranged as a unidirectional bus through which the memory controller transmits system clock signals to the memory, so that the memory controller and the memory can be synchronized to perform data communication based on the system clock signals.

[0084] Based on the foregoing, the memory controller controls the operation of the memory through the command address bus by providing various command signals CMD. As Figure 6 The control command CMD provided by the storage controller is recognized by the decoding circuit 105, so as to obtain the refresh signal REF, the activation signal ACT, the address signal ADD, and the read command signal RD and the write command signal WT used by the memory 100 for reading and writing (irrelevant to the core scheme of the present disclosure, and the embodiment will not be described in detail). The activation signal ACT can be used by the memory 100 to implement the activation operation, and can enable a specific word line in a certain memory block in the memory 100 based on the address signal ADD received together with the activation signal ACT. The memory 100 can perform the reading operation based on the read command signal RD, and can select a specific bit line based on the address signal ADD received together with the read command signal RD, and the memory 100 performs the reading operation on the data of the storage unit between the enabled word line and the bit line. Similarly, the memory 100 can perform the writing operation based on the write command signal WT, and can select a specific bit line based on the address signal ADD received together with the write command signal WT, and the memory 100 performs the writing operation on the data of the storage unit between the enabled word line and the bit line. When the reading operation or the writing operation is completed, the memory 100 ends the activation operation, and can disable the enabled word line.

[0085] Further, the storage controller can generate a control command for refreshing, at this time, the control command is decoded by the decoding circuit 105 to obtain the refresh signal, and the refresh signal includes the periodic refresh signal and the aperiodic refresh signal. For the data retention of the memory 100, the periodic refresh signal is periodically generated and provided to the memory 100 by the storage controller at a constant time interval, and the storage controller can include a clock counter, and based on the value of the clock counter, the periodic refresh command signal is generated every predetermined time. In addition, the storage controller can generate the aperiodic refresh command signal by detecting the row hammer condition, and the aperiodic refresh command signal is used to instruct the memory 100 to perform supplementary refresh on the adjacent address of the address that may cause the row hammer condition.

[0086] For the memory 100 provided in the embodiment, the row hammer refresh indication signal Flag is used to indicate the memory block 101 corresponding to the number of active signals satisfying the activation preset value, that is, the memory block 101 that may produce the Row Hammer phenomenon; the row hammer refresh control circuit 103 generates the target memory block row hammer refresh signal Ref based on the refresh signal Ref and the row hammer refresh indication signal Flag, that is, the memory needs to be protected against Row Hammer, and the memory block 101 corresponding to the number of active signals satisfying the activation preset value, generates the target memory block row hammer refresh signal Ref for the memory block 101, so as to achieve the supplementary refresh process only for the target memory block, that is, the Row Hammer protection strategy in the embodiment of the present disclosure is to only protect the memory block 101 that may produce the Row Hammer phenomenon, avoiding the supplementary refresh process for the memory block that will not produce the Row Hammer phenomenon, thereby reducing the power consumption of the memory.

[0087] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and detail without departing from the spirit and scope of the present disclosure.< / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c>

Claims

1. A memory, characterized in that, include: There are n storage blocks, where n is a positive integer; An activation control circuit is configured to receive an address signal and an activation signal, count the activation signals corresponding to each memory block based on the address signal, and generate and output a row hammer refresh indication signal corresponding to the memory block when the number of activation signals corresponding to any memory block meets an activation preset value; wherein the address signal indicates the memory block currently undergoing activation operation. A row hammer refresh control circuit, coupled to the activation control circuit, is configured to receive a refresh signal and a row hammer refresh indication signal, and generate a target memory block row hammer refresh signal corresponding to the memory block based on the refresh signal and the row hammer refresh indication signal. The target memory block row hammer refresh signal is used to instruct the corresponding memory block to perform a row hammer refresh operation. The activation control circuit includes: There are n activation control modules, and each activation control module corresponds to one of the storage blocks; The identification module receives the address signal and the activation signal, and is configured to generate a target memory block activation signal corresponding to the address signal based on the address signal and the activation signal. The target memory block activation signal is used to drive the activation control module corresponding to the memory block corresponding to the address signal. Each of the activation control modules is configured to count based on the activation signal of the corresponding target storage block to generate an activation count value, and when the activation count value meets the activation preset value, generate and output a row hammer refresh indication signal corresponding to the storage block.

2. The memory according to claim 1, characterized in that, Each of the aforementioned activation control modules includes: The counting unit is configured to count based on the corresponding target storage block activation signal to generate the activation count value; The comparison unit, coupled to the counting unit and receiving an activation preset value, is configured to generate and output the row hammer refresh indication signal corresponding to the storage block when the activation count value satisfies the activation preset value.

3. The memory according to claim 1, characterized in that, Each of the aforementioned activation control modules includes: A cascaded k-stage D flip-flop, where the input of each stage of the D flip-flop is connected to the inverting output, and k is an integer greater than 1; The clock input of the first-stage D flip-flop is used to receive the target memory block activation signal. The clock input of the j-th stage D flip-flop is connected to the inverted output of the (j-1)-th stage D flip-flop, where 2≤j≤k. The output of the last stage D flip-flop is used to output the row hammer refresh indicator signal.

4. The memory according to any one of claims 1 to 3, characterized in that, The activation control module is located in the corresponding storage block.

5. The memory according to claim 1, characterized in that, The row hammer refresh control circuit includes: The first control module, coupled to the activation control circuit, is configured to generate a row hammer refresh enable signal based on any row hammer refresh indication signal. The second control module, coupled to the first control module, is configured to generate a row hammer refresh signal based on the refresh signal and the row hammer refresh enable signal. There are n processing modules, each corresponding to one of the n storage blocks; each processing module is coupled to the second control module and the corresponding activation control circuit, and is configured to generate and output the target storage block row hammer refresh signal corresponding to the storage block based on the row hammer refresh signal and the row hammer refresh indication signal corresponding to the storage block.

6. The memory according to claim 5, characterized in that, The first control module includes: an OR logic circuit, including n input terminals, each of the n input terminals receiving n row hammer refresh indication signals corresponding to the n memory blocks, and an output terminal for outputting the row hammer refresh enable signal.

7. The memory according to claim 5, characterized in that, The first control module includes: an XOR logic circuit, including n input terminals, each of the n input terminals receiving n row hammer refresh indication signals corresponding to the n memory blocks, and an output terminal for outputting the row hammer refresh enable signal.

8. The memory according to claim 5, characterized in that, The processing module includes: an AND logic circuit, a first input terminal for receiving the row hammer refresh signal, a second input terminal for receiving the row hammer refresh indication signal corresponding to the memory block, and an output terminal for outputting the target memory block row hammer refresh signal.

9. The memory according to any one of claims 5 to 8, characterized in that, The processing module is located in the corresponding storage block.

10. The memory according to claim 1, characterized in that, Also includes: A decoding circuit is used to receive and decode control commands issued by the storage controller to generate at least one of the refresh signal, the activation signal, and the address signal.

11. A memory, characterized in that, include: There are n storage blocks, where n is a positive integer; An activation control circuit is configured to receive an address signal and an activation signal, count the activation signals corresponding to each memory block based on the address signal, and generate and output a row hammer refresh indication signal corresponding to the memory block when the number of activation signals corresponding to any memory block meets an activation preset value; wherein the address signal indicates the memory block currently undergoing activation operation. A row hammer refresh control circuit, coupled to the activation control circuit, is configured to receive a refresh signal and a row hammer refresh indication signal, and generate a target memory block row hammer refresh signal corresponding to the memory block based on the refresh signal and the row hammer refresh indication signal. The target memory block row hammer refresh signal is used to instruct the corresponding memory block to perform a row hammer refresh operation. The row hammer refresh control circuit includes: The first control module, coupled to the activation control circuit, is configured to generate a row hammer refresh enable signal based on any row hammer refresh indication signal. The second control module, coupled to the first control module, is configured to generate a row hammer refresh signal based on the refresh signal and the row hammer refresh enable signal. There are n processing modules, each corresponding to one of the n storage blocks; each processing module is coupled to the second control module and the corresponding activation control circuit, and is configured to generate and output the target storage block row hammer refresh signal corresponding to the storage block based on the row hammer refresh signal and the row hammer refresh indication signal corresponding to the storage block.

12. A storage system, characterized in that, include: A storage controller and a memory, the memory being responsive to control commands issued by the storage controller, and the memory being configured based on the memory according to any one of claims 1 to 11.

Images