Memory device and operating method of the memory device

Abstract

A memory device and an operating method of the memory device are provided. The memory device includes: a memory cell array; a page buffer circuit including first to Nth page buffers, each page buffer including a readout node; and a control logic configured to control the page buffer operation, in which the control logic is further configured to control the page buffer operation such that in a first page buffer operation included in the first group, a pre-charge period and a discharge period for a first read node of the first page buffer are performed, in operation of a fifth page buffer included in the second group, a pre-charge period and a discharge period for a fifth readout node of the fifth page buffer are performed, and in a readout period of the fifth page buffer operation, a readout operation for the first readout node and the fifth readout node is performed together.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2023-0082882 filed in the Korean Intellectual Property Office on June 27, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Apparatuses and methods consistent with example embodiments relate to a memory device, and more particularly, to a memory device having improved data processing performance and an operating method of the memory device. Background Art

[0004] In view of the increasing demand for multifunctionalization of information and communication devices, a large-capacity and highly integrated memory device is required. The memory device may include a page buffer for storing data in or fetching data from a memory cell, and the page buffer may include a semiconductor element such as a transistor. Due to the demand for reducing the size of the page buffer, the size of the semiconductor element included in the page buffer may be reduced according to the increase in the integration of the memory device and the development of process technology. Therefore, the layout of the wiring connected to the semiconductor element may become complicated.

[0005] As a way to improve the integration of memory devices, a structure in which multiple input / output units share a combined readout node has been proposed. However, since multiple input / output units share the combined readout node, the data transfer time within the page buffer or between the page buffer and the external input / output line may increase, and the increase in data transfer time may deteriorate the data processing performance of the memory device in operations such as programming and reading. Summary of the invention

[0006] One or more example embodiments provide a memory device having improved data processing performance based on control of a page buffer and an operating method of the memory device.

[0007] According to an aspect of the present disclosure, a memory device may include: a memory cell array including a plurality of memory cells; a page buffer circuit including first to Nth page buffers connected to the plurality of memory cells through bit lines and classified into a first group and a second group, wherein N is an integer greater than or equal to 2; and a control logic configured to control first to Nth page buffer operations on the first to Nth page buffers in relation to a programming or reading operation of data. The control logic may also be configured to: in a page buffer operation of a page buffer belonging to the first group, perform a precharge period and a discharge period for a readout node in the first group, and omit a readout operation; and in a page buffer operation of a page buffer belonging to the second group, perform a precharge period and a discharge period for a readout node in the second group, and perform a readout period for the readout nodes belonging to the first and second groups to be read out together.

[0008] In the first to Nth page buffers, the first to Ath page buffers are classified into a first group, and the (A+1)th page buffers to Nth page buffers are classified into a second group, where A is an integer less than N. The control logic may also be configured to control the first buffer operation to the Nth page buffer operation, so that in the first page buffer operation, a precharge period and a discharge period for a first readout node of the first page buffer are performed, and in the (A+1)th page buffer operation, a precharge period and a discharge period for an (A+1)th readout node of the (A+1)th page buffer are performed. In the first page buffer operation, a readout operation on the first readout node may be omitted, and in a readout period of the (A+1)th page buffer operation, readout operations on the first readout node and the (A+1)th readout node may be performed together.

[0009] In the readout period of the (A+1)th page buffer operation, data according to the voltage level of the first readout node is stored in the readout latch of the first page buffer. Data according to the voltage level of the (A+1)th readout node can be stored in the readout latch of the (A+1)th page buffer.

[0010] Among the first to N page buffers, the first to A page buffers are classified into a first group, and the (A+1)th to N page buffers are classified into a second group, where A is an integer less than N. A discharge period during which the (A+1)th page buffer operates may be set to be shorter than a discharge period during which the first page buffer operates.

[0011] Each of the first to Nth page buffers may include a page buffer unit including one or more master latches, a cache unit including a cache latch connected to the page buffer unit through a combined read node, and at least one pass transistor configured to control an electrical connection with a read node of an adjacent page buffer. The page buffer units of the first to Nth page buffers may be arranged in a first direction, and the cache units of the first to Nth page buffers may be arranged in the first direction in an area separated from the page buffer units.

[0012] The first group may include the first to fourth page buffers, and the second group may include the fifth to eighth page buffers. The transfer transistors of the page buffers of the first group may be controlled by the first transfer control signal, and the transfer transistors of the page buffers of the second group may be controlled by the second transfer control signal. In the precharge period and the discharge period of the first page buffer operation, the first transfer control signal and the second transfer control signal may be set to an enable level to establish an electrical connection between all readout nodes of the first to Nth page buffers. In the precharge period and the discharge period of the fifth page buffer operation, the second transfer control signal may be selectively set to an enable level to establish an electrical connection only between the readout nodes of the page buffers included in the second group. In the precharge period and the discharge period of the fifth page buffer operation, the precharge operation and the discharge operation may be selectively performed on the readout nodes of the page buffers included in the second group.

[0013] In the readout period of the fifth to eighth page buffer operations, the first and second transfer control signals may be set to a disable level to establish electrical isolation among readout nodes in the first to eighth page buffers.

[0014] After the fifth page buffer operation is completed, the second page buffer operation and the sixth page buffer operation on the second page buffer and the sixth page buffer, the third page buffer operation and the seventh page buffer operation on the third page buffer and the seventh page buffer, and the fourth page buffer operation and the eighth page buffer operation on the fourth page buffer and the eighth page buffer can be performed sequentially, and in the second page buffer operation to the fourth page buffer operation, the read-out period can be omitted.

[0015] In the readout period of the sixth to eighth page buffer operations, the readout operations of the readout nodes of the page buffers belonging to the first group and the readout nodes of the page buffers belonging to the second group may be performed together.

[0016] According to another aspect of the present disclosure, a method for operating a memory device is provided, wherein the memory device may include first to fourth page buffers belonging to a first group and fifth to eighth page buffers belonging to a second group, each of the first to eighth page buffers including a page buffer unit including a read-out node and a cache unit including a cache latch, the page buffer units of the first to eighth page buffers may be arranged in a first direction, and the cache units of the first to eighth page buffers may be connected to the page buffer units through a combined read-out node, and may be arranged in the first direction in an area separated from the page buffer units. The operation method may include: in a precharge period of a first page buffer operation on a first page buffer of a first group, electrically connecting read nodes of the first page buffer to an eighth page buffer; in a discharge period of the first page buffer operation, discharging a first read node of the first page buffer according to data stored in a cache latch of the first page buffer; omitting a read operation on the first read node and floating the first read node by isolating an electrical connection between the read nodes in the first page buffer to the eighth page buffer; in a precharge period of a fifth page buffer operation on a fifth page buffer of a second group, electrically connecting read nodes of the fifth page buffer to the eighth page buffer; in a discharge period of the fifth page buffer operation, discharging a fifth read node of the fifth page buffer according to data stored in the cache latch of the fifth page buffer; and in a read period of the fifth page buffer operation, performing a read operation for reading voltage levels of the first read node and the fifth read node together.

[0017] The operating method may also include: sequentially performing a second page buffer operation and a sixth page buffer operation on the second page buffer and the sixth page buffer; sequentially performing a third page buffer operation and a seventh page buffer operation on the third page buffer and the seventh page buffer; sequentially performing a fourth page buffer operation and an eighth page buffer operation on the fourth page buffer and the eighth page buffer; in the second page buffer operation to the fourth page buffer operation, omitting the read-out period; and in the read-out period of the sixth page buffer operation to the eighth page buffer operation, performing the read-out operation on the read-out nodes of the two page buffers together.

[0018] Each of the first to eighth page buffers may include at least one transfer transistor configured to control an electrical connection with a readout node of an adjacent page buffer, the transfer transistors of the first to fourth page buffers may be controlled by a first transfer control signal, and the transfer transistors of the fifth to eighth page buffers may be controlled by a second transfer control signal, and in a precharge period and a discharge period of the first page buffer operation, the first transfer control signal and the second transfer control signal may be set to an enable level to establish an electrical connection between all the readout nodes of the first to eighth page buffers.

[0019] In the precharge period and the discharge period of the fifth page buffer operation, the second transfer control signal may be selectively set to an enable level to establish electrical connection only between the readout nodes of the fifth to eighth page buffers.

[0020] A discharge period of the fifth page buffer operation may be set to be shorter than a discharge period of the first page buffer operation.

[0021] The cache latch of the first page buffer may be connected to the page buffer unit through the first combined readout node and the second combined readout node, and the cache latch of the fifth page buffer may be connected to the page buffer unit through the second combined readout node. The operation method may also include: precharging the first combined readout node when the first combined readout node and the second combined readout node are electrically connected; and discharging the first combined readout node according to data stored in the readout latch of the first page buffer.

[0022] The operating method may also include: precharging the second combined read node when the first combined read node and the second combined read node are electrically separated; discharging the second combined read node according to data stored in the read latch of the fifth page buffer; and storing data in the cache latches of the first page buffer and the fifth page buffer by performing read operations on the first combined read node and the second combined read node together.

[0023] According to another aspect of the present disclosure, the memory device may include: a memory cell array including a plurality of memory cells; a page buffer circuit including a first page buffer to an Nth page buffer connected to the plurality of memory cells through a bit line; and a control logic configured to control the first page buffer operation to the Nth page buffer operation on the first page buffer to the Nth page buffer in association with a programming or reading operation of data, wherein the first page buffer to the Nth page buffer may be classified into a first group to a Kth group, and K is an integer less than N, and the control logic may also be configured to: in a page buffer operation of a page buffer belonging to the first group to the (K-1)th group, perform a precharge period and a discharge period for a read-out node, and omit the read-out operation; and in a page buffer operation of a page buffer belonging to the Kth group, perform a precharge period and a discharge period for a read-out node, and perform a read-out period so that the read-out nodes of the page buffers belonging to the first group to the Kth group are read out together.

[0024] The first to Nth page buffers may be classified into the first to fourth groups, in the page buffer operation of the page buffers belonging to the first to third groups, the read operation is omitted, and in the read operation of the page buffer operation of the page buffers belonging to the fourth group, the read nodes of the first to fourth groups are read out together.

[0025] During the precharge period of the first group to the (K-1)th group, the read-out nodes of the page buffers belonging to the group in which precharge is performed are electrically connected to the read-out nodes of the page buffers belonging to the Kth group, and during the precharge period of the Kth group, the electrical connection between the read-out nodes of the page buffers belonging to the Kth group and the read-out nodes of the page buffers belonging to the first group to the (K-1)th group is cut off. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and / or other aspects will become more apparent by describing certain example embodiments with reference to the accompanying drawings, in which:

[0027] Figure 1 is a block diagram showing a memory device according to an embodiment;

[0028] Figure 2 It is shown Figure 1 A block diagram of an implementation example of a page buffer circuit region;

[0029] Figure 3 is a schematic diagram showing a Figure 1 A diagram of the structure of a memory device;

[0030] Figure 4 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A diagram of an example of a memory cell array;

[0031] Figure 5 is a perspective view showing a memory block according to an embodiment;

[0032] Figure 6 is a diagram showing connections between a memory cell array and a page buffer circuit region according to an embodiment;

[0033] Figure 7 is a circuit diagram showing in detail a page buffer according to an embodiment;

[0034] Figure 8 It is shown Figure 6 A circuit diagram of an implementation example of a page buffer circuit;

[0035] Figures 9 to 11 is a diagram showing an implementation example and an operation example of a page buffer circuit according to an embodiment;

[0036] Fig.12 and Fig.13 is a flowchart illustrating an operating method of a memory device according to an embodiment;

[0037] Fig.14 It is shown Fig.13 A diagram of an example of an operation sequence in the embodiments described in;

[0038] Fig.15 is a diagram showing an operation example of a page buffer circuit according to other embodiments;

[0039] Fig.16 is a waveform diagram showing an example of various control signals that may be applied to a page buffer operation according to an embodiment;

[0040] Fig.17A and Fig. 17B is a circuit diagram showing an operation example of a memory device according to other embodiments;

[0041] Fig.18 is a diagram illustrating a memory device according to an embodiment; and

[0042] Fig.19 is a block diagram illustrating an example of applying a memory device to a solid state drive (SSD) system according to an embodiment. DETAILED DESCRIPTION

[0043] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0044] Figure 1 is a block diagram showing a memory device 100 according to an embodiment.

[0045] Reference Figure 1, the memory device 100 may include a memory cell array 110 and a peripheral circuit 120 , and the peripheral circuit 120 may include a page buffer circuit region 121 , a control circuit 122 , a voltage generator 123 , and a row decoder 124 .

[0046] The memory cell array 110 may be connected to the page buffer circuit region 121 through a bit line BL, and may be connected to a row decoder 124 through a word line WL, a string selection line SSL, and a ground selection line GSL. The memory cell array 110 may include a plurality of memory cells, and for example, the memory cell may be a flash memory cell. Hereinafter, the embodiment will be described in detail with reference to the case where the memory cell is a NAND flash memory cell as an example. However, the inventive concept is not limited thereto. In some embodiments, the memory cell may be a resistive memory cell, such as a resistive random access memory (RAM) (ReRAM) memory cell, a phase change RAM (PRAM) memory cell, or a magnetic RAM (MRAM) memory cell.

[0047] In an embodiment, the memory cell array 110 may include a three-dimensional memory cell array, the three-dimensional memory cell array may include a plurality of NAND strings, and each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. Figure 3 and Figure 4 A detailed description is provided regarding this aspect, wherein a three-dimensional memory includes a plurality of levels, and word lines and / or bit lines are shared between the levels.

[0048] The control circuit 122 may output various control signals (e.g., a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR) based on the command CMD, the address ADDR, and the control signal CTRL for programming data into the memory cell array 110, reading data from the memory cell array 110, or erasing data stored in the memory cell array 110. Therefore, the control circuit 122 may generally control various operations in the memory device 100.

[0049] The voltage generator 123 may generate various types of voltages for performing programming operations, reading operations, and erasing operations on the memory cell array 110 based on the voltage control signal CTRL_vol. In detail, the voltage generator 123 may generate a word line voltage VWL, for example, a programming voltage, a reading voltage, a pass voltage, an erase verification voltage, a programming verification voltage, etc. The row decoder 124 may select one of a plurality of memory blocks, one of the word lines WL of the selected memory block, and one of a plurality of string selection lines SSL in response to the row address X-ADDR. The page buffer circuit region 121 may select some of the bit lines BL in response to the column address Y-ADDR. In detail, the page buffer circuit region 121 operates as a write driver or a sense amplifier according to the operation mode.

[0050] The page buffer circuit region 121 may include a plurality of page buffers PB arranged to correspond to a plurality of bit lines BL, and each page buffer PB may be connected to a single bit line. Each page buffer PB may include a page buffer unit (eg, Figure 6 any one of PBU0 to PBUn) and cache latches (e.g. Figure 6 Any one of CL0 to CLn of the page buffer unit), and each page buffer unit may include a read node. In addition, the page buffer units and cache latches of the plurality of page buffers PB may be spaced apart from each other and may have separate structures. Therefore, the degree of freedom of wiring arranged on the page buffer unit may be increased, and the complexity of the layout may be reduced. In addition, because the cache latch is arranged adjacent to the data input / output line, the distance between the cache latch and the data input / output line may be reduced, and therefore, the data input / output speed may be increased.

[0051] In an embodiment, each page buffer PB (or each page buffer unit) may further include a pair of pass transistors (eg, Figure 7 TR0 and TR0'). According to the connection states of the transfer transistors of the plurality of page buffers PB, the connection states of the readout nodes of the page buffer PB can be controlled. For example, all the transfer transistors of the page buffer PB can be turned on, and thus, all the readout nodes of the page buffer PB can be electrically connected to each other. Alternatively, the transfer transistors of some of the page buffers in the page buffer PB can be selectively turned on, and thus, only the readout nodes of some of the page buffers in the page buffer PB can be electrically connected to each other, and the electrical connection between the readout nodes of some of the page buffers in the page buffer PB and the readout nodes of some other page buffers in the page buffer PB can be cut off.

[0052] In a data read operation, the transfer transistor included in each page buffer unit may be turned off, and thus, the read nodes included in the plurality of page buffers PB may not be electrically connected to each other. On the other hand, in a data transfer operation for transferring data between latches, the transfer transistor included in each page buffer unit may be turned on, and thus, the read nodes included in the plurality of page buffers PB may be electrically connected to each other, thereby serving as a data transfer line. Therefore, the page buffer circuit region 121 does not need to separately include a plurality of data transfer lines for connecting the plurality of page buffer units to the plurality of cache latches, respectively, and thus, the area occupied by the page buffer circuit region 121 may be reduced.

[0053] In an embodiment, the control circuit 122 may include a page buffer controller (PB Ctrl) 122_1. The control circuit 122 may control various components included in the page buffer PB in a data programming operation and a read operation based on the page buffer controller 122_1. For example, the control circuit 122 may control various switches included in the page buffer PB, or may control data transfer (or dump) between a plurality of latches included in the page buffer PB. In addition, the control circuit 122 may control data transfer between a latch included in the page buffer PB and an input / output line.

[0054] In addition, the page buffer PB can perform various types of operation sequences related to data programming operations and / or read operations. The operation sequence may include one or more time periods, and for example, a specific operation sequence may include a precharge period, a discharge period (or development period), and a read period for a read node. The precharge period may be the initial stage of a memory operation, in which the page buffer itself is prepared to read or write data. During the precharge period, the read node may be reset or precharged to a specific voltage level, which is used as a reference or baseline for subsequent operations. The precharge period may allow the read node to be placed in a known and stable state before the actual data transfer or read operation begins. The discharge period may be after the precharge period, as part of the process in which the page buffer is prepared to read or write data. During the discharge period, the page buffer PB may discharge the read node to a specific voltage level suitable for the upcoming data operation. The discharge period may prepare the page buffer to accurately detect or write data in the next stage. The read period may occur during a read operation in which the page buffer PB reads data. In the read period, the page buffer PB may read data from the memory cell and may store data corresponding to the voltage level (or charge level) of the read node in the latch of the page buffer PB.

[0055] When describing the following embodiments, various types of operation sequences may be performed in association with a programming operation and / or a read operation of the memory device 100, and the operation sequence may include a control operation on the page buffer PB. When describing the embodiments, a series of control operations on the page buffer PB may be defined as a page buffer operation, and each page buffer operation may include a plurality of time periods. In addition, when the page buffer circuit includes a first page buffer to an Nth page buffer, the operation sequence will be defined as including a first page buffer operation to an Nth page buffer operation on the first page buffer to the Nth page buffer. In addition, the page buffer operation according to the embodiment may be defined as a concept including various other types of time periods in addition to the precharge period, the discharge period, and the read period described in the following embodiments.

[0056] In an embodiment, a specific number of page buffers PB may be defined as a page buffer circuit, and the page buffers PB in one page buffer circuit may be classified into at least two groups. For example, each page buffer circuit may include eight page buffers PB, and the eight page buffers PB may be classified into two groups so that each group may include four page buffers PB. In this case, the operation of the page buffer PB may be controlled differently for each group. In addition, when a page buffer operation is performed on each of the eight page buffers PB, a first page buffer operation to an eighth page buffer operation may be performed, and each page buffer operation may include at least one of a precharge period, a discharge period, and a readout period.

[0057] According to an embodiment, assuming that the first to fourth page buffers PB are included in the first group, and the fifth to eighth page buffers PB are included in the second group, in the page buffer operation of each of the first to fourth page buffers PB, only the precharge period and the discharge period can be performed, and in the page buffer operation of each of the remaining fifth to eighth page buffers PB, the precharge period, the discharge period and the readout period can be performed. In addition, in the readout period of the page buffer operation of each of the fifth to eighth page buffers PB, the readout operation of the readout node of the page buffer PB included in the first group and the readout operation of the readout node of the page buffer PB included in the second group can be performed together. The page buffers PB in multiple groups can be organized so that the adjacent page buffers belong to the same group. For example, the first to fourth page buffers PB can form a first group that is continuously arranged, and the fifth to eighth page buffers PB can constitute a second group in a similar manner. However, this grouping method is not exclusive, and alternative arrangements are feasible. For example, organizing the page buffers PB into groups can follow different patterns. One embodiment involves sequentially arranging the first page buffer PB to the eighth page buffer PB, and classifying the odd-numbered page buffers (the first page buffer, the third page buffer, the fifth page buffer, the seventh page buffer) into a first group, while the even-numbered page buffers (the second page buffer, the fourth page buffer, the sixth page buffer, the eighth page buffer) form a second group.

[0058] According to the above-described embodiments, since the readout period may be omitted or skipped in the page buffer operation of some of the page buffers in the page buffer PB, the time required for all the page buffer operations may be reduced, and thus the data processing speed may be improved.

[0059] On the other hand, in an embodiment, control information for executing the operation sequence in the above-described embodiment may be stored in the memory device 100 in a non-volatile manner. The page buffer controller 122_1 of the memory device 100 may perform a control operation on the page buffer circuit region 121 using the control information. For example, the control information may be stored in the memory cell array 110 or in a separate memory circuit in the memory device 100, and when the memory device 100 is initially driven or activated, the control information may be used to configure an environmental setting related to the operation sequence of the page buffer circuit region 121. Alternatively, in an embodiment, when the memory device 100 is initially driven or activated, the control information may be provided to the memory device 100 from an external device (e.g., a memory controller).

[0060] Figure 2 It is shown Figure 1 1 is a block diagram of an implementation example of the page buffer circuit region 121.

[0061] Reference Figure 2 , the page buffer circuit area 121 may include page buffers PB corresponding to a plurality of bit lines BL, and a certain number of page buffers PB may constitute a page buffer circuit PBC. For example, the page buffer circuit area 121 may be connected to the memory cell array 110 through the bit lines BL transmitting 16K bytes of data, and the page buffer circuit area 121 may include page buffers PB corresponding to 16K bytes. In this case, assuming that the page buffer circuit PBC includes a first page buffer PB0 to an eighth page buffer PB7 corresponding to 1 byte of data D[0] to D[7], the page buffer circuit area 121 may include a 16K page buffer circuit PBC.

[0062] According to embodiments, the terms of various components related to the page buffer circuit region 121 may be defined in various ways without being limited to the above. For example, assuming that the page buffer circuit is a component corresponding to all bit lines among the plurality of bit lines BL, the terms may be defined to indicate that the page buffer circuit includes a plurality of page buffer groups, and each page buffer group corresponds to Figure 2 In the following embodiments, although components and operations of one page buffer circuit will be described, other page buffer circuits may also include the same components and perform the same operations.

[0063] Figure 3 is a schematic diagram showing a Figure 1 Schematic diagram of the structure of the memory device 100.

[0064] Reference Figure 3 , the memory device 100 may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 may be stacked on the second semiconductor layer L2 in the vertical direction VD. In detail, the second semiconductor layer L2 may be disposed below the first semiconductor layer L1 in the vertical direction VD. In an embodiment, Figure 1 The memory cell array 110 may be formed in the first semiconductor layer L1, and Figure 1 The peripheral circuit 120 may be formed in the second semiconductor layer L2. Therefore, the memory device 100 may have a structure in which the memory cell array 110 is arranged above the peripheral circuit 120, that is, a cell-on-periphery (COP) structure. The COP structure may reduce the horizontal area and may improve the integration of the memory device 100.

[0065] In an embodiment, after forming the peripheral circuit 120 in the second semiconductor layer L2, the first semiconductor layer L1 including the memory cell array 110 may be formed, and a metal pattern for electrically connecting the word lines WL and the bit lines BL of the memory cell array 110 to the peripheral circuit 120 formed in the second semiconductor layer L2 may be formed. For example, the bit lines BL may extend in a first horizontal direction or first direction HD1, and the word lines WL may extend in a second horizontal direction or second direction HD2.

[0066] With the development of semiconductor process technology, as the number of memory cells arranged in the memory cell array 110 increases, especially by stacking more word lines WL, the area of ​​the memory cell array 110 can be reduced, and therefore, the area of ​​the peripheral circuit 120 can also be reduced. According to the present embodiment, since the page buffer circuit region 121 has a structure in which the page buffer unit and the cache latch are separated, and the read nodes included in the page buffer unit are commonly connected to the combined read node, the area occupied by the page buffer circuit region 121 can be reduced.

[0067] Figure 4 is a diagram showing a method according to an embodiment of the present invention. Figure 1 FIG. 1 is a diagram of an example of a memory cell array 110 .

[0068] Reference Figure 4 , the memory cell array 110 may include a plurality of memory blocks BLK0 to BLKi, and i may be a positive integer. Each of the plurality of memory blocks BLK0 to BLKi may have a three-dimensional structure (or a vertical structure). Each of the plurality of memory blocks BLK0 to BLKi may include a plurality of NAND strings extending in a vertical direction VD. Specifically, the plurality of NAND strings may be arranged at a specific distance apart from each other in a first direction HD1 and a second direction HD2.

[0069] Figure 5 is a stereoscopic diagram showing a memory block BLKa according to an embodiment.

[0070] Reference Figure 5 , the memory block BLKa may correspond to Figure 4One of the multiple memory blocks BLK0 to BLKi in the memory block BLKa. The memory block BLKa is formed in the vertical direction VD relative to the substrate SUB having a first conductivity type (e.g., p-type). In an embodiment, a common source line CSL doped with impurities of a second conductivity type (e.g., n-type) may be provided to the substrate SUB. In an embodiment, the substrate SUB may include polycrystalline silicon, and the common source line CSL having a plate shape may be arranged on the substrate SUB. A plurality of insulating layers IL extending in the second direction HD2 are sequentially arranged on the substrate SUB along the vertical direction VD, and the plurality of insulating layers IL are arranged at a specific distance apart from each other in the vertical direction VD. For example, the plurality of insulating layers IL may include an insulating material, such as silicon oxide.

[0071] A plurality of pillars P sequentially arranged in a first direction HD1 and passing through a plurality of insulating layers IL in a vertical direction VD are provided on a substrate SUB. For example, a plurality of pillars P may pass through a plurality of insulating layers IL to contact the substrate SUB. Specifically, a surface layer S of each pillar P may include a first type of silicon material and may be used as a channel region. Therefore, the pillars P may be referred to as a vertical channel structure. On the other hand, an inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

[0072] The charge storage layer CS is arranged along the exposed surfaces of the insulating layer IL, the pillars P and the substrate SUB. The charge storage layer CS may include a gate insulating layer, a charge trapping layer and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, a gate electrode GE including a ground selection line GSL, a string selection line SSL and word lines WL1 to WL8 is arranged on the exposed surface of the charge storage layer CS. The drains DR are respectively arranged on the plurality of pillars P. For example, the drain DR may include a silicon material doped with impurities having a second conductivity type. Bit lines BL1 to BL3 extending in the first direction HD1 and arranged at a specific distance from each other in the second direction HD2 are arranged on the drain DR.

[0073] Figure 6 is a diagram showing connections between a memory cell array 110 and a page buffer circuit according to an embodiment. Figure 6 One page buffer circuit PBC among a plurality of page buffer circuits provided in the page buffer circuit region is shown. In addition, regarding a readout node in a page buffer, the readout node may be described as being included in the page buffer, or the readout node may be described as being included in a page buffer unit.

[0074] Reference Figure 6The memory cell array 110 may include a first NAND string NS0 to an (n+1)th NAND string NSn, each of which may include a ground selection transistor GST connected to a ground selection line GSL, a plurality of memory cells MC respectively connected to a plurality of word lines WL0 to WLm, and a string selection transistor SST connected to a string selection line SSL, and the plurality of memory cells MC and the string selection transistor SST may be connected in series to each other.

[0075] The page buffer circuit PBC may include a first page buffer to an (n+1)th page buffer, and the first page buffer to the (n+1)th page buffer may include a first page buffer unit PBU0 to an (n+1)th page buffer unit PBUn. The first page buffer unit PBU0 may be connected to the first NAND string NS0 through the first bit line BL0, and the (n+1)th page buffer unit PBUn may be connected to the (n+1)th NAND string NSn through the (n+1)th bit line BLn. For example, n may be 7, and the page buffer circuit PBC may have a structure in which eight levels of first page buffer units PBU0 to (n+1)th page buffer units PBUn are arranged in a row. For example, the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn may be arranged in a row in an extension direction of the first bit line BL0 to the (n+1)th bit line BLn.

[0076] The page buffer circuit PBC may also include first cache latches CL0 to (n+1)th cache latches CLn corresponding to the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn. For example, n may be 7, and the page buffer circuit PBC may have a structure in which eight levels of first cache latches CL0 to (n+1)th cache latches CLn are arranged in a row. For example, the first cache latches CL0 to (n+1)th cache latches CLn may be arranged in a row in the extending direction of the first bit line BL0 to the (n+1)th bit line BLn.

[0077] The read nodes of the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn may be commonly connected to the combined read node SOC. In addition, the first cache latch CL0 to the (n+1)th cache latch CLn may be commonly connected to the combined read node SOC. Therefore, the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn may be connected to the first cache latch CL0 to the (n+1)th cache latch CLn through the combined read node SOC. In an implementation example, when the transfer transistor included in each page buffer unit is turned on, the read nodes of the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn may be connected in series to the combined read node SOC. In addition, the first cache latch CL0 to the (n+1)th cache latch CLn may be connected to the combined read node SOC in parallel with each other.

[0078] In an embodiment, when all the transfer transistors of the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn are turned on, the readout nodes of the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn can be electrically connected to each other. In addition, when the page buffers are classified into at least two groups, the transfer transistors of the page buffer units of the first group can be turned off, and when the transfer transistors of the page buffer units of the second group are turned on, only the readout nodes of the page buffer units of the second group can be selectively connected to each other. According to the above control, the capacitance value of the readout node in the page buffer operation of the first group can be set differently from the capacitance value of the readout node in the page buffer operation of the second group. In the operation example, when a plurality of page buffers are classified into at least two groups, two or more levels of page buffers positioned adjacent to each other can be classified into one group.

[0079] Figure 7 is a circuit diagram illustrating a page buffer PB according to an embodiment in detail.

[0080] Figure 7 The page buffer PB shown can be Figure 1 An exemplary embodiment of a page buffer PB of the present invention. The page buffer PB may include a page buffer unit PBU and a cache unit CU. The cache unit CU may include a cache latch (C-latch) CL, and because the cache latch CL is connected to the data input / output line, the cache unit CU may be arranged adjacent to the data input / output line. Therefore, the page buffer unit PBU and the cache unit CU may be arranged separately from each other, and the page buffer PB may have a structure in which the page buffer unit PBU and the cache unit CU are separated.

[0081] The page buffer unit PBU may include a main unit MU. The main unit MU may include one or more latches and one or more transistors. The page buffer unit PBU may also include a bit line selection transistor TR_hv connected to the bit line BL and driven by the bit line selection signal BLSLT. The bit line selection transistor TR_hv may be implemented as a high voltage transistor, and therefore, the bit line selection transistor TR_hv may be arranged in a well region different from the main unit MU, that is, in the high voltage unit HVU.

[0082] The main unit MU may include a sense latch (S-latch) SL, a force latch (F-latch) FL, an upper latch (M-latch) ML, and a lower latch (L-latch) LL. According to an embodiment, the sense latch SL, the force latch FL, the upper latch ML, or the lower latch LL may be referred to as a "master latch". The main unit MU may also include a precharge circuit PC that can control a precharge operation of a bit line BL or a sense node SO based on a bit line clamp control signal BLCLAMP, and may also include a transistor PM' driven by a bit line setup signal BLSETUP.

[0083] The read latch SL can store the data stored in the memory cell or the read result of the threshold voltage of the memory cell during a read operation or a program verification operation. In addition, the read latch SL can be used to apply a program bit line voltage or a program inhibit voltage to the bit line BL during a program operation. The force latch FL can be used to improve the threshold voltage distribution during a programming operation. In detail, the force latch FL can store forced data. The forced data can be initially set to "1", and then, when the threshold voltage of the memory cell enters a forced area with a lower voltage than the target area, the forced data is changed to "0". By using the forced data, during the program execution operation, the bit line voltage can be controlled, and the programming threshold voltage distribution can be formed more narrowly.

[0084] The upper latch ML, the lower latch LL, and the cache latch CL can be used to store data input from the outside during a programming operation, and can be referred to as a "data latch". When 3-bit data is programmed in one memory cell, the 3-bit data can be stored in the upper latch ML, the lower latch LL, and the cache latch CL, respectively. Before the programming of the memory cell is completed, the upper latch ML, the lower latch LL, and the cache latch CL can maintain the data stored therein. In addition, the cache latch CL can receive data read from the memory cell from the read latch SL during a read operation, and can output the data to the outside through the data input / output line.

[0085] In addition, the main unit MU may further include a first transistor NM1 to a fourth transistor NM4. The first transistor NM1 may be connected between the read node SO and the read latch SL, and may be driven by the ground control signal SOGND. The second transistor NM2 may be connected between the read node SO and the forced latch FL, and may be driven by the forced monitoring signal MON_F. The third transistor NM3 may be connected between the read node SO and the upper latch ML, and may be driven by the upper monitoring signal MON_M. The fourth transistor NM4 may be connected between the read node SO and the lower latch LL, and may be driven by the lower monitoring signal MON_L.

[0086] In addition, the main unit MU may further include a fifth transistor NM5 and a sixth transistor NM6 connected in series between the bit line selection transistor TR_hv and the read node SO. The fifth transistor NM5 may be driven by the bit line shutoff signal BLSHF, and the sixth transistor NM6 may be driven by the bit line connection control signal CLBLK. In addition, the main unit MU may further include a precharge transistor PM. The precharge transistor PM is connected to the read node SO, is driven by the load signal LOAD, and precharges the read node SO to a precharge level in the precharge period.

[0087] In an embodiment, the main unit MU may further include a pair of transfer transistors connected to the readout node SO, that is, a first transfer transistor TR and a second transfer transistor TR'. According to an embodiment, the first transfer transistor TR and the second transfer transistor TR' may be referred to as "a first readout node connection transistor and a second readout node connection transistor". The first transfer transistor TR and the second transfer transistor TR' may be driven according to a transfer control signal SO_PASS. According to an embodiment, the transfer control signal SO_PASS may be referred to as a "readout node connection control signal". In detail, the first transfer transistor TR may be connected between the first terminal SOC_U and the readout node SO, and the second transfer transistor TR' may be connected between the readout node SO and the second terminal SOC_D.

[0088] For example, when the page buffer unit PBU is Figure 6 When the second page buffer unit PBU1 is connected to the first page buffer unit PBU0, the first terminal SOC_U may be connected to one end of the pass transistor included in the first page buffer unit PBU0, and the second terminal SOC_D may be connected to one end of the pass transistor included in the third page buffer unit PBU3. Therefore, the readout node SO of the second page buffer unit PBU1 may be electrically connected to the combined readout node SOC through the pass transistor included in each of the third page buffer unit PBU2 to the (n+1)th page buffer unit PBUn.

[0089] During a programming operation, the page buffer PB may perform a page buffer operation for verifying whether programming is completed in a selected memory cell among the memory cells included in the NAND string connected to the bit line BL. For example, in a programming verification operation, a precharge operation may be performed on a read node SO of the page buffer PB, a discharge operation may be performed according to the data stored in the selected memory cell, and a read operation may be performed to store the data read through the read node SO in the read latch SL. According to the data stored in the read latch SL, an upper latch ML and a lower latch LL storing target data may be set. For example, when the read data indicates that programming is completed, the upper latch ML and the lower latch LL may be switched to a program inhibit setting of the selected memory cell in a subsequent programming cycle.

[0090] Alternatively, in a programming operation or a read operation, the page buffer PB may perform a page buffer operation for storing data in the read latch SL according to the data stored in the cache latch CL. For example, a precharge operation may be performed on the read node SO of the page buffer PB, a discharge operation may be performed on the read node SO according to the data stored in the cache latch CL, and a read operation may be performed to store the data read through the read node SO in the read latch SL. In the above-mentioned example of the page buffer operation, it has been described that the data read through the read node SO is stored in the read latch SL, but the embodiment is not necessarily limited thereto. The data read through the read node SO may also be stored in another latch in the main unit MU.

[0091] Figure 8 It is shown Figure 6 A circuit diagram of an implementation example of a page buffer circuit PBC is shown below. Figures 6 to 8 The configuration of the page buffer circuit PBC is described in detail.

[0092] Each page buffer unit may include two pass transistors, and when the page buffer circuit PBC includes eight page buffers, the page buffer circuit PBC may include 16 pass transistors, namely, first pass transistors TR0 to TR7 and second pass transistors TR0′ to TR7′ that may be connected in series to each other. Figure 8 , but each page buffer unit may also include a plurality of latches and a plurality of transistors, as described in the above embodiments. For example, the first page buffer unit PBU0 may also include a plurality of transistors (eg, Figure 7The plurality of transistors are connected between the first transfer transistor TR0 and the second transfer transistor TR0' and arranged in the first horizontal direction HD1. In addition, each of the second to eighth page buffer units PBU1 to PBU7 can be implemented the same as or similar to the first page buffer unit PBU0 described above.

[0093] In addition, each page buffer unit may include a precharge transistor, and the first precharge transistor PM0 to the eighth precharge transistor PM7 may be included in the page buffer circuit PBC to correspond to the first page buffer unit PBU0 to the eighth page buffer unit PBU7. For example, in the first page buffer unit PBU0, the first precharge transistor PM0 may be connected between the first readout node SO0 and the voltage terminal to which the precharge voltage is applied, and may have a gate to which the load signal LOAD is applied. The first precharge transistor PM0 may precharge the first readout node SO0 to a precharge level in response to the load signal LOAD.

[0094] The page buffer circuit PBC may further include a precharge circuit SOC_PRE located between the eighth page buffer unit PBU7 and the first cache unit CU0. The precharge circuit SOC_PRE may include a precharge transistor PMa for precharging the combined readout node SOC, and a shielding transistor NMa. The precharge transistor PMa may be driven by the combined readout node load signal SOC_LOAD, and when the precharge transistor PMa is turned on, the combined readout node SOC may be precharged to a precharge level. The shielding transistor NMa may be driven by the combined readout node shielding signal SOC_SHLD, and when the shielding transistor NMa is turned on, the combined readout node SOC may be precharged to a ground level.

[0095] On the other hand, each cache unit may include a monitoring transistor. For example, the first monitoring transistor NM7a to the eighth monitoring transistor NM7h included in the page buffer circuit PBC may correspond to the first cache unit CU0 to the eighth cache unit CU7. The first monitoring transistor NM7a to the eighth monitoring transistor NM7h may be connected in parallel to the combined read-out node SOC and may be controlled by the cache monitoring signal MON_C[7:0]. In addition, according to the logic level of the cache monitoring signal MON_C[7:0], the electrical connection between the cache latch in the first cache unit CU0 to the eighth cache unit CU7 and the combined read-out node SOC may be controlled.

[0096] According to the above-mentioned implementation example of the page buffer circuit PBC in the present embodiment, the separate arrangement of the page buffer unit and the cache unit provides greater flexibility for the design of the metal pattern arranged in one or more metal layers above the page buffer unit. In addition, in the structure in which the first to eighth page buffer units PBU0 to PBU7 are separated from the first to eighth cache units CU0 to CU7, the first to eighth read nodes SO0 to SO7 can be connected to each other by using the first transfer transistors TR0 to TR7 and the second transfer transistors TR0' to TR7' respectively included in the first to eighth page buffer units PBU0 to PBU7, and the first to eighth read nodes SO0 to SO7 can be connected to the first to eighth cache units CU0 to CU7 through the combined read node SOC. That is, there is no need to include metal lines arranged side by side in the second horizontal direction HD2 to individually connect each of the first to eighth read nodes SO0 to SO7 to the combined read node SOC, the first to eighth read nodes SO0 to SO7 can be connected in series to the combined read node SOC in the first horizontal direction HD1, and therefore, the size of the page buffer circuit PBC in the second horizontal direction HD2 can be prevented from increasing.

[0097] On the other hand, according to an embodiment, the first to eighth page buffers may be classified into two groups. For example, the first to fourth page buffers may be classified into the first group, and the remaining fifth to eighth page buffers may be classified into the second group. In addition, the same transmission control signal may be provided to the page buffers included in each group. For example, the first transmission control signal SOPASS[0] may be provided to the first transmission transistors TR0 to TR3 and the second transmission transistors TR0' to TR3' included in the first page buffer unit PBU0 to the fourth page buffer unit PBU3 of the page buffer of the first group, and the second transmission control signal SOPASS[1] may be provided to the first transmission transistors TR4 to TR7 and the second transmission transistors TR4' to TR7' included in the fifth page buffer unit PBU4 to the eighth page buffer unit PBU7 of the page buffer of the second group.

[0098] The page buffer operation according to the embodiment may include one or more of a precharge period, a discharge period, and a readout period. The page buffer circuit PBC may include a first page buffer to an eighth page buffer, and a page buffer operation may be performed for each page buffer, and therefore, any one operation sequence of the page buffer circuit PBC may include a first page buffer operation to an eighth page buffer operation. According to the embodiment, the readout period may be skipped in some page buffer operations, and the readout operation of at least two page buffers may be performed together in the readout period of some other page buffer operations.

[0099] In the operation example, regarding the first page buffer operation of the first page buffer of the first group, in the precharge period, when the first precharge transistor PM0 to the eighth precharge transistor PM7 are turned on, the first read node SO0 to the eighth read node SO7 can be precharged to the precharge level, when the first transfer control signal SOPASS[0] and the second transfer control signal SOPASS[1] have a logic high level, the first transfer transistors TR0 to TR7 and the second transfer transistors TR0' to TR7' can be turned on, and the first read node SO0 to the eighth read node SO7 can be electrically connected to each other. Then, in the discharge period, when the first read node SO0 is discharged through the path including the second read node SO1 to the eighth read node SO7, the voltage level of the first read node SO0 can change. For example, the degree of reduction in the voltage level can vary according to the data stored in the cache latch of the first cache unit CU0. Thereafter, when the first transmission control signal SOPASS[0] and the second transmission control signal SOPASS[1] change to a logic low level and the first transmission transistors TR0 to TR7 and the second transmission transistors TR0' to TR7' are turned off, the first readout node SO0 can be changed to a floating state, and the first readout node SO0 can maintain the voltage level changed in the discharge period.

[0100] On the other hand, in the above-mentioned first page buffer operation, the readout period can be skipped, and then proceed to the fifth page buffer operation related to the fifth page buffer of the second group. With respect to the fifth page buffer operation, in the precharge period, when the fifth precharge transistor PM4 to the eighth precharge transistor PM7 are selectively turned on, only the fifth readout node SO4 to the eighth readout node SO7 can be selectively precharged to the precharge level. In addition, the first transmission control signal SOPASS[0] can be maintained at a logic low level, while the second transmission control signal SOPASS[1] can be changed to a logic high level, and therefore, the first transmission transistors TR4 to TR7 and the second transmission transistors TR4' to TR7' of the fifth page buffer to the eighth page buffer can be turned on. Therefore, although the fifth readout node SO4 to the eighth readout node SO7 can be electrically connected to each other, the fourth readout node SO3 and the fifth readout node SO4 can be electrically separated from each other. That is, the fifth readout node SO4 can be electrically separated from the first readout node SO0 to the fourth readout node SO3.

[0101] Thereafter, in the discharge period, the fifth sensing node SO4 may be discharged through a path including the sixth sensing node SO5 to the eighth sensing node SO7, and the voltage level of the fifth sensing node SO4 may change according to the data stored in the cache latch of the fifth cache unit CU4. Then, when the first transfer transistors TR4 to TR7 and the second transfer transistors TR4' to TR7' are turned off, the fifth sensing node SO4 may change to a floating state, and the fifth sensing node SO4 may maintain the voltage level changed in the discharge period.

[0102] Thereafter, in the fifth page buffer operation, a readout period may be performed, and during the readout period, a readout operation on the first readout node SO0 and the fifth readout node SO4 may be performed together. For example, in the readout period, by controlling the readout latch included in the first page buffer unit PBU0, the first readout node SO0 and the readout latch of the first page buffer unit PBU0 may be electrically connected to each other, and data having a logic value according to the voltage level of the first readout node SO0 may be stored in the readout latch. In addition, by controlling the readout latch included in the fifth page buffer unit PBU4, the fifth readout node SO4 and the readout latch of the fifth page buffer unit PBU4 may be electrically connected to each other, and data having a logic value according to the voltage level of the fifth readout node SO4 may be stored in the readout latch.

[0103] The page buffer operation may also be performed on the remaining page buffers in the same or similar manner as the above operation. For example, the above page buffer operation may be performed on the second page buffer of the first group and the sixth page buffer of the second group, and then, the above page buffer operation may be performed on the third page buffer of the first group and the seventh page buffer of the second group, and thereafter, the above page buffer operation may be performed on the fourth page buffer of the first group and the eighth page buffer of the second group. When the page buffer operation on the first to eighth page buffers is completed as described above, data may be stored in each of the read latches of the first to eighth page buffer units PBU0 to PBU7, and data programming and / or reading operations may be performed based on the stored data.

[0104] Hereinafter, specific operations of the memory device according to the embodiment will be illustrated. Figures 9 to 11 2 are diagrams illustrating implementation examples and operation examples of a page buffer circuit according to an embodiment. Figures 9 to 11 The operation sequence described in the embodiment shows an operation example in which data stored in the cache latch is transferred to the sense latch.

[0105] Reference Fig. 9 , the memory device may include a plurality of page buffer circuits, and each page buffer circuit may include a plurality of page buffers. For example, the page buffer circuit may include a first page buffer to an eighth page buffer, each page buffer may include a page buffer unit and a cache unit that are physically separated from each other as described in the above embodiments, and the page buffer units of the plurality of page buffer circuits may have a structure in which a combined readout node is shared between the page buffer units.

[0106] According to an embodiment, a plurality of page buffers may be classified into at least two groups. Fig. 9 The first page buffer unit PBU0 and the first cache unit CU0 of the first page buffer belonging to the first group, and the fifth page buffer unit PBU4 and the fifth cache unit CU4 of the fifth page buffer belonging to the second group are schematically shown. In addition, each page buffer may include a transfer transistor (e.g., two transfer transistors), the transfer transistor of the first page buffer may receive a first transfer control signal SOPASS[0], and the transfer transistor of the fifth page buffer may receive a second transfer control signal SOPASS[1]. In addition, Fig. 9 An implementation example of a sense latch included in each page buffer unit and having a sense amplifier is shown, and it is shown that the page buffer unit and the cache unit have a physically separated structure, and therefore, the first cache unit CU0 and the fifth cache unit CU4 are located together on the right side of the drawing.

[0107] The following will refer to Fig.10describe Fig. 9 An operation example of the page buffer circuit is shown in FIG.

[0108] First to eighth page buffer operations PBO[0] to PBO[7] corresponding to the first to eighth page buffers may be performed, and each page buffer operation may include at least one of a precharge period SO_PRECH, a discharge period SO_DISCH, and a read period SEN. According to an embodiment, the read period may be skipped in some of the first to eighth page buffer operations, and in the read period of some other of the first to eighth page buffer operations, the read operation of the read nodes of at least two page buffers may be performed together. Therefore, since one or more read periods may be skipped in the entire operation sequence, the time required for the entire operation sequence may be reduced.

[0109] For example, regarding the first page buffer operation PBO[0] of the first page buffer, in the precharge period, the first load signal LOAD[0] and the fifth load signal LOAD[4] may be changed to a logic low as an enable level, and thus, the readout node of the first page buffer and the readout node of the fifth page buffer may be precharged. Fig.10 Although not shown in the figure, the pre-charge transistors in other page buffers may be turned on, and according to an embodiment, all pre-charge transistors included in the first to eighth page buffers may be turned on. In addition, during the pre-charge period, the first transfer control signal SOPASS[0] and the second transfer control signal SOPASS[1] may be changed to a logic high as an enable level, and thus, the readout nodes of the first to eighth page buffers may be electrically connected to each other through the transfer transistors of the first to eighth page buffers. Although Fig.10 It is shown that the first transmission control signal SOPASS[0] and the second transmission control signal SOPASS[1] are enabled after a certain time has passed after the start of the precharge period, but the embodiment is not necessarily limited to this. For example, the first transmission control signal SOPASS[0] and the second transmission control signal SOPASS[1] may be enabled at the start of the precharge period, or may be enabled at any point after the start of the precharge period.

[0110] Thereafter, in the discharge period of the first page buffer operation PBO[0], the first load signal LOAD[0] and the fifth load signal LOAD[4] may be changed to a logic high level, and the first transfer control signal SOPASS[0] and the second transfer control signal SOPASS[1] may be maintained in a logic high state. Therefore, the readout node of the first page buffer may be electrically connected to the combined readout node through the readout nodes of the second to eighth page buffers, the first cache monitor signal MON_C[0] may be changed to a logic high as an enable level, and therefore, the readout node of the first page buffer may be discharged according to the value of the data stored in the first cache latch. Fig. 9 As shown by the thick black solid line in FIG. 1 , the read-out node of the first page buffer may be discharged through a ground terminal included in the first cache latch.

[0111] Thereafter, after omitting the readout period of the first page buffer operation PBO[0], the precharge period of the fifth page buffer operation PBO[4] may be performed. In the precharge period of the fifth page buffer operation PBO[4], the first load signal LOAD[0] may maintain a logic high level, and the fifth load signal LOAD[4] may be changed to a logic low level as an enable level, and thus, the readout node of the fifth page buffer may be precharged. For example, the load signals provided to the fifth to eighth page buffers may be changed to a logic low level as an enable level together.

[0112] In addition, in the precharge period of the fifth page buffer operation PBO[4], only the second transfer control signal SOPASS[1] may be changed to a logic high as an enable level, and thus, the readout nodes of the fifth to eighth page buffers may be electrically connected to each other, and the electrical connection between the readout node of the fourth page buffer and the readout node of the fifth page buffer may be cut off. Therefore, the readout node of the fifth page buffer may be electrically separated from the readout nodes of the first to fourth page buffers, and the readout node of the fifth page buffer may be connected to the combined readout node through the readout nodes of the sixth to eighth page buffers.

[0113] Thereafter, in the discharge period of the fifth page buffer operation PBO[4], the fifth load signal LOAD[4] may become a logic high level, and the second transfer control signal SOPASS[1] may maintain a logic high state. In addition, the fifth cache monitor signal MON_C[4] may change to a logic high as an enable level, and thus, the read node of the fifth page buffer may be discharged according to the value of the data stored in the fifth cache latch. For example, the read node of the fifth page buffer may be discharged through a path including the read nodes of the sixth to eighth page buffers. For example, as Fig. 9As shown by the thick black solid line in FIG. 1 , the read-out node of the fifth page buffer may be discharged through the ground terminal included in the fifth cache latch.

[0114] Thereafter, in the readout period of the fifth page buffer operation PBO[4], the second transfer control signal SOPASS[1] may be changed to a logic high as a disable level, and the readout node of the fifth page buffer may be changed to a floating state. In addition, the voltage of the readout nodes of the first page buffer and the fifth page buffer may be maintained at a level according to the discharge result, the monitoring transistor may be turned on in response to the first monitoring control signal MON[0] and the fifth monitoring control signal MON[4], and thus, data according to the voltage level of the readout nodes of the first page buffer and the fifth page buffer may be stored in the readout latches of the first page buffer and the fifth page buffer. For example, the readout latch of each page buffer may include a transistor receiving a set / reset signal and a pair of buffers (or inverters) forming a latch structure, and in the readout period, at least one of the set / reset signals SET / RST[0] provided to the readout latch of the first page buffer may be changed to a logic high as an enable level. Furthermore, in the read period, at least one of the set / reset signals SET / RST[4] supplied to the read latch of the fifth page buffer may be changed to a logic high as an enable level.

[0115] According to the embodiments described above, since the read period can be skipped in four page buffer operations from the first page buffer operation to the eighth page buffer operation, the time required for the entire operation sequence associated with the programming / reading operation of the data can be reduced, and therefore, the performance of the programming / reading operation of the data can be improved.

[0116] on the other hand, Fig.11 The entire operation sequence of the first to eighth page buffer operations is schematically illustrated.

[0117] The first page buffer operation PBO[0] may include a precharge period and a discharge period associated with the first page buffer. In addition, the fifth page buffer operation PBO[4] may include a precharge period, a discharge period, and a read period associated with the fifth page buffer. In addition, in the read period of the fifth page buffer operation PBO[4], an operation of reading voltage levels of read nodes of the first page buffer and the fifth page buffer and storing the read results in the read latches of the first page buffer and the fifth page buffer may be performed together.

[0118] On the other hand, Fig. 9 and Fig.10As described in the above embodiment, in the discharge period of the fifth page buffer operation PBO[4], only the second transmission control signal SOPASS[1] can be changed to a logic high level as an enable level, and therefore, the readout nodes of the fifth to eighth page buffers can be electrically connected to each other, while the readout node of the fifth page buffer and the readout nodes of the first to fourth page buffers can be electrically separated from each other. Therefore, the capacitance value of the readout node of the fifth page buffer can be smaller than when the readout nodes of all page buffers are connected to each other. Therefore, the discharge period of the fifth page buffer operation PBO[4] can be set to a relatively shorter time than the discharge period of the first page buffer operation PBO[0]. For example, the discharge period of the page buffer operation of the fifth to eighth page buffers belonging to the second group can be set to be shorter than the discharge period of the page buffer operation of the first group.

[0119] The remaining page buffer operations can also be performed by Fig.11 The operation sequence shown is performed. For example, the readout period can be skipped in the second page buffer operation PBO[1] to the fourth page buffer operation PBO[3], and the readout period can be performed in the remaining sixth page buffer operation PBO[5] to the eighth page buffer operation PBO[7]. In addition, in the readout period of each of the sixth page buffer operation PBO[5] to the eighth page buffer operation PBO[7], the readout operation on the readout nodes of the two page buffers can be performed together. In addition, in the discharge period of the sixth page buffer operation PBO[5] to the eighth page buffer operation PBO[7], the electrical connection between the readout nodes of the first page buffer to the fourth page buffer and the readout nodes of the fifth page buffer to the eighth page buffer can be disconnected, and therefore, the discharge period of the sixth page buffer operation PBO[5] to the eighth page buffer operation PBO[7] can be set to have a relatively short time.

[0120] According to the above-described embodiment, since the discharge periods of four page buffer operations among the first to eighth page buffer operations can be set to have a relatively short time, the time required for the entire operation sequence associated with the programming / reading operation of data can be further reduced. Fig.11 As shown, according to the embodiment, the time required for the discharge period and the readout period in the entire operation sequence can be reduced compared with the existing case.

[0121] On the other hand, in the above-described embodiment, all readout nodes of the first to eighth page buffers are precharged in the precharge period of the first page buffer operation PBO[0], and the readout nodes of the fifth to eighth page buffers are precharged in the discharge period of the fifth page buffer operation PBO[4], the embodiment is not necessarily limited thereto. For example, in the precharge period of each page buffer operation, only the readout nodes of the corresponding page buffer may be precharged, or the readout nodes of some page buffers may be selectively precharged.

[0122] Fig.12 and Fig.13 is a flowchart illustrating an operating method of a memory device according to an embodiment.

[0123] Reference Fig.12 , the page buffer circuit according to the embodiment may include the first page buffer to the eighth page buffer as a plurality of page buffers. According to the above embodiment, the plurality of page buffer units and the plurality of cache units may be physically separated from each other, and the page buffer unit and the cache unit may be electrically connected to each other through a combined readout node. In addition, according to the above embodiment, the first group may include the first page buffer to the fourth page buffer, the second group may include the fifth page buffer to the eighth page buffer, and the page buffer operation on the page buffer of the first group may be performed differently from the page buffer operation on the page buffer of the second group.

[0124] The first page buffer operation to the eighth page buffer operation can be performed as an operation sequence of the first page buffer to the eighth page buffer. In the precharge period of the first page buffer operation, the read nodes of the first page buffer to the eighth page buffer can be electrically interconnected by controlling the transfer transistors of the first page buffer to the eighth page buffer (operation S11). In addition, the precharge transistor can be activated to precharge the read nodes of the first page buffer to the eighth page buffer (operation S12). Thereafter, in order to discharge the read node of the first page buffer, a switching operation can be performed to electrically connect the cache latch of the first page buffer to the combined read node, and the read node of the first page buffer can be discharged through a path including the read nodes of the second page buffer to the eighth page buffer (operation S13).

[0125] Thereafter, without performing a read operation on the read node of the first page buffer, the precharge period of the fifth page buffer operation may be entered. In the precharge period of the fifth page buffer operation, the read nodes of the fifth page buffer to the eighth page buffer may be electrically connected to each other by controlling the transfer transistors of the first page buffer to the eighth page buffer (operation S14). In addition, by turning on the precharge transistors of the fifth buffer to the eighth page buffer, the read nodes of the fifth page buffer to the eighth page buffer may be precharged (operation S15). Thereafter, in order to discharge the read node of the fifth page buffer, a switching operation may be performed to electrically connect the cache latch of the fifth page buffer to the combined read node, and the read node of the fifth page buffer may be discharged through a path including the read nodes of the sixth page buffer to the eighth page buffer (operation S16).

[0126] Thereafter, in the readout period of the fifth page buffer operation, the readout nodes of the first to eighth page buffers may be electrically separated from each other, and the readout operation of the readout nodes of the first to fifth page buffers may be performed together (operation S17). For example, a switching operation for electrically connecting the readout node of the first page buffer to its readout latch and a switching operation for electrically connecting the readout node of the fifth page buffer to its readout latch may be performed. Although Fig.12 Not shown, but after completing the fifth page buffer operation, the second page buffer operation of the first group and the sixth page buffer operation of the second group can be performed according to the above process, and the third page buffer operation and the fourth page buffer operation of the first group and the seventh page buffer operation and the eighth page buffer operation of the second group can be performed according to the above process.

[0127] On the other hand, refer to Fig.13 , the page buffers included in the page buffer circuit may be classified into a plurality of groups. For example, the page buffers may be classified into a first group to an Nth group, and N may have a value of 3 or more. In addition, in an embodiment, each of the page buffers may include one or more transfer transistors that control the connection between the readout nodes of the page buffers, and a first transfer control signal to an Nth transfer control signal may be generated corresponding to the first group to the Nth group. In addition, the page buffers of each group may receive the corresponding transfer control signal in common.

[0128] A first page buffer operation may be performed on any one of the page buffers of the first group, and in the first page buffer operation, a precharge period and a discharge period may be performed on the page buffers of the first group (operation S21). In this case, according to the above-described embodiment, the readout nodes of all the page buffers included in the first to N-th groups may be electrically connected to each other.

[0129] Thereafter, a second page buffer operation may be performed on any one of the page buffers of the second group, and in the second page buffer operation, a precharge period and a discharge period may be performed on the page buffers of the second group (operation S22). In this case, according to the above-described embodiment, the readout nodes of the page buffers included in the second to N-th groups may be electrically connected to each other, and the electrical connection between the readout nodes of the page buffers included in the first group and the readout nodes of the page buffers included in the second to N-th groups may be cut off.

[0130] The above-mentioned page buffer operations may be performed sequentially, and in the (N-1)th page buffer operation, a precharge period and a discharge period (S23) may be performed on the page buffer of the (N-1)th group. In this case, the readout nodes of the page buffers included in the (N-1)th group and the Nth group may be electrically connected to each other, and the electrical connection between the readout nodes of the page buffers included in the first group to the (N-2)th group and the readout nodes of the page buffers included in the (N-1)th group and the Nth group may be cut off. In addition, in the Nth page buffer operation, a precharge period and a discharge period (operation S24) may be performed on the page buffer of the Nth group. In this case, the readout nodes of the page buffers included in the Nth group may be electrically connected to each other, and the electrical connection between the readout nodes of the page buffers included in the first group to the (N-1)th group and the readout nodes of the page buffers included in the Nth group may be cut off.

[0131] After performing the above operations, a readout period of the Nth page buffer operation may be performed, and in the readout period, electrical connections between readout nodes of all page buffers included in the first to N groups may be cut off. In addition, the readout node of any one page buffer in each of the first to N groups may have a voltage level according to a discharge result, and in the readout period, a readout operation of the readout nodes of the page buffers in each of the first to N groups may be performed together (operation S25).

[0132] Fig.14 It is shown Fig.13 An illustration of an example of an operation sequence in the embodiment described in FIG. Fig.14 It is shown that the page buffer circuit includes a first page buffer to an eighth page buffer, and the page buffers are classified into four groups, so that the first group includes a first page buffer and a second page buffer, the second group includes a third page buffer and a fourth page buffer, the third group includes a fifth page buffer and a sixth page buffer, and the fourth group includes a seventh page buffer and an eighth page buffer.

[0133] In the first page buffer operation PBO[0] for the first page buffer of the first group, a precharge period and a discharge period may be performed, a readout node of the first page buffer may be changed to a floating state, and thus, a voltage level changed in the discharge period may be maintained in the first readout node. In addition, in the first page buffer operation PBO[0], the discharge period may be set to a first time t1. In addition, in the third page buffer operation PBO[2] for the third page buffer of the second group, a precharge period and a discharge period may be performed, a readout node of the third page buffer may be changed to a floating state, and thus, a voltage level changed in the discharge period may be maintained in the third readout node. In addition, in the third page buffer operation PBO[2], the discharge period may be set to a second time t2. Similarly, in the fifth page buffer operation PBO[4] for the fifth page buffer of the third group, a precharge period and a discharge period may be performed, a readout node of the fifth page buffer may be changed to a floating state, and thus, a voltage level changed in the discharge period may be maintained in the fifth readout node. Furthermore, in the fifth page buffer operation PBO[4], the discharge period may be set to the third time t3. In the above-described page buffer operations on the first to third groups, the readout period may be skipped.

[0134] Thereafter, in the seventh page buffer operation PBO[6] of the seventh page buffer of the fourth group, a precharge period and a discharge period may be performed, and the discharge period may be set to a fourth time t4. In this case, in the discharge period of the first page buffer operation PBO[0], the maximum number of readout nodes may be electrically connected to each other, and in the discharge period of the seventh page buffer operation PBO[6], the minimum number of readout nodes may be electrically connected to each other. In addition, the first time t1 may have the longest value, and the fourth time t4 may have the shortest value. For example, the first time t1 may be longer than the second time t2, the second time t2 may be longer than the third time t3, and the third time t3 may be longer than the fourth time t4. In addition, in the readout period of the seventh page buffer operation PBO[6], the readout operations on the first readout node, the third readout node, the fifth readout node, and the seventh readout node may be performed together.

[0135] Thereafter, similar to the above-mentioned page buffer operations, a second page buffer operation PBO[1], a fourth page buffer operation PBO[3], a sixth page buffer operation PBO[5] and an eighth page buffer operation PBO[7] may be performed, and in the read period of the eighth page buffer operation PBO[7], the read operations on the second read node, the fourth read node, the sixth read node and the eighth read node may be performed together.

[0136] Fig.152 are diagrams illustrating operation examples of page buffer circuits according to other embodiments. Fig.15 1 to 8 page buffers are each individually controlled, and therefore, the first transmission control signal SOPASS[0] to the eighth transmission control signal SOPASS[7] are provided to the page buffer circuit. In addition, although for ease of description, Fig.15 Only one pass transistor corresponding to each page buffer is shown, but a greater number of pass transistors may be arranged according to the above-described embodiments.

[0137] Each of the first to eighth page buffer units PBU0 to PBU7 may include one or more master latches and sense amplifiers (S / A), and first to eighth sense nodes SO0 to SO7 of the first to eighth page buffers may be electrically connected to each other based on first to eighth transfer control signals SOPASS[0] to SOPASS[7]. In addition, although Fig.15 Although not shown in the figure, the page buffer circuit may include a combined sense node SOC, and the first to eighth sense nodes SO0 to SO7 may be connected to the cache unit through the combined sense node SOC.

[0138] In an embodiment, the first transmission control signal SOPASS[0] to the eighth transmission control signal SOPASS[7] may have an enable level in the precharge period and the discharge period of the first page buffer. In addition, in the precharge period and the discharge period of the second page buffer, the first transmission control signal SOPASS[0] may have a disable level. In addition, in the precharge period and the discharge period of the eighth page buffer, the first transmission control signal SOPASS[0] to the seventh transmission control signal SOPASS[6] may have a disable level. In addition, in the readout period of the eighth page buffer, the readout operation of the readout nodes respectively included in the first page buffer to the eighth page buffer may be performed together.

[0139] Fig.16 is a waveform diagram showing an example of various control signals that can be applied to the page buffer operation according to an embodiment. Fig.16 As shown in Fig.10 The detailed description of the signals described in the embodiments overlaps the detailed description of the signals.

[0140] Reference Fig.16, a precharge period and a discharge period may be performed in the first page buffer operation PBO[0] for the first page buffer, and a precharge period, a discharge period, and a readout period may be performed in the fifth page buffer operation PBO[4] for the fifth page buffer. In addition, according to the above-described embodiment, in the fifth page buffer operation PBO[4], the capacitance value of the fifth readout node may be relatively small, and therefore, the discharge period of the fifth page buffer operation PBO[4] may be set to be relatively short.

[0141] In an embodiment, the precharge period and / or the discharge period may be controlled differently for each group of page buffers. For example, in the precharge period of the fifth page buffer operation PBO[4], the fifth readout node may be precharged at a relatively low level, and by adjusting the level of the fifth load signal LOAD[4], the precharge transistor may be relatively weakly turned on, thereby adjusting the precharge level of the fifth readout node. Alternatively, in an embodiment, the precharge level of the fifth readout node may be adjusted by adjusting the level of the precharge voltage provided to the precharge transistor.

[0142] Alternatively, in an embodiment, the level of the cache monitoring signal may be adjusted during the discharge period of the fifth page buffer operation PBO[4]. For example, by adjusting the level of the fifth cache monitoring signal MON_C[4] in the fifth page buffer operation PBO[4], the monitoring transistor may be relatively weakly turned on.

[0143] According to the above operation example, in the page buffer operation of the page buffer belonging to the second group, the readout node may have a relatively small value, and in response, the discharge period may be set to be short, or the levels of various control signals used in the page buffer operation may be adjusted. For example, the power consumed in the page buffer operation may be reduced by lowering the level of the control signal or setting the conduction degree of the transistor to be weak.

[0144] Fig.17A and Fig. 17B 1 is a circuit diagram showing an operation example of a memory device according to another embodiment. Fig.17A and Fig. 17B The configuration and operation examples of the memory device shown in the figure are omitted with reference to Fig. 9 A detailed description of the configuration and operation of the memory device is provided.

[0145] Reference Fig.17A , the first page buffer unit PBU0 of the first page buffer and the fifth page buffer unit PBU4 of the fifth page buffer can be connected with Fig. 9 Therefore, as the page buffer operation according to the above-mentioned embodiment, the operation of dumping data from the cache latch to the read latch can be equally applied to Fig.17A That is, based on controlling the first transmission control signal SOPASS[0] and the second transmission control signal SOPASS[1], the sensing operation of the first sensing node SO0 and the fifth sensing node SO4 can be performed together.

[0146] On the other hand, according to an embodiment, skipping the read period in some page buffer operations and the simultaneous read operation of at least two read nodes in some other page buffer operations may be equally or similarly applied to an operation sequence of dumping data from a read latch to a cache latch. For example, a first cache unit CU0 may be connected to a first combined read node SOC0 via a monitoring transistor that receives a first cache monitoring signal MON_C[0], and may include a latch circuit and a transistor controlled by a cache set / reset signal CSET / CRST[0]. In addition, a fifth cache unit CU4 may be connected to a second combined read node SOC1 via a monitoring transistor that receives a fifth cache monitoring signal MON_C[4], and may include a latch circuit and a transistor controlled by a cache set / reset signal CSET / CRST[4].

[0147] although Fig.17A , but the first cache unit to the eighth cache unit may also be classified into at least two groups, the first cache unit to the fourth cache unit may be classified into the first group, and the fifth cache unit to the eighth cache unit may be classified into the second group. In addition, one or more cache transfer transistors for controlling the electrical connection between the first combined read-out node SOC0 and the second combined read-out node SOC1 may also be provided in the page buffer circuit. For example, a first cache transfer transistor may be provided to control the electrical connection between the first combined read-out node SOC0 and the second combined read-out node SOC1, and the first cache transfer transistor may be controlled by the first transfer control signal SOPASS[0]. In addition, a second cache transfer transistor for controlling the electrical connection between the second combined read-out node SOC1 and the page buffer unit may be provided, and the second cache transfer transistor may be controlled by the second transfer control signal SOPASS[1].

[0148] exist Fig.17AIn the illustrated embodiment, the cache cells are classified into two groups, and therefore, a first transfer control signal SOPASS[0] and a second transfer control signal SOPASS[1] as well as a first cache transfer transistor and a second cache transfer transistor are illustrated, but the embodiment is not necessarily limited thereto. For example, even when the second cache transfer transistor is removed from the page buffer circuit, a page buffer operation according to the embodiment can be performed. Alternatively, based on the group classification of the cache cells, a larger number of cache transfer transistors can be provided in the page buffer circuit. In addition, in Fig.17A , as signals for controlling the electrical connection between the combined readout nodes, the first transmission control signal SOPASS[0] and the second transmission control signal SOPASS[1] which are the same as the signals for controlling the electrical connection between the readout nodes of the page buffer unit are shown, but the embodiment is not necessarily limited thereto. For example, the control signal for controlling the electrical connection between the readout nodes of the page buffer unit and the control signal for controlling the electrical connection between the combined readout nodes of the cache unit may be implemented separately.

[0149] In order to dump data from the read latch to the cache latch, the first page buffer operation to the eighth page buffer operation may be performed corresponding to the first page buffer to the eighth page buffer. In this case, the first page buffer operation for transferring data from the read latch of the first page buffer to the cache latch of the first cache unit CU0 may include a precharge period and a discharge period, and the fifth page buffer operation for transferring data from the read latch of the fifth page buffer to the cache latch of the fifth cache unit CU4 may include a precharge period, a discharge period, and a read period. In addition, the voltage level of the first combined read node SOC0 may be discharged through the discharge period of the first page buffer operation, the voltage level of the second combined read node SOC1 may be discharged through the discharge period of the fifth page buffer operation, and in the read period of the fifth page buffer operation, the read operation of the first combined read node SOC0 and the second combined read node SOC1 may be performed together, and therefore, the operation of storing (or dumping) data in the first cache latch and the fifth cache latch may be performed together.

[0150] The following will refer to Fig. 17B The waveform diagram shown in Fig.17A An operation example of a page buffer circuit is shown in FIG.

[0151] In the first page buffer operation PBO[0], the first load signal LOAD[0] and the fifth load signal LOAD[4] may be changed to an enable level, and the first transfer control signal SOPASS[0] and the second transfer control signal SOPASS[1] may also be changed to an enable level. Therefore, the readout node of the page buffer unit may be precharged, and the first combined readout node SOC0 and the second combined readout node SOC1 electrically connected to the readout node of the page buffer unit may also be precharged. Although Fig. 17B Not shown, but controlled by Figure 8 The precharge transistor PMa in the embodiment shown in FIG. 1 may perform a precharge operation on the first combined readout node SOC0 and the second combined readout node SOC1. Thereafter, the first monitoring control signal MON[0] may be changed to an enable level in the discharge period of the first page buffer operation PBO[0], and thus, a discharge operation may be performed on the first combined readout node SOC0 based on the data stored in the first readout latch.

[0152] In the case where a readout period in which data is stored in the first cache latch based on the voltage level of the first combined readout node SOC0 is not performed, in the first page buffer operation PBO[0], the fifth page buffer operation PBO[4] may be performed. In the precharge and / or discharge period of the fifth page buffer operation PBO[4], based on controlling the first transmission control signal SOPASS[0] and the second transmission control signal SOPASS[1], a precharge operation may be selectively performed only on the second combined readout node SOC1. In addition, the fifth monitoring control signal MON[4] may be changed to an enable level, and thus, a discharge operation may be performed on the second combined readout node SOC1 based on the data stored in the fifth readout latch.

[0153] According to the above operation, each of the first combined read node SOC0 and the second combined read node SOC1 can maintain a voltage level according to the discharge operation, and in the read period of the fifth page buffer operation PBO[4], the read operation of the first combined read node SOC0 and the second combined read node SOC1 can be performed together. For example, by the control of the cache set / reset signal CSET / CRST[0], data corresponding to the voltage levels of the first combined read node SOC0 and the second combined read node SOC1 can be stored together in the first cache latch and the fifth cache latch.

[0154] According to the above embodiments, data transfer or dump operations between a master latch and a cache latch can be performed in various memory operations (e.g., program / read / erase operations) of a memory device, and the time required for an operation sequence related to data transfer can be reduced.

[0155] Fig.18 is a diagram illustrating a memory device 500 according to some embodiments of the inventive concept.

[0156] Reference Fig.18 , the memory device 500 may have a chip-to-chip (C2C) structure. At least one upper chip including a cell area and a lower chip including a peripheral circuit area PERI may be manufactured separately, and then, at least one upper chip and the lower chip may be connected to each other by a bonding method to realize a C2C structure. For example, the bonding method may refer to a method of electrically or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, in the case where the bonding metal pattern is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. Alternatively, the bonding metal pattern may be formed of aluminum (Al) or tungsten (W).

[0157] The memory device 500 may include at least one upper chip, and the at least one upper chip includes a cell region. Fig.18 As shown, the memory device 500 may include two upper chips. However, the number of upper chips is not limited thereto. In the case where the memory device 500 includes two upper chips, a first upper chip including a first cell area CELL1, a second upper chip including a second cell area CELL2, and a lower chip including a peripheral circuit area PERI may be manufactured separately, and then, the first upper chip, the second upper chip, and the lower chip may be connected to each other by a bonding method to manufacture the memory device 500. The first upper chip may be flipped over and then connected to the lower chip by a bonding method, and the second upper chip may also be flipped over and then connected to the first upper chip by a bonding method. Hereinafter, the upper and lower portions of each of the first upper chip and the second upper chip will be defined based on before each of the first upper chip and the second upper chip is flipped over. In other words, in Fig.18 In the embodiment, the upper portion of the lower chip may refer to the upper portion defined based on the +Z axis direction, and the upper portion of each of the first upper chip and the second upper chip may refer to the upper portion defined based on the -Z axis direction. However, the embodiments of the present inventive concept are not limited thereto. In a specific embodiment, one of the first upper chip and the second upper chip may be flipped and then connected to the corresponding chip by a bonding method.

[0158] Each of the peripheral circuit region PERI and the first and second cell regions CELL1 and CELL2 of the memory device 500 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0159] The peripheral circuit region PERI may include a first substrate 210 and a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210. An interlayer insulating layer 215 including one or more insulating layers may be disposed on the plurality of circuit elements 220a, 220b, and 220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 220a, 220b, and 220c may be disposed in the interlayer insulating layer 215. For example, the plurality of metal lines may include first metal lines 230a, 230b, and 230c connected to the plurality of circuit elements 220a, 220b, and 220c, and second metal lines 240a, 240b, and 240c formed on the first metal lines 230a, 230b, and 230c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 230 a , 230 b , and 230 c may be formed of tungsten having a relatively high resistivity, and the second metal lines 240 a , 240 b , and 240 c may be formed of copper having a relatively low resistivity.

[0160] In the present embodiment, the first metal lines 230a, 230b and 230c and the second metal lines 240a, 240b and 240c are shown and described. However, the embodiments of the present inventive concept are not limited thereto. In a specific embodiment, at least one or more additional metal lines may be further formed on the second metal lines 240a, 240b and 240c. In this case, the second metal lines 240a, 240b and 240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 240a, 240b and 240c may be formed of copper having a resistivity lower than the resistivity of the aluminum of the second metal lines 240a, 240b and 240c.

[0161] The interlayer insulating layer 215 may be disposed on the first substrate 210 and may include an insulating material such as silicon oxide and / or silicon nitride.

[0162] Each of the first cell region CELL1 and the second cell region CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate 310 and a common source line 320. A plurality of word lines 330 (331 to 338) may be stacked on the second substrate 310 in a direction perpendicular to the top surface of the second substrate 310 (i.e., the Z-axis direction). A string selection line and a ground selection line may be disposed on and below the word line 330, and a plurality of word lines 330 may be disposed between the string selection line and the ground selection line. Similarly, the second cell region CELL2 may include a third substrate 410 and a common source line 420, and a plurality of word lines 430 (431 to 438) may be stacked on the third substrate 410 in a direction perpendicular to the top surface of the third substrate 410 (i.e., the Z-axis direction). Each of the second substrate 310 and the third substrate 410 may be formed of at least one of various materials and may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in each of the first cell region CELL1 and the second cell region CELL2.

[0163] In some embodiments, as shown in region "A1", the channel structure CH may be disposed in the bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate the word line 330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to the first metal line 350c and the second metal line 360c in the bit line bonding region BLBA. For example, the second metal line 360c may be a bit line and may be connected to the channel structure CH through the first metal line 350c. The bit line 360c may extend in a first direction (e.g., a Y-axis direction) parallel to the top surface of the second substrate 310.

[0164] In some embodiments, as shown in region "A2", the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process of forming a lower channel LCH and a process of forming an upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate the common source line 320 and the lower word lines 331 and 332. The lower channel LCH may include a data storage layer, a channel layer, and a filling insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 333 to 338. The upper channel UCH may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 350c and the second metal line 360c. As the length of the channel increases, it may be difficult to form a channel with a substantially uniform width due to the characteristics of the manufacturing process. The memory device 500 according to the present embodiment may include channels having improved width uniformity due to the lower channel LCH and the upper channel UCH formed through processes performed sequentially.

[0165] In the case where the channel structure CH includes a lower channel LCH and an upper channel UCH as shown in region "A2", a word line located near the boundary between the lower channel LCH and the upper channel UCH may be a dummy word line. For example, word lines 332 and 333 adjacent to the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Alternatively, the number of pages corresponding to the memory cells connected to the dummy word lines may be less than the number of pages corresponding to the memory cells connected to the general word lines. The level of the voltage applied to the dummy word line may be different from the level of the voltage applied to the general word line, and therefore, the effect of the uneven channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device may be reduced.

[0166] On the other hand, in the region "A2", the number of lower word lines 331 and 332 penetrated by the lower channel LCH is less than the number of upper word lines 333 to 338 penetrated by the upper channel UCH. However, the embodiments of the inventive concept are not limited thereto. In a specific embodiment, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. In addition, the structural features and connection relationships of the channel structure CH disposed in the second cell region CELL2 may be substantially the same as the structural features and connection relationships of the channel structure CH disposed in the first cell region CELL1.

[0167] In the bit line bonding area BLBA, the first through electrode THV1 may be disposed in the first cell area CELL1, and the second through electrode THV2 may be disposed in the second cell area CELL2. Fig.18 As shown, the first through electrode THV1 may penetrate the common source line 320 and the plurality of word lines 330. In a specific embodiment, the first through electrode THV1 may also penetrate the second substrate 310. The first through electrode THV1 may include a conductive material. Alternatively, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as the first through electrode THV1.

[0168] In some embodiments, the first through electrode THV1 and the second through electrode THV2 may be electrically connected to each other through the first through metal pattern 372d and the second through metal pattern 472d. The first through metal pattern 372d may be formed at the bottom end of the first upper chip including the first cell area CELL1, and the second through metal pattern 472d may be formed at the top end of the second upper chip including the second cell area CELL2. The first through electrode THV1 may be electrically connected to the first metal line 350c and the second metal line 360c. The lower through piece 371d may be formed between the first through electrode THV1 and the first through metal pattern 372d, and the upper through piece 471d may be formed between the second through electrode THV2 and the second through metal pattern 472d. The first through metal pattern 372d and the second through metal pattern 472d may be connected to each other by a bonding method.

[0169] In addition, in the bit line bonding area BLBA, the upper metal pattern 252 may be formed in the uppermost metal layer of the peripheral circuit area PERI, and the upper metal pattern 392 having the same shape as the upper metal pattern 252 may be formed in the uppermost metal layer of the first cell area CELL1. The upper metal pattern 392 of the first cell area CELL1 and the upper metal pattern 252 of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. In the bit line bonding area BLBA, the bit line 360c may be electrically connected to the page buffer included in the peripheral circuit area PERI. For example, some of the circuit elements 220c of the peripheral circuit area PERI may constitute a page buffer, and the bit line 360c may be electrically connected to the circuit element 220c constituting the page buffer through the upper bonding metal pattern 370c of the first cell area CELL1 and the upper bonding metal pattern 270c of the peripheral circuit area PERI.

[0170] Continue to refer to Fig.18In the word line bonding area WLBA, the word line 330 of the first cell area CELL1 may extend in a second direction (e.g., X-axis direction) parallel to the top surface of the second substrate 310 and may be connected to a plurality of cell contact plugs 340 (341 to 347). The first metal line 350b and the second metal line 360b may be sequentially connected to the cell contact plugs 340 connected to the word line 330. In the word line bonding area WLBA, the cell contact plugs 340 may be connected to the peripheral circuit area PERI through the upper bonding metal pattern 370b of the first cell area CELL1 and the upper bonding metal pattern 270b of the peripheral circuit area PERI.

[0171] The cell contact plug 340 may be electrically connected to a row decoder included in the peripheral circuit region PERI. For example, some of the circuit elements 220b of the peripheral circuit region PERI may constitute a row decoder, and the cell contact plug 340 may be electrically connected to the circuit element 220b constituting the row decoder through the upper bonding metal pattern 370b of the first cell region CELL1 and the upper bonding metal pattern 270b of the peripheral circuit region PERI. In some embodiments, the operating voltage of the circuit element 220b constituting the row decoder may be different from the operating voltage of the circuit element 220c constituting the page buffer. For example, the operating voltage of the circuit element 220c constituting the page buffer may be greater than the operating voltage of the circuit element 220b constituting the row decoder.

[0172] Similarly, in the word line bonding area WLBA, the word lines 430 of the second cell area CELL2 may extend in a second direction (e.g., X-axis direction) parallel to the top surface of the third substrate 410, and may be connected to a plurality of cell contact plugs 440 (441 to 447). The cell contact plugs 440 may be connected to the peripheral circuit area PERI through the upper metal pattern of the second cell area CELL2 and the lower and upper metal patterns and the cell contact plugs 348 of the first cell area CELL1.

[0173] In the word line bonding area WLBA, the upper bonding metal pattern 370b may be formed in the first cell area CELL1, and the upper bonding metal pattern 270b may be formed in the peripheral circuit area PERI. The upper bonding metal pattern 370b of the first cell area CELL1 and the upper bonding metal pattern 270b of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. The upper bonding metal pattern 370b and the upper bonding metal pattern 270b may be formed of aluminum, copper, or tungsten.

[0174] In the external pad bonding area PA, a lower metal pattern 371e may be formed in a lower portion of the first cell area CELL1, and an upper metal pattern 472a may be formed in an upper portion of the second cell area CELL2. The lower metal pattern 371e of the first cell area CELL1 and the upper metal pattern 472a of the second cell area CELL2 may be connected to each other in the external pad bonding area PA by a bonding method. Similarly, an upper metal pattern 372a may be formed in an upper portion of the first cell area CELL1, and an upper metal pattern 272a may be formed in an upper portion of the peripheral circuit area PERI. The upper metal pattern 372a of the first cell area CELL1 and the upper metal pattern 272a of the peripheral circuit area PERI may be connected to each other by a bonding method.

[0175] Common source line contact plugs 380 and 480 may be disposed in the external pad bonding area PA. Common source line contact plugs 380 and 480 may be formed of a conductive material such as a metal, a metal compound, and / or doped polysilicon. The common source line contact plug 380 of the first cell area CELL1 may be electrically connected to the common source line 320, and the common source line contact plug 480 of the second cell area CELL2 may be electrically connected to the common source line 420. The first metal line 350a and the second metal line 360a may be sequentially stacked on the common source line contact plug 380 of the first cell area CELL1, and the first metal line 450a and the second metal line 460a may be sequentially stacked on the common source line contact plug 480 of the second cell area CELL2.

[0176] The input / output pads 205, 405, and 406 may be disposed in the external pad landing area PA. Fig.18 , the lower insulating layer 201 may cover the bottom surface of the first substrate 210, and the first input / output pad 205 may be formed on the lower insulating layer 201. The first input / output pad 205 may be connected to at least one of the plurality of circuit elements 220a provided in the peripheral circuit region PERI through the first input / output contact plug 203, and may be separated from the first substrate 210 by the lower insulating layer 201. In addition, a side insulating layer may be provided between the first input / output contact plug 203 and the first substrate 210 to electrically isolate the first input / output contact plug 203 from the first substrate 210.

[0177] An upper insulating layer 401 covering the top surface of the third substrate 410 may be formed on the third substrate 410. Second input / output pads 405 and / or third input / output pads 406 may be disposed on the upper insulating layer 401. The second input / output pads 405 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through second input / output contact plugs 403 and 303, and the third input / output pads 406 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through third input / output contact plugs 404 and 304.

[0178] In some embodiments, the third substrate 410 may not be disposed in a region in which the input / output contact plug is disposed. For example, as shown in region "B", the third input / output contact plug 404 may be separated from the third substrate 410 in a direction parallel to the top surface of the third substrate 410, and may penetrate the interlayer insulating layer 415 of the second cell region CELL2 so as to be connected to the third input / output pad 406. In this case, the third input / output contact plug 404 may be formed by at least one of various processes.

[0179] In some embodiments, as shown in the region “B1”, the third input / output contact plug 404 may extend in a third direction (e.g., the Z-axis direction), and the diameter of the third input / output contact plug 404 may become gradually increased toward the upper insulating layer 401. That is, the diameter of the channel structure CH described in the region “A1” may become gradually decreased toward the upper insulating layer 401, but the diameter of the third input / output contact plug 404 may become gradually increased toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other by a bonding method.

[0180] In a specific embodiment, as shown in region "B2", the third input / output contact plug 404 may extend in a third direction (e.g., Z-axis direction), and the diameter of the third input / output contact plug 404 may become gradually reduced toward the upper insulating layer 401. In other words, like the channel structure CH, the diameter of the third input / output contact plug 404 may become gradually reduced toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

[0181] In certain embodiments, the input / output contact plug may overlap the third substrate 410. For example, as shown in region "C", the second input / output contact plug 403 may penetrate the interlayer insulating layer 415 of the second cell region CELL2 in a third direction (e.g., Z-axis direction) and may be electrically connected to the second input / output pad 405 through the third substrate 410. In this case, the connection structure of the second input / output contact plug 403 and the second input / output pad 405 may be implemented by various methods.

[0182] In some embodiments, as shown in the region “C1”, the opening 408 may be formed to penetrate the third substrate 410, and the second input / output contact plug 403 may be directly connected to the second input / output pad 405 through the opening 408 formed in the third substrate 410. In this case, as shown in the region “C1”, the diameter of the second input / output contact plug 403 may become gradually increased toward the second input / output pad 405. However, embodiments of the inventive concept are not limited thereto, and in certain embodiments, the diameter of the second input / output contact plug 403 may become gradually decreased toward the second input / output pad 405.

[0183] In a specific embodiment, as shown in the region “C2”, an opening 408 penetrating the third substrate 410 may be formed, and a contact 407 may be formed in the opening 408. One end of the contact 407 may be connected to the second input / output pad 405, and the other end of the contact 407 may be connected to the second input / output contact plug 403. Therefore, the second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 in the opening 408. In this case, as shown in the region “C2”, the diameter of the contact 407 may become gradually increased toward the second input / output pad 405, and the diameter of the second input / output contact plug 403 may become gradually decreased toward the second input / output pad 405. For example, the second input / output contact plug 403 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other, and the contact 407 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

[0184] In a specific embodiment, as shown in region "C3", compared with the embodiment of region "C2", a blocking member 409 may be further formed on the bottom end of the opening 408 of the third substrate 410. The blocking member 409 may be a metal line formed in the same layer as the common source line 420. Alternatively, the blocking member 409 may be a metal line formed in the same layer as at least one of the word lines 430. The second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 and the blocking member 409.

[0185] Like the second input / output contact plug 403 and the third input / output contact plug 404 of the second cell region CELL2, the diameter of each of the second input / output contact plug 303 and the third input / output contact plug 304 of the first cell region CELL1 may become gradually reduced toward the lower metal pattern 371e or may become gradually increased toward the lower metal pattern 371e.

[0186] On the other hand, in some embodiments, a slit 411 may be formed in the third substrate 410. For example, the slit 411 may be formed at a specific position of the external pad bonding area PA. For example, as shown in area "D", when viewed in a plan view, the slit 411 may be located between the second input / output pad 405 and the cell contact plug 440. Alternatively, when viewed in a plan view, the second input / output pad 405 may be located between the slit 411 and the cell contact plug 440.

[0187] In some embodiments, as shown in region "D1", slits 411 may be formed to penetrate the third substrate 410. For example, when forming the opening 408, the slits 411 may be used to prevent the third substrate 410 from being slightly cracked. However, embodiments of the inventive concept are not limited thereto, and in certain embodiments, the slits 411 may be formed to have a depth in the range of about 60% to about 70% of the thickness of the third substrate 410.

[0188] In a specific embodiment, as shown in region "D2", a conductive material 412 may be formed in the slit 411. For example, the conductive material 412 may be used to discharge leakage current occurring when driving the circuit elements in the external pad bonding region PA to the outside. In this case, the conductive material 412 may be connected to an external ground line.

[0189] In a specific embodiment, as shown in the region "D3", the insulating material 413 may be formed in the slit 411. For example, the insulating material 413 may be used to electrically isolate the second input / output pad 405 and the second input / output contact plug 403 disposed in the external pad bonding region PA from the word line bonding region WLBA. Since the insulating material 413 is formed in the slit 411, it is possible to prevent the voltage provided through the second input / output pad 405 from affecting the metal layer on the third substrate 410 disposed in the word line bonding region WLBA.

[0190] On the other hand, in certain embodiments, the first to third input / output pads 205, 405, and 406 may be selectively formed. For example, the memory device 500 may be implemented to include only the first input / output pad 205 disposed on the first substrate 210, only the second input / output pad 405 disposed on the third substrate 410, or only the third input / output pad 406 disposed on the upper insulating layer 401.

[0191] In some embodiments, at least one of the second substrate 310 of the first cell region CELL1 and the third substrate 410 of the second cell region CELL2 may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. Additional layers may be stacked after the substrate is removed. For example, the second substrate 310 of the first cell region CELL1 may be removed before or after the bonding process of the peripheral circuit region PERI and the first cell region CELL1, and then, an insulating layer covering the top surface of the common source line 320 or a conductive layer for connection may be formed. Similarly, the third substrate 410 of the second cell region CELL2 may be removed before or after the bonding process of the first cell region CELL1 and the second cell region CELL2, and then, an upper insulating layer 401 covering the top surface of the common source line 420 or a conductive layer for connection may be formed.

[0192] The page buffer circuit and the control circuit according to example embodiments may be provided Fig.18 According to an embodiment of the present disclosure, a plurality of page buffer units can be connected in series to a combined readout node through a transfer transistor without requiring a plurality of metal patterns for connecting the plurality of page buffer units and the combined readout node. Fig.18 The above-mentioned multiple metal patterns may not be implemented in the structural diagram shown.

[0193] Fig.19 is a block diagram illustrating an example of applying a memory device to a solid state drive (SSD) system 600 according to an embodiment.

[0194] Reference Fig.19, the SSD system 600 may include a host 610 and an SSD 620. The SSD 620 exchanges a signal SIG with the host 610 through a signal connector, and receives power PWR through a power connector. The SSD 620 may include an SSD controller 621, an auxiliary power supply 622, and memory devices (MEM) 623 to 625. The memory devices 623 to 625 may be vertically stacked NAND flash memory devices. In this case, the SSD 620 may be configured to be a memory device that is ... Figures 1 to 18 The described embodiment is implemented. That is, each of the memory devices 623 to 625 included in the SSD 620 may include a page buffer controller that controls the page buffer operation. In addition, in an embodiment, at least one memory device and the SSD controller 621 may constitute a memory system.

[0195] The foregoing exemplary embodiments are merely exemplary and should not be construed as limiting. The present teachings can be easily applied to other types of devices. In addition, the description of the exemplary embodiments is intended to be illustrative rather than limiting the scope of the claims, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A memory device, comprising: a memory cell array comprising a plurality of memory cells; a page buffer circuit including first to Nth page buffers connected to the plurality of memory cells through bit lines and classified into a first group and a second group, wherein N is an integer greater than or equal to 2; and control logic configured to control first to N page buffer operations on the first to N page buffers in association with a program or read operation of data, and The control logic is further configured to: In a page buffer operation of the page buffer belonging to the first group, a precharge period and a discharge period for a readout node in the first group are performed, and a readout operation is omitted; and In the page buffer operation of the page buffer belonging to the second group, a precharge period and a discharge period for a readout node in the second group are performed, and a readout period in which readout nodes belonging to the first group and the second group are read out together is performed.

2. The memory device according to claim 1, wherein: Among the first to N-th page buffers, the first to A-th page buffers are classified into the first group, and (A+1)-th page buffers to the N-th page buffers are classified into the second group, wherein A is an integer less than N, The control logic is further configured to control the first buffer operation to the Nth page buffer operation, so that in the first page buffer operation, a precharge period and a discharge period for a first readout node of the first page buffer are performed, and in the (A+1)th page buffer operation, a precharge period and a discharge period for an (A+1)th readout node of the (A+1)th page buffer are performed, In the first page buffer operation, the read operation on the first read node is omitted, and in the read period of the (A+1)th page buffer operation, the read operations on the first read node and the (A+1)th read node are performed together.

3. The memory device according to claim 2, wherein: During the read period of the (A+1)th page buffer operation, data according to the voltage level of the first read node is stored in the read latch of the first page buffer, and data according to the voltage level of the (A+1)th read node is stored in the read latch of the (A+1)th page buffer.

4. The memory device according to claim 1, wherein: Among the first to N-th page buffers, the first to A-th page buffers are classified into the first group, and (A+1)-th page buffers to the N-th page buffers are classified into the second group, wherein A is an integer less than N, and Here, a discharge period during which the (A+1)th page buffer operates is set to be shorter than a discharge period during which the first page buffer operates.

5. The memory device according to claim 1, wherein: Each of the first to Nth page buffers includes a page buffer unit including one or more master latches, a cache unit including a cache latch connected to the page buffer unit through a combined read node, and at least one pass transistor configured to control an electrical connection with a read node of an adjacent page buffer, The page buffer units of the first to N-th page buffers are arranged in a first direction, and the cache units of the first to N-th page buffers are arranged in the first direction in a region separated from the page buffer units.

6. The memory device according to claim 5, wherein: The first group includes the first to fourth page buffers, and the second group includes the fifth to eighth page buffers, The transfer transistors of the first group of page buffers are controlled by a first transfer control signal, and the transfer transistors of the second group of page buffers are controlled by a second transfer control signal, In a precharge period and a discharge period of the first page buffer operation, the first transfer control signal and the second transfer control signal are set to an enable level to establish electrical connections between all readout nodes of the first page buffer to the Nth page buffer, and In a precharge period and a discharge period of the fifth page buffer operation, the second transfer control signal is selectively set to an enable level to establish an electrical connection only between readout nodes of the page buffers included in the second group.

7. The memory device according to claim 6, wherein: In the precharge period and the discharge period of the fifth page buffer operation, a precharge operation and a discharge operation are selectively performed on the readout nodes of the page buffers included in the second group.

8. The memory device according to claim 6, wherein: In a readout period of the fifth to eighth page buffer operations, the first and second transfer control signals are set to a disable level to establish electrical isolation between readout nodes in the first to eighth page buffers.

9. The memory device according to claim 6, wherein: After the fifth page buffer operation is completed, a second page buffer operation and a sixth page buffer operation on the second page buffer and the sixth page buffer, a third page buffer operation and a seventh page buffer operation on the third page buffer and the seventh page buffer, and a fourth page buffer operation and an eighth page buffer operation on the fourth page buffer and the eighth page buffer are sequentially performed, and In the second to fourth page buffer operations, the readout period is omitted.

10. The memory device according to claim 9, wherein: In a readout period of the sixth to eighth page buffer operations, readout operations of readout nodes of the page buffers belonging to the first group and readout nodes of the page buffers belonging to the second group are performed together.

11. A method of operating a memory device, in, The memory device includes first to fourth page buffers belonging to a first group and fifth to eighth page buffers belonging to a second group, each of the first to eighth page buffers including a page buffer unit including a read node and a cache unit including a cache latch, The page buffer units of the first to eighth page buffers are arranged in a first direction, and the cache units of the first to eighth page buffers are connected to the page buffer units through combined readout nodes and are arranged in the first direction in a region separated from the page buffer units, The operation method comprises: electrically connecting the first page buffer to a readout node of the eighth page buffer during a precharge period of a first page buffer operation on the first page buffer of the first group; discharging a first readout node of the first page buffer according to data stored in a cache latch of the first page buffer during a discharge period of the first page buffer operation; Omitting a read operation on the first read node and floating the first read node by isolating an electrical connection between the first page buffer and a read node in the eighth page buffer; electrically connecting the fifth page buffer to a readout node of the eighth page buffer during a precharge period of the fifth page buffer operation of the second group; discharging a fifth sensing node of the fifth page buffer according to data stored in a cache latch of the fifth page buffer during a discharge period of the fifth page buffer operation; and In a readout period of the fifth page buffer operation, a readout operation for reading out voltage levels of the first and fifth readout nodes is performed together.

12. The operating method according to claim 11, further comprising: sequentially performing a second page buffer operation and a sixth page buffer operation on the second page buffer and the sixth page buffer; sequentially performing a third page buffer operation and a seventh page buffer operation on the third page buffer and the seventh page buffer; sequentially performing a fourth page buffer operation and an eighth page buffer operation on the fourth page buffer and the eighth page buffer; In the second page buffer operation to the fourth page buffer operation, omitting a readout period; and In a readout period of the sixth to eighth page buffer operations, readout operations on readout nodes of two page buffers are performed together.

13. The operating method according to claim 11, wherein: Each of the first to eighth page buffers includes at least one transfer transistor configured to control an electrical connection with a readout node of an adjacent page buffer, the transfer transistors of the first to fourth page buffers are controlled by a first transfer control signal, and the transfer transistors of the fifth to eighth page buffers are controlled by a second transfer control signal, and In a precharge period and a discharge period of the first page buffer operation, the first transfer control signal and the second transfer control signal are set to an enable level to establish electrical connections between all readout nodes of the first to eighth page buffers.

14. The operating method according to claim 13, wherein: In a precharge period and a discharge period of the fifth page buffer operation, the second transfer control signal is selectively set to an enable level to establish electrical connection only between readout nodes of the fifth to eighth page buffers.

15. The operating method according to claim 11, wherein: A discharge period during which the fifth page buffer operates is set to be shorter than a discharge period during which the first page buffer operates.

16. The operating method according to claim 11, wherein: The cache latch of the first page buffer is connected to the page buffer unit through a first combined read node and a second combined read node, and the cache latch of the fifth page buffer is connected to the page buffer unit through the second combined read node, and The operating method further includes: precharging the first combined sensing node when the first combined sensing node and the second combined sensing node are electrically connected; and The first combined sense node is discharged according to data stored in the sense latch of the first page buffer.

17. The operating method according to claim 16, further comprising: When the first combined readout node and the second combined readout node are electrically separated, precharging the second combined readout node; discharging the second combined read node according to data stored in the read latch of the fifth page buffer; as well as Data is stored in cache latches of the first and fifth page buffers by performing a read operation on the first and second combined read nodes together.

18. A memory device comprising: a memory cell array comprising a plurality of memory cells; a page buffer circuit including first to Nth page buffers connected to the plurality of memory cells through bit lines; as well as a control logic configured to control first to N page buffer operations on the first to N page buffers in association with a program or read operation of data, wherein the first to Nth page buffers are classified into a first group to a Kth group, and K is an integer less than N, and The control logic is further configured to: in a page buffer operation of the page buffers belonging to the first to (K-1)th groups, performing a precharge period and a discharge period for a readout node and omitting a readout operation; as well as In the page buffer operation of the page buffers belonging to the Kth group, a precharge period and a discharge period for a readout node are performed, and a readout period such that the readout nodes of the page buffers belonging to the first to Kth groups are read out together is performed.

19. The memory device of claim 18, wherein: The first to Nth page buffers are classified into first to fourth groups, In the page buffer operation of the page buffers belonging to the first to third groups, the read operation is omitted, and In the read operation of the page buffer operation of the page buffer belonging to the fourth group, the read nodes of the first to fourth groups are read out together.

20. The memory device of claim 18, wherein: In a precharge period of the first group to the (K-1)th group, a readout node of a page buffer belonging to a group in which precharge is performed is electrically connected to a readout node of a page buffer belonging to the Kth group, and In the precharge period of the Kth group, electrical connection between the readout nodes of the page buffers belonging to the Kth group and the readout nodes of the page buffers belonging to the first to (K-1)th groups is cut off.

Images