Voltage stabilizing circuit and memory

Abstract

The present disclosure provides a voltage stabilizing circuit and a memory. The voltage stabilizing circuit includes a first operational amplifier circuit and a second operational amplifier circuit. The first operational amplifier circuit is connected to the second operational amplifier circuit, and an enabling module is provided on the path of the second operational amplifier circuit, wherein: the enabling module is used to control the path of the second operational amplifier circuit to be in an off state according to a control signal when the voltage stabilizing circuit is in a non-enable mode; the first operational amplifier circuit includes an input circuit and a load circuit, and the input circuit is connected to the load circuit; the first operational amplifier circuit is used to control the input transistor in the input circuit and the load transistor in the load circuit to be in an off state when in the non-enable mode, and the first voltage at the connection between the input circuit and the load circuit meets a preset voltage range; thereby, while avoiding the risk of breakdown of the input transistor, the number of transistors in the voltage stabilizing circuit can be reduced, thereby achieving the purpose of reducing current loss and saving area.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a voltage stabilizing circuit and a memory. Background Art

[0002] With the widespread application of electronic technology, higher performance requirements are being placed on electronic systems. A voltage stabilizer is a power supply circuit or device that automatically adjusts the output voltage. Its function is to stabilize a power supply voltage that fluctuates widely or falls short of the requirements of an electrical device within a preset range, allowing various circuits or electrical devices to operate normally at the rated operating voltage.

[0003] In dynamic random access memory (DRAM), most voltage regulators require additional metal oxide semiconductor field effect transistors (MOSFETs, or MOS transistors for short) to protect the original circuit in disable mode to ensure stable shutdown of the circuit. This results in an increase in the number of MOSFETs in the circuit, which not only increases current loss but also increases the circuit area of ​​the voltage regulator. Summary of the Invention

[0004] Embodiments of the present disclosure provide a voltage stabilization circuit and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides a voltage stabilizing circuit, the voltage stabilizing circuit including a first operational amplifier circuit and a second operational amplifier circuit, the first operational amplifier circuit being connected to the second operational amplifier circuit, and an enabling module being provided on a path of the second operational amplifier circuit, wherein:

[0006] An enabling module, configured to control the path of the second operational amplifier circuit to be in an off state according to a control signal when the voltage stabilizing circuit is in a non-enabling mode;

[0007] The first operational amplifier circuit includes an input circuit and a load circuit, and the input circuit is connected to the load circuit; the first operational amplifier circuit is used to control the input transistor in the input circuit and the load transistor in the load circuit to be in an off state in a non-enabled mode, and a first voltage at the connection between the input circuit and the load circuit meets a preset voltage range.

[0008] In some embodiments, the enabling module includes a first transistor, and the first transistor is a PMOS transistor.

[0009] In some embodiments, the voltage stabilization circuit further includes an inverting circuit, wherein:

[0010] The inverting circuit is used for receiving the enable signal and performing a non-logical operation on the enable signal to generate a control signal.

[0011] In some embodiments, if the voltage stabilization circuit is in the enable mode, it is determined that the control signal is in the first level state and the enable signal is in the second level state;

[0012] If the voltage stabilizing circuit is in the disabled mode, it is determined that the control signal is in the second level state and the enable signal is in the first level state.

[0013] In some embodiments, the second op amp circuit includes a first sub-op amp circuit, the first sub-op amp circuit includes an enable module, a second transistor, and a third transistor, wherein:

[0014] A first terminal of the second transistor is connected to the power supply voltage, a second terminal of the second transistor is connected to the first terminal of the enabling module, and a control terminal of the second transistor is connected to the first node;

[0015] The second end of the enabling module is connected to the first end of the third transistor and the control end of the third transistor respectively, and the control end of the enabling module is used to receive a control signal;

[0016] The second terminal of the third transistor is connected to the ground voltage, and the control terminal of the third transistor is also connected to the second node.

[0017] In some embodiments, the second operational amplifier circuit further includes a second sub-op-amp circuit, and the second sub-op-amp circuit includes a fourth transistor and a fifth transistor, wherein:

[0018] a first terminal of the fourth transistor connected to the power supply voltage, a second terminal of the fourth transistor connected to the first terminal of the fifth transistor, and a control terminal of the fourth transistor connected to the third node;

[0019] The second terminal of the fifth transistor is connected to the ground voltage, and the control terminal of the fifth transistor is connected to the second node.

[0020] In some embodiments, in the load circuit, the load transistor includes a sixth transistor and a seventh transistor, wherein:

[0021] The first terminal of the sixth transistor and the first terminal of the seventh transistor are both connected to the power supply voltage, the control terminal of the sixth transistor and the second terminal of the sixth transistor are both connected to the first node, and the second terminal of the sixth transistor is further connected to the input circuit;

[0022] The control terminal of the seventh transistor and the second terminal of the seventh transistor are both connected to the third node, and the second terminal of the seventh transistor is also connected to the input circuit.

[0023] In some embodiments, the input circuit includes an input transistor, an eighth transistor, and a ninth transistor, and the input transistor includes a tenth transistor and an eleventh transistor, wherein:

[0024] a first terminal of the tenth transistor being connected to the second terminal of the sixth transistor, a first terminal of the eleventh transistor being connected to the second terminal of the seventh transistor, and a second terminal of the tenth transistor and a second terminal of the eleventh transistor being both connected to the first terminal of the eighth transistor;

[0025] The second terminal of the eighth transistor is connected to the first terminal of the ninth transistor, and the second terminal of the ninth transistor is connected to the ground voltage;

[0026] The control end of the ninth transistor and the control end of the tenth transistor are both used to receive an input voltage, the control end of the eighth transistor is used to receive an enable signal, and the control end of the eleventh transistor is used to receive a feedback voltage.

[0027] In some embodiments, the voltage stabilizing circuit further includes a pull-down circuit connected to the second node, wherein:

[0028] The pull-down circuit is used to pull down the potential of the second node to the ground voltage.

[0029] In some embodiments, the pull-down circuit includes a twelfth transistor, wherein:

[0030] A first terminal of the twelfth transistor is connected to the second node, a second terminal of the twelfth transistor is connected to the ground voltage, and a control terminal of the twelfth transistor is used to receive a control signal;

[0031] The pull-down circuit is used to control the twelfth transistor to be in a conducting state according to a control signal when the voltage stabilizing circuit is in a non-enabled mode, so as to pull the potential of the second node down to the ground voltage.

[0032] In some embodiments, the voltage stabilizing circuit further includes a pull-up circuit connected to the fourth node, wherein:

[0033] The pull-up circuit is used to pull up the potential of the fourth node to the power supply voltage.

[0034] In some embodiments, the pull-up circuit includes a thirteenth transistor, wherein:

[0035] A first terminal of the thirteenth transistor is connected to the power supply voltage, a second terminal of the thirteenth transistor is connected to the fourth node, and a control terminal of the thirteenth transistor is used to receive an enable signal;

[0036] The pull-up circuit is used to control the thirteenth transistor to be in a conducting state according to an enable signal when the voltage stabilizing circuit is in a non-enable mode, so as to pull up the potential of the fourth node to the power supply voltage.

[0037] In some embodiments, the voltage stabilization circuit further includes an output circuit, and the output circuit includes a fourteenth transistor and a resistor voltage divider module, wherein:

[0038] A first terminal of the fourteenth transistor is connected to the power supply voltage, a second terminal of the fourteenth transistor is connected to the first terminal of the resistance voltage divider module, and a control terminal of the fourteenth transistor is connected to the fourth node;

[0039] The second end of the resistor voltage divider module is connected to the ground voltage, and the third end of the resistor voltage divider module is used to output a feedback voltage.

[0040] In some embodiments, the resistor divider module includes a first resistor and a second resistor, wherein:

[0041] The first end of the first resistor is connected to the second end of the fourteenth transistor;

[0042] The second end of the second resistor is connected to the ground voltage;

[0043] The second end of the first resistor is connected to the first end of the second resistor and is used to output a feedback voltage.

[0044] In a second aspect, an embodiment of the present disclosure provides a memory, the memory including a voltage stabilizing circuit as described in any one of the first aspects.

[0045] An embodiment of the present disclosure provides a voltage stabilization circuit and a memory, the voltage stabilization circuit comprising a first operational amplifier circuit and a second operational amplifier circuit, the first operational amplifier circuit being connected to the second operational amplifier circuit, and an enabling module being provided on the path of the second operational amplifier circuit. The enabling module is configured to control the path of the second operational amplifier circuit to be in an off state according to a control signal when the voltage stabilization circuit is in a non-enable mode; the first operational amplifier circuit comprises an input circuit and a load circuit, the input circuit being connected to the load circuit; the first operational amplifier circuit is configured to control the input transistor in the input circuit and the load transistor in the load circuit to be in an off state when in the non-enable mode, and the first voltage at the connection between the input circuit and the load circuit satisfies a preset voltage range. In this way, for the voltage stabilizing circuit, in the non-enable mode, the path of the second operational amplifier circuit is in a disconnected state through the enabling module, and the input transistor in the input circuit and the load transistor in the load circuit are both in a turned-off state, thereby ensuring that the entire circuit is stably shut down; in addition, since the first voltage at the connection between the input circuit and the load circuit meets the preset voltage range, while avoiding the risk of breakdown of the input transistor, the number of transistors in the voltage stabilizing circuit can also be reduced; in this way, in the non-enable mode, the voltage stabilizing circuit can reduce current loss, improve memory performance, and save area. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 1. It is a schematic diagram of the composition structure of a voltage stabilizing circuit;

[0047] Figure 2 A schematic diagram of the structure of a voltage stabilizing circuit provided in an embodiment of the present disclosure Figure 1 ;

[0048] Figure 3 A schematic diagram of the structure of an inverting circuit provided in an embodiment of the present disclosure;

[0049] Figure 4 A schematic diagram of the structure of a voltage stabilizing circuit provided in an embodiment of the present disclosure Figure 2 ;

[0050] Figure 5 A schematic diagram of the structure of a voltage stabilizing circuit provided in an embodiment of the present disclosure Figure 3 ;

[0051] Figure 6 A schematic diagram of the structure of a voltage stabilizing circuit provided in an embodiment of the present disclosure Figure 4 ;

[0052] Figure 7 A detailed structural diagram of a voltage stabilizing circuit provided in an embodiment of the present disclosure;

[0053] Figure 8 A signal timing diagram provided in an embodiment of the present disclosure;

[0054] Figure 9 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are merely for explaining the related applications and are not intended to limit the present disclosure. It should also be noted that, for ease of description, only the portions relevant to the related applications are shown in the drawings.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0057] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0058] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0059] Before further explaining the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0060] Dynamic Random Access Memory (DRAM);

[0061] Metal Oxide Semiconductor Field Effect Transistor (MOSFET or MOS tube for short);

[0062] Positive channel Metal Oxide Semiconductor field effect transistor (PMOS transistor);

[0063] N-type metal oxide semiconductor field effect transistor (NMOS tube);

[0064] Transistor (Tr);

[0065] millivolt (mV);

[0066] Microampere (μA).

[0067] As you can understand, a voltage regulator is a circuit that maintains a relatively constant output voltage despite fluctuations in the input voltage or changes in the load. The purpose of a voltage regulator is to maintain a constant output voltage, providing the desired stable output voltage regardless of changes in the input voltage or load conditions. Electronic circuits rely on voltage regulators because they require a stable voltage supply to avoid damage.

[0068] In DRAM, the voltage regulator's disable mode typically requires forcing some key nodes to shut down to ensure a stable circuit. This requires additional MOSFETs to protect the original circuit, increasing the number of MOSFETs and leakage paths in the circuit. Therefore, in the disclosed embodiments, by rationally selecting MOSFETs for additional protection, the number of MOSFETs and leakage paths can be reduced.

[0069] For example, Figure 1 The figure is a schematic diagram of the structure of a voltage stabilizing circuit. Figure 1 As shown, the voltage stabilizing circuit 10 may include an enabling logic circuit, a gate voltage circuit and a voltage stabilizing circuit.

[0070] exist Figure 1 In the figure, (a) is an enable logic circuit, which may include a NOT gate NOT1, whose input terminal is used to receive an enable signal (EN), and whose output terminal is used to output a control signal (ENB). (b) is a gate voltage circuit, which includes a first resistor RA, a second resistor RB, a third resistor RC, and a transistor MN4, wherein a first end of the first resistor RA is connected to a power supply voltage VPPEX, a second end of the first resistor RA is connected to a first end of the second resistor RB, a second end of the second resistor RB is connected to a first end of the third resistor RC, a second end of the third resistor RC is connected to a first end (i.e., a drain) of the transistor MN4, and a second end (i.e., a source) of the transistor MN4 is grounded. The connection point between the first resistor RA and the second resistor RB is used to output a VLS signal, and the control end (i.e., a gate) of the transistor MN4 is used to receive an EN signal. (c) is a voltage stabilization circuit, which includes transistors MP1-MP8, MN1-MN3, MN5-MN8, NTN1, NTN2, a fourth resistor RD, and a fifth resistor RE. These components together constitute a two-stage operational amplifier circuit. Transistor MP6 to the right of node A1, transistor MP7 to the left of node A2, and the path between these two transistors constitute a first-stage operational amplifier 131. Transistor MP4 to the left of node A1, transistor MP5 to the right of node A2, and the path between these two transistors constitute a second-stage operational amplifier 132. In other words, transistors MP6, MP7, MN1, MN2, NTN1, NTN2, MN7, and MN8 constitute a first-stage operational amplifier circuit 131, and transistors MP4, MN5, MP5, and MN6 constitute a second-stage operational amplifier circuit 132. Furthermore, transistors NTN1 and NTN2 represent N-type doped thin-oxide MOS transistors.

[0071] It should be noted that in the secondary operational amplifier circuit used in DRAM, the relevant technology often adopts a combination of four transistors, namely MP1, MP2, MP3 and MN3 in (c), and ensures that nodes A1, A2 and A3 are forced to be high level (i.e., VPPEX voltage), and node A4 is low level (i.e., ground voltage). Therefore, through this combination of four transistors, it is ensured that the transistors (i.e., MP4~MP7, MP8 and MN5~MN6) connected to these key nodes (i.e., node A1, node A2, node A3 and node A4) are all in the off state, and at the same time, the tail current source circuit composed of transistors MN7 and MN8 is in the closed state, so that the voltage stabilization circuit 10 can achieve the purpose of saving current in the non-enabled mode.

[0072] However, in voltage regulator circuit 10, the input transistors are a pair of thin-oxide NMOS transistors (including NTN1 and NTN2). Because the drains of NTN1 and NTN2 are at risk of breakdown when nodes A1 and A2 are forced to the power supply voltage VPPEX, a pair of NMOS transistors (including MN1 and MN2) with gates biased to protect NTN1 and NTN2 are configured. The control terminals (i.e., gates) of MN1 and MN2 are both connected to the VLS signal output from (b). This adds a gate voltage circuit to the DRAM, increasing the area of ​​voltage regulator circuit 10. Therefore, while ensuring device reliability, it is also necessary to reduce the area of ​​the voltage regulator circuit.

[0073] Based on this, an embodiment of the present disclosure provides a voltage stabilizing circuit, which includes a first operational amplifier circuit and a second operational amplifier circuit, wherein the first operational amplifier circuit is connected to the second operational amplifier circuit; wherein the first operational amplifier circuit includes an input circuit and a load circuit, and an enabling module is provided on the path of the second operational amplifier circuit. In this way, for the voltage stabilizing circuit, in the non-enabling mode, the path of the second operational amplifier circuit is in a disconnected state through the enabling module, and the input transistor in the input circuit and the load transistor in the load circuit are both in a turned-off state, thereby ensuring that the entire circuit is stably shut down; in addition, since the first voltage at the connection between the input circuit and the load circuit meets the preset voltage range, while avoiding the risk of breakdown of the input transistor, the number of transistors in the voltage stabilizing circuit can also be reduced; in this way, in the non-enabling mode, the voltage stabilizing circuit can reduce current loss, improve memory performance, and save area.

[0074] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0075] In one embodiment of the present disclosure, see Figure 2 , which shows a schematic diagram of the composition structure of a voltage stabilizing circuit provided by an embodiment of the present disclosure Figure 1 .like Figure 2As shown, the voltage stabilizing circuit 20 may include a first operational amplifier circuit 21 and a second operational amplifier circuit 22. The first operational amplifier circuit 21 is connected to the second operational amplifier circuit 22, and an enabling module U1 is provided on the path of the second operational amplifier circuit 22, wherein:

[0076] The enabling module U1 is used to control the path of the second operational amplifier circuit 22 to be in an off state according to the control signal when the voltage stabilizing circuit 20 is in a non-enable mode;

[0077] The first operational amplifier circuit 21 includes an input circuit 211 and a load circuit 212, and the input circuit 211 is connected to the load circuit 212; the first operational amplifier circuit 21 is used to control the input transistor in the input circuit 211 and the load transistor in the load circuit 212 to be in the off state when in the non-enabled mode, and the first voltage at the connection point between the input circuit 211 and the load circuit 212 meets the preset voltage range.

[0078] It should be noted that the voltage stabilizing circuit 20 provided in the embodiments of the present disclosure can be used as a voltage regulator in a DRAM, and more specifically, as a two-stage op amp voltage regulator. Here, a circuit design is provided to reduce the current loss of the two-stage op amp voltage regulator in the disabled mode. Thus, through the proper design of the voltage stabilizing circuit 20, the risk of breakdown of the input transistors can be avoided while also not increasing the number of transistors. Thus, in the disabled mode, current loss can be reduced and circuit area can be saved.

[0079] It should also be noted that, in the embodiment of the present disclosure, the first operational amplifier circuit 21 can be a differential amplifier circuit, which is used to provide high gain and can effectively suppress the interference of common-mode signals; the second operational amplifier circuit 22 can provide a larger output swing for the voltage stabilization circuit 20 and further improve the gain.

[0080] It should also be noted that in the embodiment of the present disclosure, the non-enable mode can be expressed as Disable mode, that is, a mode that can stop the voltage stabilizing circuit 20 from working and ensure that the voltage stabilizing circuit 20 is stably shut down; in addition, the enable mode can be expressed as Enable mode, that is, a mode that can enable the voltage stabilizing circuit 20 to work normally.

[0081] It should also be noted that, in the embodiment of the present disclosure, the first voltage at the connection point between the input circuit 211 and the load circuit 212 needs to meet the preset voltage range. Figure 1 The drain voltage of the input transistor in the voltage regulator circuit 10 is compared with Figure 2The drain voltage of the input transistor will decrease, that is, the source-drain voltage drop of the input transistor in the input circuit 211 becomes smaller, so that the breakdown risk of the input transistor is greatly reduced. As a result, the pair of NMOS transistors (MN1 and MN2) configured by the voltage regulator circuit 10 are no longer needed for protection, and the gate voltage circuit for providing drive signals to MN1 and MN2 is no longer needed.

[0082] In short, the embodiment of the present disclosure provides a voltage stabilizing circuit 20 based on a two-stage operational amplifier. Specifically, a new non-enabling logic is adopted (including: controlling the path of the second operational amplifier circuit 22 to be in an off state, and controlling the input transistor in the input circuit 211 and the load transistor in the load circuit 212 to be in an off state, and the first voltage at the connection between the input circuit 211 and the load circuit 212 satisfies a preset voltage range, etc.). This not only avoids the risk of breakdown of the input transistor and improves memory performance, but also reduces the number of transistors and leakage paths in the voltage stabilizing circuit 20, thereby achieving the purpose of saving area.

[0083] Here, the enabling module U1 may include one transistor, or may include multiple transistors, such as a combination of at least two transistors. In addition, the transistor here may be a PMOS transistor or an NMOS transistor, which is not specifically limited.

[0084] It can be understood that for the enabling module U1, the control terminal of the enabling module U1 is used to receive a control signal. Specifically, when the enabling module U1 uses a PMOS transistor to control the path of the second operational amplifier circuit 22 to be disconnected, the control signal is in a high-level state, thereby disconnecting the path of the second operational amplifier circuit 22; when the enabling module U1 uses an NMOS transistor to control the path of the second operational amplifier circuit 22 to be disconnected, the control signal is in a low-level state, thereby disconnecting the path of the second operational amplifier circuit 22.

[0085] Specifically, in some embodiments, the enabling module U1 includes a first transistor P1 , and the first transistor P1 is a PMOS transistor.

[0086] That is, in the embodiment of the present disclosure, the gate of the first transistor P1 can serve as the control terminal of the enabling module U1 to receive the control signal, and control the path of the second operational amplifier circuit to be in an off state according to the control signal.

[0087] In some embodiments, see Figure 3 , the voltage stabilizing circuit may further include an inverting circuit 23, wherein:

[0088] The inverting circuit 23 is configured to receive the enable signal and perform a non-logical operation on the enable signal to generate a control signal.

[0089] It should be noted that in the embodiment of the present disclosure, the enable signal can be represented by EN and the control signal can be represented by ENB. Here, the enable signal is inverted by the inverting circuit 23 to generate the control signal, so that in the non-enable mode, the path of the second operational amplifier circuit 22 can be controlled to be in an off state according to the control signal.

[0090] Furthermore, in some embodiments, Figure 3 As shown, the inverting circuit 23 may include a first NOT gate 231, wherein:

[0091] The input end of the first NOT gate 231 is used to receive the enable signal, and the output end of the first NOT gate 231 is used to output the control signal. In other words, the first NOT gate 231 performs a NOT logic operation on the enable signal to obtain the control signal.

[0092] It should also be noted that in the embodiment of the present disclosure, the inverting circuit 23 here is the enable logic circuit in the voltage stabilizing circuit 10, which is mainly used to convert the enable signal into a control signal to control the path of the second operational amplifier circuit to be in an off state.

[0093] It should also be noted that, in the embodiment of the present disclosure, the inverting circuit 23 may include an odd number of first NOT gates 231, for example Figure 3 The number of the first NOT gate 231 may also be one, or multiple, such as 3, 5, or 7, which is not specifically limited.

[0094] In some embodiments, if the voltage stabilization circuit is in the enable mode, it is determined that the control signal is in the first level state and the enable signal is in the second level state;

[0095] If the voltage stabilizing circuit is in the disabled mode, it is determined that the control signal is in the second level state and the enable signal is in the first level state.

[0096] It should be noted that in the embodiment of the present disclosure, the first level state can be a low level state, and the second level state can be a high level state; or, the first level state can be a high level state, and the second level state can be a low level state, and there is no specific limitation on this.

[0097] That is to say, for the control signal and the enable signal, there can be two level states: high level and low level. Among them, taking the first level state as the low level state and the second level state as the high level state as an example, when the control signal is in the high level state and the enable signal is in the low level state, the voltage stabilizing circuit 20 is in the non-enabled mode (also referred to as the "off state" or "non-working state"); when the control signal is in the low level state and the enable signal is in the high level state, the voltage stabilizing circuit 20 is in the enabled mode (also referred to as the "working state"). In this way, when the voltage stabilizing circuit 20 is in different modes, the control signal and the enable signal are in different level states respectively, so that according to the control signal and the enable signal in different level states, the voltage stabilizing circuit 20 can be controlled to be in the working state or in the non-working state.

[0098] In some embodiments, see Figure 4 For the second operational amplifier circuit, the second operational amplifier circuit may include a first sub-operational amplifier circuit 221, and the first sub-operational amplifier circuit 221 includes an enabling module U1, a second transistor P2, and a third transistor N1, wherein:

[0099] A first terminal of the second transistor P2 is connected to the power supply voltage, a second terminal of the second transistor P2 is connected to the first terminal of the enabling module U1, and a control terminal of the second transistor P2 is connected to the first node A1;

[0100] The second end of the enabling module U1 is connected to the first end of the third transistor N1 and the control end of the third transistor N1 respectively, and the control end of the enabling module U1 is used to receive a control signal;

[0101] A second terminal of the third transistor N1 is connected to the ground voltage, and a control terminal of the third transistor N1 is further connected to the second node A4.

[0102] It should be noted that in the embodiment of the present disclosure, VPPEX represents the power supply voltage (also referred to as the "power supply terminal"), which is used to provide a high-level signal. In this embodiment, the high level refers to logic "1". In addition, VSS represents the ground voltage (also referred to as the "ground terminal"), which is used to provide a low-level signal. In this embodiment, the low level refers to logic "0".

[0103] It should also be noted that, in the embodiment of the present disclosure, the second transistor P2 may be a PMOS transistor, and the third transistor N1 may be an NMOS transistor. Thus, if the second transistor P2 is a PMOS transistor and the third transistor N1 is an NMOS transistor, then the first end of the second transistor P2 may be a source electrode connected to the power supply voltage; the second end of the second transistor P2 may be a drain electrode connected to the first end of the enable module P1; the control end of the second transistor P2 may be a gate electrode connected to the first node A1; the first end of the third transistor N1 may be a drain electrode connected to the second end of the enable module U1; the second end of the third transistor N1 may be a source electrode connected to the ground voltage; and the control end of the third transistor N1 may be a gate electrode connected to the second end of the enable module U1.

[0104] It should also be noted that in the disclosed embodiment, the conduction of the enable module U1 can be affected by a control signal, and the level of the control signal can be used to control whether the path of the first sub-op amp circuit 221 in the second op amp circuit is disconnected. When the path of the first sub-op amp circuit 221 is disconnected by the enable module U1, no current flows through the first sub-op amp circuit 221, and the second transistor P2 is in the off state. Therefore, the potential of the first node A1 is VPPEX-Vth, which reduces the source-drain voltage drop of the input transistor and avoids the risk of breakdown. Here, Vth is the threshold voltage of the second transistor P2.

[0105] In some embodiments, for the second operational amplifier circuit, in addition to the first sub-operational amplifier circuit 221, as shown in FIG. Figure 4 As shown, the second operational amplifier circuit may further include a second sub-operational amplifier circuit 222, and the second sub-operational amplifier circuit 222 includes a fourth transistor P3 and a fifth transistor N2, wherein:

[0106] A first terminal of the fourth transistor P3 is connected to the power supply voltage, a second terminal of the fourth transistor P3 is connected to the first terminal of the fifth transistor N2, and a control terminal of the fourth transistor P3 is connected to the third node A2;

[0107] A second terminal of the fifth transistor N2 is connected to the ground voltage, and a control terminal of the fifth transistor N2 is connected to the second node A4.

[0108] It should be noted that in the embodiment of the present disclosure, the fourth transistor P3 may be a PMOS transistor, and the fifth transistor N2 may be an NMOS transistor. Thus, if the fourth transistor P3 is a PMOS transistor and the fifth transistor N2 is an NMOS transistor, then the first terminal of the fourth transistor P3 may be a source electrode connected to the power supply voltage; the second terminal of the fourth transistor P3 may be a drain electrode connected to the first terminal of the fifth transistor N2, i.e., the drain electrode of the fifth transistor N2; the control terminal of the fourth transistor P3 may be a gate electrode connected to the third node A2; the second terminal of the fifth transistor N2 may be a source electrode connected to the ground voltage; and the control terminal of the fifth transistor N2 may be a gate electrode connected to the second node A4.

[0109] It should also be noted that in the embodiment of the present disclosure, when the path of the second sub-op amp circuit 222 is disconnected, no current flows through the second sub-op amp circuit 222, and the fourth transistor P3 is in an off state. Therefore, the potential of the third node A2 is VPPEX-Vth, which reduces the source-drain voltage drop of the input transistor and avoids the risk of breakdown. Here, Vth is the threshold voltage of the fourth transistor P3.

[0110] To sum up, the drain voltage of the input transistor in the input circuit 211 can be expressed as VPPEX-Vth, where VPPEX is the power supply voltage and Vth is the threshold voltage of the second transistor P2 and the fourth transistor P3; it can be understood that the drain voltage of the input transistor in the input circuit 211 is VPPEX-Vth. Compared with the drain voltage VPPEX of the input transistor in the voltage stabilization circuit 10, the drain voltage of the input transistor in the embodiment of the present disclosure becomes smaller, so that the source-drain voltage drop of the input transistor in the input circuit 211 becomes smaller.

[0111] In some embodiments, for the first stage operational amplifier 21, as Figure 4 As shown, in the load circuit 212, the load transistors may include a sixth transistor P4 and a seventh transistor P5, wherein:

[0112] The first end of the sixth transistor P4 and the first end of the seventh transistor P5 are both connected to the power supply voltage, the control end of the sixth transistor P4 and the second end of the sixth transistor P4 are both connected to the first node A1, and the second end of the sixth transistor P4 is also connected to the input circuit 211;

[0113] The control terminal of the seventh transistor P5 and the second terminal of the seventh transistor P5 are both connected to the third node A2 , and the second terminal of the seventh transistor P5 is also connected to the input circuit 211 .

[0114] It should be noted that in the embodiment of the present disclosure, both the sixth transistor P4 and the seventh transistor P5 may be PMOS transistors. Thus, the first terminal of the sixth transistor P4 may be a source electrode connected to the power supply voltage; the second terminal of the sixth transistor P4 may be a drain electrode connected to the first node A1 and the input circuit 211; the control terminal of the sixth transistor P4 may be a gate electrode connected to the first node A1; the first terminal of the seventh transistor P5 may be a source electrode connected to the power supply voltage; the second terminal of the seventh transistor P5 may be a drain electrode connected to the third node A2 and the input circuit; and the control terminal of the seventh transistor P5 may be a gate electrode connected to the third node A2.

[0115] It should also be noted that in the disclosed embodiment, in the disabled mode, when the path of the first-stage operational amplifier 21 is disconnected by the eighth transistor N3 in the input circuit 211, no current flows through the first-stage operational amplifier 21, and the sixth transistor P4 and the seventh transistor P5 are in the off state. Here, the threshold voltage of the sixth transistor P4 and the seventh transistor P5 is also Vth, that is, the threshold voltages of the second transistor P2, the fourth transistor P3, the sixth transistor P4, and the seventh transistor P5 are all the same. In addition, when the paths of the first sub-op amp circuit 221 and the second sub-op amp circuit 222 are disconnected, the potential of the first node A1 and the third node A2 is VPPEX-Vth.

[0116] It should also be noted that, in the embodiment of the present disclosure, the second end of the sixth transistor P4 and the second end of the seventh transistor P5 are both connected to the input circuit 211. Since the first node A1 is connected to the second end of the sixth transistor P4 and the third node A2 is connected to the second end of the seventh transistor P5, that is, the voltage received by the input circuit 211 is VPPEX-Vth.

[0117] In some embodiments, as Figure 4 As shown, the input circuit 211 may include an input transistor, an eighth transistor N3 and a ninth transistor N4, and the input transistor may include a tenth transistor N5 and an eleventh transistor N6, wherein:

[0118] a first end of the tenth transistor N5 is connected to the second end of the sixth transistor P4, a first end of the eleventh transistor N6 is connected to the second end of the seventh transistor P5, and second ends of the tenth transistor N5 and the eleventh transistor N6 are both connected to the first end of the eighth transistor N3;

[0119] The second end of the eighth transistor N3 is connected to the first end of the ninth transistor N4, and the second end of the ninth transistor N4 is connected to the ground voltage;

[0120] The control end of the ninth transistor N4 and the control end of the tenth transistor N5 are both used to receive an input voltage, the control end of the eighth transistor N3 is used to receive an enable signal, and the control end of the eleventh transistor N6 is used to receive a feedback voltage.

[0121] It should be noted that in the embodiments of the present disclosure, VIN represents the input voltage, which may also be referred to as the input node; Vafs represents the feedback voltage, which may also be referred to as the feedback node. The input voltage VIN may be in a low level state or any other voltage, without specific limitation.

[0122] It should also be noted that, in the embodiment of the present disclosure, the eighth transistor N3 and the ninth transistor N4 serve as a tail current source circuit, constituting a current source of the first operational amplifier circuit 21 .

[0123] It should also be noted that in the embodiment of the present disclosure, the eighth transistor N3, the ninth transistor N4, the tenth transistor N5, and the eleventh transistor N6 can all be NMOS transistors. Thus, the first terminal of the tenth transistor N5 can be a drain connected to the second terminal of the sixth transistor P4; the second terminal of the tenth transistor N5 can be a source connected to the first terminal of the eighth transistor N3, that is, the drain of the eighth transistor N3; the control terminal of the tenth transistor N5 can be a gate for receiving an input voltage; the first terminal of the eleventh transistor N6 can be a drain connected to the second terminal of the seventh transistor P5; the second terminal of the eleventh transistor N6 can be a source connected to the first terminal of the eighth transistor N3; the control terminal of the eleventh transistor N6 can be a gate for receiving a feedback voltage; the second terminal of the eighth transistor N3 can be a source connected to the first terminal of the ninth transistor N4, that is, the drain of the ninth transistor N4; the control terminal of the eighth transistor N3 can be a gate for receiving an enable signal; the second terminal of the ninth transistor N4 can be a source connected to the ground voltage; and the control terminal of the ninth transistor N4 can be a gate for receiving an input voltage. In addition, the common source node of the tenth transistor N5 and the eleventh transistor N6 can also be referred to as a Com node.

[0124] It should also be noted that, in the embodiment of the present disclosure, whether the eighth transistor N3 is turned on or off may be affected by the level of the enable signal. Since the enable signal is in a low level state in the non-enable mode, the eighth transistor N3 is in an off state. Thus, in the first operational amplifier circuit 21, there is no current path from the power supply voltage to the ground voltage, and no current flows in the first operational amplifier circuit 21. Therefore, the sixth transistor P4, the seventh transistor P5, the eighth transistor N3, the ninth transistor N4, the tenth transistor N5, and the eleventh transistor N6 are all in an off state.

[0125] It should also be noted that, in the embodiment of the present disclosure, the tenth transistor N5 and the eleventh transistor N6 serve as a pair of input transistors, and the drain voltages of the tenth transistor N5 and the eleventh transistor N6 are both VPPEX-Vth. Figure 1 In other words, the source-drain voltage drop of the tenth transistor N5 and the eleventh transistor N6 becomes smaller. At this time, an additional pair of NMOS transistors with a gate biased at a certain voltage are no longer needed for protection, and a gate voltage circuit is no longer needed, thereby reducing the number of transistors and leakage paths, saving memory area, and reducing current loss.

[0126] In some embodiments, Figure 4 Based on the voltage stabilizing circuit 20 shown, see Figure 5 The voltage stabilizing circuit 20 may further include a pull-down circuit 24 connected to the second node A4. The pull-down circuit 24 is configured to pull down the potential of the second node A4 to the ground voltage.

[0127] Furthermore, in some embodiments, Figure 5 As shown, the pull-down circuit 24 may include a twelfth transistor N7, wherein:

[0128] The first end of the twelfth transistor N7 is connected to the second node A4, the second end of the twelfth transistor N7 is connected to the ground voltage, and the control end of the twelfth transistor N7 is used to receive a control signal; wherein, the pull-down circuit 24 is used to control the twelfth transistor N7 to be in the on state according to the control signal when the voltage stabilizing circuit 20 is in the non-enabled mode, so as to pull the potential of the second node A4 down to the ground voltage.

[0129] It should be noted that in the embodiment of the present disclosure, the twelfth transistor N7 may be an NMOS transistor. Thus, the first terminal of the twelfth transistor N7 may be a drain connected to the second node A4; the second terminal of the twelfth transistor N7 may be a source connected to the ground voltage; and the control terminal of the twelfth transistor N7 may be a gate for receiving a control signal.

[0130] It should also be noted that, in the embodiment of the present disclosure, in the non-enable mode, the control signal is in a high-level state, and the conduction of the twelfth transistor N7 can be affected by the level of the control signal. Therefore, the twelfth transistor N7 is in a conducting state to pull down the potential of the second node A4 to a low level. Since the control terminal of the third transistor N1 and the control terminal of the fifth transistor N2 are both connected to the second node A4, the third transistor N1 and the fifth transistor N2 can be controlled to be in a turned-off state. In addition, when the fifth transistor N2 is in the turned-off state, the path of the second sub-op amp circuit 222 is disconnected.

[0131] In some embodiments, Figure 4 Based on the voltage stabilizing circuit 20 shown, see Figure 6 The voltage stabilizing circuit 20 may further include a pull-up circuit 25 connected to the fourth node A3. The pull-up circuit 25 is configured to pull up the potential of the fourth node A3 to the power supply voltage.

[0132] Furthermore, in some embodiments, Figure 6 As shown, the pull-up circuit 25 may include a thirteenth transistor P6, wherein:

[0133] The first end of the thirteenth transistor P6 is connected to the power supply voltage, the second end of the thirteenth transistor P6 is connected to the fourth node A3, and the control end of the thirteenth transistor P6 is used to receive an enable signal; wherein, the pull-up circuit 25 is used to control the thirteenth transistor P6 to be in the on state according to the enable signal when the voltage stabilizing circuit 20 is in the non-enabled mode, so as to pull up the potential of the fourth node A3 to the power supply voltage.

[0134] It should be noted that in the embodiment of the present disclosure, the thirteenth transistor P6 may be a PMOS transistor. Thus, the first terminal of the thirteenth transistor P6 may be a source connected to the power supply voltage; the second terminal of the thirteenth transistor P6 may be a drain connected to the fourth node A3; and the control terminal of the thirteenth transistor P6 may be a gate for receiving an enable signal.

[0135] It should also be noted that in the embodiment of the present disclosure, in the non-enable mode, the enable signal is in a low level state, and whether the thirteenth transistor P6 is turned on or not may be affected by the level of the enable signal. Therefore, the thirteenth transistor P6 is in a conductive state to pull the potential of the fourth node A3 to a high level.

[0136] In some embodiments, as Figure 6 As shown, the voltage stabilizing circuit 20 may further include an output circuit 26. The output circuit 26 may include a fourteenth transistor P7 and a resistor voltage divider module 261, wherein:

[0137] A first end of the fourteenth transistor P7 is connected to the power supply voltage, a second end of the fourteenth transistor P7 is connected to the first end of the resistor voltage divider module 261, and a control end of the fourteenth transistor P7 is connected to the fourth node A3;

[0138] A second terminal of the resistor voltage divider module 261 is connected to the ground voltage, and a third terminal of the resistor voltage divider module 261 is used to output a feedback voltage.

[0139] It should be noted that in the embodiment of the present disclosure, the fourteenth transistor P7 may be a PMOS transistor. Thus, the first terminal of the fourteenth transistor P7 may be a source connected to the power supply voltage; the second terminal of the fourteenth transistor P7 may be a drain connected to the first terminal of the resistor divider module 261; and the control terminal of the fourteenth transistor P7 may be a gate connected to the fourth node A3.

[0140] It should also be noted that, in the embodiment of the present disclosure, the control end of the fourteenth transistor P7 is connected to the fourth node A3. Since in the non-enabled mode, the pull-up circuit 25 pulls up the potential of the fourth node A3 to the power supply voltage, and whether the fourteenth transistor P7 is turned on or off can be affected by the potential of the fourth node A3, the fourteenth transistor P7 is in the off state. At this time, no current flows through the output circuit 26, thereby ensuring that the entire voltage stabilizing circuit 20 is turned off.

[0141] It should also be noted that, in the embodiment of the present disclosure, the output circuit 26 is used to output the voltage Vafs, and the control end of the eleventh transistor N6 inputs the voltage Vafs as a feedback voltage to the first operational amplifier circuit 21 for feedback regulation to achieve voltage stabilization of the voltage stabilization circuit 20.

[0142] It should also be noted that the resistor voltage divider module 261 may include one resistor or multiple resistors. The number of resistors can be set according to actual needs and is not specifically limited.

[0143] Furthermore, in some embodiments, Figure 6 As shown, the resistor voltage divider module 261 may include a first resistor R1 and a second resistor R2, wherein:

[0144] A first end of the first resistor R1 is connected to a second end of the fourteenth transistor P7;

[0145] The second end of the second resistor R2 is connected to the ground voltage;

[0146] The second end of the first resistor R1 is connected to the first end of the second resistor R2 for outputting a feedback voltage.

[0147] It should be noted that in the embodiment of the present disclosure, the first end of the first resistor R1 serves as the first end of the resistance divider module 261, the second end of the second resistor R2 serves as the second end of the resistance divider module 261, and the node connected between the first resistor R1 and the second resistor R2 serves as the third end of the resistance divider module 261.

[0148] It should also be noted that, in the disclosed embodiment, when the resistor voltage divider module 261 includes multiple resistors, a node of a resistor voltage divider can be selected as an output node, and another node of a resistor voltage divider can be selected as a feedback node. For example, the node connected between the first resistor R1 and the second resistor R2 can be used as a feedback node to obtain a feedback voltage; wherein the output node can be the feedback node connected between the first resistor R1 and the second resistor R2, or the first end of the first resistor R1 can be used as the output node to obtain the output voltage; however, this is not specifically limited.

[0149] That is, in the resistor divider module 261, the output node and the feedback node can be the same node or different nodes, and this is not specifically limited. It is understood that when the output node and the feedback node are the same node, the feedback voltage is the output voltage; when the output node and the feedback node are different nodes, the feedback voltage and the output voltage are proportional.

[0150] In some embodiments, the first transistor P1, the second transistor P2, the fourth transistor P3, the sixth transistor P4, the seventh transistor P5, the thirteenth transistor P6, and the fourteenth transistor P7 are PMOS transistors; the third transistor N1, the fifth transistor N2, the eighth transistor N3, the ninth transistor N4, the tenth transistor N5, the eleventh transistor N6, and the twelfth transistor N7 are NMOS transistors. The type of each transistor can be selected according to actual conditions and is not specifically limited in the embodiments of the present disclosure.

[0151] For the voltage stabilizing circuit 20 , in the disabled mode, different types of transistors can receive different control signals to ensure that the entire voltage stabilizing circuit 20 is stably shut down.

[0152] It should also be noted that the voltage stabilizing circuit 20 and the Figure 1 Compared with the voltage stabilizing circuit 10 shown in the figure, during the power-on process of the external power supply VPPEX, the power supply rising trend remains basically consistent, and the voltage rise of the Vafs node is not affected; and the potential of the Vafs node can reach the preset value, so the voltage stabilizing circuit 20 of the embodiment of the present disclosure will not affect the normal enable mode.

[0153] This embodiment provides a voltage stabilization circuit. In a non-enable mode, an enabling module is used to disconnect the path of the second operational amplifier circuit, and both the input transistor in the input circuit and the load transistor in the load circuit are in an off state, thereby ensuring that the entire circuit is stably shut down. In addition, because the first voltage at the connection point between the input circuit and the load circuit satisfies a preset voltage range, the drain voltage of the input transistor can be made to satisfy the preset voltage range, thereby avoiding the risk of breakdown of the input transistor and reducing the number of transistors in the voltage stabilization circuit. This can reduce current loss, improve memory performance, and save area.

[0154] In another embodiment of the present disclosure, based on the voltage stabilizing circuit 20 in the aforementioned embodiment, the voltage stabilizing circuit 20 is further refined. Figure 7 Detailed structural diagram of a voltage stabilizing circuit provided by an embodiment of the present disclosure. Figure 7 As shown, the voltage stabilizing circuit 30 may include an enabling logic circuit and a voltage stabilizing circuit.

[0155] exist Figure 7 In the figure, (a) is an enabling logic circuit, which includes a NOT gate NOT2, whose input is used to receive an enabling signal (EN), and whose output is used to output a control signal (ENB). (b) is a voltage stabilizing circuit, which is a two-stage operational amplifier circuit, wherein the PMOS transistor MP1 on the right side of the node A1, the PMOS transistor MP2 on the left side of the node A2, and the path where these two PMOS transistors are located are the first-stage operational amplifier circuit 321, and the PMOS transistor MP5 on the left side of the node A1, the PMOS transistor MP6 on the right side of the node A2, and the path where these two PMOS transistors are located are the second-stage operational amplifier circuit 322. That is to say, in Figure 7 In the figure, MP1, MP2, MN4, MN5, MN1 and MN2 constitute a first-stage operational amplifier circuit 321, and MP5, MP4, MN6, MP6 and MN7 constitute a second-stage operational amplifier circuit 322.

[0156] It should be noted that the enabling logic circuit is the inverting circuit 23 in the aforementioned embodiment, and the voltage stabilizing circuit includes the first operational amplifier circuit 21, the second operational amplifier circuit 22, the pull-down circuit 24, the pull-up circuit 25 and the output circuit 26 in the aforementioned embodiment.

[0157] It should also be noted that by using MP4 to cut off the leakage path of the second-stage operational amplifier circuit 322, the potentials of nodes A1 and A2 will be maintained at VPPEX-Vth, thereby reducing the source-drain voltage drop of the input transistors (including MN4 and MN5), and no additional pair of NMOS transistors (i.e., MN1 and MN2 in the voltage regulator circuit 10) is required for protection; at this time, the tail current source remains in the off state, which can ensure that the first-stage operational amplifier circuit 321 (i.e., the six MOS transistors, namely MP1, MP2, MN4, MN5, MN1 and MN2) remains in the off state; in addition, MP4 can also ensure that the second-stage operational amplifier circuit 322 is also in the off state, and at the same time, the potential of the A3 node is pulled up by MP3, so that the entire operational amplifier is in the disabled mode.

[0158] In this way, based on Figure 7 The signal timing of the voltage stabilizing circuit shown in FIG. Figure 8 In the disabled mode, the EN signal is in a low level state and the ENB signal is in a high level state. At this time, MP4 is turned off, while MN3 is turned on so that the potential of the A4 node is pulled to a low level, and MP3 is turned on so that the potential of the A3 node is pulled to a high level.

[0159] In summary, this embodiment provides a voltage stabilizing circuit. Based on the above embodiment, the specific implementation of the aforementioned embodiment is described in detail. It can be seen that the embodiment of the present disclosure is a voltage stabilizing circuit based on a two-stage operational amplifier. A new non-enable logic control is provided here. While avoiding the risk of breakdown of the input transistor, it can not only reduce the number of MOS tubes in the circuit to reduce the area, but also reduce current loss.

[0160] In another embodiment of the present disclosure, see Figure 9 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Figure 9 As shown, the memory 50 includes the voltage stabilizing circuit 20 described in any one of the aforementioned embodiments.

[0161] The memory 50 may be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), etc., and is not specifically limited here.

[0162] Furthermore, in some embodiments, the memory 50 may include a DRAM chip. The DRAM chip may conform not only to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, but also to memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6, which are not specifically limited herein.

[0163] In the embodiment of the present disclosure, the memory 50 includes the voltage stabilizing circuit 20 described in the aforementioned embodiment, thereby not only avoiding the risk of breakdown of the input transistor, but also reducing the number of transistors in the voltage stabilizing circuit, thereby reducing current loss, improving memory performance, and saving memory area.

[0164] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0165] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0166] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0167] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0168] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0169] The features disclosed in several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0170] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A voltage stabilizing circuit, characterized in that: The voltage stabilizing circuit includes a first operational amplifier circuit and a second operational amplifier circuit, the first operational amplifier circuit is connected to the second operational amplifier circuit, and an enabling module is provided on the path of the second operational amplifier circuit, wherein: The enabling module is configured to control the path of the second operational amplifier circuit to be in an off state according to a control signal when the voltage stabilizing circuit is in a non-enabling mode; The first operational amplifier circuit includes an input circuit and a load circuit, and the input circuit is connected to the load circuit; the first operational amplifier circuit is used to control the input transistor in the input circuit and the load transistor in the load circuit to be in an off state in a non-enabled mode, and a first voltage at the connection point between the input circuit and the load circuit satisfies a preset voltage range.

2. The voltage stabilizing circuit according to claim 1, wherein: The enabling module includes a first transistor, and the first transistor is a PMOS transistor.

3. The voltage stabilizing circuit according to claim 1, wherein: The voltage stabilizing circuit further includes an inverting circuit, wherein: The inverting circuit is used to receive an enable signal and perform a non-logical operation on the enable signal to generate the control signal.

4. The voltage stabilizing circuit according to claim 3, wherein: If the voltage stabilizing circuit is in the enable mode, determining that the control signal is in a first level state and the enable signal is in a second level state; If the voltage stabilizing circuit is in the disabled mode, it is determined that the control signal is in the second level state and the enable signal is in the first level state.

5. The voltage stabilizing circuit according to claim 3, wherein: The second operational amplifier circuit includes a first sub-operational amplifier circuit, and the first sub-operational amplifier circuit includes the enabling module, a second transistor, and a third transistor, wherein: A first terminal of the second transistor is connected to a power supply voltage, a second terminal of the second transistor is connected to a first terminal of the enabling module, and a control terminal of the second transistor is connected to a first node; The second end of the enabling module is connected to the first end of the third transistor and the control end of the third transistor respectively, and the control end of the enabling module is used to receive the control signal; The second terminal of the third transistor is connected to the ground voltage, and the control terminal of the third transistor is further connected to the second node.

6. The voltage stabilizing circuit according to claim 5, characterized in that: The second operational amplifier circuit further includes a second sub-op-amp circuit, and the second sub-op-amp circuit includes a fourth transistor and a fifth transistor, wherein: A first terminal of the fourth transistor is connected to the power supply voltage, a second terminal of the fourth transistor is connected to the first terminal of the fifth transistor, and a control terminal of the fourth transistor is connected to the third node; The second terminal of the fifth transistor is connected to the ground voltage, and the control terminal of the fifth transistor is connected to the second node.

7. The voltage stabilizing circuit according to claim 6, wherein: In the load circuit, the load transistor includes a sixth transistor and a seventh transistor, wherein: The first terminal of the sixth transistor and the first terminal of the seventh transistor are both connected to the power supply voltage, the control terminal of the sixth transistor and the second terminal of the sixth transistor are both connected to the first node, and the second terminal of the sixth transistor is further connected to the input circuit; The control terminal of the seventh transistor and the second terminal of the seventh transistor are both connected to the third node, and the second terminal of the seventh transistor is also connected to the input circuit.

8. The voltage stabilizing circuit according to claim 7, wherein: The input circuit includes the input transistor, an eighth transistor, and a ninth transistor, and the input transistor includes a tenth transistor and an eleventh transistor, wherein: a first end of the tenth transistor being connected to the second end of the sixth transistor, a first end of the eleventh transistor being connected to the second end of the seventh transistor, and a second end of the tenth transistor and a second end of the eleventh transistor being both connected to the first end of the eighth transistor; The second end of the eighth transistor is connected to the first end of the ninth transistor, and the second end of the ninth transistor is connected to the ground voltage; The control end of the ninth transistor and the control end of the tenth transistor are both used to receive an input voltage, the control end of the eighth transistor is used to receive the enable signal, and the control end of the eleventh transistor is used to receive a feedback voltage.

9. The voltage stabilizing circuit according to claim 1, wherein: The voltage stabilizing circuit further includes a pull-down circuit, and the pull-down circuit is connected to the second node, wherein: The pull-down circuit is used to pull down the potential of the second node to the ground voltage.

10. The voltage stabilizing circuit according to claim 9, wherein: The pull-down circuit includes a twelfth transistor, wherein: A first terminal of the twelfth transistor is connected to the second node, a second terminal of the twelfth transistor is connected to the ground voltage, and a control terminal of the twelfth transistor is used to receive the control signal; The pull-down circuit is configured to control the twelfth transistor to be in a conducting state according to the control signal when the voltage stabilizing circuit is in a non-enabled mode, so as to pull the potential of the second node down to the ground voltage.

11. The voltage stabilizing circuit according to claim 1, wherein: The voltage stabilizing circuit further includes a pull-up circuit, and the pull-up circuit is connected to the fourth node, wherein: The pull-up circuit is used to pull up the potential of the fourth node to the power supply voltage.

12. The voltage stabilizing circuit according to claim 11, wherein: The pull-up circuit includes a thirteenth transistor, wherein: A first terminal of the thirteenth transistor is connected to the power supply voltage, a second terminal of the thirteenth transistor is connected to the fourth node, and a control terminal of the thirteenth transistor is used to receive an enable signal; The pull-up circuit is configured to control the thirteenth transistor to be in a conducting state according to the enable signal when the voltage stabilizing circuit is in a non-enabled mode, so as to pull up the potential of the fourth node to the power supply voltage.

13. The voltage stabilizing circuit according to claim 12, wherein: The voltage stabilizing circuit further includes an output circuit, and the output circuit includes a fourteenth transistor and a resistor voltage divider module, wherein: A first terminal of the fourteenth transistor is connected to the power supply voltage, a second terminal of the fourteenth transistor is connected to the first terminal of the resistance voltage divider module, and a control terminal of the fourteenth transistor is connected to the fourth node; The second end of the resistor voltage divider module is connected to the ground voltage, and the third end of the resistor voltage divider module is used to output a feedback voltage.

14. The voltage stabilizing circuit according to claim 13, wherein: The resistor voltage divider module includes a first resistor and a second resistor, wherein: The first end of the first resistor is connected to the second end of the fourteenth transistor; The second end of the second resistor is connected to the ground voltage; The second end of the first resistor is connected to the first end of the second resistor for outputting the feedback voltage.

15. A memory, characterized in that: The memory includes the voltage stabilizing circuit according to any one of claims 1 to 14.

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