memory

Abstract

The application discloses a memory, which comprises at least one storage library, each of which comprises two storage surfaces, each of which comprises a plurality of storage resources and a plurality of redundant replacement resources; wherein a damaged storage resource of each storage surface can be replaced by a redundant replacement resource of another storage surface to perform normal read-write operation. In the above manner, the redundant replacement resources in different storage surfaces can be shared with each other, so that the flexibility of replacement and the yield of the memory are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a memory. BACKGROUND

[0002] In the manufacturing process of a memory, especially a dynamic random access memory (DRAM), there may exist defects in the memory cells (MC) in the row direction, which cannot normally perform storage operations; or there may exist defects in the memory cells in the column direction, which cannot normally perform storage operations. Therefore, in order to improve the yield of the random access memory, some spare circuits and spare memory cells are needed to replace the damaged word lines, bit lines and memory cells. These spare circuits and spare memory cells are collectively referred to as redundancy resources. Specifically, when there are defects in the memory cells in the row direction and row redundancy is needed, it is called row redundancy; when there are defects in the memory cells in the column direction and column redundancy is needed, it is called column redundancy.

[0003] With the continuous increase of the storage capacity of the dynamic random access memory, in order to facilitate access and control, the storage array is divided into a plurality of banks, each bank is divided into two adjacent storage planes, such as a first storage plane P0 and a second storage plane P1. A fixed number of redundancy resources are provided in each storage plane to replace the damaged storage resources in the corresponding storage plane. However, in the actual process of manufacturing, the probability and number of damaged storage resources in the first storage plane P0 and the second storage plane P1 are not the same, which may cause the redundancy resources of one of the two storage planes to be sufficient, while the redundancy resources of the other of the two storage planes to be insufficient. SUMMARY

[0004] In order to solve the above problems, the present application provides a memory which can share redundancy resources in different storage planes, thereby improving the flexibility of replacement and the yield of the memory.

[0005] To solve the above technical problems, one technical solution adopted by the present application is to provide a memory, comprising: at least one bank, each bank comprising two storage planes, each storage plane comprising a plurality of storage resources and a plurality of redundancy resources; wherein the damaged storage resources of each storage plane can be replaced by the redundancy resources of another storage plane to perform normal read and write operations.

[0006] Each of the storage resources comprises a plurality of normal storage units arranged in rows or columns, and each of the redundancy replacement resources comprises a plurality of redundancy storage units arranged in rows or columns.

[0007] Each of the storage surfaces can selectively operate in a first operating mode or a second operating mode; when the storage surface operates in the first operating mode, the damaged storage resource in the storage surface is replaced only by the redundancy replacement resource in the same storage surface; when the storage surface operates in the second operating mode, the damaged storage resource in the storage surface can be replaced by the redundancy replacement resource in another storage surface.

[0008] When the storage surface operates in the second operating mode, the priority of replacing the damaged storage resource in the storage surface by the redundancy replacement resource in the same storage surface is higher than the priority of replacing the damaged storage resource in the storage surface by the redundancy replacement resource in another storage surface.

[0009] The storage resources comprise column storage resources, and the redundancy replacement resources comprise column redundancy replacement resources; each of the storage banks comprises a column decoding circuit corresponding to two storage surfaces, respectively; in response to a mode signal being at a first logic level, the column decoding circuit can only enable the column redundancy replacement resource in the corresponding storage surface to replace the damaged column storage resource in the same storage surface; in response to the mode signal being at a second logic level, the column decoding circuit can enable the column redundancy replacement resource in the corresponding storage surface to replace the damaged column storage resource in another storage surface; wherein the first logic level and the second logic level are opposite.

[0010] The column storage resources comprise normal column selection signal lines, each of which is coupled to a plurality of normal storage units; the column redundancy replacement resources comprise redundancy column selection signal lines, each of which is coupled to a plurality of redundancy storage units; the column decoding circuit enables the column redundancy replacement resource to replace the damaged column storage resource by enabling the redundancy column selection signal line to replace the damaged normal column selection signal line; wherein the normal column selection signal line coupled to the damaged normal storage unit is defined as the damaged normal column selection signal line.

[0011] The memory comprises an address matching circuit, the address matching circuit is coupled to the column decoding circuit corresponding to the two memory surfaces; when performing column addressing operation, the address matching circuit compares the column addressing address with the bad block address set, and when the column addressing address matches any bad block address in the bad block address set, the address matching circuit delivers redundancy enabling information to the column decoding circuit to enable the redundant column signal line.

[0012] The memory comprises a programmable storage circuit and a redundancy latching circuit, the programmable storage circuit is coupled to the redundancy latching circuit, and the redundancy latching circuit is coupled to the address matching circuit to deliver the bad block address set to the address matching circuit; wherein the mode signal is controlled by a trimming bit in the programmable storage circuit.

[0013] Each of the memory banks comprises a row decoding circuit, the row decoding circuit is coupled to the two memory surfaces respectively and arranged between the two memory surfaces.

[0014] Each of the memory surfaces comprises a plurality of memory areas, each of the memory areas comprises a plurality of memory blocks, each of the memory blocks comprises x parts of the storage resources and y parts of the redundancy replacement resources, wherein y is less than x.

[0015] The memory provided by the present application comprises at least one memory bank, each of the memory banks comprises two memory surfaces, each of the memory surfaces comprises a plurality of storage resources and a plurality of redundancy replacement resources; wherein the damaged storage resources of each of the memory surfaces can be replaced by the redundancy replacement resources of another memory surface to perform normal read and write operation. Through the above-mentioned manner, the redundancy replacement resources in different memory surfaces can be shared with each other, thereby improving the flexibility of replacement and the yield of the memory. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Wherein:

[0018] Figure 1 is a structural schematic diagram of one embodiment of the memory provided by the present application;

[0019] Figure 2 is a structural schematic diagram of one embodiment of the memory bank provided by the present application;

[0020] Figure 3 This is a schematic diagram of the structure of an embodiment of the storage surface provided in this application;

[0021] Figure 4 This is a schematic diagram of another embodiment of the storage surface provided in this application;

[0022] Figure 5 This is a schematic diagram of another embodiment of the memory provided in this application;

[0023] Figure 6 This is a schematic diagram of the structure of an embodiment of the electronic device provided in this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0025] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] The memory provided in this application includes: at least one storage repository, each storage repository including two storage surfaces, each storage surface including multiple storage resources and multiple redundant replacement resources; wherein, a damaged storage resource in one storage surface can be replaced by a redundant replacement resource in another storage surface to perform normal read and write operations. Through this method, the redundant replacement resources in different storage surfaces can be shared, thereby improving the flexibility of replacement and the yield of the memory.

[0027] Please see Figure 1 , Figure 1 This is a schematic diagram of a memory embodiment provided in this application. The memory 1000 is a semiconductor-based storage device; in this embodiment, it is specifically a dynamic random access memory (DRAM). The memory 1000 includes at least one storage bank 100; in this embodiment, it specifically includes a storage bank (Bank). <0> To the bank <n>wherein n is a positive integer. It can be understood that, with the continuous increase of the storage capacity of the memory, in order to facilitate access and control, the memory is made in the form of multiple storage banks stacked, and each time a read-write operation is performed on one of the storage banks.

[0028] Referring to Figure 2 , Figure 2 is a structural schematic diagram of an embodiment of a storage provided by the present application. The storage 100 can include, but is not limited to, a storage surface 110, a column decoding circuit 120, and a row decoding circuit 170. The storage surface 110 includes a first storage surface P0 and a second storage surface P1. The column decoding circuit 120 includes a first column decoding circuit YDEC0 and a second column decoding circuit YDEC1. The row decoding circuit 170 is coupled to the first storage surface P0 and the second storage surface P1 respectively and is disposed between the first storage surface P0 and the second storage surface P1. The first column decoding circuit YDEC0 is coupled to the first storage surface P0. The second column decoding circuit YDEC1 is coupled to the second storage surface P1. The first storage surface P0 and the second storage surface P1 include a plurality of storage resources and a plurality of redundant replacement resources. The row decoding circuit 170 is configured to enable the storage resources or the redundant replacement resources of the first storage surface P0 and the second storage surface P1 in a row direction. The first column decoding circuit YDEC0 is configured to enable the storage resources or the redundant replacement resources of the first storage surface P0 in a column direction. The second column decoding circuit YDEC1 is configured to enable the storage resources or the redundant replacement resources of the second storage surface P1 in a column direction. Wherein, the damaged storage resource of one of the first storage surface P0 and the second storage surface P1 can be replaced by the redundant replacement resource of the other of the first storage surface P0 and the second storage surface P1 to perform normal storage operations. Specifically, the damaged storage resource in the first storage surface P0 can be replaced by the redundant replacement resource in the second storage surface P1 to perform normal read / write operations. Meanwhile, the damaged storage resource in the second storage surface P1 can also be replaced by the redundant replacement resource in the first storage surface P0 to perform normal read / write operations. Each storage resource includes a plurality of normal storage units arranged in rows or columns. Each redundant replacement resource includes a plurality of redundant storage units arranged in rows or columns. Wherein, any storage resource with a damaged normal storage unit is defined as a damaged storage resource. The first storage surface P0 and the second storage surface P1 can selectively work in a first working mode or a second working mode. Wherein, when the first storage surface P0 and the second storage surface P1 work in the first working mode, the damaged storage resource of one of the first storage surface P0 and the second storage surface P1 is replaced by the redundant replacement resource in the same storage surface. When the first storage surface P0 and the second storage surface P1 work in the second working mode, the damaged storage resource of one of the first storage surface P0 and the second storage surface P1 can be replaced by the redundant replacement resource in the other of the first storage surface P0 and the second storage surface P1. When the first storage surface P0 and the second storage surface P1 work in the second working mode, the priority of the damaged storage resource of one of the first storage surface P0 and the second storage surface P1 being replaced by the redundant replacement resource in the same storage surface is higher than the priority of the damaged storage resource of one of the first storage surface P0 and the second storage surface P1 being replaced by the redundant replacement resource in the other of the first storage surface P0 and the second storage surface P1.In this way, the redundant replacement resources in different storage surfaces can share with each other, thereby improving the flexibility of replacement and the yield of the memory.

[0029] It can be understood that in the manufacturing process of the memory, there can be a storage unit in the row direction with a defect and unable to normally perform a storage operation, or a storage unit in the column direction with a defect and unable to normally perform a storage operation. Therefore, in order to improve the yield of the random memory, some spare circuits and spare storage units need to be added to replace the damaged word line, bit line and storage unit. These spare circuits and spare storage units are collectively referred to as redundant replacement resources. Specifically, when the storage unit in the row direction has a defect and needs to be replaced in the row direction, it is referred to as row replacement; when the storage unit in the column direction has a defect and needs to be replaced in the column direction, it is referred to as column replacement. In the present embodiment, the application of the redundant replacement resources shared between the first storage surface P0 and the second storage surface P1 in the column replacement technology is taken as an example.

[0030] Please refer to Figure 3 , Figure 3 is a structural schematic diagram of an embodiment of a storage surface provided by the present application. The storage surface 110 includes a plurality of storage areas 111, in the present embodiment, k+1 storage areas 111 arranged in a column in sequence from top to bottom, specifically, storage area section<0> to storage area section <k>wherein k is a positive integer. Each memory area 111 includes a plurality of memory blocks 1111, in this embodiment, 8 memory blocks 1111 arranged in a row from left to right, specifically, memory block mat<0> to memory block mat<7>. When the memory 1000 performs a read / write operation, the read / write operation is performed on one memory area 111 at a time, and each memory block 1111 outputs or writes 8-bit data, so each memory area 111 outputs or writes 64-bit data. Each memory block 1111 includes x portions of storage resources and y portions of redundant replacement resources, wherein x and y are both positive integers and y is less than x. In this embodiment, the x portions of storage resources include normal column select signal lines YST<0> to normal column select signal lines YST <x-1>The y portions of the redundancy replacement resource include redundancy column select signal lines RYST<0> to RYST <y-1>The column decoding circuit 120 can decode the column addressing address and drive the corresponding common column strobe signal line YST or the redundant column strobe signal line RYST to access the data in each memory block 1111 in the storage area 111. The data in each memory block 1111 can be amplified by the sense amplifier circuit 130 and then output to the outside through the input / output circuit 140.

[0031] Please refer to Figure 3 and Figure 4 , Figure 4 is a structural schematic diagram of another embodiment of the storage surface provided by the present application. The storage surface 110 includes a plurality of word lines WL, a plurality of pairs of complementary bit lines BL / BL#, and a plurality of memory cells MC. The plurality of memory cells MC includes a plurality of normal memory cells and a plurality of redundant memory cells. Each memory cell MC is coupled to a word line WL and a pair of complementary bit lines BL / BL#. The pair of complementary bit lines BL / BL# includes a target bit line BL and a complementary bit line BL#. The memory cell MC includes a storage capacitor CP and an access switch CT. The storage capacitor CP is coupled between the access switch CT and a common terminal. The access switch CT is coupled between the storage capacitor CP and the target bit line BL, and the control terminal of the access switch CT is coupled to the word line WL. The storage capacitor CP represents "1" and "0" in logic by more and less of the charge stored therein, or in other words, high and low of the voltage difference across the storage capacitor. The conduction and cutoff of the access switch CT determines whether to allow or prohibit reading and rewriting of the information stored in the storage capacitor CP. Specifically, the word line WL determines the conduction or cutoff of the access switch CT, and the bit line BL is the only channel for the outside to access the storage capacitor CP. When the access switch CT is turned on, the outside can perform reading or writing operation on the storage capacitor CP through the bit line BL.

[0032] The storage surface 110 further includes a plurality of initialization modules 112, a plurality of sense amplifier modules 113, and a plurality of column strobe modules 114. Each initialization module 112 is coupled to a pair of corresponding complementary bit lines BL / BL# to charge the corresponding pair of complementary bit lines BL / BL# to an initialization potential Vref in a pre-charge phase. Each sense amplifier module 113 is coupled to a pair of corresponding complementary bit lines BL / BL# to perform signal amplification operation on the corresponding pair of complementary bit lines BL / BL#. Each column strobe module 114 is coupled to a pair of complementary bit lines BL / BL# and each column strobe module 114 is coupled to a common column strobe signal line YST / redundant column strobe signal line RYST to enable the pair of complementary bit lines BL / BL# and the pair of complementary intermediate input / output lines MIO / MIO# when the column decoding circuit 120 drives the common column strobe signal line YST / redundant column strobe signal line RYST.

[0033] The input / output circuit 140 includes a plurality of pairs of complementary intermediate input / output lines MIO / MIO# and a plurality of pairs of complementary input / output lines IO / IO#. The complementary intermediate input / output lines MIO / MIO# are coupled to the complementary bit lines BL / BL# through the column gating module 114. The complementary intermediate input / output lines MIO / MIO# include a target intermediate input / output line MIO and a complementary intermediate input / output line MIO#. The target intermediate input / output line MIO is coupled to the target bit line BL through the column gating module 114, and the complementary intermediate input / output line MIO# is coupled to the complementary bit line BL# through the column gating module 114. It is noted that in other embodiments, the input / output circuit 140 further includes a plurality of pairs of complementary local input / output lines LIO / LIO# (not shown in the figure), the plurality of pairs of complementary intermediate input / output lines MIO / MIO# and the plurality of pairs of complementary input / output lines IO / IO#, wherein the complementary local input / output lines LIO / LIO# are coupled to the complementary bit lines BL / BL# through the column gating module 114, and the complementary local input / output lines LIO / LIO# are further coupled to the complementary intermediate input / output lines MIO / MIO# through a switch circuit (not shown in the figure).

[0034] When the memory 1000 performs a read operation, the data in the memory cell MC to be accessed is first amplified by the sense amplifier module 113, and then the corresponding complementary bit lines BL / BL# and the complementary intermediate input / output lines MIO / MIO# are gated by the column gating module 114. Subsequently, the data in the memory cell MC is further amplified by the sense amplification circuit 130 and then output to the corresponding complementary input / output lines IO / IO#. The sense amplification circuit 130 includes a plurality of secondary sense amplifier modules for further amplifying the data on the complementary intermediate input / output lines MIO / MIO# and then outputting the data to the corresponding complementary input / output lines IO / IO#.

[0035] In other embodiments, the input / output circuit 140 can further include a write driving module for writing external data into the memory cell MC.

[0036] Further, each column gating module 114 is coupled to a pair of complementary bit lines BL / BL# and each column gating module 114 is coupled to a common column gate signal line YST / a redundant column gate signal line RYST to gate the complementary bit lines BL / BL# and the complementary intermediate input / output lines MIO / MIO# when the common column gate signal line YST / the redundant column gate signal line RYST is driven by the column decoding circuit 120. In the present embodiment, one common column gate signal line YST / redundant column gate signal line RYST is coupled to 8 column gating modules 114.

[0037] In the embodiment, if the first storage surface P0 and the second storage surface P1 work in the second working mode, when a storage unit MC corresponding to a certain normal column selection signal line YST in one of the first storage surface P0 and the second storage surface P1 has a defect (a damaged normal storage unit) and cannot be normally read and written, a storage unit MC (a redundant storage unit) corresponding to a redundant column selection signal line RYST in the other of the first storage surface P0 and the second storage surface P1 can be used for substitution, so as to improve the yield of the memory.

[0038] Please refer to Figure 3 , Figure 4 and Figure 5 , Figure 5 is a structural schematic diagram of another embodiment of the memory provided by the present application. The memory 1000 can include but is not limited to a storage bank 100, an address matching circuit 150 and a redundant latching circuit 160. The storage bank 100 can include but is not limited to a first storage surface P0, a second storage surface P1, a first column decoding circuit YDEC0 and a second column decoding circuit YDEC1. The storage resources in the first storage surface P0 and the second storage surface P1 include column storage resources. The column storage resources include normal column selection signal lines YST, and in the embodiment, specifically include normal column selection signal lines YST<0> to normal column selection signal lines YST <x-1>. Each common column select signal line YST is coupled to a plurality of common storage units. The redundant replacement resources in the first storage surface P0 and the second storage surface P1 include column redundant replacement resources. The column redundant replacement resources include redundant column select signal lines RYST, specifically redundant column select signal lines RYST<0> to redundant column select signal lines RYST <y-1>The redundant column selection signal line RYST is coupled to a plurality of redundant memory cells. The normal column selection signal line YST coupled to the damaged normal memory cell is defined as a damaged normal column selection signal line. The first column decoding circuit YDEC0 and / or the second column decoding circuit YDEC1 enable the column redundancy replacement resource to replace the damaged column memory resource by enabling the redundant column selection signal line RYST to replace the damaged normal column selection signal line.

[0039] Specifically, the first column decoding circuit YDEC0 corresponds to the first storage surface P0 and is configured to enable the normal column selection signal line YST or the redundant column selection signal line RYST in the first storage surface P0 to access the memory cell MC. The second column decoding circuit YDEC1 corresponds to the second storage surface P1 and is configured to enable the normal column selection signal line YST or the redundant column selection signal line RYST in the second storage surface P1 to access the memory cell MC. In response to the mode signal MOD being at a first logic level, the first column decoding circuit YDEC0 is only able to enable the column redundancy replacement resource (the redundant column selection signal line RYST) in the first storage surface P0 to replace the damaged column memory resource (the damaged normal column selection signal line YST) in the first storage surface P0; and the second column decoding circuit YDEC1 is only able to enable the column redundancy replacement resource (the redundant column selection signal line RYST) in the second storage surface P1 to replace the damaged column memory resource (the damaged normal column selection signal line YST) in the second storage surface P1. In response to the mode signal MOD being at a second logic level, the first column decoding circuit YDEC0 is able to enable the column redundancy replacement resource (the redundant column selection signal line RYST) in the first storage surface P0 to replace the damaged column memory resource (the damaged normal column selection signal line YST) in the second storage surface P1; and the second column decoding circuit YDEC1 is able to enable the column redundancy replacement resource (the redundant column selection signal line RYST) in the second storage surface P1 to replace the damaged column memory resource (the damaged normal column selection signal line YST) in the first storage surface P0. The first logic level and the second logic level are opposite. Optionally, the first logic level is a logic high level and the second logic level is a logic low level. In this way, when the first storage surface P0 and the second storage surface P1 work in the second working mode, the column redundancy replacement resources in the first storage surface P0 and the second storage surface P1 can be shared with each other, so that the replacement is more flexible, thereby improving the yield of the memory 1000.

[0040] Further, the address matching circuit 150 is coupled to the first column decode circuit YDEC0 and the second column decode circuit YDEC1. When performing a column addressing operation, the address matching circuit 150 compares the column addressing address CA<9:3> with the bad block address set m*CRCAT<9:0>, and when the column addressing address CA<9:3> matches any of the bad block addresses in the bad block address set m*CRCAT<9:0>, the address matching circuit 150 delivers the redundancy enable information CRFG <y:1>The column address CA<9:3> is compared with any one of the bad block addresses in the bad block address set m*CRCAT<9:0> in the column decoding circuit 120 to enable the redundant column select signal line RYST. Wherein, m is a positive integer. Specifically, the column address CA<9:3> is compared with any one of the bad block addresses in the bad block address set m*CRCAT<9:0> bit by bit. In an embodiment, when the column address CA<9:3> is the same as the corresponding bit of the bad block address, the column address CA<9:3> matches the bad block address, and the address matching circuit 150 generates the redundant enable information CRFG <y:1>and is supplied to the column decoding circuit 120. When the mode signal MOD is the first logic level, the first column decoding circuit YDEC0 or the second column decoding circuit YDEC1 responds to the redundancy enable information CRFG <y:1>and enables the corresponding redundant column address signal line RYST in the corresponding storage surface 110 through the column address enable signal YS_en to access the corresponding redundant storage unit, thereby replacing the corresponding damaged normal column address signal line YST in the same storage surface 110 to realize normal storage operation. When the mode signal MOD is the second logic level, the first column decoding circuit YDEC0 or the second column decoding circuit YDEC1 enables the corresponding redundant column address signal line RYST in the corresponding storage surface 110 in response to the redundant enable information CRFG <y:1>And the memory 1000 is capable of enabling the corresponding redundant column address signal line RYST in the corresponding storage surface 110 through the column address enable signal YS_en to access the corresponding redundant storage unit, so as to replace the corresponding damaged normal column address signal line YST in another storage surface 110 to realize normal storage operation.

[0041] Further, the memory 1000 further comprises a programmable storage circuit (not shown in the figure), which is coupled to the redundancy latching circuit 160. The programmable storage circuit stores the bad block address set m*CRCAT<9:0> and delivers the bad block address set m*CRCAT<9:0> to the redundancy latching circuit 160 at power-on. The redundancy latching circuit 160 is coupled to the address matching circuit 150 to deliver the bad block address set m*CRCAT<9:0> to the address matching circuit 150. Wherein, the mode signal MOD is controlled by the trim bit in the programmable storage circuit. Optionally, when the trim bit in the programmable storage circuit is 1, the mode signal MOD is the first logic level. When the trim bit in the programmable storage circuit is 0, the mode signal MOD is the second logic level.

[0042] The memory 1000 provided by the present application comprises at least one storage bank 100, each storage bank 100 comprising two storage surfaces 110, each storage surface 110 comprising a plurality of storage resources and a plurality of redundant replacement resources; wherein the damaged storage resource of each storage surface 110 can be replaced by the redundant replacement resource of another storage surface 110 to perform normal read-write operation. In the above manner, the redundant replacement resources in different storage surfaces 110 can be shared with each other, thereby improving the flexibility of replacement and the yield of the memory 1000.

[0043] Please refer to Figure 6 , Figure 6 is a structural schematic diagram of an embodiment of the electronic device provided by the present application. The electronic device 2000 can comprise but is not limited to a data storage circuit 2001, a storage controller 2002, a buffer storage 2003 and an input-output interface 2004.

[0044] According to the control signal generated by the storage controller 2002, the data storage circuit 2001 can store the data output by the storage controller 2002 or output the stored data to the storage controller 2002. The data storage circuit 2001 can comprise at least one memory 1000. The data storage circuit 2001 can further comprise a non-volatile memory capable of retaining stored data after power-off. The non-volatile memory can be a NOR type flash memory or a NAND type flash memory, a phase change random access memory (PRAM), a variable resistance memory (RRAM), a spin transfer torque random access memory (STTRAM) and a magnetic random access memory (MRAM) and the like.

[0045] The storage controller 2002 can receive an instruction from an external device through the input / output interface 2004, and can interpret the instruction to control an operation of inputting data to the data storage circuit 2001 or the buffer memory 2003, or outputting data stored in the data storage circuit 2001 or the buffer memory 2003. Alternatively, the external device can be a host device. The storage controller 2002 can include one that controls the data storage circuit 2001 including a non-volatile memory and another that controls the buffer memory 2003 including a volatile memory.

[0046] The buffer memory 2003 is used to temporarily store data generated by the storage controller 2002. That is, the buffer memory 2003 is used to temporarily store data output from the data storage circuit 2001 or to be stored in the data storage circuit 2001. Based on a control signal, the buffer memory 2003 can store data output from the storage controller 2002. Also, the buffer memory 2003 can read and output data stored in the storage controller 2002. The buffer memory 2003 can include a volatile random access memory, such as a dynamic random access memory (DRAM), a mobile memory, or a solid state random access memory (SRAM).

[0047] The input / output interface 2004 is used to physically and electrically connect the storage controller 2002 and an external device. The external device can be a host. Accordingly, the storage controller 2002 can receive an instruction and data from the external device through the input / output interface 2004, and can output data generated by itself to the external device through the input / output interface 2004. That is, the electronic device 2000 can exchange data with the external device through the input / output interface 2004. The input / output interface 2004 can include any one of various interfaces, such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect express (PCI-E), a serial attached SCSI (SAS), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small device interface (ESDI), and an integrated drive electronics (IDE).

[0048] The electronic device 2000 can be used as a host's auxiliary storage device or an external storage device. The electronic device 2000 can include a solid state disk (SSD), a USB memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro-SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded multimedia card (eMMC), and a standard flash memory card, etc.

[0049] The above merely describes the embodiments of the present application, and does not limit the patent scope of the application. Any equivalent structure or equivalent process transformation according to the content of the specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application. < / k> < / n>

Claims

1. A memory, characterized in that, include: At least one repository, each repository comprising two storage surfaces, each storage surface comprising multiple storage resources and multiple redundant replacement resources; In this configuration, the damaged storage resource of each storage surface can be replaced by the redundant replacement resource of another storage surface to perform normal read and write operations. Each of the aforementioned storage repositories includes a row decoding circuit, which is coupled to two of the storage surfaces and disposed between the two storage surfaces; each of the aforementioned storage repositories includes column decoding circuits corresponding to the two storage surfaces respectively. The storage resources include column storage resources, and the redundancy replacement resources include column redundancy replacement resources; The priority of replacing a damaged column storage resource in one storage plane with a column redundancy replacement resource in the same storage plane is greater than the priority of replacing a damaged column storage resource in one storage plane with a column redundancy replacement resource in another storage plane.

2. The memory according to claim 1, characterized in that, Each of the storage resources includes a plurality of ordinary storage units arranged in rows or columns, and each of the redundant replacement resources includes a plurality of redundant storage units arranged in rows or columns. When any of the storage resources has a damaged ordinary storage unit, the storage resource is defined as the damaged storage resource.

3. The memory according to claim 1, characterized in that, Each of the storage surfaces can selectively operate in a first operating mode or a second operating mode; Wherein, when the storage plane is working in the first working mode, the damaged storage resources in the storage plane are only replaced by the redundant replacement resources in the same storage plane; When the storage plane is operating in the second operating mode, the damaged storage resource in the storage plane can be replaced by the redundant replacement resource in another storage plane.

4. The memory according to claim 1, characterized in that, In response to the mode signal being at the first logic level, the column decoding circuit can only enable the column redundancy replacement resource in the corresponding storage plane to replace the damaged column storage resource in the same storage plane; In response to the mode signal being at the second logic level, the column decoding circuit can enable the column redundancy replacement resource in the corresponding storage plane to replace the damaged column storage resource in another storage plane; The first logic level and the second logic level are opposite.

5. The memory according to claim 4, characterized in that, The column storage resource includes ordinary column strobe signal lines, each of which is coupled to multiple ordinary storage cells. The column redundancy replacement resource includes redundant column strobe signal lines, each of which is coupled to multiple redundant memory cells. The column decoding circuit enables the column redundancy replacement resource to replace the damaged column storage resource by enabling the redundant column strobe signal line to replace the damaged ordinary column strobe signal line; The ordinary column strobe signal line coupled to the damaged ordinary memory cell is defined as the damaged ordinary column strobe signal line.

6. The memory according to claim 5, characterized in that, The memory includes an address matching circuit, which is coupled to the column decoding circuits corresponding to the two memory surfaces. When performing column addressing operation, the address matching circuit compares the column addressing address with the bad block address set, and when the column addressing address matches any bad block address in the bad block address set, the address matching circuit sends redundancy enable information to the column decoding circuit to enable the redundant column strobe signal line.

7. The memory according to claim 6, characterized in that, The memory includes a programmable storage circuit and a redundant latch circuit. The programmable storage circuit is coupled to the redundant latch circuit, and the redundant latch circuit is coupled to the address matching circuit to send the bad block address set to the address matching circuit. The mode signal is controlled by the trimming bit in the programmable storage circuit.

8. The memory according to any one of claims 1-7, characterized in that, Each of the aforementioned storage surfaces includes multiple storage areas, each of the aforementioned storage areas includes multiple storage blocks, and each of the aforementioned storage blocks includes x portions of the aforementioned storage resources and y portions of the aforementioned redundant replacement resources, wherein y is less than x.

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