Integrated circuit, semiconductor device and method of operating semiconductor device

Abstract

An integrated circuit, a semiconductor device and a method of operating the semiconductor device are provided. An integrated circuit includes a sense amplifier connected to a bit line and a complementary bit line; a first memory unit for storing a data signal and selectively outputting the data signal on at least one of a bit line and a complementary bit line in response to a word line signal; a first circuit connected between a first voltage terminal for receiving a first external voltage and the bit line and having a first enable terminal for receiving a first enable signal, wherein the first external voltage is different from the data signal; and a second circuit connected between a second voltage terminal for receiving a second external voltage and the complementary bit line and having a second enable terminal for receiving a second enable signal, wherein the second external voltage is different from the data signal and the first external voltage.

Description

Technical Field

[0001] An embodiment of the present disclosure relates to a semiconductor device and an operating method thereof, and more particularly to a semiconductor device having complementary bit lines and an operating method thereof. Background Art

[0002] Typically, electronic systems store data in memory devices such as dynamic random-access memory (DRAM) devices. Due to the relatively fast access time of DRAM, DRAM is often the primary storage medium of the system. One type of DRAM includes a one transistor one capacitor (1T1C) memory cell, each memory cell storing one data bit. The transistor is an access control transistor located between the capacitor and the bit line (BL) or complementary bit line bar (BLB) of a sense amplifier (SA). The access control transistor is activated to read data from the capacitor or write data to the capacitor. Summary of the invention

[0003] One embodiment of the present disclosure provides an integrated circuit, the integrated circuit comprising a sense amplifier, a first memory cell, a first circuit, and a second circuit. The sense amplifier has a plurality of input terminals connected to a bit line and a complementary bit line. The first memory cell stores a data signal and selectively outputs the data signal on at least one of the bit line and the complementary bit line in response to a word line signal. The first circuit is connected between a first voltage terminal receiving a first external voltage and the bit line and has a first enable terminal receiving a first enable signal. The first external voltage is different from the data signal. The second circuit is connected between a second voltage terminal receiving a second external voltage and the complementary bit line and has a second enable terminal receiving a second enable signal. The second external voltage is different from the data signal and the first external voltage.

[0004] One embodiment of the present disclosure provides a semiconductor device, which includes a sense amplifier, a memory cell array, a precharge and equalization circuit, a first circuit, and a second circuit. The sense amplifier is connected to a bit line and a complementary bit line. The memory cell array includes a plurality of memory cells. The first memory cell has a first access control transistor connected to the bit line and a first storage capacitor. The second memory cell has a second access control transistor connected to the complementary bit line and a second storage capacitor. The precharge and equalization circuit is connected to the bit line and the complementary bit line and provides an equalized precharge voltage to each of the bit line and the complementary bit line in response to an effective precharge enable signal. The first circuit includes a first metal oxide semiconductor field effect transistor, the first metal oxide semiconductor field effect transistor having a first drain / source terminal connected to the bit line, a second drain / source terminal receiving a first external voltage, and a gate terminal receiving an enable signal. The second circuit includes a second metal oxide semiconductor field effect transistor, the second metal oxide semiconductor field effect transistor having a third drain / source terminal connected to the complementary bit line, a fourth drain / source terminal receiving a second external voltage, and a gate terminal receiving an enable signal.

[0005] An embodiment of the present disclosure provides a method of operating a semiconductor device. The method includes the following steps: receiving a first enable signal at a first circuit connected to a bit line of a sense amplifier; receiving a second enable signal at a second circuit connected to a complementary bit line of the sense amplifier; providing a first voltage from the first circuit to the bit line in response to receiving the first enable signal; and providing a second voltage from the second circuit to the complementary bit line in response to receiving the second enable signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] An aspect of an embodiment of the present disclosure is in accordance with the accompanying Figure 1 The following detailed description is best understood when read together. It should be noted that various features are not drawn to scale, in accordance with standard practices in the industry. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion. In addition, the drawings are illustrated as examples of embodiments of the present disclosure and are not intended to be limiting.

[0007] Figure 1 is a diagram schematically illustrating a semiconductor device including a sensing circuit for providing different voltages to BL and BLB of SA according to some embodiments;

[0008] Figure 2 is a diagram schematically illustrating a sensing circuit connected to a first memory unit and a second memory unit according to some embodiments;

[0009] Figure 3is a diagram schematically illustrating an example of a sensing circuit, a first memory unit, and a second memory unit according to some embodiments;

[0010] Figure 4 is a diagram schematically illustrating a first memory unit, a second memory unit, and a sensing circuit configured for testing SA according to some embodiments;

[0011] Figure 5 is a schematic diagram illustrating a method according to some embodiments Figure 4 A diagram showing the relationship between the voltage of the complementary data line DLB and the voltage of the BLB in a test configuration of the sensing circuit;

[0012] Figure 6 is a schematic diagram illustrating a method according to some embodiments Figure 4 A diagram of the operation of a test configuration of a sensing circuit;

[0013] Figure 7 is a diagram schematically illustrating a first memory unit, a second memory unit, and a sensing circuit for determining a read sensing margin of SA according to some embodiments;

[0014] Figure 8 is a schematic diagram of a method for determining Figure 7 A diagram showing the relationship between the voltage of the complementary data line DLB and the voltage of the BLB of the sensing margin of the SA in the sensing circuit;

[0015] Fig. 9 is a diagram schematically illustrating a first memory cell, a second memory cell, and a sensing circuit for measuring leakage currents of BL and BLB and measuring leakage currents of a first storage capacitor and a second storage capacitor according to some embodiments;

[0016] Fig.10 is a diagram schematically illustrating first and second PMOS channel gate transistors in a first charging circuit and a second charging circuit, respectively, according to some embodiments;

[0017] Fig.11 is a diagram schematically illustrating first and second CMOS channel gates in a first charging circuit and a second charging circuit, respectively, according to some embodiments;

[0018] Fig.12 is a diagram schematically illustrating additional Y-decoding gating in a first charging circuit and a second charging circuit according to some embodiments;

[0019] Fig.13 are diagrams schematically illustrating first and second multiplexers in first and second charging circuits, respectively, according to some embodiments;

[0020] Fig.14is a diagram schematically illustrating a method of operating a semiconductor device such as a sensing circuit according to some embodiments;

[0021] Fig.15 is a block diagram schematically illustrating an example of a computer system for providing a semiconductor device and method of an embodiment of the present disclosure according to some embodiments;

[0022] Fig.16 is a block diagram schematically illustrating a semiconductor device manufacturing system and its associated semiconductor device manufacturing process according to some embodiments.

[0023]

Explanation of symbols

[0024] 20: Semiconductor devices

[0025] 22: Sensing circuit

[0026] 24: Sense Amplifier

[0027] 26:Memory Array

[0028] 28: Row decoder circuit

[0029] 30: Column decoder circuit

[0030] 32a~32n: Line

[0031] 34a~34n: Column lines

[0032] 36: Control circuit

[0033] 38: Conductive path

[0034] 40: Conductive path

[0035] 42: Memory array conductive path

[0036] 44: Memory array conductive path

[0037] 46: First charging circuit

[0038] 48: Second charging circuit

[0039] 50: First memory unit

[0040] 52: Second memory unit

[0041] 54: Pre-charging and equalization circuit

[0042] 56: Data output circuit

[0043] 60: first NMOS access control transistor

[0044] 62: First storage capacitor

[0045] 64: Second NMOS access control transistor

[0046] 66: Second storage capacitor

[0047] 68: First NMOS channel gate transistor

[0048] 70: Second NMOS channel gate transistor

[0049] 72: First NMOS sense amplifier transistor

[0050] 74: First PMOS sense amplifier transistor

[0051] 76: Second NMOS sense amplifier transistor

[0052] 78: Second PMOS sense amplifier transistor

[0053] 80:NMOS sense amplifier enable transistor

[0054] 82: PMOS sense amplifier enable transistor

[0055] 84: First NMOS pre-charge transistor

[0056] 86: Second NMOS pre-charge transistor

[0057] 88:NMOS Balance Transistor

[0058] 90: first NMOS output transistor

[0059] 92: Second NMOS output transistor

[0060] 100: First switch

[0061] 102: Second switch

[0062] 106: x-axis

[0063] 108:y-axis

[0064] 110: x-axis

[0065] 112:y-axis

[0066] 114: first PMOS channel gate transistor

[0067] 116: second PMOS channel gate transistor

[0068] 120: First CMOS channel gate

[0069] 122: Second CMOS channel gate

[0070] 126: first NMOS transistor

[0071] 128: Second NMOS transistor

[0072] 130: third NMOS transistor

[0073] 132: Fourth NMOS transistor

[0074] 136: First Multiplexer

[0075] 138: Second multiplexer

[0076] 150~156: Steps of the method

[0077] 200: Computer Systems

[0078] 202: Processor

[0079] 204: Non-transitory computer readable storage medium

[0080] 206: Instructions

[0081] 208: Manufacturing Tools

[0082] 210: Bus

[0083] 212:I / O interface

[0084] 214: Network interface

[0085] 216: Network

[0086] 218: Database

[0087] 220:UI

[0088] 222:Semiconductor device manufacturing system

[0089] 224: Design Studio

[0090] 226: Masking Room

[0091] 228:Semiconductor device fab

[0092] 230:Semiconductor device design layout

[0093] 232: Data Preparation

[0094] 234:Mask Manufacturing

[0095] 236: Mask

[0096] 238:Semiconductor Wafer

[0097] 240: Wafer Manufacturing

[0098] 242:Semiconductor structure or semiconductor device

[0099] BL: Bit Line

[0100] BLB: Complementary Bit Line

[0101] BL_EXT: External bit line voltage

[0102] BLB_EXT: External complementary bit line voltage

[0103] BL / BLB_C_EN: Charging enable signal

[0104] BL / BLB_C_ENB: Complementary charging enable signal

[0105] BLEQ_EN: Bit line equalization enable signal

[0106] CSL: Column select line signal

[0107] DL: Data line

[0108] DLB: complementary data line

[0109] MUX: Multiplexer

[0110] SAEN: Sense amplifier enable signal

[0111] SAENB: Complementary Sense Amplifier Enable Signal

[0112] VBLEQ: Equalized bit line voltage

[0113] VCC: voltage

[0114] VCC / 2: voltage

[0115] WL1: word line signal

[0116] WL2: word line signal

[0117] YDEC:Y decoding signal DETAILED DESCRIPTION

[0118] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify an embodiment of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0119] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0120] During standby mode, the DRAM provides an equalizing precharge voltage to the BL and BLB of the SA. When reading data from a memory cell, the selected word line activates the selected access control transistor, thereby transferring the data voltage on the corresponding capacitor to one of the BL and BLB. The other of the BL and BLB provides the equalizing precharge voltage as a reference voltage. In this configuration, it is difficult to check the functionality of the SA without using data from the memory cell. In addition, since both the BL and BLB are charged to the same voltage, it is difficult to determine the offset voltage of the SA and the sensing margin of the SA.

[0121] The disclosed embodiments provide an integrated circuit, which includes a SA having a BL and a BLB, a first charging circuit connected to the BL, and a second charging circuit connected to the BLB. The first charging circuit receives one or more enable signals and provides a first voltage to the BL in response to the one or more enable signals, and the second charging circuit receives one or more enable signals and provides a second voltage to the BLB in response to the one or more enable signals. The first charging circuit and the second charging circuit can provide different voltages to the BL and the BLB.

[0122] The disclosed embodiments further provide that at least one of the first charging circuit and the second charging circuit is an n-type channel gate, a p-type channel gate, a CMOS channel gate, a multiplexer, or includes a decoder gate.

[0123] Advantages of the integrated circuit include testing functionality of the SA without using memory cells; determining the offset of the SA; determining the sensing margin of the SA; and measuring leakage current of the BL, BLB, and storage nodes such as storage node capacitors.

[0124] Figure 1 2 is a diagram schematically illustrating a semiconductor device 20 including a sensing circuit 22 for providing different voltages to the BL and BLB of the SA 24 according to some embodiments. The semiconductor device 20 includes a memory device. In some embodiments, the semiconductor device 20 includes a DRAM. In some embodiments, the semiconductor device 20 includes a 1T1C memory array. In some embodiments, the semiconductor device 20 is an integrated circuit.

[0125] The semiconductor device 20 includes a memory array 26, a row decoder circuit 28, and a column decoder circuit 30. The memory array 26 includes memory cells, such as 1T1C memory cells, arranged in an xy grid. The row decoder circuit 28 is electrically connected to the memory array 26 through row lines 32a-32n extending in the x direction. The column decoder circuit 30 is electrically connected to the memory array 26 through column lines 34a-34n extending in the y direction. The rows extend along the x-axis of the xy grid of the memory array 26, and the columns extend along the y-axis.

[0126] The semiconductor device 20 includes a control circuit 36 ​​electrically connected to the row decoder circuit 28 and the column decoder circuit 30 through conductive paths 38 and 40. The row decoder circuit 28 receives and decodes the row address, and the column decoder circuit 30 receives and decodes the column address. In addition, the row decoder circuit 28 and the column decoder circuit 30 receive instructions from the control circuit 36 ​​to control the operation of the semiconductor device 20.

[0127] The sensing circuit 22 is electrically connected to the memory array 26 through the memory array conductive paths 42 and 44. The sensing circuit 22 includes the SA 24, which includes the BL and the BLB; the first charging circuit 46, which is electrically connected to the BL; and the second charging circuit 48, which is electrically connected to the BLB. The first charging circuit 46 receives one or more enable signals and provides a first voltage to the BL in response to the one or more enable signals, and the second charging circuit 48 receives one or more enable signals and provides a second voltage to the BLB in response to the one or more enable signals. The first charging circuit 46 and the second charging circuit 48 can provide different voltages to the BL and the BLB. The sensing circuit 22 provides and receives data via a data line (DL) and a complementary data line bar (DLB).

[0128] Figure 2is a diagram schematically illustrating a sensing circuit 22 connected to a first memory cell 50 and a second memory cell 52 according to some embodiments. The sensing circuit 22 includes a SA 24, a first charging circuit 46, a second charging circuit 48, a pre-charge and equalization circuit 54, and a data output circuit 56.

[0129] The first memory cell 50 is electrically connected to the first charging circuit 46 and the SA 24 through the BL, and the second memory cell 52 is electrically connected to the second charging circuit 48 and the SA 24 through the BLB. The SA 24 is further electrically connected to the pre-charging and equalizing circuit 54 and the data output circuit 56 through the BL and the BLB. In some embodiments, at least one of the first memory cell 50 and the second memory cell 52 is a 1T1C memory cell.

[0130] When reading data from one of the first memory cell 50 and the second memory cell 52, such as from the first memory cell 50, the precharge and equalization circuit 54 is enabled to provide the equalized bit line voltage VBLEQ to each of BL and BLB. Next, the first memory cell 50 is connected to BL, so that the data stored in the first memory cell 50 causes the voltage on BL to increase or decrease relative to BLB. SA 24 detects the difference and latches the data from the first memory cell 50. The data output circuit 56 outputs the data to DL and DLB. Both the first charging circuit 46 and the second charging circuit 48 are not enabled to read data from one of the first memory cell 50 and the second memory cell 52.

[0131] When writing data to the first memory cell 50 and the second memory cell 52, the data may be provided to the BL and BLB through the data output circuit 56 and latched into the SA 24. The latched data is provided to the first memory cell 50 or the second memory cell 52 and stored in the selected memory cell. Both the first charging circuit 46 and the second charging circuit 48 are not activated to write data to one of the first memory cell 50 and the second memory cell 52.

[0132] In the operation of the first charging circuit 46 and the second charging circuit 48, the first charging circuit 46 receives one or more enable signals and provides a first voltage to BL in response to the one or more enable signals. In addition, the second charging circuit 48 receives one or more enable signals and provides a second voltage to BLB in response to the one or more enable signals. The first charging circuit 46 and the second charging circuit 48 can provide different voltages to BL and BLB.

[0133] In addition, the first charging circuit 46 and the second charging circuit 48 can provide voltages on BL and BLB to test the functionality of SA 24 without using data from the memory cells; determine the offset of SA 24; determine the sensing margin of SA 24; and measure the leakage current of BL, BLB, and the storage nodes of the first memory cell 50 and the second memory cell 52.

[0134] Figure 3 is a diagram schematically illustrating an example of a sensing circuit 22, a first memory cell 50, and a second memory cell 52 according to some embodiments. The sensing circuit 22 includes a SA 24, a first charging circuit 46, a second charging circuit 48, a pre-charging and equalizing circuit 54, and a data output circuit 56.

[0135] The first memory cell 50 is a 1T1C memory cell, which includes a first NMOS access control transistor 60 and a first storage capacitor 62. One end of the drain / source path of the first NMOS access control transistor 60 is electrically connected to the BL of the sensing circuit 22, and the other end is electrically connected to one end of the first storage capacitor 62. The other end of the first storage capacitor 62 is connected to receive a memory cell reference voltage of voltage VCC / 2. The gate of the first NMOS access control transistor 60 receives a word line signal WL1.

[0136] The second memory cell 52 is a 1T1C memory cell, which includes a second NMOS access control transistor 64 and a second storage capacitor 66. One end of the drain / source path of the second NMOS access control transistor 64 is electrically connected to the BLB of the sensing circuit 22, and the other end is electrically connected to one end of the second storage capacitor 66. The other end of the second storage capacitor 66 is connected to receive a memory cell reference voltage of voltage VCC / 2. The gate of the second NMOS access control transistor 64 receives the word line signal WL2.

[0137] The first memory cell 50 is electrically connected to the first charging circuit 46 through BL. The first charging circuit 46 includes a first NMOS channel gate transistor 68. One end of the drain / source path of the first NMOS channel gate transistor 68 receives the external bit line voltage BL_EXT, and the other end is electrically connected to BL. The gate of the first NMOS channel gate transistor 68 receives the charging enable signal BL / BLB_C_EN.

[0138] The second memory cell 52 is electrically connected to the second charging circuit 48 through BLB. The second charging circuit 48 includes a second NMOS channel gate transistor 70. One end of the drain / source path of the second NMOS channel gate transistor 70 receives the external complementary bit line voltage BLB_EXT, and the other end is electrically connected to BLB. The gate of the second NMOS channel gate transistor 70 receives the charging enable signal BL / BLB_C_EN. In other embodiments, the first charging circuit 46 and the second charging circuit 48 receive different enable signals.

[0139] SA 24 includes a first NMOS SA transistor 72 and a first PMOS SA transistor 74 in a first cross-coupled inverter, and a second NMOS SA transistor 76 and a second PMOS SA transistor 78 in a second cross-coupled inverter. The drain / source path of the first NMOS SA transistor 72 is electrically coupled to BL at one end, and is electrically coupled to the drain / source path of the second NMOS SA transistor 76 and the drain / source path of the NMOS SA enable transistor 80 at the other end. The other end of the drain / source path of the second NMOS SA transistor 76 is electrically connected to BLB, and the other end of the drain / source path of the NMOS SA enable transistor 80 is electrically connected to a reference such as ground. The drain / source path of the first PMOS SA transistor 74 is electrically coupled to BL at one end, and is electrically coupled to the drain / source path of the second PMOS SA transistor 78 and the drain / source path of the PMOS SA enable transistor 82 at the other end. The other end of the drain / source path of the second PMOS SA transistor 78 is electrically connected to BLB, and the other end of the drain / source path of the PMOS SA enable transistor 82 is electrically connected to a power source such as voltage VCC. The gates of the first NMOS SA transistor 72 and the first PMOS SA transistor 74 are connected to BLB, and the gates of the second NMOS SA transistor 76 and the second PMOS SA transistor 78 are connected to BL. In addition, the gate of the NMOS SA enable transistor 80 receives the SA enable signal SAEN, and the gate of the PMOS SA enable transistor 82 receives the complementary SA enable signal SAENB.

[0140] The precharge and equalization circuit 54 includes a first NMOS precharge transistor 84, a second NMOS precharge transistor 86, and an NMOS equalization transistor 88. The drain / source path of the first NMOS precharge transistor 84 is electrically coupled to BL at one end, and is electrically coupled to the drain / source path of the second NMOS precharge transistor 86 at the other end and receives the bit line equalization voltage VBLEQ. The other end of the drain / source path of the second NMOS precharge transistor 86 is electrically connected to BLB. The drain / source path of the NMOS equalization transistor 88 is electrically coupled to BL at one end, and is electrically coupled to BLB at the other end. The gates of the first NMOS precharge transistor 84, the second NMOS precharge transistor 86, and the NMOS equalization transistor 88 are connected to receive the bit line equalization enable signal BLEQ_EN.

[0141] The data output circuit 56 includes a first NMOS output transistor 90 and a second NMOS output transistor 92. One side of the drain / source path of the first NMOS output transistor 90 is electrically connected to BL, and the other end is electrically connected to DL. In addition, one end of the drain / source path of the second NMOS transistor 92 is electrically connected to BLB, and the other end is electrically connected to DLB. The gates of the first NMOS output transistor 90 and the second NMOS output transistor 92 are electrically connected to receive the column selection line signal CSL.

[0142] When reading data from one of the first memory cell 50 and the second memory cell 52, such as from the first memory cell 50, the precharge and equalization circuit 54 receives the active high bit line equalization enable signal BLEQ_EN biased on the first NMOS precharge transistor 84 and the second NMOS precharge transistor 86 to provide the bit line equalization voltage VBLEQ to BL and BLB. In addition, the NMOS equalization transistor 88 is biased on to equalize the voltages on BL and BLB.

[0143] Next, the bit line equalization enable signal BLEQ_EN is set low to bias off the first NMOS pre-charge transistor 84, the second NMOS pre-charge transistor 86, and the NMOS equalization transistor 88. The word line signal WL1 is set to a high voltage to bias on the first NMOS access control transistor 60, which connects the first storage capacitor 62 to BL and transfers the voltage stored on the first storage capacitor 62 to BL, such as a voltage above the voltage VCC / 2 if the data is a one, and a voltage below the voltage VCC / 2 if the data is a zero. This causes the voltage on BL to increase or decrease relative to BLB at the bit line equalization voltage VBLEQ. SA 24 detects the different voltages on BL and BLB and latches the data through cross-coupled inverters and SA enable signal SAEN and complementary SA enable signal SAENB. The data output circuit 56 receives the active high column select line signal CSL biased on the first NMOS output transistor 90 and the second NMOS output transistor 92, and outputs the data on DL and DLB. Both the first charging circuit 46 and the second charging circuit 48 are inactivated to read data from one of the first memory cell 50 and the second memory cell 52 .

[0144] When writing data to the first memory cell 50 and the second memory cell 52, the data output circuit 56 receives the active high column select line signal CSL biased on the first NMOS output transistor 90 and the second NMOS output transistor 92, so that the data on DL and DLB are transferred to BL and BLB, respectively, and latched into SA 24. The word line signal WL1 or the word line signal WL2 is set high to access the first memory cell 50 or the second memory cell 52, and the data is stored on the storage capacitor of the selected memory cell. Both the first charging circuit 46 and the second charging circuit 48 are not activated to write data into one of the first memory cell 50 and the second memory cell 52.

[0145] In the operation of the first charging circuit 46 and the second charging circuit 48, the first charging circuit 46 receives an active high charging enable signal BL / BLB_C_EN, which biases on the first NMOS channel gate transistor 68 and provides the external bit line voltage BL_EXT to BL; the second charging circuit 48 receives an active high charging enable signal BL / BLB_C_EN, which biases on the second NMOS channel gate transistor 70 and provides the external bit line voltage BLB_EXT to BLB. As described below, in order to provide different functions, the first charging circuit 46 and the second charging circuit 48 provide different voltages including voltage ranges to BL and / or BLB.

[0146] The first charging circuit 46 and the second charging circuit 48 provide voltages on BL and BLB to test the functionality of SA 24 without using data from the memory cells; to determine the offset of SA 24; to determine the sensing margin of SA 24; and to measure the leakage current of BL, BLB, and the storage capacitors of the first memory cell 50 and the second memory cell 52.

[0147] In this example, the first charging circuit 46 and the second charging circuit 48 include n-type channel gates, i.e., NMOS transistors. In other embodiments, at least one of the first charging circuit 46 and the second charging circuit 48 may include a different type of channel gate, such as a p-type channel gate. In some embodiments, at least one of the first charging circuit 46 and the second charging circuit 48 includes a CMOS channel gate. In some embodiments, at least one of the first charging circuit 46 and the second charging circuit 48 includes a multiplexer. In some embodiments, at least one of the first charging circuit 46 and the second charging circuit 48 includes an X or Y decode gating.

[0148] Figure 4 is a diagram schematically illustrating a first memory cell 50, a second memory cell 52, and a sensing circuit 22 configured for testing the SA 24 according to some embodiments. The first memory cell 50, the second memory cell 52, and the sensing circuit 22 are used to test the functionality of the SA 24 and determine one or more offset voltages of the SA 24 without using data from one of the first memory cell 50 and the second memory cell 52.

[0149] The first memory cell 50 is a 1T1C memory cell including a first NMOS access control transistor 60 and a first storage capacitor 62. The second memory cell 52 is a 1T1C memory cell including a second NMOS access control transistor 64 and a second storage capacitor 66. The gate of the first NMOS access control transistor 60 receives a word line signal WL1, and the gate of the second NMOS access control transistor 64 receives a word line signal WL2.

[0150] The first memory cell 50 is electrically connected to the first charging circuit 46 through BL. The first charging circuit 46 includes a first switch or channel gate 100 connected to BL at one end and receiving an external bit line voltage BL_EXT at another end.

[0151] The second memory cell 52 is electrically connected through BLB to the second charging circuit 48. The second charging circuit 48 includes a second switch or channel gate 102 connected to BLB at one end and receiving the external complementary bit line voltage BLB_EXT at the other end.

[0152] To test the functionality of SA 24 and determine one or more offset voltages of SA 24 without using data from one of the first memory cell 50 and the second memory cell 52, each of the word line signals WL1 and WL2 is set to a low voltage to bias off the first access control transistor 60 and the second access control transistor 64, which disconnects the first storage capacitor 62 and the second storage capacitor 66 from BL and BLB, respectively. The external bit line voltage BL_EXT is set to a precharge voltage of VBLEQ, such as 0.4 volts, and the first switch 100 is closed to provide the precharge voltage of VBLEQ to BL. Next, the second switch 102 is closed and the external complementary bit line voltage BLB_EXT rises from 0 volts to the voltage VCC.

[0153] If SA 24 is operating normally, when the voltage on BLB matches and rises to a precharge voltage (such as 0.4 volts) higher than VBLEQ on BL, SA 24 switches from the voltage of the high output voltage DL and the low complementary data line DLB to the voltage of the low output voltage DL and the high complementary data line DLB. In addition, when SA 24 switches states, the offset voltage of SA 24 is determined based on the difference between the BL and BLB voltages. In other embodiments, the external complementary bit line voltage BLB_EXT can drop from the voltage VCC to 0 volts.

[0154] Figure 5 is a schematic diagram of a method for Figure 4 FIG. 1 is a graph showing the relationship between the voltage of the complementary data line DLB and the BLB voltage for the test configuration of the sensing circuit 22 of FIG.

[0155] In this example, BL has a precharge voltage of 0.4 volts and the BLB voltage rises from 0.1 volts to 0.7 volts. When the BLB voltage is less than 0.4 volts, the voltage of the complementary data line DLB is at a low voltage. When the BLB voltage approaches 0.4 volts on BL, the voltage of the complementary data line DLB begins to rise. When the voltage of BLB matches and rises to a BL voltage higher than 0.4 volts, SA24 changes state and the output voltage DL rises to a high voltage. Therefore, SA 24 operates normally.

[0156] Figure 6 is a schematic diagram illustrating a method according to some embodiments Figure 41 is a diagram of the operation of the test configuration of the sensing circuit 22 of FIG. Each of the word line signals, including each of the word line signals WL1 and WL2, is set to a low voltage to bias off the first access control transistor 60 and the second access control transistor 64, which disconnects the first storage capacitor 62 and the second storage capacitor 64 from BL and BLB, respectively. BL is set to a bit line equalization voltage VBLEQ, such as 0.4 volts, and the first switch 100 is closed to provide the bit line equalization voltage VBLEQ to BL. Next, the second switch 102 is closed and the BLB voltage gradually increases from a low voltage (such as 0.1 volts) lower than the bit line equalization voltage VBLEQ to a high voltage (such as 0.7 volts) higher than the bit line equalization voltage VBLEQ.

[0157] As the BLB voltage gradually increases to a higher voltage, the operation of SA 24 provides an output voltage DL that is one (high) if the BLB voltage is less than the BL voltage and zero (low) if the BLB voltage is greater than the BL voltage. The offset of SA 24 is determined by incrementally increasing the BLB voltage.

[0158] Figure 7 FIG. 2 is a diagram schematically illustrating a first memory cell 50, a second memory cell 52, and a sensing circuit 22 for determining a read sensing margin of SA 24 according to some embodiments. The first memory cell 50, the second memory cell 52, and the sensing circuit 22 are used to determine a read 0 sensing margin and a read 1 sensing margin.

[0159] The first memory cell 50 is a 1T1C memory cell including a first NMOS access control transistor 60 and a first storage capacitor 62. The second memory cell 52 is a 1T1C memory cell including a second NMOS access control transistor 64 and a second storage capacitor 66. The gate of the first NMOS access control transistor 60 receives a word line signal WL1, and the gate of the second NMOS access control transistor 64 receives a word line signal WL2.

[0160] The first memory cell 50 is electrically connected to the first charging circuit 46 through BL, and the second memory cell 52 is electrically connected to the second charging circuit 48 through BLB. The first charging circuit 46 includes a first switch 100 connected to BL at one end and receiving an external bit line voltage BL_EXT at the other end. The second charging circuit 48 includes a second switch 102 connected to BLB at one end and receiving an external complementary bit line voltage BLB_EXT at the other end.

[0161] To determine the read sensing margin of SA 24, the external bit line voltage BL_EXT is set to a precharge voltage of VBLEQ, such as 0.4 volts, and the first switch 100 is closed to provide the precharge voltage of VBLEQ to BL. The word line signal WL1 is set to a high voltage to bias on the first access control transistor 60 and provide the data voltage of zero (0) or one (1) stored on the first storage capacitor 62 to BL. The word line signal WL2 is set to a low voltage to bias off the second access control transistor 64, which disconnects the second storage capacitor 66 from BLB. Next, the second switch 102 is closed and the external complementary bit line voltage BLB_EXT rises from 0 volts to the voltage VCC. When the voltage on BLB matches and rises above the voltage on BL, SA 24 switches from the voltage of the high output voltage DL and the low complementary data line DLB to the voltage of the low output voltage DL and the high complementary data line DLB. In other embodiments, the external complementary bit line voltage BLB_EXT can drop from the voltage VCC to 0 volts.

[0162] To determine the read 0 sensing margin, the data voltage of zero (0) stored on the first storage capacitor 62 is combined with a precharge voltage of VBLEQ, such as 0.4 volts, which reduces the voltage on BL. When the voltage on BLB matches the voltage on BL, the SA 24 switches from the voltage of the high output voltage DL and the low complementary data line DLB to the voltage of the low output voltage DL and the high complementary data line DLB. The difference between this switching voltage and the precharge voltage of VBLEQ is the read 0 sensing margin.

[0163] To determine the read 1 sensing margin, the data voltage of one (1) stored on the first storage capacitor 62 is combined with a precharge voltage of VBLEQ, such as 0.4 volts, which increases the voltage on BL. When the voltage on BLB matches the voltage on BL, the SA 24 switches from the voltage of the high output voltage DL and the low complementary data line DLB to the voltage of the low output voltage DL and the high complementary data line DLB. The difference between this switching voltage and the precharge voltage of VBLEQ is the read 1 sensing margin.

[0164] Figure 8 is a schematic diagram of a method for determining Figure 7 1 is a graph showing the relationship between the voltage of the complementary data line DLB and the BLB voltage for the sensing margin of the SA 24 in the sensing circuit 22. The BLB voltage is on the x-axis 110 and the voltage of the complementary data line DLB is on the y-axis 112. In this example, the precharge voltage of VBLEQ is 0.4 volts and the BLB voltage rises from 0.1 volt to 0.7 volts.

[0165] To determine the read 0 sensing margin, the data voltage of zero (0) stored on the first storage capacitor 62 is combined with the precharge voltage of 0.4 volts to reduce the voltage on BL to about 0.25 volts. When the voltage on BLB matches the voltage on BL, the SA 24 switches from the voltage of the low complementary data line DLB to the voltage of the high complementary data line DLB. The difference between this switching voltage of about 0.25 volts and the precharge voltage of 0.4 volts is a read 0 sensing margin of about 0.15 volts.

[0166] To determine the read 1 sensing margin, the data voltage of one (1) stored on the first storage capacitor 62 is combined with the precharge voltage of 0.4 volts to raise the voltage on BL to about 0.625 volts. When the voltage on BLB matches the voltage on BL, the SA 24 switches from the voltage of the low complementary data line DLB to the voltage of the high complementary data line DLB. The difference between this switching voltage of about 0.625 volts and the precharge voltage of 0.4 volts is a read 1 sensing margin of about 0.225 volts.

[0167] Fig. 9 is a diagram schematically illustrating a first memory cell 50 , a second memory cell 52 , and a sensing circuit 22 for measuring leakage currents of BL and BLB and measuring leakage currents of a first storage capacitor 62 and a second storage capacitor 66 according to some embodiments.

[0168] The first memory cell 50 is a 1T1C memory cell including a first NMOS access control transistor 60 and a first storage capacitor 62. The second memory cell 52 is a 1T1C memory cell including a second NMOS access control transistor 64 and a second storage capacitor 66. The gate of the first NMOS access control transistor 60 receives a word line signal WL1, and the gate of the second NMOS access control transistor 64 receives a word line signal WL2.

[0169] The first memory cell 50 is electrically connected to the first charging circuit 46 through BL, and the second memory cell 52 is electrically connected to the second charging circuit 48 through BLB. The first charging circuit 46 includes a first switch 100 connected to BL at one end and receiving an external bit line voltage BL_EXT at the other end. The second charging circuit 48 includes a second switch 102 connected to BLB at one end and receiving an external complementary bit line voltage BLB_EXT at the other end.

[0170] To determine the leakage current of BL, the word line signal WL1 is set to a low voltage to bias off the first access control transistor 60, which disconnects the first storage capacitor 62 from BL. The external bit line voltage BL_EXT is set to a high voltage such as voltage VCC, and the first switch 100 is closed to provide the external bit line voltage BL_EXT to BL. Then, the leakage current of BL is measured.

[0171] To determine the leakage current of BLB, the word line signal WL2 is set to a low voltage to bias off the second access control transistor 64, which disconnects the second storage capacitor 66 from BLB. The external complementary bit line voltage BLB_EXT is set to a high voltage such as voltage VCC, and the second switch 102 is closed to provide the external complementary bit line voltage BLB_EXT to BLB. Then, the leakage current of BLB is measured.

[0172] To determine the leakage current of the first storage capacitor 62, the word line signal WL1 is set to a high voltage to bias on the first access control transistor 60, which connects the first storage capacitor 62 to BL. The external bit line voltage BL_EXT is set to a high voltage such as the voltage VCC, and the first switch 100 is closed to provide the external bit line voltage BL_EXT to BL and the first storage capacitor 62. Then, the leakage current of the first storage capacitor 62 is measured.

[0173] To determine the leakage current of the second storage capacitor 66, the word line signal WL2 is set to a high voltage to bias on the second access control transistor 64, which connects the second storage capacitor 66 to BLB. The external complementary bit line voltage BLB_EXT is set to a high voltage such as the voltage VCC, and the second switch 102 is closed to provide the external bit line voltage BLB_EXT to BLB and the second storage capacitor 66. Then, the leakage current of the second storage capacitor 66 is measured.

[0174] Fig.10 1 is a diagram schematically illustrating a first PMOS channel-gate transistor 114 and a second PMOS channel-gate transistor 116 in a first charging circuit 46 and a second charging circuit 48, respectively, according to some embodiments. In some embodiments, the sensing circuit 22 includes the first PMOS channel-gate transistor 114 and the second PMOS channel-gate transistor 116 instead of the first NMOS channel-gate transistor 68 and the second NMOS channel-gate transistor 70 (e.g., Figure 3 ).

[0175] The first charging circuit 46 includes a first PMOS channel gate transistor 114. One end of the drain / source path of the first PMOS channel gate transistor 114 receives the external bit line voltage BL_EXT and the other end is electrically connected to BL. The gate of the first PMOS channel gate transistor 114 receives the complementary charging enable signal BL / BLB_C_ENB.

[0176] The second charging circuit 48 includes a second PMOS channel gate transistor 116. One end of the drain / source path of the second PMOS channel gate transistor 116 receives the external complementary bit line voltage BLB_EXT, and the other end is electrically connected to BLB. The gate of the second PMOS channel gate transistor 116 receives the complementary charging enable signal BL / BLB_C_ENB. In other embodiments, the first charging circuit 46 and the second charging circuit 48 receive different enable signals.

[0177] Fig.11 1 is a diagram schematically illustrating a first CMOS channel gate 120 and a second CMOS channel gate 122 in a first charging circuit 46 and a second charging circuit 48, respectively, according to some embodiments. In some embodiments, the sensing circuit 22 includes the first CMOS channel gate 120 and the second CMOS channel gate 122 instead of the first NMOS channel gate transistor 68 and the second NMOS channel gate transistor 70 (e.g., Figure 3 ).

[0178] The first charging circuit 46 includes a first CMOS channel gate 120. One end of the first CMOS channel gate 120 receives the external bit line voltage BL_EXT, and the other end is electrically connected to BL. The first CMOS channel gate 120 includes an NMOS input receiving a charging enable signal BL / BLB_C_EN and a PMOS input receiving a complementary charging enable signal BL / BLB_C_ENB.

[0179] The second charging circuit 48 includes a second CMOS channel gate 122. One end of the second CMOS channel gate 122 receives the external complementary bit line voltage BLB_EXT, and the other end is electrically connected to BLB. The second CMOS channel gate 122 includes an NMOS input receiving the charging enable signal BL / BLB_C_EN and a PMOS input receiving the complementary charging enable signal BL / BLB_C_ENB. In other embodiments, the first charging circuit 46 and the second charging circuit 48 receive different enable signals.

[0180] Fig.122 is a diagram schematically illustrating additional Y-decoding gating in the first charging circuit 46 and the second charging circuit 48 according to some embodiments. In some embodiments, the sensing circuit 22 includes the first charging circuit 46 and the second charging circuit 48 with additional Y-decoding gating instead of the first NMOS channel gate transistor 68 and the second NMOS channel gate transistor 70 (e.g., Figure 3 ).

[0181] The first charging circuit 46 includes a first NMOS transistor 126 and a second NMOS transistor 128. One end of the drain / source path of the first NMOS transistor 126 receives the external bit line voltage BL_EXT, and the other end is electrically connected to one end of the drain / source path of the second NMOS transistor 128. The other end of the second NMOS transistor 128 is electrically connected to BL. The gate of the first NMOS transistor 126 receives the Y decoding signal YDEC, and the gate of the second NMOS transistor 128 receives the charging enable signal BL / BLB_C_EN.

[0182] The second charging circuit 48 includes a third NMOS transistor 130 and a fourth NMOS transistor 132. One end of the drain / source path of the third NMOS transistor 130 receives the external complementary bit line voltage BLB_EXT, and the other end is electrically connected to one end of the drain / source path of the fourth NMOS transistor 132. The other end of the fourth NMOS transistor 132 is electrically connected to BLB. The gate of the third NMOS transistor 130 receives the Y decoding signal YDEC, and the gate of the fourth NMOS transistor 132 receives the charging enable signal BL / BLB_C_EN. In other embodiments, the first charging circuit 46 and the second charging circuit 48 receive different enable signals.

[0183] Fig.13 1 is a diagram schematically illustrating a first multiplexer 136 and a second multiplexer 138 in a first charging circuit 46 and a second charging circuit 48, respectively, according to some embodiments. In some embodiments, the sensing circuit 22 includes the first multiplexer 136 and the second multiplexer 138 instead of the first NMOS channel gate transistor 68 and the second NMOS channel gate transistor 70 (e.g., Figure 3 In some embodiments, at least one of the first multiplexer 136 and the second multiplexer 138 includes a combination of circuits including NMOS channel gates, PMOS channel gates, and / or CMOS channel gates.

[0184] The first charging circuit 46 includes a first multiplexer 136. One side of the first multiplexer 136 receives an external bit line voltage BL_EXT, and the other side is electrically connected to BL. The first multiplexer 136 receives a control signal to control the operation of the first multiplexer 136. The control signal includes a feature enable signal and / or a partition select signal. The feature enable signal includes a mode enable signal, a compute-in-memory (CIM) signal, a machine learning signal, and an artificial intelligence application signal. The partition select signal includes different macro signals, different layer signals of a 3D array, an X address decode signal, and a Y address decode signal.

[0185] The second charging circuit 48 includes a second multiplexer 138. One side of the second multiplexer 138 receives the external complementary bit line voltage BLB_EXT, and the other side is electrically connected to BLB. The second multiplexer 138 receives a control signal to control the operation of the second multiplexer 138. The control signal includes a feature enable signal and / or a partition select signal. The feature enable signal includes a mode enable signal, a CIM signal, a machine learning signal, and an artificial intelligence application signal. The partition select signal includes different macro signals, different layer signals of the 3D array, an X address decoding signal, and a Y address decoding signal. In other embodiments, the first charging circuit 46 and the second charging circuit 48 receive different enable signals.

[0186] Fig.14 is a diagram schematically illustrating a method of operating a semiconductor device, such as sensing circuit 22 , according to some embodiments.

[0187] At 150, the method includes receiving a first enable signal at a first circuit connected to the BL of the SA, and at 152, the method includes receiving a second enable signal at a second circuit connected to the BLB of the SA. In some embodiments, the first circuit is a first charging circuit 46 and the second circuit is a second charging circuit 48. In some embodiments, the SA is the SA 24. In some embodiments, the first enable signal and the second enable signal are the same signal. In some embodiments, the first enable signal and the second enable signal are different signals.

[0188] At 154 , the method includes providing a first voltage from the first circuit to BL in response to receiving the first enable signal, and at 156 , the method includes providing a second voltage from the second circuit to BLB in response to receiving the second enable signal.

[0189] In some embodiments, providing the first voltage and providing the second voltage includes providing one of the first voltage and the second voltage as a constant voltage and providing the other of the first voltage and the second voltage as a voltage range from a low voltage to a high voltage and / or from a high voltage to a low voltage to switch the state of SA.

[0190] In some embodiments, the method includes enabling the first circuit and the second circuit; starting a first access control transistor connected to BL and a first storage capacitor; providing a constant voltage of the first voltage to BL; providing a data voltage from the first storage capacitor to BL; and raising the second voltage from a low voltage to a high voltage and / or lowering it from a high voltage to a low voltage to switch the state of SA.

[0191] In some embodiments, the method includes enabling a first circuit; disabling a first access control transistor connected between the BL and the first storage capacitor; and providing a first voltage that is a high voltage to the BL to measure a leakage current of the BL. In some embodiments, the method includes enabling a first circuit; activating a first access control transistor connected between the BL and the first storage capacitor, and providing a first voltage that is a high voltage to the BL to measure a leakage current of the first storage capacitor.

[0192] Fig.15 2 is a block diagram schematically illustrating an example of a computer system 200 for providing a semiconductor device and method of an embodiment of the present disclosure according to some embodiments. Some or all of the design, layout, manufacturing, testing, and operation of a semiconductor device, also referred to as a semiconductor circuit, may be performed by or in conjunction with the computer system 200. In some embodiments, the computer system 200 includes an electronic design automation (EDA) system. In some embodiments, the semiconductor device is an IC.

[0193] In some embodiments, system 200 is a general purpose computing device including processor 202 and non-transitory computer readable storage medium 204. Computer readable storage medium 204 may be encoded with, for example, computer program code such as executable instructions 206. Execution of instructions 206 by processor 202 (at least in part) provides tools for implementing some or all of the functionality of system 200, such as pre-layout simulation, post-layout simulation, routing, rerouting, final layout, testing, and operation of semiconductor devices. In addition, manufacturing tools 208 are included to further layout and physically implement the design and manufacture of semiconductor devices. In some embodiments, execution of instructions 206 by processor 202 (at least in part) provides tools for implementing some or all of the functionality of system 200. In some embodiments, system 200 includes a commercial router. In some embodiments, system 200 includes an automatic place and route (APR) system.

[0194] The processor 202 is electrically coupled to the computer-readable storage medium 204 through the bus 210, and is electrically coupled to the input / output (I / O) interface 212 through the bus 210. The network interface 214 is also electrically connected to the processor 202 through the bus 210. The network interface 214 is connected to the network 216, so that the processor 202 and the computer-readable storage medium 204 can be connected to external components using the network 216. The processor 202 is used to execute computer program code or instructions 206 encoded in the computer-readable storage medium 204 to enable the system 200 to perform a part or all of the functions of the system 200, such as providing a semiconductor device and method of an embodiment of the present disclosure and other functions of the system 200. In some embodiments, the processor 202 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0195] In some embodiments, the computer-readable storage medium 204 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system or device or apparatus. For example, the computer-readable storage medium 204 may include semiconductor or solid-state memory, magnetic tape, removable computer disk, random-access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In some embodiments using optical disks, the computer-readable storage medium 204 may include compact disk read only memory (CD-ROM), compact disk read / write memory (CD-R / W), and / or digital video disc (DVD).

[0196] In some embodiments, computer readable storage medium 204 stores computer program code or instructions 206 for causing system 200 to perform some or all of the functions of system 200. In some embodiments, computer readable storage medium 204 also stores information that facilitates performing some or all of the functions of system 200. In some embodiments, computer readable storage medium 204 stores database 218 that includes one or more of a component library, a digital circuit cell library, and a database.

[0197] System 200 includes an I / O interface 212 coupled to external circuitry. In some embodiments, I / O interface 212 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor keys for conveying information and commands to processor 202.

[0198] The network interface 214 is coupled to the processor 202 and allows the system 200 to communicate with a network 216 to which one or more other computer systems are connected. The network interface 214 may include a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In some embodiments, some or all of the functions of the system 200 may be performed in two or more systems similar to the system 200.

[0199] The system 200 is configured to receive information via the I / O interface 212. The information received via the I / O interface 212 includes one or more of instructions, data, design rules, libraries of components and units, and / or other parameters for processing by the processor 202. The information is transmitted to the processor 202 via the bus 210. In addition, the system 200 is configured to receive information related to a user interface (UI) via the I / O interface 212. This UI information can be stored as UI 220 in the computer-readable storage medium 204.

[0200] In some embodiments, some or all of the functions of system 200 are implemented by a separate software application for execution by a processor. In some embodiments, some or all of the functions of system 200 are implemented in a software application that is part of an additional software application. In some embodiments, some or all of the functions of system 200 are implemented as a plug-in for a software application. In some embodiments, at least one of the functions of system 200 is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the functions of system 200 are implemented as a software application used by system 200. In some embodiments, the layout diagram is generated using a tool such as VIRTUOSO purchased from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool.

[0201] In some embodiments, routing, placement, and other processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / embedded storage or memory units, for example, one or more optical disks, such as digital video disks or digital versatile disks (DVDs); magnetic disks, such as hard disks; semiconductor memories, such as ROM and RAM, and memory cards; and the like.

[0202] As described above, embodiments of the system 200 include a fabrication tool 208 for implementing the fabrication process of the system 200. For example, based on the final layout, a photolithography mask may be generated, which is used to fabricate a semiconductor device by the fabrication tool 208.

[0203] Combination Fig.16 Further aspects of device fabrication are disclosed, Fig.16 is a block diagram of a semiconductor device manufacturing system 222 and its associated semiconductor device manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 222 is used to manufacture one or more semiconductor masks and / or at least one component in a layer of a semiconductor device.

[0204] exist Fig.16 , a semiconductor device manufacturing system 222 includes entities such as a design room 224, a mask room 226, and a semiconductor device manufacturer / fab (“Fab”) 228 that interact with each other in the design, development, and manufacturing cycles and / or services associated with manufacturing semiconductor devices, such as the semiconductor devices described herein. The entities in the system 222 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as Ethernet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of the design room 224, the mask room 226, and the semiconductor device fab 228 are owned by a single larger company. In some embodiments, two or more of the design room 224, the mask room 226, and the semiconductor device fab 228 coexist in a common facility and use common resources.

[0205] The design office (or design team) 224 generates a semiconductor device design layout 230. The semiconductor device design layout 230 includes various geometric patterns, or semiconductor device layouts designed for semiconductor devices. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the semiconductor structure to be manufactured. Various layers are combined to form various semiconductor device features. For example, a portion of the semiconductor device design layout 230 includes various semiconductor device features, such as diagonal vias, active regions or regions, gate electrodes, sources, drains, metal wiring, regional vias, and openings for bonding pads to be formed in a semiconductor substrate (such as a silicon wafer) and in various material layers disposed on the semiconductor substrate. The design office 224 implements a design program to form the semiconductor device design layout 230. The semiconductor device design layout 230 is presented in one or more data files having information of the geometric patterns. For example, the semiconductor device design layout 230 can be expressed in a GDSII file format or a DFII file format. In some embodiments, the design process includes one or more of analog circuit design, digital circuit design, logic circuit design, standard cell circuit design, power distribution network (PDN) design including power path design, supply voltage track design, reference voltage track design, placement and routing routines, and physical layout design.

[0206] The mask chamber 226 includes data preparation 232 and mask manufacturing 234. The mask chamber 226 uses the semiconductor device design layout drawing 230 to manufacture one or more masks 236 to be used to manufacture various layers of a semiconductor device or semiconductor structure. The mask library 226 performs mask data preparation 232, wherein the semiconductor device design layout drawing 230 is translated into a representative data file (RDF). The mask data preparation 232 provides the RDF to the mask manufacturing 234. The mask manufacturing 234 includes a mask writer that converts the RDF into an image on a substrate such as a mask (master mask) 236 or a semiconductor wafer 238. The design layout drawing 230 is manipulated by the mask data preparation 232 to conform to the characteristics of the mask writer and / or the standards of the semiconductor device fab 228. In Fig.16 In FIG. 2 , mask data preparation 232 and mask manufacturing 234 are illustrated as separate elements. In some embodiments, mask data preparation 232 and mask manufacturing 234 may be collectively referred to as mask data preparation.

[0207] In some embodiments, mask data preparation 232 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may result from self-diffraction, interference, other process effects, and the like. OPC adjusts semiconductor device design layout 230. In some embodiments, mask data preparation 232 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0208] In some embodiments, mask data preparation 232 includes a mask rule checker (MRC) that checks semiconductor device design layout 230, which has been through a process in OPC using a set of mask generation rules that contain certain geometric and / or connectivity constraints to ensure adequate margins, account for variability in semiconductor manufacturing processes, and the like. In some embodiments, MRC modifies semiconductor device design layout 230 to compensate for the constraints during mask generation 234, which may undo portions of the modifications performed by OPC to satisfy the mask generation rules.

[0209] In some embodiments, mask data preparation 232 includes lithography process checking (LPC), which simulates the process that will be performed by semiconductor device fab 228. LPC simulates this process based on semiconductor device design layout 230 to produce simulated manufactured devices. Process parameters in LPC simulation may include parameters associated with various processes of semiconductor device manufacturing cycle, parameters associated with tools used to manufacture semiconductor devices, and / or other aspects of manufacturing processes. LPC considers various factors such as virtual image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like or combinations thereof. In some embodiments, after the simulated manufactured device has been generated by LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine the semiconductor device design layout 230.

[0210] The above description of mask data preparation 232 has been simplified for the purpose of clarity. In some embodiments, data preparation 232 includes additional features, such as logic operations (LOP) to modify semiconductor device design layout 230 according to manufacturing rules. In addition, the processes applied to semiconductor device design layout 230 during data preparation 232 can be performed in a variety of different orders.

[0211] After the mask data preparation 232 and during the mask manufacturing 234, a mask 236 or a group of masks 236 are manufactured based on the modified semiconductor device design layout 230. In some embodiments, the mask manufacturing 234 includes performing one or more lithography exposures based on the semiconductor device design layout 230. In some embodiments, an electron-beam (e-beam) or multiple electron-beam mechanisms are used to form a pattern on a mask (mask or master mask) 236 based on the modified semiconductor device design layout 230. The mask 236 can be formed by various techniques. In some embodiments, the mask 236 is formed using a binary technique. In some embodiments, the mask pattern includes an opaque area and a transparent area. A radiation beam such as an ultraviolet (UV) beam used to expose an image-sensitive material layer (e.g., a photoresist layer) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask version of mask 236 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque area of ​​the binary mask. In another example, mask 236 is formed using a phase transfer technique. In a phase shift mask (PSM) version of mask 236, various features in the pattern formed on the phase shift mask are used to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. Masks produced by mask manufacturing 234 are used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 238, in etching processes to form various etched regions in semiconductor wafer 238, and / or in other suitable processes.

[0212] Semiconductor device fab 228 includes wafer fabrication 240. Semiconductor device fab 228 is a semiconductor device manufacturing business that includes one or more manufacturing facilities for manufacturing a variety of different semiconductor device products. In some embodiments, semiconductor device fab 228 is a semiconductor foundry. For example, there may be a manufacturing facility for front end of line (FEOL) manufacturing of a plurality of semiconductor device products, while a second manufacturing facility may provide back end of line (BEOL) manufacturing for interconnection and packaging of semiconductor device products, and a third manufacturing facility may provide other services for the foundry business.

[0213] The semiconductor device fab 228 uses the mask 236 manufactured by the mask chamber 226 to manufacture a semiconductor structure or semiconductor device 242 of an embodiment of the present disclosure. Therefore, the semiconductor device fab 228 at least indirectly uses the semiconductor device design layout 230 to manufacture the semiconductor structure or semiconductor device 242 of an embodiment of the present disclosure. In addition, the semiconductor wafer 238 includes a silicon substrate or other appropriate substrate with a material layer formed thereon, and the semiconductor wafer 238 further includes one or more of various doped regions, dielectric features, multi-level interconnects, and the like (formed in subsequent manufacturing steps). In some embodiments, the semiconductor wafer 238 is manufactured by the semiconductor device fab 228 using the mask 236 to form a semiconductor structure or semiconductor device 242 of an embodiment of the present disclosure. In some embodiments, semiconductor device manufacturing includes performing one or more lithography exposures based at least indirectly on the semiconductor device design layout 230.

[0214] Therefore, the disclosed embodiments include a semiconductor device including a SA having a BL and a BLB, a first charging circuit connected to the BL, and a second charging circuit connected to the BLB. The first charging circuit receives one or more enable signals and provides a first voltage to the BL, and the second charging circuit receives the first enable signal and provides a second voltage to the BLB. The first charging circuit and the second charging circuit provide different voltages, voltage ranges, and measurement functions to the BL and the BLB.

[0215] Advantages of the semiconductor device include testing functionality of the SA without using a memory cell; determining one or more offsets of the SA; determining one or more sensing margins of the SA; and measuring leakage current of the BL, BLB, and storage nodes of the memory (such as storage node capacitors).

[0216] According to some embodiments, an integrated circuit includes a SA having an input terminal connected to a BL and a BLB, for storing a data signal and selectively outputting a data signal on at least one of the BL and the BLB in response to a word line signal; a first circuit connected between a first voltage terminal for receiving a first external voltage and the BL and having a first enable terminal for receiving a first enable signal, wherein the first external voltage is different from the data signal; and a second circuit connected between a second voltage terminal for receiving a second external voltage and the BLB and having a second enable terminal for receiving a second enable signal, wherein the second external voltage is different from the data signal and the first external voltage.

[0217] In some embodiments, the first enable signal and the second enable signal are the same enable signal.

[0218] In some embodiments, a circuit includes a memory cell array having a plurality of memory cells, the memory cells including a first memory cell connected to a bit line and a second memory cell connected to a complementary bit line.

[0219] In some embodiments, the first memory cell includes a first access control transistor connected between a bit line and a first storage node, and the second memory cell includes a second access control transistor connected between a complementary bit line and a second storage node.

[0220] In some embodiments, the first circuit receives a first enable signal and provides a first external voltage to the bit line, and the first access control transistor receives a word line signal and provides a data signal from the first storage node to the bit line. The second circuit receives a second enable signal and provides a second external voltage to the complementary bit line. The second external voltage rises from a low voltage to a high voltage and / or falls from a high voltage to a low voltage to switch multiple states of the sense amplifier.

[0221] In some embodiments, the first circuit receives a first enable signal and provides a first external voltage that is a high voltage to the bit line, and the first access control transistor is biased off to measure a leakage current of the bit line; and / or the second circuit receives a second enable signal and provides a second external voltage that is a high voltage to the complementary bit line, and the second access control transistor is biased off to measure a leakage current of the complementary bit line.

[0222] In some embodiments, the first circuit receives a first enable signal and provides a first external voltage that is a high voltage to the bit line, and the first access control transistor is biased on to measure the leakage current of the first storage node; and / or the second circuit receives a second enable signal and provides a second external voltage that is a high voltage to the complementary bit line, and the second access control transistor is biased on to measure the leakage current of the second storage node.

[0223] In some embodiments, one of the first external voltage and the second external voltage is an equilibrated precharge voltage, and the other of the first external voltage and the second external voltage rises from a low voltage to a high voltage and / or falls from a high voltage to a low voltage to switch multiple states of the sense amplifier.

[0224] In some embodiments, a circuit including a precharge and equalize circuit is connected to a bit line and a complementary bit line and provides an equalize voltage to each of the bit line and the complementary bit line in response to an active precharge enable signal.

[0225] In some embodiments, at least one of the first circuit and the second circuit is an n-type channel gate, a p-type channel gate, a CMOS channel gate, a multiplexer, or includes a decoder gate.

[0226] According to a further embodiment, a semiconductor device includes a SA, a memory cell array, a precharge and equalization circuit, a first circuit, and a second circuit. SA is connected to BL and BLB. The memory cell array includes a plurality of memory cells, wherein a first memory cell has a first access control transistor connected to BL and a first storage capacitor, and a second memory cell has a second access control transistor connected to BLB and a second storage capacitor. The precharge and equalization circuit is connected to BL and BLB and is used to provide an equalized precharge voltage to each of BL and BLB in response to an effective precharge enable signal. The first circuit includes a first metal oxide semiconductor field effect transistor having a first drain / source terminal connected to BL, a second drain / source terminal for receiving a first external voltage, and a gate terminal for receiving an enable signal; the second circuit includes a second metal oxide semiconductor field effect transistor having a third drain / source terminal connected to BLB, a fourth drain / source terminal for receiving a second external voltage, and a gate terminal for receiving an enable signal.

[0227] In some embodiments, each of the first MOSFET and the second MOSFET is an n-channel MOSFET.

[0228] In some embodiments, each of the first metal oxide semiconductor field effect transistor and the second metal oxide semiconductor field effect transistor is a p-channel metal oxide semiconductor field effect transistor.

[0229] In some embodiments, the first MOSFET is part of a first CMOS channel gate and the second MOSFET is part of a second CMOS channel gate.

[0230] In some embodiments, the second drain / source terminal of the first metal oxide semiconductor field effect transistor is connected to a fifth metal oxide semiconductor field effect transistor that receives a first external voltage, and the fourth drain / source path of the second metal oxide semiconductor field effect transistor is connected to a sixth metal oxide semiconductor field effect transistor that receives a second external voltage.

[0231] According to still further disclosed aspects, a method of operating a semiconductor device includes receiving a first enable signal at a first circuit connected to a BL of an SA, receiving a second enable signal at a second circuit connected to a BLB of an SA, providing a first voltage from the first circuit to the BL in response to receiving the first enable signal, and providing a second voltage from the second circuit to the BLB in response to receiving the second enable signal.

[0232] In some embodiments, the first enable signal and the second enable signal are the same signal.

[0233] In some embodiments, the steps of providing a first voltage and providing a second voltage include the following steps: providing one of the first voltage and the second voltage as a constant voltage, and providing the other of the first voltage and the second voltage as a voltage range from a low voltage to a high voltage and / or from a high voltage to a low voltage to switch multiple states of the sensing amplifier.

[0234] In some embodiments, the method includes the following steps: enabling the first circuit and the second circuit; starting the first access control transistor connected to the bit line and the first storage capacitor; providing a constant voltage of the first voltage to the bit line; providing the data voltage from the first storage capacitor to the bit line; and raising the second voltage from a low voltage to a high voltage and / or lowering it from a high voltage to a low voltage to switch multiple states of the sensing amplifier.

[0235] In some embodiments, the method includes the following steps: enabling a first circuit; disabling a first access control transistor connected between a bit line and a first storage capacitor; providing a first voltage of a high voltage to the bit line to measure a leakage current of the bit line; activating the first access control transistor connected between the bit line and the first storage capacitor; and providing the first voltage of a high voltage to the bit line to measure a leakage current of the first storage capacitor.

[0236] This disclosure summarizes various embodiments so that those skilled in the art can better understand the aspects of an embodiment of the present disclosure. Those skilled in the art should understand that they can readily use an embodiment of the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of an embodiment of the present disclosure, and such equivalent constructions may be variously changed, substituted, and replaced herein without departing from the spirit and scope of an embodiment of the present disclosure.

Claims

1. An integrated circuit, characterized in that: Include: a sense amplifier having a plurality of input terminals connected to a bit line and a complementary bit line; a first memory cell for storing a data signal and selectively outputting the data signal on at least one of the bit line and the complementary bit line in response to a word line signal; a first circuit connected between a first voltage terminal for receiving a first external voltage and the bit line and having a first enable terminal for receiving a first enable signal, wherein the first external voltage is different from the data signal; and A second circuit is connected between a second voltage terminal for receiving a second external voltage and the complementary bit line and has a second enable terminal for receiving a second enable signal, wherein the second external voltage is different from the data signal and the first external voltage.

2. The integrated circuit according to claim 1, wherein: The first enabling signal and the second enabling signal are the same enabling signal.

3. The integrated circuit according to claim 1, wherein: The invention comprises a memory cell array having a plurality of memory cells, wherein the plurality of memory cells include the first memory cell, wherein the first memory cell is used to be connected to the bit line, wherein a second memory cell is used to be connected to the complementary bit line, The first memory cell includes a first access control transistor connected between the bit line and a first storage node, and the second memory cell includes a second access control transistor connected between the complementary bit line and a second storage node.

4. The integrated circuit according to claim 3, characterized in that The first circuit is used to receive the first enable signal and provide the first external voltage to the bit line, and the first access control transistor is used to receive the word line signal and provide the data signal from the first storage node to the bit line; the second circuit is used to receive the second enable signal and provide the second external voltage to the complementary bit line, wherein the second external voltage rises from a low voltage to a high voltage and / or falls from a high voltage to a low voltage to switch multiple states of the sense amplifier.

5. A semiconductor device, characterized in that: Include: a sense amplifier connected to a bit line and a complementary bit line; A memory cell array comprising a plurality of memory cells, wherein a first memory cell has a first access control transistor connected to the bit line and a first storage capacitor, and a second memory cell has a second access control transistor connected to the complementary bit line and a second storage capacitor; a precharge and equalize circuit connected to the bit line and the complementary bit line and configured to provide an equalized precharge voltage to each of the bit line and the complementary bit line in response to an active precharge enable signal; a first circuit comprising a first metal oxide semiconductor field effect transistor having a first drain / source terminal connected to the bit line, a second drain / source terminal for receiving a first external voltage, and a gate terminal for receiving an enable signal; and A second circuit includes a second metal oxide semiconductor field effect transistor having a third drain / source terminal connected to the complementary bit line, a fourth drain / source terminal for receiving a second external voltage, and a gate terminal for receiving the enable signal.

6. The semiconductor device according to claim 5, wherein: The first metal oxide semiconductor field effect transistor is a part of a first complementary metal oxide semiconductor channel gate, and the second metal oxide semiconductor field effect transistor is a part of a second complementary metal oxide semiconductor channel gate.

7. The semiconductor device according to claim 5, wherein: The second drain / source terminal of the first metal oxide semiconductor field effect transistor is connected to a fifth metal oxide semiconductor field effect transistor for receiving the first external voltage, and the fourth drain / source terminal of the second metal oxide semiconductor field effect transistor is connected to a sixth metal oxide semiconductor field effect transistor for receiving the second external voltage.

8. A method of operating a semiconductor device, characterized in that: The following steps are involved: receiving a first enable signal at a first circuit connected to a bit line of a sense amplifier; receiving a second enable signal at a second circuit connected to a complementary bit line of the sense amplifier; providing the first voltage from the first circuit to the bit line in response to receiving the first enable signal; and The second voltage is provided from the second circuit to the complementary bit line in response to receiving the second enable signal.

9. The method according to claim 8, characterized in that It includes the following steps: activating the first circuit and the second circuit; activating a first access control transistor connected to the bit line and a first storage capacitor; providing a constant voltage among the first voltages to the bit line; providing a data voltage from the first storage capacitor to the bit line; and The second voltage is increased from a low voltage to a high voltage and / or decreased from a high voltage to a low voltage to switch the states of the sense amplifier.

10. The method according to claim 8, characterized in that It includes the following steps: enabling the first circuit; disabling a first access control transistor connected between the bit line and a first storage capacitor; providing the first voltage, which is a high voltage, to the bit line to measure a leakage current of the bit line; activating the first access control transistor connected between the bit line and the first storage capacitor; and The first voltage, which is the high voltage, is provided to the bit line to measure a leakage current of the first storage capacitor.

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