Multi-channel bidirectional SCR device with adjustable trigger voltage and maintaining voltage for ESD protection of high-voltage integrated circuit

Abstract

The invention belongs to the field of design of an electrostatic discharge (ESD) protection device of a high-voltage integrated circuit (IC), aims at an improved bidirectional silicon controlled rectifier (MDDSCR), and particularly provides a multi-channel bidirectional silicon controlled rectifier (SCR) device with adjustable trigger voltage and maintaining voltage for ESD protection of the high-voltage integrated circuit, and the multi-channel bidirectional SCR device can be used for realizing ESD protection of an input / output (I / O) port and a power domain. The device has the advantages of being adjustable in trigger voltage and maintaining voltage, high in robustness and the like, and can be suitable for integrated circuit ESD protection in various high-voltage power supply domains.

Description

Technical Field

[0001] The present invention belongs to the field of electrostatic discharge (ESD) protection device design of high voltage integrated circuits (ICs), and specifically relates to a structural design of an ESD protection device, in particular to a modified dual-directional silicon controlled rectifier (MDDSCR). Background Art

[0002] Electrostatic discharge (ESD) refers to the process of charge transfer when the electric field strength induced by two objects with different electric potentials is greater than the dielectric breakdown electric field between the two objects, forming a conductive path between the two objects. ESD damage to integrated circuits is characterized by concealment, latency, randomness and complexity. With the development of semiconductor process technology, IC failure and damage caused by ESD have become an increasingly serious problem. Therefore, the development of ESD protection devices with excellent comprehensive performance such as adjustable trigger voltage and holding voltage and high robustness is of great economic and social significance for building full-chip electrostatic protection under advanced processes of various integrated circuits.

[0003] In a specific semiconductor process, ESD protection devices need to meet a certain ESD design window when working, that is, the safe operating range of the device should be less than the minimum breakdown voltage of the protected circuit and greater than the operating voltage of the protected circuit. For ESD protection devices with hysteresis characteristics, the trigger voltage and the holding voltage should be within the ESD design window. In the design of ESD protection devices for high-voltage integrated circuits, the holding voltage and trigger voltage of ESD protection devices need to meet the requirements of higher operating voltages. The characteristics of ESD protection devices that can meet the appropriate design window while also having high robustness have always been the focus and difficulty of ESD protection device design. Therefore, it is of great significance to design ESD protection devices with adjustable trigger voltage and holding voltage and high robustness.

[0004] Silicon controlled rectifier (SCR) is a commonly used ESD protection device with advantages such as small off-state leakage current, high area utilization, and high robustness. Therefore, SCR and its improved structure are widely used in the field of integrated circuit ESD protection design. However, there are still some problems with traditional SCR devices in ESD protection applications, such as excessively high trigger voltage. In order to reduce the trigger voltage of traditional SCR devices, a modified lateral silicon controlled rectifier (MLSCR) is proposed to reduce the trigger voltage by changing the reverse bias PN junction concentration.

[0005] In addition, in actual production applications, ESD stress may act on the positive direction of the IC pin or on the negative direction of the IC pin. Therefore, in order to meet the needs of bidirectional protection during design, a bidirectional silicon-controlled rectifier (DDSCR) is proposed.

[0006] The bidirectional ESD protection device DDSCR with hysteresis characteristics has the characteristics of high robustness, simple structure, high area utilization, etc., and is very suitable for ESD protection in chips. The device structure is as follows Figure 1 As shown, including: A P-type substrate 110; a first N-type doping region 120 is formed on the P-type substrate 110; a second N-type doping region 121, a first P-type doping region 130, a third N-type doping region 122, a second P-type doping region 131, and a fourth N-type doping region 123 are formed on the first N-type doping region 120; the first P-type doping region 130 is fully surrounded by the first N-type doping region 120, the second N-type doping region 121, and the third N-type doping region 122; the second P-type doping region 131 is fully surrounded by the first N-type doping region 120, the third N-type doping region 122, and the fourth N-type doping region 123; In the first P-type doping region 130, a first P-type heavily doped region 140 and a first N-type heavily doped region 150 are sequentially provided from near to far with reference to the second N-type doping region 121; in the second P-type doping region 121, a fourth P-type heavily doped region 143 and a second N-type heavily doped region 151 are sequentially provided from near to far with reference to the fourth N-type doping region 123; a second P-type heavily doped region 141 spanning the two regions is provided between the third N-type doping region 122 and the first P-type doping region 130, and a third P-type heavily doped region 142 spanning the two regions is provided between the third N-type doping region 122 and the second P-type doping region 131; The first P-type heavily doped region 140 and the first N-type heavily doped region 150 are connected to the T1 end; the second N-type heavily doped region 151 and the fourth P-type heavily doped region 143 are connected to the T2 end; Shallow trench isolation is respectively provided between the first P-type heavily doped region 140 and the first N-type heavily doped region 150, between the first N-type heavily doped region 150 and the second P-type heavily doped region 141, between the second P-type heavily doped region 141 and the third P-type heavily doped region 142, between the third P-type heavily doped region 142 and the second N-type heavily doped region 151, and between the second N-type heavily doped region 151 and the fourth P-type heavily doped region 143.

[0007] The device consists of a parasitic PNP transistor, two parasitic NPN transistors, and two well resistors: The first parasitic PNP transistor Q p1 , including a first P-type heavily doped region 140, a first P-type doped region 130, a second P-type heavily doped region 141, a third N-type doped region 122, a third P-type heavily doped region 142, a second P-type doped region 131, and a fourth P-type heavily doped region 143; the first parasitic NPN transistor Q n1 , including a first N-type heavily doped region 150, a first P-type doped region 130, and a third N-type doped region 122; the second parasitic NPN transistor Q n2 , including a second N-type heavily doped region 151, a second P-type doped region 131, and a third N-type doped region 122; the first well resistor R PW1 , refers to the well resistance of the first P-type doped region 130; the second well resistance R PW2 , refers to the well resistance of the second P-type doping region 131.

[0008] Working principle of the device: When an ESD event reaches the TI port of the device, such as Figure 1 (a). The ESD voltage is greater than the parasitic PNP transistor Q in the device. p1 BV CEO (avalanche breakdown voltage of the common emitter-collector junction of a bipolar transistor), Q p1 When it is turned on, current will flow through R PW2 , that is, the current flows from T1 to T2 in sequence through the first P-type heavily doped region 140, the first P-type doped region 130, the third N-type doped region 122, the second P-type doped region 131, and the second N-type heavily doped region 151. As the current increases, the well resistance R PW2 The pressure drop increases, making Q n2 The emitter junction voltage increases, Q n2 On. n2 The collector current increases, Q p1 The emitter junction voltage increases, and the parasitic NPN transistor Qn2 and the parasitic PNP transistor Q p1 The coupling between them forms positive feedback, and the SCR channel is turned on; When an ESD event reaches the T2 port of the device, such as Figure 1 (b) The ESD voltage is greater than the parasitic PNP transistor Q in the device. p1 BV CEO (avalanche breakdown voltage of the common emitter-collector junction of a bipolar transistor), Q p1 When it is turned on, current will flow through R PW1 , that is, the current flows from T2 to T1 through the fourth P-type heavily doped region 143, the second P-type doped region 131, the third N-type doped region 122, the first P-type doped region 130, and the first N-type heavily doped region 150 in sequence. As the current increases, the well resistance R PW2 The pressure drop increases, making Q n2 The emitter junction voltage increases, Q n2 On. n2 The collector current increases, Q p1 The emitter junction voltage increases, and the parasitic NPN transistor Q n2 and the parasitic PNP transistor Q p1 The coupling between them forms positive feedback, and the SCR channel is turned on.

[0009] The conventional DDSCR controls the parasitic PNP transistor BV CEO The size of the SCR channel can effectively control the trigger voltage, but the main way to discharge ESD current is still through the SCR channel. Although the SCR channel has a strong ESD current discharge capability, due to the positive feedback between its two bipolar transistors, the maintenance voltage of the SCR channel is about 1.5V. This maintenance voltage cannot meet the requirements of the ESD protection design of high-voltage integrated circuits, and latch-up effect is prone to occur, making the device unable to shut down and affecting the normal operation of the circuit. In severe cases, it will cause chip damage.

[0010] Therefore, the present invention proposes an MDDSCR device capable of regulating the trigger voltage and the holding voltage, and the device has more trigger channels and more ESD current discharge channels. Different trigger channels can adjust the trigger voltage, and different ESD current discharge channels can adjust the holding voltage, thereby making it suitable for ESD protection of integrated circuits under various high-voltage power domains. In addition, its multi-channel characteristics also make it have bidirectional protection characteristics and high robustness. Summary of the invention

[0011] The purpose of the present invention is to provide a multi-channel bidirectional SCR device with adjustable trigger voltage and holding voltage for high-voltage integrated circuit ESD protection. The device has the characteristics of adjustable trigger voltage and holding voltage and high robustness, and can be applied to high-voltage integrated circuit ESD protection in various power domains.

[0012] The technical solution adopted by the present invention is: A multi-channel MDDSCR device with adjustable trigger voltage and holding voltage, comprising: The device comprises a P-type silicon substrate, a first N-type doping region is formed on the P-type silicon substrate; a second N-type doping region, a first P-type doping region, a third N-type doping region, a second P-type doping region, and a fourth N-type doping region are formed on the first N-type doping region; the first P-type doping region is fully surrounded by the first N-type doping region, the second N-type doping region, and the third N-type doping region; the second P-type doping region is fully surrounded by the first N-type doping region, the third N-type doping region, and the fourth N-type doping region; The second N-type doping region is provided with a first P-type heavily doped region; a second P-type heavily doped region spanning the two regions is provided between the second N-type doping region and the first P-type doping region; in the first P-type doping region, a third P-type heavily doped region, a first N-type heavily doped region and a fourth P-type heavily doped region are provided in sequence from near to far with the second P-type heavily doped region as a reference; a fifth P-type heavily doped region spanning the two regions is provided between the first P-type doping region and the third N-type doping region; a sixth P-type heavily doped region spanning the two regions is provided between the third N-type doping region and the second P-type doping region; in the second P-type doping region, a seventh P-type heavily doped region, a second N-type heavily doped region and an eighth P-type heavily doped region are provided in sequence from near to far with the sixth P-type heavily doped region as a reference; a ninth P-type heavily doped region spanning the two regions is provided between the second P-type doping region and the fourth N-type doping region; the fourth N-type doping region is provided with a tenth P-type heavily doped region; The third P-type heavily doped region, the first N-type heavily doped region, the fourth P-type heavily doped region and the tenth P-type heavily doped region are connected to the T1 port; the first P-type heavily doped region, the seventh P-type heavily doped region, the second N-type heavily doped region and the eighth P-type heavily doped region are connected to the T2 port; Shallow trench isolations are respectively provided between the second P-type heavily doped region and the third P-type heavily doped region, between the third P-type heavily doped region and the first N-type heavily doped region, between the first N-type heavily doped region and the fourth P-type heavily doped region, between the fourth P-type heavily doped region and the fifth P-type heavily doped region, between the sixth P-type heavily doped region and the seventh P-type heavily doped region, between the seventh P-type heavily doped region and the second N-type heavily doped region, between the second N-type heavily doped region and the eighth P-type heavily doped region, and between the eighth P-type heavily doped region and the ninth P-type heavily doped region; The first P-type doping region and the second P-type doping region are formed by longitudinally stacking one or more P-type doping regions with different doping doses, and the first N-type doping region, the second N-type doping region, the third N-type doping region and the fourth N-type doping region are formed by longitudinally stacking one or more N-type doping regions with different doping doses.

[0013] The device is composed of six parasitic PNP transistors, four lateral parasitic NPN transistors, two vertical parasitic NPN transistors, and six well resistors: The first parasitic PNP transistor includes a first P-type heavily doped region, a second N-type doped region, a second P-type heavily doped region, a first P-type doped region, and a third P-type heavily doped region; the second parasitic PNP transistor includes a first P-type heavily doped region, a second N-type doped region, a first P-type doped region, and a third P-type heavily doped region; the third parasitic PNP transistor includes a fourth P-type heavily doped region, a first P-type doped region, a fifth P-type heavily doped region, a third N-type doped region, a sixth P-type heavily doped region, a second P-type doped region, The seventh P-type heavily doped region; the fourth parasitic PNP transistor includes the fourth P-type heavily doped region, the first P-type doped region, the third N-type doped region, the second P-type doped region, and the seventh P-type heavily doped region; the fifth parasitic PNP transistor includes the eighth P-type heavily doped region, the second P-type doped region, the ninth P-type heavily doped region, the fourth N-type doped region, and the tenth P-type heavily doped region; the sixth parasitic PNP transistor includes the tenth P-type heavily doped region, the fourth N-type doped region, the second P-type doped region, and the eighth P-type heavily doped region; The first lateral parasitic NPN transistor includes a first N-type heavily doped region, a first P-type doped region, and a second N-type doped region; the second lateral parasitic NPN transistor includes a first N-type heavily doped region, a first P-type doped region, and a third N-type doped region; the third lateral parasitic NPN transistor includes a second N-type heavily doped region, a second P-type doped region, and a third N-type doped region; the fourth lateral parasitic NPN transistor includes a second N-type heavily doped region, a second P-type doped region, and a fourth N-type doped region; the first vertical parasitic NPN transistor includes a first N-type heavily doped region, a first P-type doped region, a first N-type doped region, and a second N-type doped region; the second vertical parasitic NPN transistor includes a second N-type heavily doped region, a second P-type doped region, a first N-type doped region, and a fourth N-type doped region; The first well resistance includes the well resistance of the P-type doping region from below the third P-type heavily doped region to below the first N-type heavily doped region in the first P-type doping region; the second well resistance includes the well resistance of the P-row doping region from below the first N-type heavily doped region to below the fourth P-type heavily doped region in the first P-type doping region; the third well resistance includes the well resistance of the P-type doping region from below the seventh P-type heavily doped region to below the second N-type heavily doped region in the second P-type doping region; the fourth well resistance includes the well resistance of the P-type doping region from below the second N-type heavily doped region to below the eighth P-type heavily doped region in the second P-type doping region; the fifth well resistance refers to the resistance of the collector region of the first vertical parasitic NPN transistor in the first N-type doping region and the second N-type doping region; the sixth well resistance refers to the resistance of the collector region of the second vertical parasitic NPN transistor in the first N-type doping region and the fourth N-type doping region.

[0014] The first parasitic PNP transistor forms the first PNP channel, the third parasitic PNP transistor forms the second PNP channel, and the fifth parasitic PNP transistor forms the third PNP channel; the second parasitic PNP transistor, the first lateral parasitic NPN transistor, and the first well resistor together form the SCR1.1 channel, the second parasitic PNP transistor, the first vertical parasitic NPN transistor, and the first well resistor together form the SCR1.2 channel, and the SCR1.1 and SCR1.2 channels together form the SCR1 channel; the third parasitic PNP transistor, the second lateral parasitic NPN transistor, the third lateral parasitic NPN transistor, the second well resistor, and the third well resistor together form the bidirectional SCR2 channel; the sixth parasitic PNP transistor, the fourth lateral parasitic NPN transistor, and the fourth well resistor together form the SCR3.1 channel, the sixth parasitic PNP transistor, the second vertical parasitic NPN transistor, and the fourth well resistor together form the SCR3.2 channel, and the SCR3.1 and SCR3.2 channels together form the SCR3 channel.

[0015] The present invention provides a multi-channel bidirectional SCR device with adjustable trigger voltage and holding voltage for high-voltage integrated circuit ESD protection. The device not only inherits the characteristics of high robustness, simple structure, high area utilization rate, etc. of traditional DDSCR devices, but also has adjustable trigger voltage and holding voltage. Compared with traditional DDSCR devices, the device has more trigger channels and discharge channels. When a positive voltage reaches the T1 port, the device is triggered by the first PNP channel, the second PNP channel and the third PNP channel, and the main ESD discharge paths of the device are the first, second, third PNP channels, SCR2 channels and SCR3 channels; when a positive voltage reaches the T2 port, the device is triggered by the first PNP channel, the second PNP channel and the third PNP channel, and the main ESD discharge paths of the device are the first, second, third PNP channels, SCR1 channels and SCR2 channels; more adjustable trigger channels and discharge channels can make the device suitable for different ESD design windows, and can avoid the occurrence of latch-up effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is the structure diagram and equivalent circuit diagram of the traditional DDSCR device.

[0017] Figure 2 This is the MDDSCR structure diagram and equivalent circuit diagram of the device described in Example 1. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0020] In addition, the descriptions of "first", "second", etc. in the present invention are only for descriptive purposes and cannot be understood as referring to or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features.

[0021] In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0022] Example 1 This embodiment provides a multi-channel bidirectional SCR device with adjustable trigger voltage and holding voltage for high-voltage integrated circuit ESD protection. The device structure and equivalent circuit diagram are shown in FIG. Figure 2 shown.

[0023] The device of Embodiment 1 includes a P-type silicon substrate 110, on which a first N-type doping region 120 is formed; on which a second N-type doping region 121, a first P-type doping region 130, a third N-type doping region 122, a second P-type doping region 131, and a fourth N-type doping region 123 are formed; the first P-type doping region 130 is fully surrounded by the first N-type doping region 120, the second N-type doping region 121, and the third N-type doping region 122; the second P-type doping region 131 is fully surrounded by the first N-type doping region 120, the third N-type doping region 122, and the fourth N-type doping region 123; The second N-type doping region 121 is provided with a first P-type heavily doped region 140; a second P-type heavily doped region 141 is provided between the second N-type doping region 121 and the first P-type doping region 130, spanning the two regions; in the first P-type doping region 130, a third P-type heavily doped region 142, a first N-type heavily doped region 150 and a fourth P-type heavily doped region 143 are provided in sequence from near to far with reference to the second P-type heavily doped region 141; a fifth P-type heavily doped region 144 is provided between the first P-type doping region 130 and the third N-type doping region 122, spanning the two regions; A sixth P-type heavily doped region 145 is provided between the third N-type doping region 122 and the second P-type doping region 131, spanning the two regions; a seventh P-type heavily doped region 146, a second N-type heavily doped region 151 and an eighth P-type heavily doped region 147 are provided in the second P-type doping region 131 in order from near to far with reference to the sixth P-type heavily doped region 145; a ninth P-type heavily doped region 148 is provided between the second P-type doping region 131 and the fourth N-type doping region 123, spanning the two regions; and a tenth P-type heavily doped region 149 is provided in the fourth N-type doping region 123; The third P-type heavily doped region 142, the first N-type heavily doped region 150, the fourth P-type heavily doped region 143 and the tenth P-type heavily doped region 149 are connected to the T1 port; the first P-type heavily doped region 140, the seventh P-type heavily doped region 146, the second N-type heavily doped region 151 and the eighth P-type heavily doped region 147 are connected to the T2 port; Shallow trench isolations are respectively provided between the second P-type heavily doped region 141 and the third P-type heavily doped region 142, between the third P-type heavily doped region 142 and the first N-type heavily doped region 150, between the first N-type heavily doped region 150 and the fourth P-type heavily doped region 143, between the fourth P-type heavily doped region 143 and the fifth P-type heavily doped region 144, between the sixth P-type heavily doped region 145 and the seventh P-type heavily doped region 146, between the seventh P-type heavily doped region 146 and the second N-type heavily doped region 151, between the second N-type heavily doped region 151 and the eighth P-type heavily doped region 147, and between the eighth P-type heavily doped region 147 and the ninth P-type heavily doped region 148; The first P-type doping region 130 and the second P-type doping region 131 are formed by longitudinally stacking one or more P-type doping regions with different doping doses, and the first N-type doping region 120, the second N-type doping region 121, the third N-type doping region 122 and the fourth N-type doping region 123 are formed by longitudinally stacking one or more N-type doping regions with different doping doses.

[0024] The device described in Example 1 is composed of six parasitic PNP transistors, four lateral parasitic NPN transistors, two vertical parasitic NPN transistors, and six well resistors: The first parasitic PNP transistor Q p1 , including a first P-type heavily doped region 140, a second N-type doped region 121, a second P-type heavily doped region 141, a first P-type doped region 130, and a third P-type heavily doped region 142; the second parasitic PNP transistor Q p2 , including a first P-type heavily doped region 140, a second N-type doped region 121, a first P-type doped region 130, and a third P-type heavily doped region 142; the third parasitic PNP transistor Q p3 , including a fourth P-type heavily doped region 143, a first P-type doped region 130, a fifth P-type heavily doped region 144, a third N-type doped region 122, a sixth P-type heavily doped region 145, a second P-type doped region 131, and a seventh P-type heavily doped region 146; the fourth parasitic PNP transistor Q p4 , including a fourth P-type heavily doped region 143, a first P-type doped region 130, a third N-type doped region 122, a second P-type doped region 131, and a seventh P-type heavily doped region 146; the fifth parasitic PNP transistor Q p5 , including an eighth P-type heavily doped region 147, a second P-type doped region 131, a ninth P-type heavily doped region 148, a fourth N-type doped region 123, and a tenth P-type heavily doped region 149; the sixth parasitic PNP transistor Q p6 , including a tenth P-type heavily doped region 149, a fourth N-type doped region 123, a second P-type doped region 131, and an eighth P-type heavily doped region 147; The first lateral parasitic NPN transistor Qn1 , including a first N-type heavily doped region 150, a first P-type doped region 130, and a second N-type doped region 121; the second lateral parasitic NPN transistor Q n3 , including a first N-type heavily doped region 150, a first P-type doped region 130, and a third N-type doped region 122; the third lateral parasitic NPN transistor Q n4 , including a second N-type heavily doped region 151, a second P-type doped region 131, and a third N-type doped region 122; the fourth lateral parasitic NPN transistor Q n6 , including a second N-type heavily doped region 151, a second P-type doped region 131, and a fourth N-type doped region 123; the first vertical parasitic NPN transistor Q n2 , including a first N-type heavily doped region 150, a first P-type doped region 130, a first N-type doped region 120, and a second N-type doped region 121; the second vertical parasitic NPN transistor Q n5 , including a second N-type heavily doped region 151 , a second P-type doped region 131 , a first N-type doped region 120 , and a fourth N-type doped region 123 ; The first well resistor R PW1 , including the well resistance of the P-type doping region from below the third P-type heavily doped region 142 to below the first N-type heavily doped region 150 in the first P-type doping region 130; the second well resistance R PW2 , including the well resistance of the P-type doping region from below the first N-type heavily doped region 150 to below the fourth P-type heavily doped region 143 in the first P-type doping region 130; the third well resistance R PW3 , including the well resistance of the P-type doping region from below the seventh P-type heavily doped region 146 to below the second N-type heavily doped region 151 in the second P-type doping region 131; the fourth well resistance R PW4 , including the well resistance of the P-type doping region from below the second N-type heavily doped region 151 to below the eighth P-type heavily doped region 147 in the second P-type doping region 131; the fifth well resistance R NW1 , refers to the first vertical parasitic NPN transistor Q in the first N-type doping region 120 and the second N-type doping region 121. n2 The resistance of the collector region; the sixth well resistance R NW2 , refers to the second vertical parasitic NPN transistor Q in the first N-type doping region 120 and the fourth N-type doping region 123. n5 The resistance of the collector region.

[0025] The first parasitic PNP transistor Q p1 The first PNP channel and the third parasitic PNP transistor Q p3 The second PNP channel and the fifth parasitic PNP transistor Q p5The third PNP channel is formed by the second parasitic PNP transistor Q p2 , the first lateral parasitic NPN transistor Q n1 , the first well resistance R PW1 Together they form the SCR1.1 channel, which is composed of the second parasitic PNP transistor Q p2 , the first vertical parasitic NPN transistor Q n2 , the first well resistance R PW1 Together they form the SCR1.2 channel, and the SCR1.1 and SCR1.2 channels together form the SCR1 channel. p3 , the second lateral parasitic NPN transistor Q n3 , the third lateral parasitic NPN transistor Q n4 , the second well resistance R PW2 , the third well resistor R PW3 Together they form a bidirectional SCR2 channel; the sixth parasitic PNP transistor Q p6 , the fourth lateral parasitic NPN transistor Q n6 , the fourth well resistor R PW4 Together they form the SCR3.1 channel, which is composed of the sixth parasitic PNP transistor Q p6 , the second vertical parasitic NPN transistor Q n5 , the fourth well resistor R PW4 Together they form the SCR3.2 channel, and the SCR3.1 and SCR3.2 channels together form the SCR3 channel.

[0026] The working principle of the device described in Example 1 can be divided into two types according to the ESD positive voltage reaching different ports T1 and T2: When a positive ESD voltage reaches the T1 port, Figure 2 (a). The ESD voltage is greater than Q p1 BV CEO When the hole current flows through Q p1 The collector junction flows to the T2 end of the device, Q p1 On; ESD voltage is greater than Q p5 BV CEO When p5 Turn on, the electron current flows through Q p5 The emitter junction flows to the T1 end of the device, and the hole current flows to the T2 end through the ninth P-type heavily doped region 148, the second P-type doped region 131, and the eighth P-type heavily doped region 147. As the voltage at the T1 end increases, Q p5 The emitter junction voltage increases, making Q p6 The emitter junction voltage also increases, Q p6 Turn on and conduct current, as Q p5 and Q p6 The collector current increases, making RPW4 The pressure drop increases, Q n5 and Q n6 The emitter junction voltage increases, Q n5 and Q n6 It will open, Q n5 and Q n6 The increase of collector current makes Q p5 and Q p6 The emitter junction voltage increases, and positive feedback is formed between the parasitic NPN transistor and the parasitic PNP transistor. The SCR3.1 and SCR3.2 channels are turned on, and the SCR3 channel is turned on. The ESD voltage is greater than Q p3 BV CEO When p3 When it is turned on, the hole current flows to the T2 terminal through the sixth P-type heavily doped region 145, the second P-type heavily doped region 131, and the seventh P-type heavily doped region 146, and the electron current flows to the T1 terminal through the third N-type doped region 122, the fifth P-type heavily doped region 144, the first P-type doped region 130, and the fourth P-type heavily doped region 143. As the voltage at the T1 terminal increases, Q p3 The emitter junction voltage increases, making Q p4 The emitter junction voltage also increases, Q p4 Turn on and conduct current, as Q p3 and Q p4 The collector current increases, making R PW3 The pressure drop increases, Q n4 The emitter junction voltage increases, Q n4 It will open, Q n4 The collector current increases, Q p3 and Q p4 The emitter junction voltage increases, and positive feedback is formed by coupling between the parasitic NPN transistor and the parasitic PNP transistor, so that the SCR2 channel is turned on. At this time, there are five main ESD discharge channels, namely the SCR2 and SCR3 channels and the first, second and third PNP channels.

[0027] When a positive ESD voltage reaches the T2 port, Figure 2 _A. The ESD voltage is greater than Q p5 BV CEO When the hole current flows through Q p5 The collector junction flows to the T1 end of the device, Q p5 On; ESD voltage is greater than Q p1 BV CEO When p1 Turn on, the electron current flows through Q p1The emitter junction flows to the T2 end of the device, and the hole current flows to the T1 end through the second P-type heavily doped region 141, the first P-type doped region 130, and the third P-type heavily doped region 142. As the voltage at the T2 end increases, Q p1 The emitter junction voltage increases, making Q p2 The emitter junction voltage also increases, Q p2 Turn on and conduct current, as Q p1 and Q p2 The collector current increases, making R PW1 The pressure drop increases, Q n1 and Q n2 The emitter junction voltage increases, Q n1 and Q n2 It will open, Q n1 and Q n2 The collector current increases, making Q p1 and Q p2 The emitter junction voltage increases, and positive feedback is formed between the parasitic NPN transistor and the parasitic PNP transistor. The SCR1.1 and SCR1.2 channels are turned on, and the SCR1 channel is turned on. The ESD voltage is greater than Q p3 BV CEO When p3 When it is turned on, the hole current flows to the T1 terminal through the fifth P-type heavily doped region 144, the first P-type heavily doped region 130, and the fourth P-type heavily doped region 143, and the electron current flows to the T2 terminal through the third N-type doped region 122, the sixth P-type heavily doped region 145, the second P-type doped region 131, and the seventh P-type heavily doped region 146. As the voltage at the T2 terminal increases, Q p3 The emitter junction voltage increases, making Q p4 The emitter junction voltage also increases, Q p4 Turn on and conduct current, as Q p3 and Q p4 The collector current increases, making R PW2 The pressure drop increases, Q n3 The emitter junction voltage increases, Q n3 It will open, Q n3 The collector current increases, Q p3 and Q p4 The emitter junction voltage increases, and positive feedback is formed by coupling between the parasitic NPN transistor and the parasitic PNP transistor, so that the SCR2 channel is turned on. At this time, there are five main ESD discharge channels, namely the SCR1 and SCR2 channels and the first, second and third PNP channels.

[0028] The device of embodiment 1 is provided by three transistors Q p1 , Q p3 and Q p5Trigger, when the applied voltage is greater than the BV of the transistor CEO When the transistor is turned on, the Q p1 , Q p3 and Q p5 BV CEO The size of the device trigger voltage is adjusted by the size of

[0029] BV CEO The size of can be obtained by the following formula: {BV}_{CEO}\approx \frac {{BV}_{CBO}} {\sqrt[{S}] {β}} Among them BV CBO is the collector junction avalanche breakdown voltage when the emitter is open. β is the common emitter DC short-circuit current amplification factor, and S is a constant.

[0030] The Q can be adjusted by adjusting the dosage of the second N-type doping region 121, the third N-type doping region 122, and the third N-type doping region 123. p1 , Q p3 and Q p5 BV CBO Q can be adjusted by adjusting the distance between the first P-type heavily doped region 140 and the second P-type heavily doped region 141, the distance between the fifth P-type heavily doped region 144 and the sixth P-type heavily doped region 145, and the distance between the ninth P-type heavily doped region 148 and the tenth P-type heavily doped region 149. p1 , Q p3 and Q p5 of β The above method can adjust Q p1 , Q p3 and Q p5 BV CEO , thereby achieving the purpose of regulating the trigger voltage. If the second N-type doping region 121, the third N-type doping region 122 and the fourth N-type doping region 123 are set to the same doping amount, and the distances between the first P-type heavily doped region 140 and the second P-type heavily doped region 141, between the fifth P-type heavily doped region 144 and the sixth P-type heavily doped region 145, and between the ninth P-type heavily doped region 148 and the tenth P-type heavily doped region 149 are equal, Q p1 , Q p3 and Q p5 BV CEO Equal size, Q p1 , Q p3 and Q p5 will be triggered simultaneously; on the contrary, if the parameters of the three transistors are set differently, Q p1 , Qp3 and Q p5 According to its BV CEO By adjusting in the above manner, the trigger voltage of the device described in Example 1 can be adapted to different ESD design windows.

[0031] The holding voltage of the device described in Example 1 is proportional to the ratio of the current through the PNP channel to the current through the SCR channel. Since there are parasitic PNP and parasitic NPN tubes in the SCR, when the SCR is turned on, positive feedback will be formed between the parasitic PNP and parasitic NPN tubes. This positive feedback effect will enable the SCR to maintain the on state even with a small external voltage, and the holding voltage of the SCR path is relatively low; while when the triode is turned on, a large external voltage is required to make the emitter junction forward biased and the collector junction reverse biased to maintain the on state, and the holding voltage of the triode path is higher. Therefore, the regulation of the holding voltage can be achieved by changing the size of the resistance on the PNP and SCR current paths, that is, mainly through the following methods: The resistance on the first PNP channel current path can be controlled by adjusting the distance between the first P-type heavily doped region 140 and the second P-type heavily doped region 141, the distance between the second P-type heavily doped region 141 and the third P-type heavily doped region 142, the doping amount of the second N-type doping region 121, and the doping amount of the first P-type doping region 130; the resistance on the first PNP channel current path can be controlled by adjusting the distance between the fourth P-type heavily doped region 143 and the fifth P-type heavily doped region 144, the distance between the fifth P-type heavily doped region 144 and the sixth P-type heavily doped region 145, the distance between the sixth P-type heavily doped region 145 and the seventh P-type heavily doped region 1 The resistance on the second PNP channel current path can be regulated by adjusting the distance between the eighth P-type heavily doped region 147 and the ninth P-type heavily doped region 148, the distance between the ninth P-type heavily doped region 148 and the tenth P-type heavily doped region 149, the doping dose of the fourth N-type doping region 123, and the doping dose of the second P-type doping region 131; the resistance on the third PNP channel current path can be regulated by adjusting the distance between the eighth P-type heavily doped region 147 and the ninth P-type heavily doped region 148, the distance between the ninth P-type heavily doped region 148 and the tenth P-type heavily doped region 149, the doping dose of the fourth N-type doping region 123, and the doping dose of the second P-type doping region 131; The distance between the first P-type heavily doped region 140 and the first P-type doped region 130, the distance between the second N-type doped region 121 and the first N-type heavily doped region 150, the doping amount of the second N-type doped region 121, the doping amount of the first N-type doped region 120 and the doping amount of the first P-type doped region 130 can regulate the size of the resistance on the current path of the first SCR channel; by regulating the distance between the first N-type heavily doped region 150 and the third N-type doped region 122, the width of the third N-type doped region 122, the distance between the third N-type doped region 122 and the second N-type heavily doped region 151, The doping dose of the third N-type doping region 122, the doping dose of the first P-type doping region 130 and the doping dose of the second P-type doping region 131 can regulate the size of the resistance on the second SCR channel current path; the size of the resistance on the third SCR channel current path can be regulated by regulating the distance between the tenth P-type heavy doping 149 and the second P-type doping region 131, the distance between the fourth N-type doping region 123 and the second N-type heavy doping region 151, the doping dose of the fourth N-type doping region 123, the doping dose of the first N-type doping region 120 and the doping dose of the second P-type doping region 131.

[0032] Meanwhile, compared with the reference device DDSCR, the device adds a fourth P-type heavily doped region 143 and a seventh P-type heavily doped region 146, which are closer to the third N-type doped region 122. This design increases the lateral parasitic NPN transistor Q n3 and Q n4 The width of the base region reduces its β The size of the positive feedback is not easy to form, the SCR opens slowly, and the maintenance voltage will be further increased, which can better meet the needs of high-voltage integrated circuit ESD protection.

[0033] The above examples are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described with reference to preferred examples, those skilled in the art should understand that any feature disclosed in this specification, unless otherwise specified, may be replaced by other alternative features that are equivalent or have similar purposes. All disclosed features, or steps in all methods or processes, except for mutually exclusive features and / or steps, may be combined in any manner without departing from the purpose and scope of the technical solutions of the present invention, and should all be included in the scope of the claims of the present invention.

Claims

1. A multi-channel MDDSCR with adjustable trigger voltage and holding voltage, characterized in that: The device comprises a P-type silicon substrate, a first N-type doping region is formed on the P-type silicon substrate; a second N-type doping region, a first P-type doping region, a third N-type doping region, a second P-type doping region, and a fourth N-type doping region are formed on the first N-type doping region; the first P-type doping region is fully surrounded by the first N-type doping region, the second N-type doping region, and the third N-type doping region; the second P-type doping region is fully surrounded by the first N-type doping region, the third N-type doping region, and the fourth N-type doping region; A first P-type heavily doped region is formed on the second N-type doped region; a second P-type heavily doped region spanning the two regions is provided between the second N-type doped region and the first P-type doped region; a third P-type heavily doped region, a first N-type heavily doped region and a fourth P-type heavily doped region are provided in the first P-type doped region in order from near to far with the second P-type heavily doped region as a reference; a fifth P-type heavily doped region spanning the two regions is provided between the first P-type doped region and the third N-type doped region; a sixth P-type heavily doped region spanning the two regions is provided between the third N-type doped region and the second P-type doped region; a seventh P-type heavily doped region, a second N-type heavily doped region and an eighth P-type heavily doped region are provided in the second P-type doped region in order from near to far with the sixth P-type heavily doped region as a reference; a ninth P-type heavily doped region spanning the two regions is provided between the second P-type doped region and the fourth N-type doped region; and a tenth P-type heavily doped region is provided in the fourth N-type doped region; The third P-type heavily doped region, the first N-type heavily doped region, the fourth P-type heavily doped region and the tenth P-type heavily doped region are connected to the T1 port; the first P-type heavily doped region, the seventh P-type heavily doped region, the second N-type heavily doped region and the eighth P-type heavily doped region are connected to the T2 port; Shallow trench isolation is respectively provided between the second P-type heavily doped region and the third P-type heavily doped region, between the third P-type heavily doped region and the first N-type heavily doped region, between the first N-type heavily doped region and the fourth P-type heavily doped region, between the fourth P-type heavily doped region and the fifth P-type heavily doped region, between the sixth P-type heavily doped region and the seventh P-type heavily doped region, between the seventh P-type heavily doped region and the second N-type heavily doped region, between the second N-type heavily doped region and the eighth P-type heavily doped region, and between the eighth P-type heavily doped region and the ninth P-type heavily doped region.

Images