Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and is used for improving the brightness uniformity of the display panel. The display panel comprises a substrate, a data line and a pixel driving circuit, wherein the data line and the pixel driving circuit are located on one side of the substrate; the pixel driving circuit comprises a driving transistor, a bias adjusting transistor and a first connecting part, a grid electrode of the driving transistor is electrically connected with the first node, a first pole of the driving transistor is electrically connected with the second node, and a second pole of the driving transistor is electrically connected with the third node; the first connecting part is electrically connected with the bias adjusting transistor and the second node; the display panel further comprises a first semiconductor layer and a first metal layer, and the first semiconductor layer and the first metal layer are sequentially stacked in the direction away from the substrate. The first semiconductor layer comprises a channel of the driving transistor and a channel of the bias adjusting transistor, and the first metal layer comprises a grid electrode of the driving transistor and a grid electrode of the bias adjusting transistor; the first connection member is located on the first semiconductor layer.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is one of the hot topics in the current research field of flat panel displays. Compared with liquid crystal displays, OLED has the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle and fast response speed. Currently, OLED has begun to replace traditional liquid crystal displays (LCD) in the field of flat panel displays such as mobile phones, PDAs, and digital cameras.

[0003] The pixel driving circuit in the OLED display panel provides the driving current required for display to the light-emitting element, so that the display panel emits light for display. However, the current display panel has a visible display unevenness (Mura) phenomenon in the display state, which affects the display quality. Summary of the invention

[0004] In view of this, the present invention provides a display panel and a display device to improve the display uniformity of the display panel.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0006] substrate;

[0007] A data line and a pixel driving circuit located on one side of the substrate;

[0008] The pixel driving circuit includes a driving transistor, a bias adjusting transistor and a first connecting component, wherein the gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node; the first connecting component is electrically connected to the bias adjusting transistor and the second node;

[0009] The display panel further includes a first semiconductor layer and a first metal layer, which are stacked in sequence in a direction away from the substrate; the first semiconductor layer includes a channel of the driving transistor and a channel of the bias regulating transistor, and the first metal layer includes a gate of the driving transistor and a gate of the bias regulating transistor;

[0010] The first connecting member is located on the first semiconductor layer

[0011] In a second aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned display panel.

[0012] The display panel and display device provided by the embodiments of the present invention can arrange the data line on the side of the second metal layer away from the substrate by arranging the first connecting component on the first semiconductor layer. For example, the data line is arranged on the second source-drain layer which is at a greater distance from the first semiconductor layer, so that the distance between the first connecting component and the data line in the direction perpendicular to the plane where the substrate is located can be increased, thereby reducing the coupling capacitance between the first connecting component and the data line. When the data voltage changes, the signal change amount of the second node can be weakened, thereby avoiding the potential change of the second node from affecting the potential of the first node through the driving transistor and the threshold compensation transistor, thereby avoiding affecting the light emitting brightness of the light emitting element and improving the brightness uniformity of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A simplified schematic diagram of a display panel provided by an embodiment of the present invention;

[0015] Figure 2 for Figure 1 A circuit diagram of a sub-pixel in FIG.

[0016] Figure 3 A working timing diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0017] Figure 4 A wiring diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0018] Figure 5 A schematic cross-sectional view of a display panel provided by an embodiment of the present invention;

[0019] Figure 6 A schematic top view of a first semiconductor layer provided in an embodiment of the present invention;

[0020] Figure 7 A schematic top view of a first metal layer provided in an embodiment of the present invention;

[0021] Figure 8 A schematic top view of a second metal layer provided in an embodiment of the present invention;

[0022] Fig. 9 A schematic top view of a second semiconductor layer provided by an embodiment of the present invention;

[0023] Fig.10 A schematic top view of a third metal layer provided in an embodiment of the present invention;

[0024] Fig.11 A schematic top view of a first source and drain layer provided in an embodiment of the present invention;

[0025] Fig.12 A schematic top view of a second source and drain layer provided in an embodiment of the present invention;

[0026] Fig.13 An enlarged schematic diagram of a light-emitting control signal line provided by an embodiment of the present invention;

[0027] Fig.14 An enlarged schematic diagram of another light-emitting control signal line provided by an embodiment of the present invention;

[0028] Fig.15 A schematic top view of another first semiconductor layer provided by an embodiment of the present invention;

[0029] Fig.16 A simplified schematic diagram of another display panel provided by an embodiment of the present invention;

[0030] Fig.17 A wiring diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0031] Fig.18 A schematic top view of another first source and drain layer provided by an embodiment of the present invention;

[0032] Fig.19 A schematic top view of another second source and drain layer provided by an embodiment of the present invention;

[0033] Fig. 20 A simplified schematic diagram of another display panel provided by an embodiment of the present invention;

[0034] Fig.21 A simplified schematic diagram of another display panel provided by an embodiment of the present invention;

[0035] Fig. 22 A simplified schematic diagram of another display panel provided by an embodiment of the present invention;

[0036] Fig.23 A simplified schematic diagram of another display panel provided by an embodiment of the present invention;

[0037] Fig.24 A simplified schematic diagram of another display panel provided by an embodiment of the present invention;

[0038] Fig.25 A wiring diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0039] Fig.26 for Fig.25 A schematic diagram of the second electrode plate and the shielding component;

[0040] Fig. 27 A wiring diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0041] Fig.28 for Fig. 27 A schematic diagram of a shielding component and a second sub-bias adjustment signal line;

[0042] Fig.29 A wiring diagram of another pixel driving circuit provided by an embodiment of the present invention is shown.

[0043] Fig.30 for Fig.29 A schematic diagram of a shielding component and a fourth sub-reset signal line in FIG.

[0044] Fig.31 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0048] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0049] An embodiment of the present invention provides a display panel, such as Figure 1 As shown, Figure 1This is a simplified schematic diagram of a display panel provided by an embodiment of the present invention, the display panel 100 includes a substrate 1 and a plurality of sub-pixels 2 located on one side of the substrate 1. The display panel 100 includes a display area AA, and the sub-pixels 2 are located in the display area AA.

[0050] like Figure 2 As shown, Figure 2 for Figure 1 A circuit diagram of a sub-pixel in FIG. 2 is provided, wherein the sub-pixel 2 includes an electrically connected pixel driving circuit 21 and a light-emitting element 22. Exemplarily, the light-emitting element 22 includes any one of an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), and a micro light-emitting diode (Micro-LED).

[0051] like Figure 2 As shown, the pixel driving circuit 21 includes a first light emission control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, a first reset transistor T5, a second light emission control transistor T6, a second reset transistor T7 and a bias adjustment transistor T8.

[0052] like Figure 2 As shown, the display panel 100 also includes a data line DATA, a first power voltage line PVDD, a bias adjustment signal line DVH, a first reset signal line REF1, a second reset signal line REF2, a first scan control signal line SP*, a second scan control signal line S1N, a third scan control signal line S2N, a light emitting control signal line EM and a fourth scan control signal line SP.

[0053] Among them, the first power voltage line PVDD transmits the first power voltage Vpvdd, the data line DATA transmits the data voltage Vdata, the first reset signal line REF1 transmits the first reset voltage Vref1, the second reset signal line REF2 transmits the second reset voltage Vref2, and the bias adjustment signal line DVH transmits the bias adjustment voltage Vdvh.

[0054] The first light emission control transistor T1 has a gate electrically connected to the light emission control signal line EM, a first electrode electrically connected to the first power supply voltage line PVDD, and a second electrode electrically connected to the second node N2.

[0055] The data writing transistor T2 has a gate electrically connected to the fourth scanning control signal line SP, a first electrode electrically connected to the data line DATA, and a second electrode electrically connected to the second node N2.

[0056] The driving transistor T3 has a gate electrically connected to the first node N1 , a first electrode electrically connected to the second node N2 , and a second electrode electrically connected to the third node N3 .

[0057] The threshold compensation transistor T4 has a gate electrically connected to the third scan control signal line S2N, a first electrode electrically connected to the third node N3, and a second electrode electrically connected to the first node N1.

[0058] The first reset transistor T5 has a gate electrically connected to the second scanning control signal line S1N, a first electrode electrically connected to the first reset signal line REF1, and a second electrode electrically connected to the first node N1.

[0059] The second light emission control transistor T6 has a gate electrically connected to the light emission control signal line EM, a first electrode electrically connected to the third node N3 , and a second electrode electrically connected to the light emitting element 22 .

[0060] The second reset transistor T7 has a gate electrically connected to the first scanning control signal line SP*, a first electrode electrically connected to the second reset signal line REF2 , and a second electrode electrically connected to the light emitting element 22 .

[0061] The bias adjustment transistor T8 has a gate electrically connected to the first scan control signal line SP*, a first electrode electrically connected to the bias adjustment signal line DVH, and a second electrode electrically connected to the second node N2.

[0062] like Figure 2 As shown, the pixel driving circuit 21 further includes a storage capacitor Cst, a first plate of the storage capacitor Cst is electrically connected to the first node N1, and a second plate of the storage capacitor Cst is electrically connected to the first power voltage line PVDD.

[0063] like Figure 3 As shown, Figure 3 The working timing diagram of a pixel driving circuit provided by an embodiment of the present invention, the driving cycle of the pixel driving circuit 21 includes a first bias adjustment stage t11, a reset stage t2, a data writing and threshold compensation stage t3, a second bias adjustment stage t12 and a light emitting stage t4.

[0064] In the first bias adjustment stage t11, the first scan control signal line SP* provides an enable level, the bias adjustment transistor T8 is turned on, and the bias adjustment voltage Vdvh provided by the bias adjustment signal line DVH is written into the second node N2, and the potential of the first electrode of the driving transistor T3 is refreshed, so that the device characteristics of the driving transistor T3 are set to a certain initial state, eliminating the influence of the data voltage written in the previous frame on the device characteristics of the driving transistor T3.

[0065] In the reset phase t2 , the second scan control signal line S1N provides an enable level, the first reset transistor T5 is turned on, and the first reset voltage Vref1 transmitted by the first reset signal line REF1 resets the potential of the first node N1 through the first reset transistor T5 .

[0066] In the data writing and threshold compensation stage t3, the fourth scan control signal line SP provides an enable level, the data writing transistor T2 is turned on, the third scan control signal line S2N provides an enable level, the threshold compensation transistor T4 is turned on, and the data voltage Vdata transmitted by the data line DATA is written into the first node N1 through the data writing transistor T2, the driving transistor T3 and the threshold compensation transistor T4 until the driving transistor T3 is turned off. At this time, the voltage difference between the gate and the source of the driving transistor T3 is its threshold voltage, thereby realizing compensation for the threshold voltage of the driving transistor T3.

[0067] In the second bias adjustment stage t12, the first scanning control signal line SP* provides an enable level, the bias adjustment transistor T8 is turned on, and the bias adjustment voltage Vdvh provided by the bias adjustment signal line DVH is written into the second node N2, and the potential of the first electrode of the driving transistor T3 is refreshed. In the related art, after the data voltage is written into the gate of the driving transistor T3, that is, the first node N1, the voltage of the first electrode of the driving transistor T3, that is, the second node N2, will leak, resulting in a large deviation of the potential of the first electrode of the driving transistor T3. The embodiment of the present invention sets the second bias adjustment stage t12, controls the bias adjustment transistor T8 to be turned on in the second bias adjustment stage t12, and uses the bias adjustment transistor T8 to write the bias adjustment voltage Vdvh into the first electrode of the driving transistor T3, wherein the bias adjustment voltage Vdvh is related to the data voltage Vdata, so that the bias state of the driving transistor T3 can be maintained consistent with the bias state when the data voltage is just written, which can improve the stability of the working state of the driving transistor T3, improve the low-frequency flicker problem, and enhance the display effect of the display panel 100.

[0068] In the second bias adjustment stage t12 , the first scan control signal line SP* provides an enable level, the second reset transistor T7 is turned on, and the second reset voltage Vref2 provided by the second reset signal line REF2 is written into the anode of the light emitting element 22 to reset the anode potential of the light emitting element 22 .

[0069] In the light emitting stage t3 , the light emitting control signal line EM provides an enable level, the first light emitting control transistor T1 and the second light emitting control transistor T6 are turned on, and the light emitting element 22 emits light.

[0070] Exemplarily, in the embodiment of the present invention, at least one of the first light emission control transistor T1, the data writing transistor T2, the driving transistor T3 and the second light emission control transistor T6 and the second reset transistor T7 may be configured to include a low temperature polysilicon (LTPS) transistor.

[0071] Optionally, in the embodiment of the present invention, at least one of the first reset transistor T5 and the threshold compensation transistor T4 may be configured to include an oxide transistor. Exemplarily, the oxide transistor includes Indium Gallium Zinc Oxide (IGZO).

[0072] Oxide transistors have advantages such as low leakage current, and low-temperature polysilicon transistors have advantages such as high switching speed, high carrier mobility, and low power. The embodiment of the present invention adopts the LTPO (Low Temperature Polycrystalline Oxide) display panel technology that combines LTPO and IGZO, so that the display panel not only has the advantages of high resolution, high response speed, high brightness, and high aperture ratio of the LTPS display panel, but also has the advantage of low leakage current of IGZO, which can improve the potential stability of the first node N1, improve the display effect, and is conducive to improving the display effect under low frequency. Figure 2 As an example, the first light emission control transistor T1 , the data writing transistor T2 , the driving transistor T3 , the second light emission control transistor T6 , and the second reset transistor T7 are all set as low-temperature polysilicon transistors, and the first reset transistor T5 and the threshold compensation transistor T4 are all set as oxide transistors.

[0073] Exemplarily, the first light-emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the second light-emitting control transistor T6, and the reset transistor T7 may be P-type transistors; the first reset transistor T5 and the threshold compensation transistor T4 may be N-type transistors. The P-type transistor is turned on when the voltage difference between the gate and the source is less than the threshold voltage, which can also be understood as a low-level turn-on, that is, the enable level is a low level. The N-type transistor is turned on when the voltage difference between the gate and the source is greater than the threshold voltage, which can also be understood as a high-level turn-on, that is, the enable level is a high level.

[0074] Combination Figure 2 and Figure 4 As shown, Figure 4A wiring diagram of a pixel driving circuit provided in an embodiment of the present invention is shown, in which two pixel driving circuits 21 arranged along a first direction h21 are used as an illustration, and the pixel driving circuit 21 also includes a first connecting component 30, which electrically connects the bias adjustment transistor T8 and the second node N2.

[0075] like Figure 4 and Figure 5 As shown, Figure 5 A cross-sectional schematic diagram of a display panel provided in an embodiment of the present invention, the display panel 100 further includes a plurality of conductive film layers, the conductive film layers including a first semiconductor layer SC1, a first metal layer M1 and a second metal layer MC. In a direction away from the substrate 1, the first semiconductor layer SC1, the first metal layer M1 and the second metal layer MC are stacked in sequence, and two adjacent conductive film layers are separated by an insulating layer.

[0076] Combination Figure 4 and Figure 6 As shown, Figure 6 A top view schematic diagram of a first semiconductor layer provided for an embodiment of the present invention shows an area where two pixel driving circuit rows and four pixel driving circuit columns are located, the pixel driving circuit rows include a plurality of pixel driving circuits 21 arranged along a first direction h21, the pixel driving circuit columns include a plurality of pixel driving circuits 21 arranged along a second direction h22, and the first semiconductor layer SC1 includes at least a channel T10 of a first light-emitting control transistor T1, a channel T20 of a data writing transistor T2, a channel T30 of a driving transistor T3, a channel T60 of a second light-emitting control transistor T6, a channel T70 of a second reset transistor T7, and a channel T80 of a bias adjustment transistor T8.

[0077] Optionally, the first semiconductor layer SC1 includes a silicon material, the silicon material includes amorphous silicon or polycrystalline silicon, and the polycrystalline silicon may include low-temperature polycrystalline silicon.

[0078] Combination Figure 4 and Figure 7 As shown, Figure 7A schematic top view of a first metal layer provided in an embodiment of the present invention, wherein two pixel drive circuit rows and four pixel drive circuit columns are shown, wherein the pixel drive circuit row includes a plurality of pixel drive circuits 21 arranged along a first direction h21, and the pixel drive circuit column includes a plurality of pixel drive circuits 21 arranged along a second direction h22, and the first metal layer M1 includes a first plate C1 of a storage capacitor Cst, a gate G3 of a driving transistor T3, and a gate G8 of a bias adjustment transistor T8; along a direction h1 perpendicular to the plane where the substrate 1 is located, the first plate C1 of the storage capacitor Cst is located between the substrate 1 and the second plate C2, and the gate G3 of the driving transistor T3 overlaps with the channel of the driving transistor T3, and the gate G8 of the bias adjustment transistor T8 overlaps with the channel T80 of the bias adjustment transistor T8. Among them, the portion of the first plate C1 of the storage capacitor Cst that overlaps with the channel T30 of the driving transistor T3 is reused as the gate G3 of the driving transistor T3.

[0079] Optionally, the first conductive layer M1 may include an alloy of one or more materials such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and copper (Cu), and may be formed into a single-layer or multi-layer structure.

[0080] Combination Figure 4 and Figure 8 As shown, Figure 8 A schematic top view of a second metal layer provided in an embodiment of the present invention, showing the area where two pixel drive circuit rows and four pixel drive circuit columns are located, the pixel drive circuit row includes a plurality of pixel drive circuits 21 arranged along a first direction h21, the pixel drive circuit column includes a plurality of pixel drive circuits 21 arranged along a second direction h22, and the second metal layer MC includes a second plate C2 of a storage capacitor Cst. Along a direction h1 perpendicular to the plane where the substrate 1 is located, the second plate C2 at least partially overlaps with the first plate C1.

[0081] Exemplarily, the second metal layer MC may include an alloy of one or more materials such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and copper (Cu), and may be formed into a single-layer or multi-layer structure.

[0082] Exemplarily, the embodiment of the present invention may make the first reset transistor T5 include an oxide transistor. When the first reset transistor T5 includes an oxide transistor, optionally, the embodiment of the present invention may set the first reset transistor T5 as a top-bottom dual-gate transistor. In the embodiment of the present invention, Figure 5 As shown, the conductive film layer further includes a second semiconductor layer SC2 and a third metal layer MG located on a side of the second metal layer MC away from the substrate 1 . The third metal layer MG is located on a side of the second semiconductor layer SC2 away from the substrate 1 .

[0083] Exemplary, combined Figure 4 , Figure 5 , Fig. 9 and Fig.10 As shown, Fig. 9 A schematic top view of a second semiconductor layer provided in an embodiment of the present invention, Fig.10 A top view schematic diagram of a third metal layer provided for an embodiment of the present invention shows an area where two pixel driving circuit rows and four pixel driving circuit columns are located, the pixel driving circuit rows include a plurality of pixel driving circuits 21 arranged along a first direction h21, the pixel driving circuit columns include a plurality of pixel driving circuits 21 arranged along a second direction h22, and the second semiconductor layer SC2 includes a channel T50 of a first reset transistor T5.

[0084] Optionally, the second semiconductor layer SC2 includes an oxide semiconductor, such as IGZO.

[0085] For example, Figure 8 As shown, in the embodiment of the present invention, the bottom gate G51 of the first reset transistor T5 can also be disposed on the second metal layer MC.

[0086] like Fig.10 As shown, in an embodiment of the present invention, a top gate G52 of a first reset transistor T5 can be disposed in the third metal layer MG, and along a direction h1 perpendicular to the plane where the substrate 1 is located, a channel T50 of the first reset transistor T5 at least partially overlaps with the bottom gate G51 and the top gate G52 of the first reset transistor T5, respectively.

[0087] like Figure 4As shown, the display panel 100 further includes a second scan control signal line S1N, and the second scan control signal line S1N includes a fourth portion S1N1 and a fifth portion S1N2. Along a direction h1 perpendicular to the plane where the substrate 1 is located, the fourth portion S1N1 overlaps with the channel T50 of the first reset transistor T5, and the fifth portion S1N2 does not overlap with the channel T50 of the first reset transistor T5. In the embodiment of the present invention, the fourth portion S1N1 includes a third sub-portion S1N11 and a fourth sub-portion S1N12 that are stacked and electrically connected to each other, wherein the third sub-portion S1N11 is located on a side of the second semiconductor layer SC2 close to the substrate 1, and the fourth sub-portion S1N12 is located on a side of the second semiconductor layer SC2 away from the substrate 1. The third sub-portion S1N11 can be reused as the bottom gate G51 of the first reset transistor T5, and the fourth sub-portion S1N12 can be reused as the top gate G52 of the first reset transistor T5. Based on this arrangement, the control effect of turning on and off the first reset transistor T5 can be made more stable.

[0088] For example, Figure 4 and Figure 8 As shown, in the embodiment of the present invention, the third sub-portion S1N11 can be located in the second metal layer MC. Figure 4 and Fig.10 As shown, in the embodiment of the present invention, the fourth sub-portion S1N12 can be located in the third metal layer MG.

[0089] Optionally, the embodiment of the present invention may allow the fifth part S1N2 and the fourth sub-part S1N12 to be arranged in the same layer. Fig.10 The two are arranged in the same layer on the third metal layer MG as an example.

[0090] Exemplarily, the third metal layer MG may include an alloy of one or more materials such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), and vanadium (V), and may be formed into a single-layer or multi-layer structure.

[0091] Optionally, the embodiment of the present invention may further make the threshold compensation transistor T4 include an oxide transistor. When the threshold compensation transistor T4 includes an oxide transistor, optionally, the embodiment of the present invention may set the threshold compensation transistor T4 as a top-bottom dual-gate transistor.

[0092] like Fig. 9 As shown, the second semiconductor layer SC2 includes a channel T40 of the threshold compensation transistor T4.

[0093] For example, Figure 8As shown, in the embodiment of the present invention, the bottom gate G41 of the threshold compensation transistor T4 can also be set in the second metal layer MC. Fig.10 As shown, in the embodiment of the present invention, a top gate G42 of the threshold compensation transistor T4 may be provided in the third metal layer MG. Along the direction h1 perpendicular to the plane where the substrate 1 is located, the channel T40 of the threshold compensation transistor T4 at least partially overlaps with the bottom gate G41 and the top gate G42 of the threshold compensation transistor T4.

[0094] For example, Figure 4 As shown, the display panel 100 further includes a third scan control signal line S2N; the third scan control signal line S2N includes a sixth portion S2N1 and a seventh portion S2N2. Along the direction h1 perpendicular to the plane where the substrate 1 is located, the sixth portion S2N1 overlaps with the channel T40 of the threshold compensation transistor T4, and the seventh portion S2N2 does not overlap with the channel T40 of the threshold compensation transistor T4. The sixth portion S2N1 includes a fifth sub-portion S2N11 and a sixth sub-portion S2N12 which are stacked and electrically connected to each other, wherein the fifth sub-portion S2N11 is located on a side of the second semiconductor layer SC2 close to the substrate 1, and the sixth sub-portion S2N12 is located on a side of the second semiconductor layer SC2 away from the substrate 1. The fifth sub-portion S2N11 can be used as the bottom gate G41 of the threshold compensation transistor T4, and the sixth sub-portion S2N12 can be used as the top gate G42 of the threshold compensation transistor T4. Based on this arrangement, the control effect of turning on and off the threshold compensation transistor T4 can be made more stable.

[0095] For example, Figure 4 and Figure 8 As shown, the embodiment of the present invention can make the fifth sub-portion S2N11 located in the second metal layer MC. Figure 4 and Fig.10 As shown, in the embodiment of the present invention, the sixth sub-portion S2N12 can be located in the third metal layer MG.

[0096] Optionally, the embodiment of the present invention may allow the sixth sub-part S2N12 and the seventh part S2N2 to be arranged in the same layer. Fig.10 The two are arranged in the same layer on the third metal layer MG as an example.

[0097] Optional, such as Fig. 9 As shown, the channel T50 of the first reset transistor T5 and the channel T40 of the threshold compensation transistor T4 are arranged along the second direction h22, and both extend along the second direction h22.

[0098] For example, Figure 5 As shown, the display panel further includes a first source-drain electrode layer M2, and the first source-drain electrode layer M2 is located on a side of the second metal layer MC away from the substrate 1. Figure 5As shown, when the display panel includes the third metal layer MG, the first source and drain electrode layer M2 is located on a side of the third metal layer MG away from the substrate 1 .

[0099] Exemplarily, the first source-drain electrode layer M2 may include an alloy composed of one or more materials such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and copper (Cu), and may be formed into a single layer or a multilayer structure. For example, the first source-drain electrode layer M2 may be formed into a three-layer structure including Ti / Al / Ti to reduce the resistance of the wiring provided in the first source-drain electrode layer M2.

[0100] Optional, such as Figure 5 As shown, the display panel 100 further includes a second source-drain electrode layer M3, which is located on a side of the first source-drain electrode layer M2 away from the substrate 1. Figure 5 and Fig.12 As shown, Fig.12 A schematic top view of a second source-drain layer provided in an embodiment of the present invention. In the embodiment of the present invention, the data line DATA may be disposed in the second source-drain layer M3.

[0101] Exemplarily, the second source-drain electrode layer M3 may include an alloy composed of one or more materials such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and copper (Cu), and may be formed into a single layer or a multilayer structure. For example, the second source-drain electrode layer M3 may be formed into a three-layer structure including Ti / Al / Ti to reduce the resistance of the wiring arranged in the second source-drain electrode layer M3.

[0102] In the embodiment of the present invention, the first connection member 30 is located on a side of the second metal layer MC close to the substrate 1, and the data line DATA is located on a side of the second metal layer MC away from the substrate 1. For example, Figure 6 As shown, in the embodiment of the present invention, the first connection member 30 can be disposed on the first semiconductor layer SC1. Fig.12 As shown, the embodiment of the present invention can set the data line DATA in the second source and drain layer M3.

[0103] When the pixel driving circuit 21 is working, when the charging of the first node N1 is completed and the data voltage provided by the data line DATA changes, if the coupling capacitance between the data line DATA and the first connecting component 30 is large, the voltage change on the data line DATA will affect the potential on the first connecting component 30 through coupling. Since the first connecting component 30 is electrically connected to the second node N2, the signal change on the first connecting component 30 will affect the potential of the second node N2.

[0104] When the pixel driving circuit 21 is working, Figure 3 As shown, after the fourth scanning control signal line SP is switched from the enable level to the non-enable level, since the threshold compensation transistor T4 is still in the on state under the action of the third scanning control signal line S2N, if the potential of the second node N2 changes, the potential change of the second node N2 will be written into the first node N1 through the driving transistor T3 and the threshold compensation transistor T4, affecting the on state of the driving transistor T3. For example, in the light-emitting stage, when the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned on, the potential change of the first node N1 may cause the driving transistor T3 that should be in the off state to turn on, causing the light-emitting element 22 that should not emit light to emit light, resulting in unnecessary light emission. For example, when writing black to a local area of ​​the display panel, there will be bright lines or dark lines at the edge of the area, affecting the display effect of the display panel.

[0105] In the embodiment of the present invention, by placing the first connection member 30 on the first semiconductor layer SC1, the data line DATA can be placed on the side of the second metal layer MC away from the substrate 1. Figure 5 As shown, the data line DATA is arranged on the second source-drain layer M3 which is at a greater distance from the first semiconductor layer SC1, so that the distance between the first connection component 30 and the data line DATA in the direction h1 perpendicular to the plane where the substrate 1 is located can be increased, thereby reducing the coupling capacitance between the first connection component 30 and the data line DATA. When the data voltage transmitted by the data line DATA changes, the signal change amount of the second node N2 can be weakened, so that the potential change of the second node N2 can be prevented from affecting the potential change of the first node N1 through the driving transistor T3 and the threshold compensation transistor T4, thereby avoiding affecting the light emitting brightness of the light emitting element 22, and improving the brightness uniformity of the display panel.

[0106] It should be noted that Figure 2The pixel driving circuit 21 is merely described by taking the "8T1C" structure including 8 transistors and 1 storage capacitor as an example, where "T" represents a transistor and "C" represents a storage capacitor. Those skilled in the art may also set the pixel driving circuit 21 to other structures according to different design requirements, and the embodiment of the present invention does not limit the specific design of the pixel driving circuit 21.

[0107] Optional, such as Figure 4 As shown, in an embodiment of the present invention, a light-emitting control signal line EM is arranged on the connection path between the bias adjustment transistor T8 and the driving transistor T3, that is, along a direction h1 perpendicular to the plane where the substrate 1 is located, the first connecting component 30 will overlap with the light-emitting control signal line EM. Based on this arrangement, the area of ​​the pixel driving circuit 21 can be compressed, which is beneficial to improving the resolution of the display panel 100.

[0108] like Figure 4 and Fig.13 As shown, Fig.13 The enlarged schematic diagram of a light emitting control signal line provided by an embodiment of the present invention, the light emitting control signal line EM extends along a first direction h21, and the light emitting control signal line EM includes a first portion EM1 and a second portion EM2 that are electrically connected. Along the direction h1 perpendicular to the plane where the substrate 1 is located, the first portion EM1 and the channel T10 ( Fig.13 (not shown) overlap, the second portion EM2 and the first connecting member 30 ( Fig.13 Also, the first portion EM1 and the first connecting member 30 ( Fig.13 (not shown) do not overlap, the second portion EM2 and the channel T10 ( Fig.13 In the embodiment of the present invention, the first part EM1 is multiplexed as the gate G1 of the first light emitting control transistor T1.

[0109] like Fig.13 As shown, the first part EM1 includes a first sub-part EM11 and a second sub-part EM12 which are stacked. Along a direction h1 perpendicular to the plane where the substrate 1 is located, the first sub-part EM11 and the second sub-part EM12 overlap with the channel T10 of the first light emission control transistor T1. The first sub-part EM11 and the second sub-part EM12 are electrically connected. Exemplarily, the first sub-part EM11 and the second sub-part EM12 are electrically connected through a via K passing through the insulating layer therebetween.

[0110] In the embodiment of the present invention, combined with Figure 7 and Fig.13As shown, in the embodiment of the present invention, the first sub-portion EM11 can be disposed on the first metal layer M1 , and the second sub-portion EM2 can be disposed on a side of the first metal layer M1 away from the substrate 1 .

[0111] In the embodiment of the present invention, the second part EM2 is located on a side of the first metal layer M1 away from the substrate 1. Compared with the method of setting the second part EM2 on the first metal layer M1 or on a side of the first metal layer M1 close to the first semiconductor layer SC1, the distance between the second part EM2 and the first connecting part 30 can be increased. On the one hand, it can avoid the second part EM2 and the first connecting part 30 located on the first semiconductor layer SC1 from overlapping to form a thin film transistor device; on the other hand, it can reduce the coupling capacitance between the first connecting part 30 and the second part EM2, thereby reducing the interference of the high-frequency changing signal on the light-emitting control signal line EM on the potential on the first connecting part 30 electrically connected to the second node N2.

[0112] For example, Fig.10 and Fig.13 As shown, the embodiment of the present invention can make the second part EM2 located in the third metal layer MG to increase the distance between the second part EM2 and the first connecting part 30, avoid the second part EM2 and the first connecting part 30 overlapping to form a thin film transistor device, and reduce the interference of the high-frequency changing signal on the light-emitting control signal line EM on the potential on the first connecting part 30 electrically connected to the second node N2.

[0113] Or, if Fig.14 As shown, Fig.14 This is an enlarged schematic diagram of another light emitting control signal line provided by an embodiment of the present invention. In this embodiment of the present invention, the second portion EM2 can be located in the second metal layer MC.

[0114] In the embodiment of the present invention, the second sub-portion EM12 can play the role of connecting the first sub-portion EM11 and the second portion EM2 located in different film layers. Exemplarily, in the embodiment of the present invention, the second sub-portion EM12 and the second portion EM2 can be arranged in the same layer, that is, the entirety including the second sub-portion EM12 and the second portion EM2 is arranged to include a line segment extending along the first direction h21, so as to reduce the number of film layers of the light emitting control signal line EM and reduce the thickness of the display panel 100. Exemplarily, as Fig.10 and Fig.13 As shown, the second sub-portion EM12 and the second portion EM2 are arranged on the same layer in the third metal layer MG as an illustration. Fig.14 As an example, the second sub-portion EM12 and the second portion EM2 are arranged on the same layer in the second metal layer MC.

[0115] like Fig.10 , Fig.13 and Fig.14 As shown, the light emission control signal line EM further includes a third portion EM3, and along a direction h1 perpendicular to the plane of the substrate 1, the third portion EM3 does not overlap with the channel T10 of the first light emission control transistor T1 and the first connecting component 30. In the embodiment of the present invention, the third portion EM3 is disposed in the same layer or in a different layer as the second portion EM2.

[0116] Fig.10 and Fig.13 The third portion EM3 and the second portion EM2 are arranged on the same layer in the third metal layer MG as an example. Fig.14 The third part EM3 and the second part EM2 are arranged in the same layer on the second metal layer MC as an example. The third part EM3 and the second part EM2 arranged in the same layer can be formed by using the same material in the same patterning process, which simplifies the manufacturing process of the display panel. Fig.10 , Fig.13 and Fig.14 As shown, the third part EM3 and the second part EM2 can be connected to each other. When the two are arranged in the same layer, there may be no interface between the two, that is, the two can be regarded as an integral structure.

[0117] like Fig.10 , Fig.13 and Fig.14 As shown, the light emission control signal line EM also includes a fourth portion EM4, along the direction h1 perpendicular to the plane where the substrate 1 is located, the fourth portion EM4 overlaps with the channel T60 of the second light emission control transistor T6, and the fourth portion EM4 is multiplexed as the gate G6 of the second light emission control transistor T6. Figure 7 , Fig.10 , Fig.13 and Fig.14 As shown, the fourth part EM4 includes two parts stacked together, and the two parts are electrically connected through a via K passing through the insulating layer between the two parts. Fig.10 As shown, in the embodiment of the present invention, a part EM42 of the fourth part EM4 can be arranged in the same layer as the second part EM2 and the second sub-part EM12, such as Figure 7 As shown, in the embodiment of the present invention, another part EM41 in the fourth part EM4 can be arranged on the same layer as the first sub-part EM11. The third part EM3 can be used to electrically connect the fourth part EM4 and the second part EM2.

[0118] When the first semiconductor layer SC1 is provided, illustratively, as Figure 6As shown, the pixel driving circuit 21 includes a connection node N4, which is electrically connected to the bias adjustment transistor T8, the first light emission control transistor T1 and the driving transistor T3; specifically, the connection node N4 is electrically connected to the channel T80 of the bias adjustment transistor T8, the channel T10 of the first light emission control transistor T1 and the channel T30 of the driving transistor T3.

[0119] like Figure 6 As shown, the channel T80 of the bias adjustment transistor T8 and the channel T10 of the first light emission control transistor T1 are respectively located on both sides of the connection node N4. Wherein, the channel T80 of the bias adjustment transistor T8 and the channel T10 of the first light emission control transistor T1 are respectively located on both sides of the connection node N4, which can be understood as the channel T80 of the bias adjustment transistor T8 and the channel T10 of the first light emission control transistor T1 are located on both sides of a first reference line passing through the connection node N4, and the first reference line passes through the connection node N4 and extends along the first direction h21.

[0120] Optional, such as Figure 6 As shown, the first semiconductor layer SC1 includes a first sub-semiconductor portion X1 extending along the second direction h22, the first sub-semiconductor portion X1 includes a channel T80 of the bias adjustment transistor T8, a channel T10 of the first light emission control transistor T1, and a connection node N4. The first connection component 30 includes a first line segment 301 extending along the first direction h21 and a second line segment 302 extending along the second direction h22, the first line segment 301 electrically connects the connection node N4 and the second line segment 302, and the second line segment 302 electrically connects the first line segment 301 and the channel T30 of the driving transistor T3.

[0121] Or, if Fig.15 As shown, Fig.15 A top view schematic diagram of another first semiconductor layer provided by an embodiment of the present invention, wherein the channel T80 of the bias adjustment transistor T8 and the channel T10 of the first light emission control transistor T1 are located on the same side of the connection node N4. The channel T80 of the bias adjustment transistor T8 and the channel T10 of the first light emission control transistor T1 are located on the same side of the connection node N4, which can be understood as the channel T80 of the bias adjustment transistor T8 and the channel T10 of the first light emission control transistor T1 are located on the same side of the first reference line, and the first reference line passes through the connection node N4 and extends along the first direction h21.

[0122] like Fig.15 As shown, the channel T80 of the bias adjusting transistor T8 is electrically connected to the connection node N4 through the first connection part 30, and the connection node N4 is electrically connected to the channel T30 of the driving transistor T3.

[0123] Optional, such as Fig.15As shown, the first semiconductor layer SC1 includes a second sub-semiconductor portion X2, a third sub-semiconductor portion X3 and a fourth sub-semiconductor portion X4, the second sub-semiconductor portion X2 includes a channel T80 of a bias adjustment transistor T8; the third sub-semiconductor portion X3 includes a channel T10 of a first light emission control transistor T1; and the fourth sub-semiconductor portion X4 includes a first connecting component 30.

[0124] For example, Fig.15 As shown, the second sub-semiconductor portion X2 and the third sub-semiconductor portion X3 are parallel, and both intersect and connect with the first connection member 30. Fig.15 It is taken as an example that both extend along the second direction h22.

[0125] Optional, such as Fig.15 As shown, part of the first connecting member 30 extends along the third direction h23, and the third direction h23 intersects with both the first direction h21 and the second direction h22.

[0126] For example, Figure 6 and Fig.15 As shown, the embodiment of the present invention can arrange the channel T70 of the second reset transistor T7 and the channel T80 of the bias adjustment transistor T8 along the first direction h21, and arrange the channel T60 of the second light emission control transistor T6 and the channel T10 of the first light emission control transistor T1 along the first direction h21.

[0127] Optional, such as Figure 6 and Fig.15 As shown, along the first direction h21, the channel T60 of the second light emission control transistor T6 and the channel T10 of the first light emission control transistor T1 are respectively located on both sides of the channel T30 of the driving transistor T3. Along the second direction h22, the channel T20 of the data writing transistor T2 and the channel T80 of the bias adjustment transistor T8 are located on both sides of the channel T30 of the driving transistor T3.

[0128] For example, Figure 4 As shown, the first power voltage line PVDD includes a first sub power voltage line PVDD1 extending along a first direction h21.

[0129] Combination Figure 8 and Fig.11 As shown, Fig.11 A schematic top view of a first source-drain layer provided in an embodiment of the present invention, wherein the first sub-power supply voltage line PVDD1 includes a first sub-portion PVDD11 and a second sub-portion PVDD12 stacked, and the first sub-portion PVDD11 and the second sub-portion PVDD12 are electrically connected to reduce the resistance of the first sub-power supply voltage line PVDD1. Figure 8As shown, the first sub-portion PVDD11 is located in the second metal layer MC, and the first sub-portion PVDD11 is electrically connected to the second plate C2 of the storage capacitor Cst to provide the first sub-power supply voltage Vpvdd to the second plate C2 of the storage capacitor Cst. Fig.11 As shown, the second sub-portion PVDD12 of the first sub-power voltage line PVDD1 is located at the first source-drain layer M2.

[0130] Exemplarily, along a direction h1 perpendicular to the plane where the substrate 1 is located, the second sub-portion PVDD12 and the first sub-portion PVDD11 at least partially overlap.

[0131] Optional, such as Fig.11 As shown, the first source-drain layer M2 further includes a first connection portion L1 electrically connecting the second sub-portion PVDD12 and the first sub-portion PVDD11 .

[0132] For example, Fig.11 As shown, the first connection portion L1 extends from the second sub-portion PVDD12 along the second direction h22 to a side away from the second sub-portion PVDD12. The orthographic projection of the first connection portion L1 on the plane where the substrate 1 is located is located between two adjacent pixel circuits 21.

[0133] like Figure 4 As shown, the first power supply voltage line PVDD also includes a second sub-power supply voltage line PVDD2 extending along the second direction h22, and the second sub-power supply voltage line PVDD2 is electrically connected to the first sub-power supply voltage line PVDD1. The second sub-power supply voltage line PVDD2 and the first sub-power supply voltage line PVDD1 are arranged so that the first power supply voltage line PVDD can be formed into a grid structure, which can reduce the voltage drop of the first power supply voltage signal Vpvdd during transmission, and is conducive to improving the display uniformity of sub-pixels at different positions.

[0134] Optionally, the second sub-power supply voltage line PVDD2 and the first sub-power supply voltage line PVDD1 are arranged in different layers. Fig.12 The second sub-power voltage line PVDD2 is located at the second source-drain layer M3 as an example.

[0135] like Figure 4 As shown, the first scan control signal line SP* overlaps with the channel T80 of the bias adjustment transistor T8 along the direction h1 perpendicular to the plane of the substrate 1. The portion of the first scan control signal line SP* overlapping with the channel T80 of the bias adjustment transistor T8 is reused as the gate G8 of the bias adjustment transistor T8. Figure 4 and Figure 7 The first scan control signal line SP* is located in the first metal layer M1 as an example.

[0136] For example, Figure 4As shown, along a direction h1 perpendicular to the plane where the substrate 1 is located, the first scan control signal line SP* and the bias adjustment signal line DVH at least partially overlap, so as to reduce the area of ​​the pixel driving circuit 21 and improve the resolution of the display panel 100.

[0137] Figure 4 and Figure 7 The first scanning control signal line SP* is located in the first metal layer M1. Figure 4 and Fig.10 As an illustration, the bias adjustment signal line DVH includes a second sub-bias adjustment signal line DVH2 extending along the first direction h21, the second sub-bias adjustment signal line DVH2 is located in the third metal layer MG, and the first scan control signal line SP* and the second sub-bias adjustment signal line DVH2 at least partially overlap in the direction h1 perpendicular to the plane of the substrate 1.

[0138] For example, Fig.16 As shown, Fig.16 A simplified schematic diagram of another display panel provided by an embodiment of the present invention, the display area AA includes a first display area AA1 and a second display area AA2, and along a first direction h21, the first display area AA1 is located at least on one side of the second display area AA2. Fig.16 As shown, the display area AA includes two first display areas AA1. Along the first direction h21, the two first display areas AA1 are located on both sides of the second display area AA2. In other words, the first display area AA1 is closer to the edge E of the display panel 100 than the second display area AA2.

[0139] In the embodiment of the present invention, the data lines DATA include a first data line DATA1 located in the first display area AA1 and a second data line DATA2 located in the second display area AA2.

[0140] like Fig.16 As shown, the display panel 100 also includes a non-display area NA at least partially surrounding the display area AA; the non-display area NA includes a fan-out area FA located on one side of the display area AA along the second direction h22, the fan-out area FA includes multiple fan-out wirings 6, and the data lines DATA are connected to the fan-out wirings 6.

[0141] like Fig.16 As shown, the display area AA further includes a connection line 5. Exemplarily, the fan-out line 6 includes a first fan-out line 61 and a second fan-out line 62, and the first data line DATA1 is connected to the first fan-out line 61 through the connection line 5; the second data line DATA2 can be directly electrically connected to the second fan-out line 62. The first fan-out line 61 and the second fan-out line 62 are electrically connected to the pin 63.

[0142] like Fig.16As shown, the connection line 5 includes a first connection line 51 and a second connection line 52 that are electrically connected. The first connection line 51 is electrically connected to the first data line DATA1 . The first connection line 51 extends along a first direction h21 , and the second connection line 52 extends along a second direction h22 .

[0143] In an embodiment of the present invention, the first data line DATA1 in the first display area AA1 can be electrically connected to the first fan-out wiring 61 through the connecting line 5, and the second data line DATA2 in the second display area AA2 can be directly electrically connected to the second fan-out wiring 62. Adopting this setting mode is equivalent to laying out part of the fan-out lines in the display area (Fanout in AA, referred to as FIAA), which can reduce the space occupied by the fan-out wiring 6, and further reduce the area of ​​the fan-out area FA, so as to reduce the area ratio of the non-display area NA in the display panel, and increase the area ratio of the display area AA in the display panel, that is, improve the screen-to-body ratio of the display panel and improve the user experience.

[0144] Moreover, if Fig.16 As shown, the second connection line 52 is located on the side of the first data line DATA1 connected thereto close to the second display area AA2. Based on this arrangement, the first fan-out line 61 to be connected to the first data line DATA1 can be led out from a position close to the middle area in the display area AA, thereby preventing the first fan-out line 61 connected to the first data line DATA1 in the first display area AA1 from being led out from an area close to a corner in the frame of the display panel 100, which is beneficial to reducing the frame width at the corner of the display panel 100 and optimizing the visual effect of the display panel.

[0145] The embodiment of the present invention can adjust the film layer positions of the first connection line 51 and the second connection line 52 according to the different film layer settings in the display panel 100. For example, the embodiment of the present invention can make the first connection line 51 and the second connection line 52 be set in different layers, and the two are electrically connected through vias. Alternatively, the embodiment of the present invention can also make the first connection line 51 and the second connection line 52 be set in the same layer.

[0146] When the first connection line 51 and the second connection line 52 are arranged in different layers, illustratively, the embodiment of the present invention can make the second connection line 52 and the first connection line 51 located in two adjacent conductive layers to reduce the difficulty of setting the via hole, wherein the via hole is used to electrically connect the first connection line 51 and the second connection line 52. The two adjacent conductive layers refer to the two conductive layers closest to each other in the display panel 100. For example, Figure 5 The first source-drain electrode layer M2 and the second source-drain electrode layer M3 are two adjacent conductive layers.

[0147] When the first connection line 51 and the second connection line 52 are arranged in different layers, optionally, the embodiment of the present invention can make the second connection line 52 be located on a side of the first connection line 51 away from the substrate.

[0148] Exemplary, reference Fig.17 and Fig.18 As shown, Fig.17 A wiring diagram of another display panel provided by an embodiment of the present invention, Fig.18 This is a schematic top view of another first source-drain layer provided by an embodiment of the present invention. In this embodiment of the present invention, the first connecting line 51 can be located in the first source-drain layer M2.

[0149] refer to Fig.17 and Fig.19 As shown, Fig.19 This is a schematic top view of another second source-drain layer provided by an embodiment of the present invention. The second connecting line 52 may be located in the second source-drain layer M3.

[0150] In the embodiment of the present invention, the second connecting line 52 is located on a side of the first connecting component 30 away from the substrate 1 .

[0151] For example, in the embodiment of the present invention, the second connection line 52 may be located on a side of the second metal layer MC away from the substrate 1, for example, Fig.19 As shown, the second connection line 52 is set in the second source-drain layer M3 which is at a greater distance from the first connection component 30, so that the distance between the first connection component 30 and the second connection line 52 in the direction h1 perpendicular to the plane where the substrate 1 is located can be increased, thereby reducing the coupling capacitance between the first connection component 30 and the second connection line 52. When the data voltage transmitted by the second connection line 52 changes, the signal change amount of the second node N2 can be weakened, thereby avoiding the potential change of the second node N2 from affecting the potential change of the first node N1 through the driving transistor T3 and the threshold compensation transistor T4, thereby avoiding affecting the luminous brightness of the light-emitting element 22 and improving the brightness uniformity of the display panel.

[0152] For example, in the embodiment of the present invention, along the direction h1 perpendicular to the plane of the substrate 1, one of the data line DATA and the second connection line 52 at least partially overlaps with the first connection component 30. Based on this arrangement, the area of ​​the pixel driving circuit 21 can be compressed, which is beneficial to improving the resolution of the display panel 100. Fig.17 In the direction h1 perpendicular to the plane of the substrate 1, the data line DATA overlaps with the first connection component 30 as an illustration. In other configurations, the relative positions of the data line DATA and the second connection line 52 can be adjusted to set the second connection line 52 to at least partially overlap with the first connection component 30, which is not illustrated in the figure.

[0153] Exemplarily, in the embodiment of the present invention, along the first direction h21, the fixed signal line and the second connection line 52 are located between two adjacent data lines DATA; wherein the fixed signal line is used to transmit one of the first reset voltage Vref1, the second reset voltage Vref2 and the bias adjustment voltage Vdvh. Fig.19 As shown, two fixed signal lines 8 are shown, one transmitting the second reset voltage Vref2, and the other transmitting the bias adjustment voltage Vdvh, that is, one fixed signal line 8 is the second reset signal line REF2, and the other fixed signal line 8 is the bias adjustment signal line DVH as an illustration.

[0154] For example, Fig. 20 As shown, Fig. 20 A simplified schematic diagram of another display panel provided for an embodiment of the present invention, wherein the first reset signal line REF1 includes a first sub-reset signal line REF11 extending along a second direction h22; the second reset signal line REF2 includes a second sub-reset signal line REF21 extending along the second direction h22; the bias adjustment signal line DVH includes a first sub-bias adjustment signal line DVH1 extending along the second direction h22; the above-mentioned fixed signal line includes any one or more of the first sub-reset signal line REF11, the second sub-reset signal line REF21 and the first sub-bias adjustment signal line DVH1.

[0155] In the embodiment of the present invention, any two or three of the first sub reset signal line REF11 , the second sub reset signal line REF21 , and the first sub bias adjustment signal line DVH1 are alternately arranged along the first direction h21 .

[0156] like Fig. 20 As shown, the three are alternately arranged in the order of the second sub-reset signal line REF21, the first sub-reset signal line REF11 and the first sub-bias adjustment signal line DVH1 as an illustration. Of course, they can also be alternately arranged in other arrangements such as the first sub-reset signal line REF11, the first sub-bias adjustment signal line DVH and the second sub-reset signal line REF21, which are not illustrated one by one here. Based on this setting method, the fixed signal lines that transmit different signals can be dispersed as evenly as possible in the display panel, and the voltage drop of multiple fixed signals can be reduced in a limited space.

[0157] like Fig.21 As shown, Fig.21 A simplified schematic diagram of another display panel provided by an embodiment of the present invention is shown, in which the first sub-reset signal line REF11 and the second sub-reset signal line REF21 are alternately arranged in sequence along the first direction h21 as an illustration.

[0158] like Fig. 22 As shown, Fig. 22A simplified schematic diagram of another display panel provided by an embodiment of the present invention is shown, in which the first sub-reset signal line REF11 and the first sub-bias adjustment signal line DVH1 are alternately arranged in sequence along the first direction h21 as an illustration.

[0159] like Fig.23 As shown, Fig.23 A simplified schematic diagram of another display panel provided by an embodiment of the present invention is shown, in which the second sub-reset signal line REF21 and the first sub-bias adjustment signal line DVH1 are alternately arranged in sequence along the first direction h21 as an illustration.

[0160] For example, Figure 4 and Fig.17 As shown, the first reset signal line REF1 also includes a third sub-reset signal line REF12 electrically connected to the first sub-reset signal line REF11, and the third sub-reset signal line REF12 extends along the first direction h21. Based on this arrangement, the first reset signal line REF1 can be formed into a grid structure, increasing the transmission path of the first reset voltage Vref1, reducing the voltage drop of the first reset voltage Vref1 during the transmission process, and improving the potential consistency of the first reset voltage Vref1 received by the pixel driving circuit 21 at different positions, thereby making the display effects of the light-emitting elements 22 at different positions tend to be consistent.

[0161] like Figure 4 and Fig.17 As shown, the second reset signal line REF2 also includes a fourth sub-reset signal line REF22 electrically connected to the second sub-reset signal line REF21, and the fourth sub-reset signal line REF22 extends along the first direction h21. Based on this arrangement, the second reset signal line REF2 can be formed into a grid structure, increasing the transmission path of the second reset voltage Vref2, reducing the voltage drop of the second reset voltage Vref2 during the transmission process, and improving the potential consistency of the second reset voltage Vref2 received by the pixel driving circuits at different positions, thereby making the display effects of the light-emitting elements 22 at different positions tend to be consistent.

[0162] like Figure 4 and Fig.17As shown, the bias adjustment signal line DVH includes a second sub-bias adjustment signal line DVH2 electrically connected to the first sub-bias adjustment signal line DVH1, and the second sub-bias adjustment signal line DVH2 extends along the first direction h21. Based on this arrangement, the bias adjustment signal line DVH can be formed into a grid structure, increasing the transmission path of the bias adjustment voltage Vdvh, reducing the voltage drop of the bias adjustment voltage Vdvh during the transmission process, and improving the potential consistency of the corresponding fixed signals received by the pixel driving circuit 21 at different positions, such as the first reset voltage Vref1, the second reset voltage Vref2 and the bias adjustment voltage Vdvh, so as to make the display effects of the light-emitting elements 22 at different positions tend to be consistent.

[0163] Exemplarily, in the embodiment of the present invention, the third sub-reset signal line REF12 and the first sub-reset signal line REF11 are arranged at different layers. The fourth sub-reset signal line REF22 and the second sub-reset signal line REF21 are arranged at different layers. The second sub-bias adjustment signal line DVH2 and the first sub-bias adjustment signal line DVH1 are arranged at different layers.

[0164] Optionally, in the embodiment of the present invention, at least two of the first sub-reset signal line REF11 , the second sub-reset signal line REF21 , and the first sub-bias adjustment signal line DVH1 may be disposed in the same layer.

[0165] Optional, such as Figure 7 As shown, in the embodiment of the present invention, the third sub-reset signal line REF12 can be located in the first metal layer M1, and the first sub-reset signal line REF11 can be located in the second source-drain layer M3, and the two can be electrically connected through vias.

[0166] For example, Figure 8 As shown, the embodiment of the present invention can make the fourth sub-reset signal line REF22 located in the second metal layer MC, and as Fig.12 and Fig.19 As shown, the second sub-reset signal line REF21 is located at the second source-drain layer M3, and the fourth sub-reset signal line REF22 is electrically connected to the second sub-reset signal line REF21 through a via hole.

[0167] Optional, such as Fig.10 As shown, the embodiment of the present invention can make the second sub-bias adjustment signal line DVH2 located in the third metal layer MG, and as Fig.12 and Fig.19 As shown, the first sub-bias adjustment signal line DVH1 is located in the second source-drain layer M3, and the second sub-bias adjustment signal line DVH2 is electrically connected to the first sub-bias adjustment signal line DVH1 through a via hole.

[0168] In the embodiment of the present invention, at least two of the data line DATA, the second connection line 52, the first sub-reset signal line REF11, the second sub-reset signal line REF21 and the first sub-bias adjustment signal line DVH1 are arranged in the same layer. Based on this arrangement, the number of film layers in the display panel can be reduced, the manufacturing process of the display panel can be simplified, and the thickness of the display panel can be reduced. Fig.19 As an example, the second sub power voltage line PVDD2 , the data line DATA, the second connection line 52 , the second sub reset signal line REF21 , and the first sub bias adjustment signal line DVH1 are all disposed in the second source-drain layer M3 .

[0169] For example, Fig.19 As shown, along the first direction h21, the second connection line 52 is located between two adjacent data lines DATA.

[0170] Or, if Fig.24 As shown, Fig.24 A simplified schematic diagram of another display panel provided by an embodiment of the present invention, the embodiment of the present invention can adjust the relative position relationship between the data line DATA and the second connection line 52, so that the data line DATA is located between two adjacent second connection lines 52 along the first direction h21. The second sub-power voltage line PVDD2 is located on the side of the second connection line 52 away from the data line DATA. For example, Fig.24 As shown, along a direction perpendicular to the plane where the substrate is located, the second connection line 52 at least partially overlaps with the pixel driving circuit 21.

[0171] For example, Fig.25 and Fig.26 As shown, Fig.25 A wiring diagram of another pixel driving circuit provided by an embodiment of the present invention is shown. Fig.26 for Fig.25 A schematic diagram of the second electrode plate and the shielding component, the display panel also includes a shielding component 7, and the shielding component 7 receives a constant signal.

[0172] In the embodiment of the present invention, Fig.25 As shown, along the direction perpendicular to the plane where the substrate 1 is located, the shielding component 7 is located between the data line DATA and the first connecting component 30, and the shielding component 7 at least partially overlaps with the data line DATA and the first connecting component 30. In the embodiment of the present invention, the provision of the shielding component 7 can further weaken the coupling capacitance between the data line DATA and the first connecting component 30, thereby reducing the interference of the signal change on the data line DATA on the signal on the first connecting component 30, which is beneficial to improving the potential stability of the second node N2, thereby improving the potential stability of the first node N1, and improving the display uniformity of the display panel.

[0173] Alternatively, when adjusting the relative positional relationship between the data line DATA and the second connection line 52, the embodiment of the present invention can also make the shielding component located between the second connection line and the first connection component, and make the shielding component at least partially overlap with the second connection line and the first connection component in a direction perpendicular to the plane where the substrate is located. Based on this setting, the shielding component can reduce the coupling capacitance between the second connection line and the first connection component, thereby reducing the interference of the signal change on the second connection line on the signal on the first connection component, which is conducive to improving the potential stability of the second node N2, thereby improving the potential stability of the first node N1, and improving the display uniformity of the display panel.

[0174] Optionally, the constant signal transmitted by the shielding component 7 includes any one of the first power supply voltage Vpvdd, the first reset voltage Vref1, the second reset voltage Vref2, and the bias adjustment voltage Vdvh.

[0175] For example, Fig.25 and Fig.26 As shown, the shielding component 7 is electrically connected to the second electrode plate C2, so that the shielding component 7 receives the first power supply voltage Vpvdd through the second electrode plate C2.

[0176] For example, Fig.25 and Fig.26 As shown, the shielding component 7 is disposed on the second metal layer MC in the same layer as the second electrode plate C2. The shielding component 7 protrudes from the second electrode plate C2 along the second direction h22 toward a side away from the second electrode plate C2.

[0177] Or, if Fig. 27 and Fig.28 As shown, Fig. 27 A wiring diagram of another pixel driving circuit provided by an embodiment of the present invention is shown. Fig.28 for Fig. 27 Schematic diagram of the shielding component and the second sub-bias adjustment signal line in FIG. 1 , wherein the shielding component 7 is electrically connected to the bias adjustment signal line DVH so that the shielding component 7 receives the bias adjustment voltage Vdvh. Fig. 27 As an illustration, the shielding component 7 is arranged on the same layer as the second sub-bias adjustment signal line on the third metal layer MG, and the second sub-portion and the second portion of the light emitting control signal line EM are located on the second metal layer MC.

[0178] Alternatively, the embodiment of the present invention may also electrically connect the shielding component 7 to the first reset signal line REF1 or the second reset signal line REF2. Fig.29 and Fig.30 As shown, Fig.29 A wiring diagram of another pixel driving circuit provided by an embodiment of the present invention is shown. Fig.30 for Fig.29Schematic diagram of a shielding component and a fourth sub-reset signal line in , wherein the shielding component 7 is electrically connected to the fourth sub-reset signal line REF22 in the second reset signal line REF2, so that the shielding component 7 receives the biased second reset voltage Vref2.

[0179] For example, Figure 4 , Fig.17 , Fig.25 and Fig. 27 As shown, the embodiment of the present invention can symmetrically arrange two adjacent pixel driving circuits 21 in the first direction h21, and the symmetry line extends along the second direction h22. Specifically, the transistors in the two adjacent pixel driving circuits 21 in the first direction h21 are symmetrically arranged about the symmetry line, such as the first light-emitting control transistors T1 in the two adjacent pixel driving circuits 21 in the first direction h21 are symmetrical about the symmetry line. Based on this arrangement, some transistors in the two adjacent pixel driving circuits 21 can share a via hole to be electrically connected to the corresponding signal line, which can simplify the structure of the pixel driving circuit and help reduce the area of ​​the pixel driving circuit. For example, Figure 4 As shown, in the embodiment of the present invention, the bias adjustment transistors T8 in two adjacent pixel driving circuits 21 in the first direction h21 can be electrically connected to the bias adjustment signal line DVH through the same via hole.

[0180] For example, Figure 4 , Fig.17 , Fig.25 and Fig. 27 As shown, the orthographic projection of the fourth sub-reset signal line REF22 on the plane where the substrate 1 is located, the orthographic projection of the first scan control signal line SP* on the plane where the substrate 1 is located, the orthographic projection of the light-emitting control signal line EM on the plane where the substrate 1 is located, the orthographic projection of the first sub-power supply voltage line PVDD1 on the plane where the substrate 1 is located, the orthographic projection of the fourth scan control signal line SP on the plane where the substrate 1 is located, the orthographic projection of the third scan control signal line S2N on the plane where the substrate 1 is located, the orthographic projection of the second scan control signal line S1N on the plane where the substrate 1 is located and the orthographic projection of the third sub-reset signal line REF12 on the plane where the substrate 1 is located are arranged in sequence along the second direction h22.

[0181] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.31 As shown, Fig.31 Schematic diagram of a display device provided in an embodiment of the present invention, the display device includes the above-mentioned display panel 100. The specific structure of the display panel 100 has been described in detail in the above-mentioned embodiment, and will not be repeated here. Fig.31The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a car display screen, a tablet computer, a laptop computer, an e-reader or a television.

[0182] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0183] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: substrate; A data line and a pixel driving circuit located on one side of the substrate; The pixel driving circuit includes a driving transistor, a bias adjusting transistor and a first connecting component, wherein the gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node; the first connecting component is electrically connected to the bias adjusting transistor and the second node; The display panel further includes a first semiconductor layer and a first metal layer, and the first semiconductor layer and the first metal layer are sequentially stacked in a direction away from the substrate; the first semiconductor layer includes a channel of the driving transistor and a channel of the bias adjusting transistor, and the first metal layer includes a gate of the driving transistor and a gate of the bias adjusting transistor; The first connecting component is located in the first semiconductor layer.

2. The display panel according to claim 1, characterized in that: The pixel driving circuit further includes a first light emission control transistor, and the first semiconductor layer further includes a channel of the first light emission control transistor; The display panel further includes a light emitting control signal line, the light emitting control signal line extending in a first direction, the light emitting control signal line including a first portion and a second portion electrically connected, the first portion overlapping with a channel of the first light emitting control transistor in a direction perpendicular to a plane where the substrate is located, and the second portion overlapping with the first connecting component; The first portion includes a first sub-portion and a second sub-portion arranged in a stacked manner, and the first sub-portion and the second sub-portion are electrically connected; The first sub-portion is located at the first metal layer, and the second sub-portion and the second portion are located at a side of the first metal layer away from the substrate.

3. The display panel according to claim 2, characterized in that: The pixel driving circuit includes a connection node, the connection node electrically connecting the bias adjustment transistor, the first light emission control transistor and the driving transistor; The channel of the bias adjustment transistor and the channel of the first light emission control transistor are respectively located on both sides of the connection node; or, A channel of the bias adjustment transistor and a channel of the first light emission control transistor are located on the same side of the connection node.

4. The display panel according to claim 2, characterized in that: The light-emitting control signal line also includes a third part, which does not overlap with the channel of the first light-emitting control transistor and the first connecting component along a direction perpendicular to the plane of the substrate, and is arranged in the same layer or in a different layer as the second part.

5. The display panel according to claim 2, characterized in that: Also comprising a second metal layer, the second metal layer is located on a side of the first metal layer away from the substrate; The second portion is located in the second metal layer.

6. The display panel according to claim 1, characterized in that: Also includes a first scan control signal line and a bias adjustment signal line; The bias adjustment transistor is electrically connected to the bias adjustment signal line and the second node; Along a direction perpendicular to a plane where the substrate is located, the first scanning control signal line overlaps with a channel of the bias adjustment transistor.

7. The display panel according to claim 6, characterized in that: Along a direction perpendicular to a plane where the substrate is located, the first scanning control signal line at least partially overlaps with the bias adjustment signal line.

8. The display panel according to claim 2, characterized in that: The pixel driving circuit further includes a first reset transistor; the first reset transistor is electrically connected to the first reset signal line and the first node; the first reset transistor includes an oxide transistor; The display panel further comprises a second semiconductor layer, a second metal layer and a third metal layer, wherein the second metal layer is located on a side of the first metal layer away from the substrate; The second semiconductor layer is located between the second metal layer and the third metal layer; the second semiconductor layer includes a channel of the first reset transistor.

9. The display panel according to claim 8, characterized in that: The second portion is located in the third metal layer.

10. The display panel according to claim 8, characterized in that: Also includes a second scanning control signal line, The second scanning control signal line includes a fourth portion and a fifth portion, and along a direction perpendicular to the plane where the substrate is located, the fourth portion overlaps with the channel of the first reset transistor, and the fifth portion does not overlap with the channel of the first reset transistor; The fourth portion includes a third sub-portion and a fourth sub-portion which are stacked, the third sub-portion is located in the second metal layer, and the fourth sub-portion and the fifth portion are located in the third metal layer.

11. The display panel according to claim 8, characterized in that: The pixel driving circuit further includes a threshold compensation transistor, the threshold compensation transistor electrically connecting the third node and the first node; the threshold compensation transistor includes an oxide transistor; The second semiconductor layer includes a channel of the threshold compensation transistor.

12. The display panel according to claim 11, characterized in that: It also includes a third scan control signal line; the third scan control signal line includes a sixth portion and a seventh portion, along a direction perpendicular to the plane where the substrate is located, the sixth portion overlaps with the channel of the threshold compensation transistor, and the seventh portion does not overlap with the channel of the threshold compensation transistor; The sixth portion includes a fifth sub-portion and a sixth sub-portion which are stacked, the fifth sub-portion is located in the second metal layer, and the sixth sub-portion and the seventh portion are located in the third metal layer.

13. The display panel according to claim 2, characterized in that: Also comprising a first power supply voltage line, the first power supply voltage line being electrically connected to the first light emission control transistor; The display panel further includes a second metal layer and a first source-drain electrode layer, wherein the second metal layer is located on a side of the first metal layer away from the substrate, and the first source-drain electrode layer is located on a side of the second metal layer away from the substrate; The first power supply voltage line includes a first sub-power supply voltage line extending along the first direction, the first sub-power supply voltage line includes a first sub-portion and a second sub-portion arranged in a stacked manner, the first sub-portion is located in the second metal layer, the second sub-portion is located in the first source and drain layer, and the first sub-portion and the second sub-portion are electrically connected.

14. The display panel according to claim 1, characterized in that: The data line includes a first data line; The display panel further includes connecting lines, the connecting lines including a first connecting line and a second connecting line that are electrically connected, the first connecting line is electrically connected to the first data line, the first connecting line extends along a first direction, the second connecting line extends along a second direction, and the first direction intersects the second direction; The second connection line is located at a side of the first connection component away from the substrate.

15. The display panel according to claim 14, characterized in that: The display panel includes a first source-drain layer and a second source-drain layer, the first source-drain layer is located on a side of the first metal layer away from the substrate, the second source-drain layer is located on a side of the first source-drain layer away from the first metal layer, the first connecting line is located in the first source-drain layer, and the second connecting line is located in the second source-drain layer.

16. The display panel according to claim 14, characterized in that: Along a direction perpendicular to a plane where the substrate is located, one of the second connection line and the data line at least partially overlaps with the first connection component.

17. The display panel according to claim 14, characterized in that: It also includes a light emitting element electrically connected to the pixel driving circuit; the pixel driving circuit also includes a first reset transistor and a second reset transistor; The first reset transistor is electrically connected to a first reset signal line and the first node, the first reset signal line transmitting a first reset voltage; The second reset transistor is electrically connected to the second reset signal line and the light emitting element, and the second reset signal line transmits a second reset voltage; The bias adjustment transistor is electrically connected to a bias adjustment signal line and the second node, and the bias adjustment signal line transmits a bias adjustment voltage; Along the first direction, the fixed signal line and the second connection line are located between two adjacent data lines; wherein the fixed signal line is used to transmit one of the first reset voltage, the second reset voltage and the bias adjustment voltage.

18. The display panel according to claim 17, characterized in that: The first reset signal line includes a first sub-reset signal line extending along the second direction; The second reset signal line includes a second sub-reset signal line extending along the second direction; The bias adjustment signal line includes a first sub-bias adjustment signal line extending along the second direction; Any two or three of the first sub-reset signal lines, the second sub-reset signal lines, and the first sub-bias adjustment signal lines are alternately arranged along the first direction.

19. The display panel according to claim 18, characterized in that: The first reset signal line further includes a third sub-reset signal line electrically connected to the first sub-reset signal line, and the third sub-reset signal line extends along the first direction; The second reset signal line further includes a fourth sub-reset signal line electrically connected to the second sub-reset signal line, and the fourth sub-reset signal line extends along the first direction; The bias adjustment signal line includes a second sub-bias adjustment signal line electrically connected to the first sub-bias adjustment signal line, and the second sub-bias adjustment signal line extends along the first direction.

20. The display panel according to claim 18, characterized in that: At least two of the data line, the second connection line, the first sub-reset signal line, the second sub-reset signal line, and the first sub-bias adjustment signal line are disposed in the same layer.

21. The display panel according to claim 14, characterized in that: Along the first direction, the data line is located between two adjacent second connection lines.

22. The display panel according to claim 21, characterized in that: The display panel includes a first source-drain layer and a second source-drain layer, the first source-drain layer is located on a side of the first metal layer away from the substrate, the second source-drain layer is located on a side of the first source-drain layer away from the first metal layer, the first connecting line is located in the first source-drain layer, and the second connecting line is located in the second source-drain layer.

23. The display panel according to claim 14, characterized in that: Also included is a shielding component, the shielding component receiving a constant signal; Along a direction perpendicular to the plane where the substrate is located, the shielding component is located between the second connecting line and the first connecting component, and the shielding component at least partially overlaps with the second connecting line and the first connecting component; or, Along a direction perpendicular to the plane where the substrate is located, the shielding component is located between the data line and the first connecting component, and the shielding component at least partially overlaps with the data line and the first connecting component.

24. The display panel according to claim 23, characterized in that: The pixel driving circuit further includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, and along a direction perpendicular to the plane where the substrate is located, the first electrode plate overlaps with the channel of the driving transistor; The first electrode plate is located between the substrate and the second electrode plate; The shielding component is electrically connected to the second electrode plate.

25. The display panel according to claim 23, characterized in that: The bias adjustment transistor is electrically connected to the bias adjustment signal line and the second node; The shielding member is electrically connected to the bias adjustment signal line.

26. The display panel according to claim 23, characterized in that: Also includes a light emitting element electrically connected to the pixel driving circuit; The pixel driving circuit includes a first reset transistor and a second reset transistor, the first reset transistor is electrically connected to a first reset signal line and the first node, and the second reset transistor is electrically connected to a second reset signal line and the light emitting element; The shielding component is electrically connected to the first reset signal line or the second reset signal line.

27. A display device, characterized in that: A display panel comprising any one of claims 1-26.

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