Bidirectional thyristor electrostatic protection device and preparation method thereof

Abstract

The application provides a bidirectional thyristor electrostatic protection device and a preparation method thereof. The bidirectional thyristor electrostatic protection device comprises, from bottom to top, a P-type substrate, an N-type buried layer and a P-type epitaxial layer, and a device structure formed in the P-type epitaxial layer; wherein the device structure comprises a first P-type buried layer and a second P-type buried layer, a first P-type well, a first N-type well, a second P-type well, a second N-type well and a third P-type well formed above the two P-type buried layers, a first P+ injection region, a first N+ injection region, a second P+ injection region, a third P+ injection region, a fourth P+ injection region, a second N+ injection region, a fifth P+ injection region, a sixth P+ injection region, a seventh P+ injection region, a third N+ injection region and an eighth P+ injection region formed in each well, and a first gate and a second gate formed on part of the P-type epitaxial layer. The application solves the problem of high trigger voltage and low holding voltage of the existing thyristor device applied to a 5V window.

Description

Technical Field

[0001] The present invention relates to the field of electrostatic protection, and in particular to a bidirectional thyristor electrostatic protection device and a preparation method thereof. Background Art

[0002] With the advancement of semiconductor manufacturing processes, electrostatic discharge (ESD) has caused more and more serious failures of integrated circuit chips and electronic products. Therefore, ESD protection for integrated circuit chips and electronic products has become one of the major challenges facing product engineers.

[0003] Compared with other ESD devices, traditional thyristor devices (SCRs) have advantages such as high discharge efficiency per unit area, low unit parasitic capacitance, and good robustness. However, in the low-voltage application window, traditional thyristor devices have the disadvantages of too high a trigger voltage and too low a holding voltage. Excessively high trigger voltage will cause the device to fail to protect the core circuit in a timely manner and there is a risk of breakdown of the gate oxide layer of the 5V device in the core circuit. Excessively low holding voltage will cause the device to experience a latch-up effect, and the integrity of the I / O port transmission signal cannot be guaranteed.

[0004] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of the present invention and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the technical background section of the present invention, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a bidirectional thyristor electrostatic protection device and a preparation method thereof, which are used to solve the problem of high trigger voltage and low holding voltage of the existing thyristor devices used in the 5V design window.

[0006] To achieve the above-mentioned and other related purposes, the present invention provides a bidirectional thyristor electrostatic protection device, the bidirectional thyristor electrostatic protection device comprising:

[0007] A P-type substrate, an N-type buried layer, and a P-type epitaxial layer stacked from bottom to top, and a device structure formed in the P-type epitaxial layer; wherein the device structure includes:

[0008] a first P-type buried layer and a second P-type buried layer formed on the N-type buried layer, and the two are arranged in a lateral interval; a first P-type well and a first N-type well formed on the first P-type buried layer, a second P-type well formed on the interval between the first P-type buried layer and the second P-type buried layer, a second N-type well and a third P-type well formed on the second P-type buried layer, and each well is arranged adjacent to each other in the lateral direction; a first P+ injection region formed in the first P-type well, a first N+ injection region, a second P+ injection region and a third P+ injection region formed in the first N-type well, a fourth P+ injection region formed in the first N-type well and the second P-type well a P+ injection region, a second N+ injection region formed in the second P-type well, a fifth P+ injection region formed in the second P-type well and the second N-type well, a sixth P+ injection region, a seventh P+ injection region and a third N+ injection region formed in the second N-type well, and an eighth P+ injection region formed in the third P-type well, wherein the injection regions are sequentially spaced apart in a lateral direction; a first gate formed on the P-type epitaxial layer at a gap between the third P+ injection region and the fourth P+ injection region, and a second gate formed on the P-type epitaxial layer at a gap between the fifth P+ injection region and the sixth P+ injection region;

[0009] Among them, the first P+ injection region, the first N+ injection region and the second P+ injection region are connected together and serve as anodes, the first gate, the fourth P+ injection region, the second N+ injection region, the fifth P+ injection region and the second gate are connected together, and the seventh P+ injection region, the third N+ injection region and the eighth P+ injection region are connected together and serve as cathodes.

[0010] Optionally, the device structure also includes: a first field oxygen isolation region formed between the first P+ injection region and the first N+ injection region, a second field oxygen isolation region formed between the first N+ injection region and the second P+ injection region, a third field oxygen isolation region formed between the second P+ injection region and the third P+ injection region, a fourth field oxygen isolation region formed between the fourth P+ injection region and the second N+ injection region, a fifth field oxygen isolation region formed between the second N+ injection region and the fifth P+ injection region, a sixth field oxygen isolation region formed between the sixth P+ injection region and the seventh P+ injection region, a seventh field oxygen isolation region formed between the seventh P+ injection region and the third N+ injection region, and an eighth field oxygen isolation region formed between the third N+ injection region and the eighth P+ injection region.

[0011] Optionally, the bidirectional thyristor electrostatic protection device further includes: an isolation structure formed outside the device structure in the P-type epitaxial layer.

[0012] Optionally, the isolation structure includes: a first high-voltage N-well and a second high-voltage N-well formed on the N-type buried layer, a third N-type well and a fourth N-type well formed on the first high-voltage N-well and the second high-voltage N-well respectively, and a fourth N+ injection region and a fifth N+ injection region formed in the third N-type well and the fourth N-type well respectively, wherein the first high-voltage N-well is arranged at intervals on the outside of the first P-type buried layer, and the second high-voltage N-well is arranged at intervals on the outside of the second P-type buried layer.

[0013] Optionally, the isolation structure also includes: a ninth field oxygen isolation region formed between the first side wall of the P-type epitaxial layer and the fourth N+ injection region, a tenth field oxygen isolation region formed between the fourth N+ injection region and the first P+ injection region, an eleventh field oxygen isolation region formed between the eighth P+ injection region and the fifth N+ injection region, and a twelfth field oxygen isolation region formed between the fifth N+ injection region and the second side wall of the P-type epitaxial layer.

[0014] Optionally, on the forward path of the bidirectional thyristor electrostatic protection device, the first P+ injection region, the first P-type well, the first N-type well and the second P-type well constitute a first PNP transistor, the second P+ injection region, the first N-type well and the second P-type well constitute a second PNP transistor, the first N-type well, the second P-type well and the second N-type well constitute a first NPN transistor, and the second N+ injection region, the second P-type well and the second N-type well constitute a second NPN transistor; on the reverse path of the bidirectional thyristor electrostatic protection device, the eighth P+ injection region, the third P-type well, the second N-type well and the second P-type well constitute a third PNP transistor, the seventh P+ injection region, the second N-type well and the second P-type well constitute a fourth PNP transistor, the second N-type well, the second P-type well and the first N-type well constitute a third NPN transistor, and the second N+ injection region, the second P-type well and the first N-type well constitute a fourth NPN transistor.

[0015] The present invention also provides a method for preparing a bidirectional thyristor electrostatic protection device, the preparation method comprising:

[0016] Providing a P-type substrate, and sequentially forming an N-type buried layer and a P-type epitaxial layer on the P-type substrate;

[0017] forming a first P-type buried layer and a second P-type buried layer on the N-type buried layer in the P-type epitaxial layer, and the first P-type buried layer and the second P-type buried layer are arranged laterally and spaced apart from each other;

[0018] forming a first P-type well and a first N-type well on the first P-type buried layer, forming a second P-type well in the gap between the first P-type buried layer and the second P-type buried layer, and forming a second N-type well and a third P-type well on the second P-type buried layer, wherein the wells are arranged adjacent to each other in a transverse direction;

[0019] forming a first P+ injection region in the first P-type well, forming a first N+ injection region, a second P+ injection region, and a third P+ injection region in the first N-type well, forming a fourth P+ injection region in the first N-type well and the second P-type well, forming a second N+ injection region in the second P-type well, forming a fifth P+ injection region in the second P-type well and the second N-type well, forming a sixth P+ injection region, a seventh P+ injection region, and a third N+ injection region in the second N-type well, forming an eighth P+ injection region in the third P-type well, and performing an annealing treatment on each of the injection regions, wherein the injection regions are sequentially spaced apart in a transverse direction;

[0020] forming a first gate on the P-type epitaxial layer at a location between the third P+ injection region and the fourth P+ injection region, and forming a second gate on the P-type epitaxial layer at a location between the fifth P+ injection region and the sixth P+ injection region;

[0021] A first metal wire is formed on the first P+ injection region, the first N+ injection region and the second P+ injection region to connect the three together and serve as an anode, a second metal wire is formed on the first gate, the fourth P+ injection region, the second N+ injection region, the fifth P+ injection region and the second gate to connect the five together, and a third metal wire is formed on the seventh P+ injection region, the third N+ injection region and the eighth P+ injection region to connect the three together and serve as a cathode.

[0022] Optionally, before forming each well, the preparation method further includes: forming a first field oxygen isolation region to an eighth field oxygen isolation region in the P-type epitaxial layer, wherein the field oxygen isolation regions are sequentially spaced apart in a lateral direction.

[0023] Optionally, the preparation method also includes: forming a first high-voltage N-well and a second high-voltage N-well on the N-type buried layer, forming a third N-type well and a fourth N-type well on the first high-voltage N-well and the second high-voltage N-well respectively, and forming a fourth N+ injection region and a fifth N+ injection region in the third N-type well and the fourth N-type well respectively, wherein the first high-voltage N-well is arranged at intervals on the outside of the first P-type buried layer, and the second high-voltage N-well is arranged at intervals on the outside of the second P-type buried layer.

[0024] Optionally, when forming the first field oxygen isolation region to the eighth field oxygen isolation region, the ninth field oxygen isolation region to the twelfth field oxygen isolation region are also formed synchronously, wherein the ninth field oxygen isolation region and the tenth field oxygen isolation region are arranged at intervals on the outside of the first field oxygen isolation region, and the eleventh field oxygen isolation region and the twelfth field oxygen isolation region are arranged at intervals on the outside of the eighth field oxygen isolation region.

[0025] As described above, the bidirectional thyristor electrostatic protection device of the present invention and its preparation method have an avalanche breakdown surface with a lower breakdown voltage, which can effectively reduce the trigger voltage of the device; at the same time, the size of the avalanche breakdown surface is adjustable, and the avalanche breakdown voltage and trigger voltage of the device can be directly adjusted by adjusting the size to adapt to different ESD design windows. The present invention forms additional parasitic PNP transistors and parasitic NPN transistors, so that these additional parasitic transistors can participate in the discharge of ESD current, significantly improving the holding voltage of the device, thereby improving the anti-latch capability of the device. The present invention adopts a 0.18μm BCDMOS process for device preparation, which is simple in process and easy to operate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a structural schematic diagram of an existing bidirectional thyristor electrostatic protection device.

[0027] Figure 2 Display as Figure 1 The equivalent circuit diagram of the bidirectional thyristor electrostatic protection device shown is shown.

[0028] Figure 3 Shown is a structural schematic diagram of a bidirectional thyristor electrostatic protection device in an embodiment of the present invention.

[0029] Figure 4 Display as Figure 3 The equivalent circuit diagram of the bidirectional thyristor electrostatic protection device shown is shown.

[0030] Figure 5 It shows a schematic structural diagram of forming an N-type buried layer and a P-type epitaxial layer on a P-type substrate.

[0031] Figure 6 It shows a schematic structural diagram of forming a first P-type buried layer and a second P-type buried layer in a P-type epitaxial layer.

[0032] Figure 7 It is a schematic diagram showing the structure of forming each field oxygen isolation region in the P-type epitaxial layer.

[0033] Figure 8 It is a schematic structural diagram showing the formation of high-voltage N-wells, N-type wells and P-type wells in a P-type epitaxial layer.

[0034] Figure 9It is a schematic diagram showing the structure of forming each implantation region in the P-type epitaxial layer.

[0035] Figure 10 It is a schematic structural diagram showing a first gate and a second gate formed on a P-type epitaxial layer.

[0036] Component number description

[0037] 100 P-type substrate

[0038] 200 N-type buried layer

[0039] 300 P-type epitaxial layer

[0040] 400 device structure

[0041] 401 first P-type buried layer

[0042] 402 second P-type buried layer

[0043] 403 First P-type well

[0044] 404 First N-type well

[0045] 405 Second P-type well

[0046] 406 Second N-type well

[0047] 407 Third P-type well

[0048] 408 first P+ injection region

[0049] 409 first N+ implantation region

[0050] 410 Second P+ injection region

[0051] 411 Third P+ injection region

[0052] 412 Fourth P+ injection region

[0053] 413 Second N+ implantation region

[0054] 414 Fifth P+ injection region

[0055] 415 Sixth P+ injection region

[0056] 416 Seventh P+ injection region

[0057] 417 Third N+ implantation region

[0058] 418 Eighth P+ injection region

[0059] 419 First Gate

[0060] 420 Second Gate

[0061] 421 First Metal Wire

[0062] 422 Second Metal Wire

[0063] 423 Third Metal Wire

[0064] 424 First Oxygen Isolation Area

[0065] 425 Second Oxygen Isolation Area

[0066] 426 Third Oxygen Isolation Area

[0067] 427 The Fourth Oxygen Isolation Area

[0068] 428 Fifth Oxygen Isolation Area

[0069] 429 Sixth Oxygen Isolation Area

[0070] 430 Seventh Oxygen Isolation Area

[0071] 431 The Eighth Oxygen Isolation Area

[0072] 500 Isolation Structure

[0073] 501 First High-Voltage N-Well

[0074] 502 Second high voltage N well

[0075] 503 Third N-type well

[0076] 504 Fourth N-type well

[0077] 505 Fourth N+ implantation region

[0078] 506 Fifth N+ implantation region

[0079] 507 Ninth Field Oxygen Isolation Area

[0080] 508 The Tenth Oxygen Isolation Zone

[0081] 509 Eleventh Oxygen Isolation Area

[0082] 510 Field 12 Oxygen Isolation Area DETAILED DESCRIPTION

[0083] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0084] See also Figures 1 to 10It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the form, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0085] Figure 1 The structure of an existing bidirectional thyristor electrostatic protection device is shown in FIG. Figure 2 Its operating principle is the same as that of traditional unidirectional thyristors, capable of clamping voltage in both the forward and reverse directions. However, existing bidirectional thyristors suffer from high trigger voltages and low holding voltages. The trigger voltage is approximately 13-14V, and the holding voltage is less than 5V. When using existing bidirectional thyristors for low-voltage port protection, excessively high trigger voltages can easily exceed the design window, preventing timely ESD protection and causing breakdown of the core circuit. Furthermore, excessively low holding voltages pose the risk of latch-up.

[0086] In order to solve the above technical problems, this embodiment provides a bidirectional thyristor electrostatic protection device with low trigger voltage and strong anti-latch capability and a preparation method thereof, wherein the trigger voltage of the device can be reduced to 9V~10V, ensuring that the device can be turned on in time to protect the core circuit when the ESD pulse arrives. At the same time, the maintenance voltage is increased to avoid the latch effect.

[0087] like Figure 3 As shown, the bidirectional thyristor electrostatic protection device of this embodiment includes a P-type substrate 100, an N-type buried layer 200, a P-type epitaxial layer 300 and a device structure 400; wherein, the P-type substrate 100, the N-type buried layer 200 and the P-type epitaxial layer 300 are stacked from bottom to top, that is, the N-type buried layer 200 is formed on the upper end surface of the P-type substrate 100, and the P-type epitaxial layer 300 is formed on the upper end surface of the N-type buried layer 200; the device structure 400 is formed in the P-type epitaxial layer 300, and the device structure 400 has a completely symmetrical structural layout to facilitate bidirectional control.

[0088] The device structure 400 includes a first P-type buried layer 401, a second P-type buried layer 402, a first P-type well 403, a first N-type well 404, a second P-type well 405, a second N-type well 406, a third P-type well 407, a first P+ implantation region 408, a first N+ implantation region 409, a second P+ implantation region 410, a third P+ implantation region 411, a fourth P+ implantation region 412, a second N+ implantation region 413, a fifth P+ implantation region 414, a sixth P+ injection region 415, seventh P+ injection region 416, third N+ injection region 417, eighth P+ injection region 418, first gate 419 and second gate 420, further including first field oxygen isolation region 424, second field oxygen isolation region 425, third field oxygen isolation region 426, fourth field oxygen isolation region 427, fifth field oxygen isolation region 428, sixth field oxygen isolation region 429, seventh field oxygen isolation region 430 and eighth field oxygen isolation region 431.

[0089] The first P-type buried layer 401 and the second P-type buried layer 402 are formed on the N-type buried layer 200, and the first P-type buried layer 401 and the second P-type buried layer 402 are arranged in a lateral direction. In one embodiment, the first P-type buried layer 401 and the second P-type buried layer 402 are formed on the upper end surface of the N-type buried layer 200, the first P-type buried layer 401 is arranged on the first side (e.g., the left side), and the second P-type buried layer 402 is arranged on the second side (e.g., the right side).

[0090] The first P-type well 403 and the first N-type well 404 are formed on the first P-type buried layer 401, the second P-type well 405 is formed in the gap between the first P-type buried layer 401 and the second P-type buried layer 402, the second N-type well 406 and the third P-type well 407 are formed on the second P-type buried layer 402, and the first P-type well 403, the first N-type well 404, the second P-type well 405, the second N-type well 406 and the third P-type well 407 are arranged adjacent to each other in sequence along the horizontal direction. In one embodiment, the first P-type well 403 and the first N-type well 404 are formed above the first P-type buried layer 401, the second P-type well 405 is formed above the gap between the first P-type buried layer 401 and the second P-type buried layer 402, and the second N-type well 406 and the third P-type well 407 are formed above the second P-type buried layer 402, wherein the lower end surfaces of the first P-type well 403, the first N-type well 404, the second P-type well 405, the second N-type well 406 and the third P-type well 407 are flush and have a certain distance from the upper end surfaces of the corresponding P-type buried layers and are not in direct contact.

[0091] The first P+ injection region 408 is formed in the first P-type well 403, the first N+ injection region 409, the second P+ injection region 410 and the third P+ injection region 411 are formed in the first N-type well 404, the fourth P+ injection region 412 is partially formed in the first N-type well 404 and partially formed in the second P-type well 405, the second N+ injection region 413 is formed in the second P-type well 405, the fifth P+ injection region 414 is partially formed in the second P-type well 405 and partially formed in the second N-type well 406, the sixth P+ injection region 415 and the seventh P+ injection region 416 are formed in the first N-type well 404. + injection region 416 and the third N+ injection region 417 are formed in the second N-type well 406, the eighth P+ injection region 418 is formed in the third P-type well 407, and the first P+ injection region 408, the first N+ injection region 409, the second P+ injection region 410, the third P+ injection region 411, the fourth P+ injection region 412, the second N+ injection region 413, the fifth P+ injection region 414, the sixth P+ injection region 415, the seventh P+ injection region 416, the third N+ injection region 417 and the eighth P+ injection region 418 are arranged in sequence along the horizontal direction.

[0092] The first gate 419 is formed on the P-type epitaxial layer 300 at the interval between the third P+ injection region 411 and the fourth P+ injection region 412, and the second gate 420 is formed on the P-type epitaxial layer 300 at the interval between the fifth P+ injection region 414 and the sixth P+ injection region 415. In one embodiment, the first gate 419 is formed on the upper end surface of the P-type epitaxial layer 300 at the interval between the third P+ injection region 411 and the fourth P+ injection region 412, and the second gate 420 is formed on the upper end surface of the P-type epitaxial layer 300 at the interval between the fifth P+ injection region 414 and the sixth P+ injection region 415. Among them, the first P+ injection region 408, the first N+ injection region 409, and the second P+ injection region 410 are connected together and serve as the anode of the bidirectional thyristor electrostatic protection device, the first gate 419, the fourth P+ injection region 412, the second N+ injection region 413, the fifth P+ injection region 414, and the second gate 420 are connected together, and the seventh P+ injection region 416, the third N+ injection region 417, and the eighth P+ injection region 418 are connected together and serve as the cathode of the bidirectional thyristor electrostatic protection device. In one embodiment, the first P+ injection region 408, the first N+ injection region 409, and the second P+ injection region 410 are connected together through a first metal wire 421, the first gate 419, the fourth P+ injection region 412, the second N+ injection region 413, the fifth P+ injection region 414, and the second gate 420 are connected together through a second metal wire 422, and the seventh P+ injection region 416, the third N+ injection region 417, and the eighth P+ injection region 418 are connected together through a third metal wire 423.

[0093] When the device structure 400 further includes the first field oxygen isolation region 424 to the eighth field oxygen isolation region 431, the first field oxygen isolation region 424 is formed between the first P+ implantation region 408 and the first N+ implantation region 409, the second field oxygen isolation region 425 is formed between the first N+ implantation region 409 and the second P+ implantation region 410, the third field oxygen isolation region 426 is formed between the second P+ implantation region 410 and the third P+ implantation region 411, and the fourth field oxygen isolation region 427 is formed between the fourth P+ implantation region 412 and the second N+ injection region 413, the fifth field oxygen isolation region 428 is formed between the second N+ injection region 413 and the fifth P+ injection region 414, the sixth field oxygen isolation region 429 is formed between the sixth P+ injection region 415 and the seventh P+ injection region 416, the seventh field oxygen isolation region 430 is formed between the seventh P+ injection region 416 and the third N+ injection region 417, and the eighth field oxygen isolation region 431 is formed between the third N+ injection region 417 and the eighth P+ injection region 418.

[0094] like Figure 3 As shown, the bidirectional thyristor electrostatic protection device provided in this embodiment further includes an isolation structure 500, which is formed outside the device structure 400 in the P-type epitaxial layer 300 and isolates the device structure 400 by cooperating with the N-type buried layer 200. The isolation structure 500 includes a first high-voltage N-well 501, a second high-voltage N-well 502, a third N-type well 503, a fourth N-type well 504, a fourth N+ implantation region 505, and a fifth N+ implantation region 506. Furthermore, the isolation structure 500 further includes a ninth field oxygen isolation region 507, a tenth field oxygen isolation region 508, an eleventh field oxygen isolation region 509, and a twelfth field oxygen isolation region 510.

[0095] The first high-voltage N-well 501 and the second high-voltage N-well 502 are formed on the N-type buried layer 200, the third N-type well 503 is formed on the first high-voltage N-well 501, the fourth N-type well 504 is formed on the second high-voltage N-well 502, the fourth N+ injection region 505 is formed in the third N-type well 503, and the fifth N+ injection region 506 is formed in the fourth N-type well 504. In addition, the first high-voltage N-well 501 is arranged at intervals on the outside of the first P-type buried layer 401, and the second high-voltage N-well 502 is arranged at intervals on the outside of the second P-type buried layer 402. In one embodiment, the first high-voltage N-well 501 and the second high-voltage N-well 502 are both formed on the upper end surface of the N-type buried layer 200, the third N-type well 503 is formed on the upper end surface of the first high-voltage N-well 501, and the fourth N-type well 504 is formed on the upper end surface of the second high-voltage N-well 502; wherein the height of the corresponding high-voltage N-well is greater than the height of the corresponding P-type buried layer in the device structure 400, and the lower end surface of the corresponding well is flush with the lower end surface of the corresponding well in the device structure 400.

[0096] When the isolation structure 500 also includes the ninth field oxygen isolation region 507 to the twelfth field oxygen isolation region 510, the ninth field oxygen isolation region 507 is formed between the first side wall (for example, the left side wall) of the P-type epitaxial layer 300 and the fourth N+ injection region 505, the tenth field oxygen isolation region 508 is formed between the fourth N+ injection region 505 and the first P+ injection region 408, the eleventh field oxygen isolation region 509 is formed between the eighth P+ injection region 418 and the fifth N+ injection region 506, and the twelfth field oxygen isolation region 510 is formed between the fifth N+ injection region 506 and the second side wall (for example, the right side wall) of the P-type epitaxial layer 300.

[0097] In the bidirectional thyristor electrostatic protection device of this embodiment: in the forward path, the first P+ injection region 408, the first P-type well 403, the first N-type well 404 and the second P-type well 405 constitute a first PNP transistor PNP1, the second P+ injection region 410, the first N-type well 404 and the second P-type well 405 constitute a second PNP transistor PNP2, the first N-type well 404, the second P-type well 405 and the second N-type well 406 constitute a first NPN transistor NPN1, the second N+ injection region 413, the second P-type well 405 and the second N-type well 406 constitute a second NPN transistor N transistor NPN2; in the reverse path, the eighth P+ injection region 418, the third P-type well 407, the second N-type well 406 and the second P-type well 405 constitute a third PNP transistor PNP3, the seventh P+ injection region 416, the second N-type well 406 and the second P-type well 405 constitute a fourth PNP transistor PNP4, the second N-type well 406, the second P-type well 405 and the first N-type well 404 constitute a third NPN transistor NPN3, and the second N+ injection region 413, the second P-type well 405 and the first N-type well 404 constitute a fourth NPN transistor NPN4.

[0098] When there is an ESD pulse at the anode and the cathode is connected to a low potential, the first P+ injection region 408, the first N+ injection region 409, the second P+ injection region 410 and the first N-type well 404 are at a high potential, the seventh P+ injection region 416, the third N+ injection region 417, the eighth P+ injection region 418 and the second N-type well 406 are at a low potential, and the first N-type well 404 and the fourth P+ injection region 412 are reverse biased; when the voltage of the ESD pulse is higher than the avalanche breakdown voltage of the reverse-biased PN junction formed by the first N-type well 404 and the fourth P+ injection region 412, the reverse-biased PN junction undergoes avalanche breakdown, and a large amount of avalanche current is generated inside the device. The avalanche current flows into the second P-type well 405 and the second N-type well 406 through the fourth P+ injection region 412 and the second metal line 422 and finally flows into the cathode, Figure 4 It can be seen that when the avalanche current flows through the parasitic resistance R N1When the voltage drop across the transistor is large enough, the second PNP transistor PNP2 is triggered to turn on, providing current to the base of the first NPN transistor NPN1 and the second NPN transistor NPN2 to trigger the turn-on, forming a positive feedback loop. The positive SCR is turned on to discharge the ESD current. When the voltage of the ESD pulse reaches a certain value, the first PNP transistor PNP1 is also triggered to turn on and participate in discharging the ESD current.

[0099] When there is an ESD pulse at the cathode and the anode is connected to a low potential, the seventh P+ injection region 416, the third N+ injection region 417, the eighth P+ injection region 418 and the second N-type well 406 are at a high potential, the first P+ injection region 408, the first N+ injection region 409, the second P+ injection region 410 and the first N-type well 404 are at a low potential, and the second N-type well 406 and the fifth P+ injection region 414 are reverse biased; when the voltage of the ESD pulse is higher than the avalanche breakdown voltage of the reverse-biased PN junction formed by the second N-type well 406 and the fifth P+ injection region 414, the reverse-biased PN junction undergoes avalanche breakdown, and a large amount of avalanche current is generated inside the device. The avalanche current flows into the second P-type well 405 and the first N-type well 404 through the fifth P+ injection region 414 and the second metal wire 422 and finally flows into the anode, Figure 4 It can be seen that when the avalanche current flows through the parasitic resistance R N2 When the voltage drop across the transistor is large enough, the fourth PNP transistor PNP4 is triggered to turn on, providing current to the bases of the third and fourth NPN transistors NPN3 and NPN4 to trigger the turn-on, forming a positive feedback loop. The reverse SCR is turned on to discharge the ESD current. When the voltage of the ESD pulse reaches a certain value, the third PNP transistor PNP3 is also triggered to turn on and participate in discharging the ESD current.

[0100] This embodiment improves the structure of the avalanche breakdown surface. The first N-type well 404 and the second N-type well 406 are respectively provided with an embedded parasitic PMOS with a floating gate. Taking the forward ESD pulse as an example, the avalanche breakdown surface of the device is located below the floating first gate 419, which is composed of the first N-type well 404 and the fourth P+ injection region 412. The fourth P+ injection region 412 will be affected by the concentration diffusion of the third P+ injection region, thereby reducing the avalanche breakdown voltage of the device. In addition, the size of the avalanche breakdown surface is adjustable, that is, the width S1 of the first gate 419 is adjustable. By adjusting the size of S1, the avalanche breakdown voltage and trigger voltage of the device can be directly adjusted. The same applies to the reverse ESD pulse and will not be repeated.

[0101] By forming a first P-type well 403 and a first P+ injection region 408 on the left side of the first N-type well 404, and forming a third P-type well 407 and an eighth P+ injection region 418 on the right side of the second N-type well 406, an additional parasitic PNP transistor (for example, a first PNP transistor PNP1 on the forward path and a third PNP transistor PNP3 on the reverse path) is formed in the SCR discharge path, and participates in discharging ESD current, thereby improving the holding voltage of the device, that is, improving the anti-latch capability of the device. In addition, by forming a second N+ injection region 413 in the second P-type well 405 and connecting the fourth P+ injection region 412, the second N+ injection region 413 and the fifth P+ injection region 414 together, an additional longitudinal parasitic NPN transistor (for example, a second NPN transistor NPN2 on the forward path and a fourth NPN transistor NPN4 on the reverse path) can be formed. The path distance is longer, which can further improve the anti-latch capability of the device.

[0102] This embodiment also provides a method for preparing a bidirectional thyristor electrostatic protection device, comprising the following steps. Figure 3 、 Figures 5 to 10 , the preparation method of this embodiment is described in detail.

[0103] Step S1: provide a P-type substrate 100, and sequentially form an N-type buried layer 200 and a P-type epitaxial layer 300 on the P-type substrate 100. Figure 5 In one embodiment, an N-type buried layer 200 is first formed on the upper end surface of the P-type substrate 100 , and then a P-type epitaxial layer 300 is formed on the upper end surface of the N-type buried layer 200 .

[0104] In actual applications, before forming the N-type buried layer 200, step S1 also includes a step of pre-treating the P-type substrate 100; specifically, forming a growth inhibition layer on the P-type substrate (for example, the growth inhibition layer includes a stacked silicon dioxide layer and a silicon nitride layer), spin-coating a photoresist layer on the growth inhibition layer and exposing and developing based on a mask to form an isolation pattern to divide the device preparation area, removing the growth inhibition layer in the device preparation area and removing the isolation pattern.

[0105] Step S2, forming a first P-type buried layer 401 and a second P-type buried layer 402 on the N-type buried layer 200 in the P-type epitaxial layer 300, and the first P-type buried layer 401 and the second P-type buried layer 402 are arranged in a lateral direction, as shown in FIG. Figure 6 As shown; in one embodiment, a first P-type buried layer 401 and a second P-type buried layer 402 are formed on the upper end surface of the N-type buried layer 200, the first P-type buried layer 401 is arranged on the first side (for example, the left side), and the second P-type buried layer 402 is arranged on the second side (for example, the right side).

[0106] Step S3, forming the first field oxygen isolation region 424 to the eighth field oxygen isolation region 431 in the P-type epitaxial layer 300, and the first field oxygen isolation region 424 to the eighth field oxygen isolation region 43 are sequentially spaced apart in the transverse direction, as shown in FIG. Figure 7 As shown. Further, step S3 further forms the ninth field oxygen isolation region 507 to the twelfth field oxygen isolation region 510 in the P-type epitaxial layer 300, and the ninth field oxygen isolation region 507 and the tenth field oxygen isolation region 508 are sequentially spaced apart along the lateral direction on the first side (e.g., the left side) of the first field oxygen isolation region 424, and the eleventh field oxygen isolation region 509 and the twelfth field oxygen isolation region 510 are sequentially spaced apart along the lateral direction on the second side (e.g., the right side) of the eighth field oxygen isolation region 431, as shown. Figure 7 shown.

[0107] In step S4, a first P-type well 403 and a first N-type well 404 are formed on the first P-type buried layer 401, a second P-type well 405 is formed in the gap between the first P-type buried layer 401 and the second P-type buried layer 402, and a second N-type well 406 and a third P-type well 407 are formed on the second P-type buried layer 402. In addition, the first P-type well 403, the first N-type well 404, the second P-type well 405, the second N-type well 406 and the third P-type well 407 are arranged adjacent to each other in the transverse direction. Figure 8 In one embodiment, an N-type well is formed first and then a P-type well is formed; for example, a first N-type well 404 and a second N-type well 406 are formed above the first P-type buried layer 401 and the second P-type buried layer 402, respectively. Then, a first P-type well 403, a second P-type well 405, and a third P-type well 407 are formed above the first P-type buried layer 401, above the gap between the first P-type buried layer 401 and the second P-type buried layer 402, and above the second P-type buried layer 402, respectively.

[0108] Furthermore, step S4 further includes forming a first high-voltage N-well 501 and a second high-voltage N-well 502 on the N-type buried layer 200, forming a third N-type well 503 on the first high-voltage N-well 501, and forming a fourth N-type well 504 on the second high-voltage N-well 502, and the first high-voltage N-well 501 is arranged at intervals on the outside of the first P-type buried layer 401, and the second high-voltage N-well 502 is arranged at intervals on the outside of the second P-type buried layer 402, as shown in FIG. Figure 8 In one embodiment, the third N-type well 503 and the fourth N-type well 504 are formed simultaneously with the first N-type well 404 and the second N-type well 406, and the first high-voltage N-well 501 and the second high-voltage N-well 502 are formed before the third N-type well 503 and the fourth N-type well 504. For example, the first high-voltage N-well 501 and the second high-voltage N-well 502 are formed on the upper surface of the N-type buried layer 200, and then the third N-type well 503 and the fourth N-type well 504 are formed on the upper surfaces of the first high-voltage N-well 501 and the second high-voltage N-well 502, respectively.

[0109] Step S5: forming a first P+ injection region 408 in the first P-type well 403, forming a first N+ injection region 409, a second P+ injection region 410, and a third P+ injection region 411 in the first N-type well 404, forming a fourth P+ injection region 412 in the first N-type well 404 and the second P-type well 405, forming a second N+ injection region 413 in the second P-type well 405, forming a fifth P+ injection region 414 in the second P-type well 405 and the second N-type well 406, and forming a sixth P+ injection region 415 and a seventh P+ injection region 416 in the second N-type well 406. and a third N+ implantation region 417, an eighth P+ implantation region 418 is formed in the third P-type well 407, and each implantation region is annealed to eliminate the migration of impurities in the implantation region, wherein the first P+ implantation region 408, the first N+ implantation region 409, the second P+ implantation region 410, the third P+ implantation region 411, the fourth P+ implantation region 412, the second N+ implantation region 413, the fifth P+ implantation region 414, the sixth P+ implantation region 415, the seventh P+ implantation region 416, the third N+ implantation region 417 and the eighth P+ implantation region 418 are sequentially spaced in the transverse direction, as shown in FIG. Figure 9 shown.

[0110] Furthermore, step S5 further includes: forming a fourth N+ implantation region 505 in the third N-type well 503, and forming a fifth N+ implantation region 506 in the fourth N-type well 504, as shown in FIG. Figure 9 shown.

[0111] Step S6, forming a first gate 419 on the P-type epitaxial layer 300 at the interval between the third P+ implantation region 414 and the fourth P+ implantation region 415, and forming a second gate 420 on the P-type epitaxial layer 300 at the interval between the fifth P+ implantation region 414 and the sixth P+ implantation region 415, as shown in FIG. Figure 10 In one embodiment, a first gate 419 is formed on the upper end surface of the P-type epitaxial layer 300 at the interval between the third P+ injection region 414 and the fourth P+ injection region 415, and a second gate 420 is formed on the upper end surface of the P-type epitaxial layer 300 at the interval between the fifth P+ injection region 414 and the sixth P+ injection region 415; wherein the first gate 419 and the second gate 420 are polysilicon gates, and the size of the avalanche breakdown surface is determined by designing the width of the first gate 419 and the second gate 420.

[0112] Step S7, forming a first metal wire 421 on the first P+ injection region 408, the first N+ injection region 409, and the second P+ injection region 410, connecting the first P+ injection region 408, the first N+ injection region 409, and the second P+ injection region 410 together and serving as an anode, forming a second metal wire 422 on the first gate 419, the fourth P+ injection region 412, the second N+ injection region 413, the fifth P+ injection region 414, and the second gate 420, connecting the first gate 419, the fourth P+ injection region 412, the second N+ injection region 413, the fifth P+ injection region 414, and the second gate 420 together, forming a third metal wire 423 on the seventh P+ injection region 416, the third N+ injection region 417, and the eighth P+ injection region 418, connecting the seventh P+ injection region 416, the third N+ injection region 417, and the eighth P+ injection region 418 together and serving as a cathode, as shown in FIG. Figure 3 shown.

[0113] It should be noted that, for each of the above steps, if the device of this embodiment does not include a corresponding field oxygen isolation region, step S3 can be omitted; if the device of this embodiment does not include an isolation structure, the portion of forming the first high-voltage N-well 501, the second high-voltage N-well 502, the third N-type well 503, and the fourth N-type well 504 in step S4 and the portion of forming the fourth N+ injection region 505 and the fifth N+ injection region 506 in step S5 can be omitted.

[0114] In summary, the bidirectional thyristor electrostatic protection device and its preparation method of the present invention have an avalanche breakdown surface with a lower breakdown voltage, which can effectively reduce the triggering voltage of the device; at the same time, the size of the avalanche breakdown surface is adjustable, and the avalanche breakdown voltage and triggering voltage of the device can be directly adjusted by adjusting the size to adapt to different ESD design windows. The present invention forms additional parasitic PNP transistors and parasitic NPN transistors, so that these additional parasitic transistors can participate in the discharge of ESD current, significantly improving the holding voltage of the device, thereby improving the anti-latch capability of the device. The present invention adopts a 0.18μm BCDMOS process for device preparation, which is simple and easy to operate. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0115] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A bidirectional thyristor electrostatic protection device, characterized in that: The bidirectional thyristor electrostatic protection device includes: A P-type substrate, an N-type buried layer, and a P-type epitaxial layer stacked from bottom to top, and a device structure formed in the P-type epitaxial layer; wherein the device structure includes: a first P-type buried layer and a second P-type buried layer formed on the N-type buried layer, and the two are arranged in a lateral interval; a first P-type well and a first N-type well formed on the first P-type buried layer, a second P-type well formed on the interval between the first P-type buried layer and the second P-type buried layer, a second N-type well and a third P-type well formed on the second P-type buried layer, and each well is arranged adjacent to each other in the lateral direction; a first P+ injection region formed in the first P-type well, a first N+ injection region, a second P+ injection region and a third P+ injection region formed in the first N-type well, a fourth P+ injection region formed in the first N-type well and the second P-type well a P+ injection region, a second N+ injection region formed in the second P-type well, a fifth P+ injection region formed in the second P-type well and the second N-type well, a sixth P+ injection region, a seventh P+ injection region and a third N+ injection region formed in the second N-type well, and an eighth P+ injection region formed in the third P-type well, wherein the injection regions are sequentially spaced apart in a lateral direction; a first gate formed on the P-type epitaxial layer at a gap between the third P+ injection region and the fourth P+ injection region, and a second gate formed on the P-type epitaxial layer at a gap between the fifth P+ injection region and the sixth P+ injection region; Among them, the first P+ injection region, the first N+ injection region and the second P+ injection region are connected together and serve as anodes, the first gate, the fourth P+ injection region, the second N+ injection region, the fifth P+ injection region and the second gate are connected together, and the seventh P+ injection region, the third N+ injection region and the eighth P+ injection region are connected together and serve as cathodes.

2. The bidirectional thyristor electrostatic protection device according to claim 1, characterized in that: The device structure also includes: a first field oxygen isolation region formed between the first P+ injection region and the first N+ injection region, a second field oxygen isolation region formed between the first N+ injection region and the second P+ injection region, a third field oxygen isolation region formed between the second P+ injection region and the third P+ injection region, a fourth field oxygen isolation region formed between the fourth P+ injection region and the second N+ injection region, a fifth field oxygen isolation region formed between the second N+ injection region and the fifth P+ injection region, a sixth field oxygen isolation region formed between the sixth P+ injection region and the seventh P+ injection region, a seventh field oxygen isolation region formed between the seventh P+ injection region and the third N+ injection region, and an eighth field oxygen isolation region formed between the third N+ injection region and the eighth P+ injection region.

3. The bidirectional thyristor electrostatic protection device according to claim 1, characterized in that: The bidirectional thyristor electrostatic protection device further includes: an isolation structure formed outside the device structure in the P-type epitaxial layer.

4. The bidirectional thyristor electrostatic protection device according to claim 3, characterized in that: The isolation structure includes: a first high-voltage N-well and a second high-voltage N-well formed on the N-type buried layer, a third N-type well and a fourth N-type well formed on the first high-voltage N-well and the second high-voltage N-well respectively, and a fourth N+ injection region and a fifth N+ injection region formed in the third N-type well and the fourth N-type well respectively, wherein the first high-voltage N-well is arranged at intervals outside the first P-type buried layer, and the second high-voltage N-well is arranged at intervals outside the second P-type buried layer.

5. The bidirectional thyristor electrostatic protection device according to claim 4, characterized in that: The isolation structure also includes: a ninth field oxygen isolation region formed between the first side wall of the P-type epitaxial layer and the fourth N+ injection region, a tenth field oxygen isolation region formed between the fourth N+ injection region and the first P+ injection region, an eleventh field oxygen isolation region formed between the eighth P+ injection region and the fifth N+ injection region, and a twelfth field oxygen isolation region formed between the fifth N+ injection region and the second side wall of the P-type epitaxial layer.

6. The bidirectional thyristor electrostatic protection device according to any one of claims 1 to 5, characterized in that: On the forward path of the bidirectional thyristor electrostatic protection device, the first P+ injection region, the first P-type well, the first N-type well and the second P-type well constitute a first PNP transistor, the second P+ injection region, the first N-type well and the second P-type well constitute a second PNP transistor, the first N-type well, the second P-type well and the second N-type well constitute a first NPN transistor, and the second N+ injection region, the second P-type well and the second N-type well constitute a second NPN transistor; on the reverse path of the bidirectional thyristor electrostatic protection device, the eighth P+ injection region, the third P-type well, the second N-type well and the second P-type well constitute a third PNP transistor, the seventh P+ injection region, the second N-type well and the second P-type well constitute a fourth PNP transistor, the second N-type well, the second P-type well and the first N-type well constitute a third NPN transistor, and the second N+ injection region, the second P-type well and the first N-type well constitute a fourth NPN transistor.

7. A method for preparing a bidirectional thyristor electrostatic protection device, characterized in that: The preparation method comprises: Providing a P-type substrate, and sequentially forming an N-type buried layer and a P-type epitaxial layer on the P-type substrate; forming a first P-type buried layer and a second P-type buried layer on the N-type buried layer in the P-type epitaxial layer, and the first P-type buried layer and the second P-type buried layer are arranged laterally and spaced apart from each other; forming a first P-type well and a first N-type well on the first P-type buried layer, forming a second P-type well in the gap between the first P-type buried layer and the second P-type buried layer, and forming a second N-type well and a third P-type well on the second P-type buried layer, wherein the wells are arranged adjacent to each other in a transverse direction; forming a first P+ injection region in the first P-type well, forming a first N+ injection region, a second P+ injection region, and a third P+ injection region in the first N-type well, forming a fourth P+ injection region in the first N-type well and the second P-type well, forming a second N+ injection region in the second P-type well, forming a fifth P+ injection region in the second P-type well and the second N-type well, forming a sixth P+ injection region, a seventh P+ injection region, and a third N+ injection region in the second N-type well, forming an eighth P+ injection region in the third P-type well, and performing an annealing treatment on each of the injection regions, wherein the injection regions are sequentially spaced apart in a transverse direction; forming a first gate on the P-type epitaxial layer at a location between the third P+ injection region and the fourth P+ injection region, and forming a second gate on the P-type epitaxial layer at a location between the fifth P+ injection region and the sixth P+ injection region; A first metal wire is formed on the first P+ injection region, the first N+ injection region and the second P+ injection region to connect the three together and serve as an anode, a second metal wire is formed on the first gate, the fourth P+ injection region, the second N+ injection region, the fifth P+ injection region and the second gate to connect the five together, and a third metal wire is formed on the seventh P+ injection region, the third N+ injection region and the eighth P+ injection region to connect the three together and serve as a cathode.

8. The method for preparing a bidirectional thyristor electrostatic protection device according to claim 7, characterized in that: Before forming each well, the preparation method further includes: forming a first field oxygen isolation region to an eighth field oxygen isolation region in the P-type epitaxial layer, wherein the field oxygen isolation regions are sequentially spaced apart in a lateral direction.

9. The method for preparing a bidirectional thyristor electrostatic protection device according to claim 7 or 8, characterized in that: The preparation method also includes: forming a first high-voltage N-well and a second high-voltage N-well on the N-type buried layer, forming a third N-type well and a fourth N-type well on the first high-voltage N-well and the second high-voltage N-well respectively, and forming a fourth N+ injection region and a fifth N+ injection region in the third N-type well and the fourth N-type well respectively, wherein the first high-voltage N-well is arranged at intervals outside the first P-type buried layer, and the second high-voltage N-well is arranged at intervals outside the second P-type buried layer.

10. The method for preparing a bidirectional thyristor electrostatic protection device according to claim 9, characterized in that: When forming the first field oxygen isolation region to the eighth field oxygen isolation region, the ninth field oxygen isolation region to the twelfth field oxygen isolation region are also formed synchronously, wherein the ninth field oxygen isolation region and the tenth field oxygen isolation region are arranged at intervals on the outside of the first field oxygen isolation region, and the eleventh field oxygen isolation region and the twelfth field oxygen isolation region are arranged at intervals on the outside of the eighth field oxygen isolation region.

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