Electrostatic discharge protection device

Abstract

The invention discloses an electrostatic discharge protection device, which comprises a clamping bipolar junction transistor and at least one electrostatic discharge circuit, and the electrostatic discharge circuit is coupled between a first voltage rail and a second voltage rail. The electrostatic discharge circuit comprises a silicon controlled rectifier and a diode. An anode and a cathode of the silicon controlled rectifier are respectively coupled to an input / output (I / O) port and a first voltage rail. The cathode of the diode is coupled to the anode of the silicon controlled rectifier and the I / O port. An anode of the diode is coupled to the second voltage rail. The absolute value of the reverse breakdown voltage of the diode is larger than the absolute value of the trigger voltage from the anode to the cathode of the silicon controlled rectifier, and the absolute value of the trigger voltage from the anode to the cathode of the silicon controlled rectifier is larger than the absolute value of the trigger voltage of the clamping bipolar junction transistor.

Description

Technical Field

[0001] This invention relates to a protective device, and more particularly to an electrostatic discharge protection device. Background Technology

[0002] As integrated circuits (ICs) shrink to the nanometer scale, consumer electronics such as laptops and mobile devices are becoming smaller than ever before. Without proper protection, these electronic devices could be reset or even damaged when subjected to electrostatic discharge (ESD) events. Currently, all consumer electronics ICs are required to pass the ESD testing requirements of the IEC 61000-4-2 standard. Therefore, ESD protection devices are essential to release ESD energy and prevent ESD damage to electronic systems. The Universal Serial Bus (USB) Type-C port is now widely used in electronic systems. In the pin configuration of a USB Type-C port, the Configuration Channel (CC) pin and the Side Band Use (SBU) pin are located adjacent to the Voltage Bus (VBUS) pin. The voltage on the VBUS pin can be very high, for example, from 20 volts (V) to 48V. If the USB plug is pulled out at an angle, it may cause a short circuit between the VBUS pin and the CC or SBU pin, exposing the CC or SBU pin to this high voltage, potentially burning out the USB IC. In this situation, an ESD protection device with a breakdown voltage exceeding this high voltage is needed to protect the CC and SBU pins. Figure 1 This is a schematic diagram of a prior art electrostatic discharge (ESD) protection device. Please refer to [link / reference needed]. Figure 1 An electrostatic discharge (ESD) protection device 1 includes a bipolar junction transistor (BJT) 10 and two diodes 11 and 12. The BJT 10 is coupled between voltages Vdd and Vss. An input / output (I / O) port 13 is coupled between the anode of diode 11 and the cathode of diode 12. For the CC and SBU pins, Vdd is 5 volts (V) and Vss is 0V. Therefore, when the CC or SBU pin is exposed to a high voltage (e.g., 20V–48V), the USB IC will burn out, and the ESD protection device 1 will be triggered. Therefore, the ESD protection device 1 is not suitable for the CC and SBU pins.

[0003] Therefore, the present invention addresses the aforementioned problems by proposing an electrostatic discharge protection device to solve the issues arising from the prior art. Summary of the Invention

[0004] The purpose of this invention is to provide an electrostatic discharge protection device that can maintain a high voltage without being triggered during malfunctions and improve electrostatic discharge performance in a low capacitance state, thus making it suitable for high-speed interfaces.

[0005] In one embodiment of the present invention, an electrostatic discharge (ESD) protection device is provided, comprising a clamped bipolar junction transistor (BJT) and at least one ESD circuit. The clamped BJT is coupled between a first voltage rail and a second voltage rail. The ESD circuit is coupled between the first and second voltage rails and to an input / output (I / O) port. The ESD circuit includes a silicon controlled rectifier (SCR) and a diode. The anode of the SCR is coupled to the I / O port, and the cathode of the SCR is coupled to the first voltage rail. The cathode of the diode is coupled to the anode of the SCR and the I / O port, and the anode of the diode is coupled to the second voltage rail. The absolute value of the reverse breakdown voltage of the diode is greater than the absolute value of the anode-to-cathode trigger voltage of the SCR, and the absolute value of the anode-to-cathode trigger voltage of the SCR is greater than the absolute value of the trigger voltage of the clamped BJT. The silicon controlled rectifier includes a parasitic PNP bipolar junction transistor and a parasitic NPN bipolar junction transistor, and the base of the parasitic PNP bipolar junction transistor is decoupled from the I / O port.

[0006] In one embodiment of the present invention, at least one electrostatic discharge circuit includes a plurality of electrostatic discharge circuits.

[0007] In one embodiment of the present invention, the clamped bipolar junction transistor is an NPN bipolar junction transistor with its base electrically floating, an NPN bipolar junction transistor with its emitter coupled to its base, a PNP bipolar junction transistor with its base electrically floating, or a PNP bipolar junction transistor with its emitter coupled to its base.

[0008] In one embodiment of the invention, the first voltage rail is electrically floating.

[0009] In one embodiment of the present invention, the silicon-controlled rectifier includes an N-type semiconductor substrate, a first P-type well region, a first heavily doped P-type region, a first heavily doped N-type region, and a second heavily doped P-type region. The N-type semiconductor substrate decouples the I / O ports. The first P-type well region is disposed in the N-type semiconductor substrate. The first heavily doped P-type region and the first heavily doped N-type region are disposed in the first P-type well region and coupled to a first voltage rail. The two heavily doped P-type regions are disposed in the N-type semiconductor substrate and coupled to the I / O ports and the cathode of a diode. The first heavily doped P-type region, the first P-type well region, the N-type semiconductor substrate, and the second heavily doped P-type region form a parasitic PNP bipolar junction transistor. The first heavily doped N-type region, the first P-type well region, and the N-type semiconductor substrate form a parasitic NPN bipolar junction transistor. A clamped bipolar junction transistor and a diode are disposed in the N-type semiconductor substrate, with the diode disposed between each of the first P-type well region and the second heavily doped P-type region and the clamped bipolar junction transistor. The diode includes a second P-type well region, a second heavily doped N-type region, and a third heavily doped P-type region. The second P-type well region is disposed in an N-type semiconductor substrate. The second heavily doped N-type region and the third heavily doped P-type region are disposed within the second P-type well region. The second heavily doped N-type region is coupled to the second heavily doped P-type region and an I / O port, and the third heavily doped P-type region is coupled to a second voltage rail. The clamped bipolar junction transistor includes a third P-type well region, a third heavily doped N-type region, and a fourth heavily doped N-type region. The third P-type well region is disposed in an N-type semiconductor substrate. The third heavily doped N-type region and the fourth heavily doped N-type region are disposed within the third P-type well region and are respectively coupled to a second voltage rail and a first voltage rail.

[0010] In one embodiment of the present invention, the doping concentration of the third P-type well region is greater than that of the first P-type well region, and the doping concentration of the first P-type well region is greater than that of the second P-type well region.

[0011] In one embodiment of the present invention, the electrostatic discharge protection device further includes a semiconductor substrate, at least one first isolation trench, and at least one second isolation trench. The silicon-controlled rectifier includes an N-type epitaxial layer, a first P-type well region, a first heavily doped P-type region, a first heavily doped N-type region, and a second heavily doped P-type region. The first P-type well region is disposed in the first N-type epitaxial region, and the first heavily doped P-type and first N-type regions are disposed in the first P-type well region and coupled to a first voltage rail. The second heavily doped P-type region is disposed in the first N-type epitaxial region and coupled to an I / O port and the cathode of a diode. The first heavily doped P-type region, the first P-type well region, the first N-type epitaxial region, and the second heavily doped P-type region form a parasitic PNP bipolar junction transistor, and the first heavily doped N-type region, the first P-type well region, and the first N-type epitaxial region form a parasitic NPN bipolar junction transistor. The diode includes a second P-type well region, a second heavily doped N-type region, and a third heavily doped P-type region. The second P-type well region is located within the second N-type epitaxial region. A second N-type heavily doped region and a third P-type heavily doped region are located within the second P-type well region, wherein the second N-type heavily doped region is coupled to the second P-type heavily doped region and the I / O port, and the third P-type heavily doped region is coupled to the second voltage rail. The clamped bipolar junction transistor includes a third P-type well region, a third N-type heavily doped region, and a fourth N-type heavily doped region. The third P-type well region is located within the third N-type epitaxial region, and the third N-type heavily doped region and the fourth N-type heavily doped region are located within the third P-type well region and are respectively coupled to the second voltage rail and the first voltage rail.

[0012] In one embodiment of the present invention, the electrostatic discharge protection device further includes a semiconductor substrate, at least one first isolation trench, and at least one second isolation trench, and the silicon controlled rectifier includes an N-type epitaxial layer, a first P-type well region, a first P-type heavily doped region, a first N-type heavily doped region, and a second P-type heavily doped region. The N-type epitaxial layer is disposed on the semiconductor substrate. The first isolation trench and the second isolation trench are disposed in the N-type epitaxial layer and the semiconductor substrate, dividing the N-type epitaxial layer into at least one first N-type epitaxial region, at least one second N-type epitaxial region, and a third N-type epitaxial region. A diode and a clamped bipolar junction transistor are respectively disposed in the second N-type epitaxial region and the third N-type epitaxial region, and the first N-type epitaxial region decouples the I / O port. The first P-type well region is disposed in the first N-type epitaxial region. The first P-type heavily doped region and the first N-type heavily doped region are disposed in the first P-type well region and coupled to a first voltage rail. A second P-type heavily doped region is located within a first N-type epitaxial region and coupled to the I / O port and the diode's cathode. The first P-type heavily doped region, the first P-type well region, the first N-type epitaxial region, and the second P-type heavily doped region form a parasitic PNP bipolar junction transistor, and the first N-type heavily doped region, the first P-type well region, and the first N-type epitaxial region form a parasitic NPN bipolar junction transistor. The diode includes a second P-type well region, a second N-type heavily doped region, and a third P-type heavily doped region. The second P-type well region is located within the second N-type epitaxial region, and the second N-type heavily doped region and the third P-type heavily doped region are located within the second P-type well region. The second N-type heavily doped region is coupled to the second P-type heavily doped region and the I / O port, and the third P-type heavily doped region is coupled to the second voltage rail. The clamped bipolar junction transistor includes a third P-type well region, a third N-type heavily doped region, and a fourth N-type heavily doped region. The third P-type well region is located in the third N-type epitaxial region, and the third N-type heavily doped region and the fourth N-type heavily doped region are located in the third P-type well region, and are respectively coupled to the second voltage rail and the first voltage rail.

[0013] In one embodiment of the present invention, the doping concentration of the third P-type well region is greater than that of the first P-type well region, and the doping concentration of the first P-type well region is greater than that of the second P-type well region.

[0014] In one embodiment of the present invention, the electrostatic discharge protection device further includes a semiconductor substrate, at least one first isolation trench, and at least one second isolation trench, and the silicon controlled rectifier includes an N-type epitaxial layer, a first P-type well region, a first P-type heavily doped region, a first N-type heavily doped region, and a second P-type heavily doped region. The N-type epitaxial layer is disposed on the semiconductor substrate. The first isolation trench and the second isolation trench are disposed in the N-type epitaxial layer and the semiconductor substrate, dividing the N-type epitaxial layer into at least one first N-type epitaxial region, at least one second N-type epitaxial region, and a third N-type epitaxial region. A diode and a clamped bipolar junction transistor are respectively disposed in the second N-type epitaxial region and the third N-type epitaxial region, and the first N-type epitaxial region decouples the I / O port. The first P-type well region is disposed in the first N-type epitaxial region. The first P-type heavily doped region and the first N-type heavily doped region are disposed in the first P-type well region and coupled to a first voltage rail. The second P-type heavily doped region is located within the first N-type epitaxial region and is coupled to the I / O port and the cathode of the diode. The first P-type heavily doped region, the first P-type well region, the first N-type epitaxial region, and the second P-type heavily doped region form a parasitic PNP bipolar junction transistor, and the first N-type heavily doped region, the first P-type well region, and the first N-type epitaxial region form a parasitic NPN bipolar junction transistor. The diode includes a second P-type well region, a second N-type heavily doped region, and a third P-type heavily doped region. The second P-type well region is located within the second N-type epitaxial region, and the second N-type heavily doped region and the third P-type heavily doped region are located within the second N-type epitaxial region and the second P-type well region, respectively. The second N-type heavily doped region is coupled to the second P-type heavily doped region and the I / O port, and the third P-type heavily doped region is coupled to the second voltage rail. The clamped bipolar junction transistor includes a third P-type well region, a third N-type heavily doped region, and a fourth N-type heavily doped region. The third P-type well region is located within the third N-type epitaxial region. The third N-type heavily doped region and the fourth N-type heavily doped region are located within the third P-type well region and are coupled to the second voltage rail and the first voltage rail, respectively.

[0015] In one embodiment of the present invention, the doping concentration of the third P-type well region is greater than that of the first P-type well region, and the doping concentration of the first P-type well region is greater than that of the second P-type well region.

[0016] Based on the above, the electrostatic discharge protection device sets the absolute value of the reverse breakdown voltage of the diode to be greater than the absolute value of the anode-to-cathode trigger voltage of the silicon controlled rectifier, and the absolute value of the anode-to-cathode trigger voltage of the silicon controlled rectifier to be greater than the absolute value of the trigger voltage of the clamped bipolar junction transistor, so as to maintain a high voltage without being triggered during misoperation and improve electrostatic discharge performance under low capacitance conditions. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of an existing electrostatic discharge (ESD) protection device.

[0018] Figure 2 This is a schematic diagram of an electrostatic discharge protection device according to a first embodiment of the present invention.

[0019] Figure 3 This is a current-to-voltage curve of a silicon controlled rectifier according to an embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram of an electrostatic discharge protection device according to a second embodiment of the present invention.

[0021] Figure 5 This is a structural cross-sectional view of an electrostatic discharge protection device according to an embodiment of the present invention.

[0022] Figure 6 This is a structural cross-sectional view of an electrostatic discharge protection device according to another embodiment of the present invention.

[0023] Figure 7 This is a structural cross-sectional view of an electrostatic discharge protection device according to another embodiment of the present invention.

[0024] Explanation of reference numerals in the attached figures: 1 – Electrostatic discharge protection device; 10 – Bipolar junction transistor; 11 – Diode; 12 – Diode; 13 – Input / output (I / O) port; 2 – Electrostatic discharge (ESD) protection device; 20 – Electrostatic discharge circuit; 21 – Clamped bipolar transistor; 210 – Third P-type well region; 211 – Third N-type heavily doped region; 212 – Fourth N-type heavily doped region; 213 – Fourth P-type heavily doped region; 22 – Parasitic resistance; 23 – Input / output (I / O) port; 24 – Silicon controlled rectifier; 240 – N-type semiconductor substrate; 241 – First P-type well region; 242 – First P-type heavily doped region; 243 – First N-type heavily doped region; 24 4 – Second P-type heavily doped region; 25 – Diode; 250, 250' – Second P-type well region; 251, 251' – Second N-type heavily doped region; 252, 252' – Third P-type heavily doped region; 26 – Parasitic PNP bipolar transistor; 27 – Parasitic NPN bipolar transistor; 28 – Parasitic resistance; 29 – Semiconductor substrate; Vdd, Vss, VDD, VSS – Voltage; Vt – Anode-to-cathode trigger voltage; Vh – Anode-to-cathode holding voltage; -Vt – Trigger voltage; S1 – First isolation trench; S2 – Second isolation trench; E – N-type epitaxial layer; E1 – First N-type epitaxial region; E2 – Second N-type epitaxial region; E3 – Third N-type epitaxial region. Detailed Implementation

[0025] Embodiments of the present invention will be further explained below with reference to the accompanying drawings. Wherever possible, the same reference numerals represent the same or similar components in the drawings and description. In the drawings, shapes and thicknesses may be exaggerated for simplicity and convenience. It is understood that elements not specifically shown in the drawings or described in the description are forms known to those skilled in the art. Those skilled in the art can make various changes and modifications based on the content of this invention.

[0026] Unless otherwise specified, certain conditional clauses or words, such as "can," "could," "might," or "may," are generally intended to express features, elements, or steps that are present in the embodiments of this invention, but may also be interpreted as features, elements, or steps that may not be required. In other embodiments, these features, elements, or steps may be unnecessary.

[0027] In the following description of "one embodiment" or "an embodiment," the term refers to a specific element, structure, or feature associated with at least one embodiment. Therefore, the multiple descriptions of "one embodiment" or "an embodiment" appearing in various places below do not refer to the same embodiment. Furthermore, specific components, structures, and features in one or more embodiments may be combined in a suitable manner.

[0028] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but by differences in function. The word "comprising" in the specification and claims is an open-ended term and should be interpreted as "including but not limited to". Furthermore, "coupled" here includes any direct and indirect connection means. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission or optical transmission, or indirectly electrically or signal connected to the second element through other elements or connection means.

[0029] This invention is described in particular by way of the following examples, which are merely illustrative. Various modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this invention is determined by the appended claims. Throughout the specification and claims, unless explicitly stated otherwise, the words “a” and “described” mean that such a description includes “a or at least one” of the stated elements or components. Furthermore, as used herein, the singular article also includes descriptions of multiple elements or components unless clearly indicated from the specific context. Moreover, when applied in this description and all the following claims, unless explicitly stated otherwise, “in which” means both “in which” and “therein”. The terms used throughout the specification and claims, unless otherwise specified, generally have their ordinary meaning in the art, in the context of this invention, and in the specific context. Certain terms used to describe the invention will be discussed below or elsewhere in this specification to provide additional guidance to practitioners in describing the invention. Examples throughout this specification, including examples of any terms discussed herein, are for illustrative purposes only and do not limit the scope or meaning of the invention or any of the illustrative terms. Similarly, the invention is not limited to the various embodiments set forth in this specification.

[0030] When an element is referred to as “on”, it can mean that the element is directly on another element, or that another element exists between the two. Conversely, when an element is referred to as “directly on” another element, it cannot mean that another element exists between the two. As used herein, the term “and / or” includes any combination of one or more of the listed related items.

[0031] In the following description, an electrostatic discharge (ESD) protection device is provided, wherein the absolute value of the reverse breakdown voltage of a diode is greater than the absolute value of the anode-to-cathode trigger voltage of a silicon controlled rectifier, and the absolute value of the anode-to-cathode trigger voltage of the silicon controlled rectifier is greater than the absolute value of the trigger voltage of a clamped bipolar transistor, so as to withstand high voltage without being triggered during misoperation and improve ESD performance in a low capacitance state.

[0032] Figure 2 This is a schematic diagram of the electrostatic discharge protection device according to the first embodiment of the present invention. Figure 3 This is a current-to-voltage curve of a silicon-controlled rectifier according to an embodiment of the present invention. Please refer to [link / reference]. Figure 2The following describes a first embodiment of an electrostatic discharge (ESD) protection device 2 of the present invention. The ESD protection device 2 includes a clamped bipolar transistor 21 and at least one electrostatic discharge circuit 20. For convenience and clarity, the first embodiment uses an electrostatic discharge circuit 20 as an example. The clamped bipolar transistor 21 is coupled between a first voltage rail and a second voltage rail. In the energized mode, the first voltage rail and the second voltage rail are respectively a high voltage rail and a low voltage rail. The voltage of the high voltage rail is denoted as VDD. The voltage of the low voltage rail is denoted as VSS. The clamped bipolar transistor 21 can be an NPN bipolar transistor with its base electrically floating, an NPN bipolar transistor with its emitter coupled to its base, a PNP bipolar transistor with its base electrically floating, or a PNP bipolar transistor with its emitter coupled to its base. In the first embodiment, the clamped bipolar transistor 21 may have a parasitic resistance 22. The base of the clamped bipolar transistor 21 is coupled to its emitter through the parasitic resistance 22.

[0033] An electrostatic discharge (ESD) circuit 20 is coupled between a first voltage rail and a second voltage rail, and is also coupled to an input / output (I / O) port 23. The ESD circuit 20 includes a silicon controlled rectifier (SCR) 24 and a diode 25. The anode of the SCR 24 is coupled to the I / O port 23. The cathode of the SCR 24 is coupled to the first voltage rail. The cathode of the diode 25 is coupled to the anode of the SCR 24 and the I / O port 23. The anode of the diode 25 is coupled to the second voltage rail. (See also...) Figure 2 and Figure 3The absolute value of the anode-to-cathode trigger voltage Vt of the silicon controlled rectifier 24 is greater than the absolute value of the trigger voltage of the clamped bipolar transistor 21 and the absolute value of the anode-to-cathode holding voltage Vh of the silicon controlled rectifier 24. Therefore, when the I / O port 23 receives a high voltage, the electrostatic discharge protection device 2 can withstand the high voltage without being triggered. To prevent ESD current from flowing from the I / O port 23 to the second voltage rail and damaging the diode 25, the absolute value of the reverse breakdown voltage of the diode 25 is greater than the absolute value of the anode-to-cathode trigger voltage Vt of the silicon controlled rectifier 24. The silicon controlled rectifier 24 includes a parasitic PNP bipolar transistor 26 and a parasitic NPN bipolar transistor 27. The base of the parasitic PNP bipolar transistor 26 is electrically floating and decoupled from the I / O port 23. Therefore, the input capacitance of the electrostatic discharge protection device 2 can be reduced. Generally, the input capacitance can be in the range of 0.2 to 5 picofarads (pF), but the invention is not limited thereto. Furthermore, the anode-to-cathode characteristics of the silicon controlled rectifier 24 exhibit a non-significant snapback current-voltage profile and a very high absolute trigger voltage -Vt. In other embodiments, the silicon controlled rectifier 24 also includes a parasitic resistor 28 coupled between the base and emitter of a parasitic NPN bipolar transistor 27. When a positive ESD event occurs at I / O port 23, ESD current flows from I / O port 23 through the silicon controlled rectifier 24 and the clamped bipolar transistor 21 to the second voltage rail. In other embodiments, the first voltage rail may be electrically floating due to a power-off mode.

[0034] Therefore, the electrostatic discharge protection device 2 can be applied to the Configuration Channel (CC) and Side Band Use (SBU) pins of a Universal Serial Bus (USB) Type-C port. When the CC or SBU pin is exposed to a high voltage on the Voltage Bus (VBUS) pin during a misoperation, the electrostatic discharge protection device 2 can withstand the high voltage without being triggered, thus improving ESD performance in a low-capacitance state.

[0035] Figure 4 This is a schematic diagram of an electrostatic discharge protection device according to a second embodiment of the present invention. Please refer to [link / reference]. Figure 4The following describes the ESD protection device 2 according to a second embodiment of the present invention. The difference between the first and second embodiments is that the ESD protection device 2 of the second embodiment includes multiple electrostatic discharge circuits 20. Because the anode-to-cathode characteristic of the silicon controlled rectifier 24 exhibits a high trigger voltage, ESD current is difficult to flow from the left I / O port 23 through the right silicon controlled rectifier 24 to the right I / O port 23, thus avoiding damage to the right silicon controlled rectifier 24. When the ESD current flows from the left I / O port 23 to the right I / O port 23, the ESD tolerance can be improved. When a positive ESD event occurs at the left I / O port 23, and the right I / O port 23 is relatively grounded, the ESD current flows from the left I / O port 23 through the left silicon controlled rectifier 24, the clamped bipolar transistor 21, and the right diode 25 to the right I / O port 23.

[0036] Figure 5 This is a structural cross-sectional view of an electrostatic discharge protection device according to an embodiment of the present invention. Please refer to [link / reference]. Figure 4 and Figure 5 The silicon controlled rectifier 24 may include an N-type semiconductor substrate 240, a first P-type well region 241, a first P-type heavily doped region 242, a first N-type heavily doped region 243, and a second P-type heavily doped region 244. The N-type semiconductor substrate 240 is electrically floating. The first P-type well region 241 is disposed in the N-type semiconductor substrate 240. The first P-type heavily doped region 242 and the first N-type heavily doped region 243 are disposed in the first P-type well region 241 and coupled to a first voltage rail. The second P-type heavily doped region 244 is disposed in the N-type semiconductor substrate 240 and coupled to the I / O port 23 and the cathode of the diode 25. The second P-type heavily doped region 244 can directly contact the N-type semiconductor substrate 240. The first P-type heavily doped region 242, the first P-type well region 241, the N-type semiconductor substrate 240, and the second P-type heavily doped region 244 form a parasitic PNP bipolar transistor 26. A parasitic NPN bipolar transistor 27 is formed by a first N-type heavily doped region 243, a first P-type well region 241, and an N-type semiconductor substrate 240. A parasitic resistor 28 is formed in the first P-type well region 241. A clamping bipolar transistor 21 and a diode 25 are disposed in the N-type semiconductor substrate 240. The diode 25 is disposed between the clamping bipolar transistor 21 and each of the first P-type well region 241 and the second P-type heavily doped region 244 to suppress the parasitic silicon controlled rectifier (SCR) path from the I / O port 23 to the second voltage rail and to improve ESD tolerance.

[0037] Diode 25 may include a second P-type well region 250, a second heavily doped N-type region 251, and a third heavily doped P-type region 252. The second P-type well region 250 is disposed in the N-type semiconductor substrate 240. The second heavily doped N-type region 251 and the third heavily doped P-type region 252 are disposed in the second P-type well region 250. The second heavily doped N-type region 251 is coupled to the second heavily doped P-type region 244 and the I / O port 23. The third heavily doped P-type region 252 is coupled to the second voltage rail.

[0038] The clamped bipolar transistor 21 may include a third P-type well region 210, a third heavily doped N-type region 211, a fourth heavily doped N-type region 212, and a fourth heavily doped P-type region 213. The third P-type well region 210 is disposed in the N-type semiconductor substrate 240. The third heavily doped N-type region 211 and the fourth heavily doped N-type region 212 are disposed in the third P-type well region 210 and are coupled to the second voltage rail and the first voltage rail, respectively. The fourth heavily doped P-type region 213 is disposed in the third P-type well region 210 and is coupled to the third heavily doped N-type region 211, and forms a parasitic resistance 22. In order to ensure that the absolute value of the reverse breakdown voltage of diode 25 is greater than the absolute value of the anode-to-cathode trigger voltage of silicon controlled rectifier 24, and the absolute value of the anode-to-cathode trigger voltage of silicon controlled rectifier 24 is greater than the absolute value of the trigger voltage of clamped bipolar transistor 21, the doping concentration of the third P-type well region 210 is greater than the doping concentration of the first P-type well region 241, and the doping concentration of the first P-type well region 241 is greater than the doping concentration of the second P-type well region 250.

[0039] Figure 6 This is a structural cross-sectional view of an electrostatic discharge protection device according to another embodiment of the present invention. (See also...) Figure 4 and Figure 6The electrostatic discharge protection device 2 further includes a semiconductor substrate 29, at least one first isolation trench S1, and at least one second isolation trench S2. The semiconductor substrate 29 can be N-type, P-type, or intrinsically type. The first isolation trench S1 and the second isolation trench S2 include insulating material. For convenience and clarity, there are two first isolation trenches S1 and two second isolation trenches S2. The silicon controlled rectifier 24 may include an N-type epitaxial layer E, a first P-type well region 241, a first P-type heavily doped region 242, a first N-type heavily doped region 243, and a second P-type heavily doped region 244. The N-type epitaxial layer E is disposed on the semiconductor substrate 29. The first isolation trench S1 and the second isolation trench S2 are disposed in the N-type epitaxial layer E and the semiconductor substrate 29, and divide the N-type epitaxial layer E into at least one first N-type epitaxial region E1, at least one second N-type epitaxial region E2, and a third N-type epitaxial region E3. The first isolation trench S1 and the second isolation trench S2 are used to suppress the parasitic silicon controlled rectifier (SCR) path from I / O port 23 to the second voltage rail and improve ESD tolerance. In this embodiment, there are two first N-type epitaxial regions E1 and two second N-type epitaxial regions E2. Diode 25 and clamped bipolar transistor 21 are respectively disposed in the second N-type epitaxial region E2 and the third N-type epitaxial region E3. The first N-type epitaxial region E1 decouples I / O port 23. A first P-type well region 241 is disposed in the first N-type epitaxial region E1. A first P-type heavily doped region 242 and a first N-type heavily doped region 243 are disposed in the first P-type well region 241 and coupled to the first voltage rail. A second P-type heavily doped region 244 is disposed in the first N-type epitaxial region E1 and coupled to I / O port 23 and the cathode of diode 25. The second P-type heavily doped region 244 can directly contact the first N-type epitaxial region E1. The first P-type heavily doped region 242, the first P-type well region 241, the first N-type epitaxial region E1, and the second P-type heavily doped region 244 form a parasitic PNP bipolar transistor 26. The first N-type heavily doped region 243, the first P-type well region 241, and the first N-type epitaxial region E1 form a parasitic NPN bipolar transistor 27. The first P-type well region 241 forms a parasitic resistor 28.

[0040] Diode 25 may include a second P-type well region 250, a second N-type heavily doped region 251, and a third P-type heavily doped region 252. The second P-type well region 250 is located within the second N-type epitaxial region E2. The second N-type heavily doped region 251 and the third P-type heavily doped region 252 are located within the second P-type well region 250. The second N-type heavily doped region 251 is coupled to the second P-type heavily doped region 244 and the I / O port 23. The third P-type heavily doped region 252 is coupled to the second voltage rail.

[0041] The clamped bipolar transistor 21 may include a third P-type well region 210, a third N-type heavily doped region 211, a fourth N-type heavily doped region 212, and a fourth P-type heavily doped region 213. The third P-type well region 210 is located in the third N-type epitaxial region E3. The third N-type heavily doped region 211 and the fourth N-type heavily doped region 212 are located in the third P-type well region 210 and are coupled to the second voltage rail and the first voltage rail, respectively. The fourth P-type heavily doped region 213 is located in the third P-type well region 210 and is coupled to the third N-type heavily doped region 211, forming a parasitic resistance 22. In order to ensure that the absolute value of the reverse breakdown voltage of diode 25 is greater than the absolute value of the anode-to-cathode trigger voltage of silicon controlled rectifier 24, and the absolute value of the anode-to-cathode trigger voltage of silicon controlled rectifier 24 is greater than the absolute value of the trigger voltage of clamped bipolar transistor 21, the doping concentration of the third P-type well region 210 is greater than the doping concentration of the first P-type well region 241, and the doping concentration of the first P-type well region 241 is greater than the doping concentration of the second P-type well region 250.

[0042] Figure 7 This is a structural cross-sectional view of an electrostatic discharge protection device according to another embodiment of the present invention. Please refer to [link / reference]. Figure 4 and Figure 7 , Figure 6 Implementation examples and Figure 7 The embodiment differs in diode 25. Figure 7 In one embodiment, diode 25 may include a second P-type well region 250', a second N-type heavily doped region 251', and a third P-type heavily doped region 252'. The second P-type well region 250' is located in the second N-type epitaxial region E2. The second N-type heavily doped region 251' and the third P-type heavily doped region 252' are respectively located in the second N-type epitaxial region E2 and the second P-type well region 250'. The second N-type heavily doped region 251' is coupled to the second P-type heavily doped region 244 and the I / O port 23, and the third P-type heavily doped region 252' is coupled to the second voltage rail. Figure 7 The embodiment is used to further increase the absolute value of the reverse breakdown voltage of diode 25. Figure 7 Other structures of the embodiments have been described above and will not be repeated here.

[0043] According to the above embodiments, the electrostatic discharge protection device can withstand high voltage without being triggered during misoperation and improve ESD performance under low capacitance conditions.

[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent variations and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present invention should be included within the scope of the claims of the present invention.

Claims

1. An electrostatic discharge protection device, characterized in that, include: A clamped bipolar junction transistor is coupled between a first voltage rail and a second voltage rail. as well as At least one electrostatic discharge circuit is coupled between the first voltage rail and the second voltage rail, and coupled to an I / O port, the at least one electrostatic discharge circuit comprising: A silicon controlled rectifier, the anode of which is coupled to the I / O port, and the cathode of which is coupled to the first voltage rail; and A diode, the cathode of which is coupled to the anode of the silicon controlled rectifier and the I / O port, and the anode of the diode is coupled to the second voltage rail; The absolute value of the reverse breakdown voltage of the diode is greater than the absolute value of the anode-to-cathode trigger voltage of the silicon controlled rectifier, and the absolute value of the anode-to-cathode trigger voltage of the silicon controlled rectifier is greater than the absolute value of the trigger voltage of the clamped bipolar junction transistor. The silicon-controlled rectifier includes a parasitic PNP bipolar junction transistor and a parasitic NPN bipolar junction transistor, and the base of the parasitic PNP bipolar junction transistor is decoupled from the I / O port.

2. The electrostatic discharge protection device as described in claim 1, characterized in that, The at least one electrostatic discharge circuit includes multiple electrostatic discharge circuits.

3. The electrostatic discharge protection device as described in claim 1, characterized in that, The clamped bipolar junction transistor is an NPN bipolar junction transistor with its base electrically floating, an NPN bipolar junction transistor with its emitter coupled to its base, a PNP bipolar junction transistor with its base electrically floating, or a PNP bipolar junction transistor with its emitter coupled to its base.

4. The electrostatic discharge protection device as described in claim 1, characterized in that, The first voltage rail is electrically floating.

5. The electrostatic discharge protection device as described in claim 1, characterized in that, The silicon-controlled rectifier includes: An N-type semiconductor substrate is used to decouple the I / O ports; A first P-type well region is disposed in the N-type semiconductor substrate; A first P-type heavily doped region and a first N-type heavily doped region are disposed in the first P-type well region and coupled to the first voltage rail; and A second P-type heavily doped region is disposed in the N-type semiconductor substrate and coupled to the I / O port and the cathode of the diode. The first P-type heavily doped region, the first P-type well region, the N-type semiconductor substrate, and the second P-type heavily doped region form the parasitic PNP bipolar junction transistor. The first N-type heavily doped region, the first P-type well region, and the N-type semiconductor substrate form the parasitic NPN bipolar junction transistor. The clamped bipolar junction transistor and the diode are disposed in the N-type semiconductor substrate, and the diode is disposed between each of the first P-type well region and the second P-type heavily doped region and the clamped bipolar junction transistor. The diode includes: A second P-type well region is disposed in the N-type semiconductor substrate; and A second N-type heavily doped region and a third P-type heavily doped region are disposed in the second P-type well region, wherein the second N-type heavily doped region is coupled to the second P-type heavily doped region and the I / O port, and the third P-type heavily doped region is coupled to the second voltage rail. The clamped bipolar junction transistor includes: A third P-type well region is disposed in the N-type semiconductor substrate; and A third N-type heavily doped region and a fourth N-type heavily doped region are disposed in the third P-type well region and are respectively coupled to the second voltage rail and the first voltage rail.

6. The electrostatic discharge protection device as described in claim 5, characterized in that, The doping concentration of the third P-type well region is greater than that of the first P-type well region, and the doping concentration of the first P-type well region is greater than that of the second P-type well region.

7. The electrostatic discharge protection device as described in claim 1, characterized in that, It also includes a semiconductor substrate, at least one first isolation trench and at least one second isolation trench, and the silicon controlled rectifier includes: An N-type epitaxial layer is disposed on the semiconductor substrate, wherein at least one first isolation trench and at least one second isolation trench are disposed in the N-type epitaxial layer and the semiconductor substrate, and the N-type epitaxial layer is divided into at least one first N-type epitaxial region, at least one second N-type epitaxial region and a third N-type epitaxial region, the diode and the clamped bipolar junction transistor are respectively disposed in the at least one second N-type epitaxial region and the third N-type epitaxial region, and the at least one first N-type epitaxial region decouples the I / O port; A first P-type well region is disposed within the at least one first N-type epitaxial region; A first P-type heavily doped region and a first N-type heavily doped region are disposed in the first P-type well region and coupled to the first voltage rail; and A second P-type heavily doped region is disposed in the at least one first N-type epitaxial region and coupled to the I / O port and the cathode of the diode, wherein the first P-type heavily doped region, the first P-type well region, the at least one first N-type epitaxial region and the second P-type heavily doped region form the parasitic PNP bipolar junction transistor, and the first N-type heavily doped region, the first P-type well region and the at least one first N-type epitaxial region form the parasitic NPN bipolar junction transistor; The diode includes: A second P-type well region is disposed within the at least one second N-type epitaxial region; and A second N-type heavily doped region and a third P-type heavily doped region are disposed in the second P-type well region, wherein the second N-type heavily doped region is coupled to the second P-type heavily doped region and the I / O port, and the third P-type heavily doped region is coupled to the second voltage rail. The clamped bipolar junction transistor includes: A third P-type well region is located within the third N-type epitaxial region; and A third N-type heavily doped region and a fourth N-type heavily doped region are disposed in the third P-type well region and are respectively coupled to the second voltage rail and the first voltage rail.

8. The electrostatic discharge protection device as described in claim 7, characterized in that, The doping concentration of the third P-type well region is greater than that of the first P-type well region, and the doping concentration of the first P-type well region is greater than that of the second P-type well region.

9. The electrostatic discharge protection device as described in claim 1, characterized in that, It also includes a semiconductor substrate, at least one first isolation trench and at least one second isolation trench, and the silicon controlled rectifier includes: An N-type epitaxial layer is disposed on the semiconductor substrate, wherein at least one first isolation trench and at least one second isolation trench are disposed in the N-type epitaxial layer and the semiconductor substrate, and the N-type epitaxial layer is divided into at least one first N-type epitaxial region, at least one second N-type epitaxial region and a third N-type epitaxial region, the diode and the clamped bipolar junction transistor are respectively disposed in the at least one second N-type epitaxial region and the third N-type epitaxial region, and the at least one first N-type epitaxial region decouples the I / O port; A first P-type well region is disposed within the at least one first N-type epitaxial region; A first P-type heavily doped region and a first N-type heavily doped region are disposed in the first P-type well region and coupled to the first voltage rail; and A second P-type heavily doped region is disposed in the at least one first N-type epitaxial region and coupled to the I / O port and the cathode of the diode, wherein the first P-type heavily doped region, the first P-type well region, the at least one first N-type epitaxial region and the second P-type heavily doped region form the parasitic PNP bipolar junction transistor, and the first N-type heavily doped region, the first P-type well region and the at least one first N-type epitaxial region form the parasitic NPN bipolar junction transistor; The diode includes: A second P-type well region is disposed within the at least one second N-type epitaxial region; and A second N-type heavily doped region and a third P-type heavily doped region are respectively disposed in the at least one second N-type epitaxial region and the second P-type well region, wherein the second N-type heavily doped region is coupled to the second P-type heavily doped region and the I / O port, and the third P-type heavily doped region is coupled to the second voltage rail. The clamped bipolar junction transistor includes: A third P-type well region is located within the third N-type epitaxial region; and A third N-type heavily doped region and a fourth N-type heavily doped region are disposed in the third P-type well region and are respectively coupled to the second voltage rail and the first voltage rail.

10. The electrostatic discharge protection device as described in claim 9, characterized in that, The doping concentration of the third P-type well region is greater than that of the first P-type well region, and the doping concentration of the first P-type well region is greater than that of the second P-type well region.

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