Laminated solar cell and preparation method thereof

Abstract

The invention relates to the technical field of solar cells, in particular to a laminated solar cell and a preparation method thereof. The laminated solar cell comprises a crystalline silicon bottom cell, a passivation layer, a transparent conductive oxide layer and an antimony sulfide top cell which are sequentially laminated along a first direction, the passivation layer comprises at least one slotted region arranged along a second direction, and the second direction is perpendicular to the first direction; the transparent conductive oxide layer comprises at least one first part and at least one second part, the second parts are in one-to-one correspondence with the slotting areas, are arranged in the slotting areas and are in contact with the crystalline silicon bottom battery, and the first parts and the second parts are arranged in a stepped manner along the second direction; wherein the first direction is the thickness direction of the crystal silicon bottom battery. Compared with a perovskite cell, the laminated solar cell has better stability, and meanwhile, compared with an existing antimony sulfide crystalline silicon cell, the preparation method is simplified while the conversion efficiency is guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a stacked solar cell and a preparation method thereof. Background Art

[0002] Wind and solar power generation is considered to be the most promising pollution-free, sustainable new energy that can replace thermal power generation. Among them, photovoltaic power generation is not restricted by the site and can be laid out in farmland, deserts, rooftops and other places. It is flexible and safer to install. At present, N-type TOPCon cell technology has become one of the mainstream choices in the photovoltaic industry due to its high conversion efficiency, high reliability and industrial feasibility. With the advancement of technology and the advancement of industrialization, the mass production efficiency of TOPCon cells has exceeded 25%, but limited by the band gap width of crystalline silicon, its single junction theoretical limit is about 29.4%. In order to break through the theoretical limit of single-junction cells, researchers have been exploring a variety of technical approaches, one of which is to use stacked solar cells. The current mainstream crystalline silicon stacked cell top cells are all perovskite cells, but perovskite cells still have difficulties in large-area preparation and stability needs to be further optimized. Antimony sulfide cells also have the potential to be used as crystalline silicon cell top cells due to their wide band gap advantages, but there is currently very little research on this in the industry. Summary of the invention

[0003] The present invention aims to solve one of the technical problems in the related art to at least some extent. To this end, the present invention provides a tandem solar cell and a method for preparing the same, which has better stability than a perovskite cell and simplifies the preparation method while ensuring conversion efficiency compared to the existing antimony sulfide crystalline silicon cell.

[0004] To this end, the first aspect of the present invention provides a stacked solar cell, comprising:

[0005] A crystalline silicon bottom cell, a passivation layer, a transparent conductive oxide layer and an antimony sulfide top cell are sequentially stacked along a first direction;

[0006] The passivation layer includes at least one grooved region arranged along a second direction, wherein the second direction is perpendicular to the first direction;

[0007] The transparent conductive oxide layer includes at least one first portion and at least one second portion, the second portion corresponds to the groove area one by one, and is arranged in the groove area to contact the crystalline silicon bottom cell, and the first portion and the second portion are arranged in a stepped manner along the second direction;

[0008] Wherein, the first direction is the thickness direction of the crystalline silicon bottom cell.

[0009] In order to solve the deficiencies in the prior art, the present invention connects the antimony sulfide solar cell and the crystalline silicon solar cell in series through a passivation layer and a transparent conductive oxide layer. At the same time, the passivation layer includes at least one grooved area, which can realize direct contact between the transparent conductive oxide layer and the crystalline silicon bottom cell, so that the carriers can be transmitted vertically and the photoelectric conversion efficiency can be improved.

[0010] According to an embodiment of the present invention, a thickness of the second portion of the transparent conductive oxide layer along the first direction is greater than or equal to a thickness of the passivation layer along the first direction.

[0011] According to an embodiment of the present invention, the difference between the thickness of the second portion along the first direction and the thickness of the passivation layer does not exceed 10% of the thickness of the crystalline silicon bottom cell along the first direction.

[0012] According to an embodiment of the present invention, the material of the passivation layer includes at least one of aluminum oxide, silicon nitride, silicon oxynitride, silicon oxide, and silicon carbide.

[0013] According to an embodiment of the present invention, the crystalline silicon bottom cell comprises a p-poly layer, a first tunneling oxide layer, a silicon substrate, a second tunneling oxide layer, and an n-poly layer which are sequentially stacked in sequence along the first direction;

[0014] The n-poly layer is disposed on a surface of the passivation layer away from the transparent conductive oxide layer;

[0015] and / or, the surface concentration of the p-poly layer is 1×10 19 ~2×10 21 cm -3 .

[0016] According to an embodiment of the present invention, the antimony sulfide top cell comprises a hole transport layer, an antimony sulfide layer, and an electron transport layer stacked in sequence along the first direction;

[0017] The hole transport layer is disposed on a surface of the transparent conductive oxide layer away from the passivation layer;

[0018] And / or, the stacked solar cell satisfies at least one of the following conditions:

[0019] (A) the hole transport layer includes at least one third portion and at least one fourth portion, the fourth portion corresponds to the groove region one by one, and is disposed in the groove region in contact with the second portion of the transparent conductive oxide layer, and the third portion and the fourth portion are arranged in a stepped manner along the second direction;

[0020] (B) the antimony sulfide layer includes at least one fifth portion and at least one sixth portion, the sixth portion corresponds to the grooved region one by one, and is arranged in the grooved region in contact with the fourth portion of the hole transport layer, and the fifth portion and the sixth portion are arranged in a stepped manner along the second direction;

[0021] (C) The electron transport layer includes at least one seventh portion and at least one eighth portion, the eighth portion corresponds to the grooved region one by one, and is arranged in the grooved region to contact the sixth portion of the antimony sulfide layer, and the seventh portion and the eighth portion are arranged in a stepped manner along the second direction.

[0022] According to an embodiment of the present invention, the stacked solar cell further comprises:

[0023] A composite layer, a positive metal electrode and an anti-reflection layer are sequentially stacked along the first direction;

[0024] The composite layer is disposed on a surface of the antimony sulfide top cell away from the transparent conductive oxide layer;

[0025] And / or, the stacked solar cell satisfies at least one of the following conditions:

[0026] (A) the composite layer includes at least one ninth portion and at least one tenth portion, the tenth portion corresponds to the grooved region one by one, and is arranged in the grooved region in contact with the eighth portion of the electron transport layer, and the ninth portion and the tenth portion are arranged in a stepped manner along the second direction;

[0027] (B) The positive metal electrode corresponds to the grooved region and is disposed in the grooved region in contact with the tenth portion of the composite layer.

[0028] According to an embodiment of the present invention, the stacked solar cell satisfies at least one of the following conditions:

[0029] (A) the material of the composite layer includes at least one of ITO, IWO, and ICO;

[0030] (B) The material of the hole transport layer includes NiO x , PEDOT, PTAA;

[0031] (C) The material of the electron transport layer includes C60, SnO x At least one of;

[0032] And / or, the stacked solar cell satisfies at least one of the following conditions:

[0033] Along the first direction, the difference in thickness between the hole transport layer and the transparent conductive oxide layer does not exceed 10%;

[0034] The difference in thickness between the antimony sulfide layer and the hole transport layer does not exceed 10%;

[0035] The difference in thickness between the electron transport layer and the antimony sulfide layer does not exceed 10%;

[0036] The thickness difference between the composite layer and the electron transport layer does not exceed 10%.

[0037] According to an embodiment of the present invention, the stacked solar cell further comprises:

[0038] A back passivation layer and a back metal electrode are sequentially stacked along the first direction;

[0039] The back passivation layer is arranged on the surface of the crystalline silicon bottom cell away from the passivation layer;

[0040] And / or, the material of the back passivation layer includes at least one of aluminum oxide, silicon nitride, silicon oxynitride, silicon oxide, and silicon carbide.

[0041] A second aspect of the present invention provides a method for preparing the stacked solar cell according to the first aspect, comprising:

[0042] Preparation of crystalline silicon bottom cells;

[0043] Depositing a passivation layer on a surface of the crystalline silicon bottom cell, and performing laser grooving on the passivation layer to form at least one grooved area on the passivation layer;

[0044] Depositing a passivation layer on a surface of the crystalline silicon bottom cell along a first direction, and performing a groove process on the passivation layer to form at least one groove region arranged along a second direction;

[0045] Depositing a transparent conductive oxide layer on a surface of the passivation layer away from the crystalline silicon bottom cell to form a first portion in contact with the passivation layer and a second portion in contact with the crystalline silicon bottom cell;

[0046] An antimony sulfide top cell is prepared on the surface of the transparent conductive oxide layer away from the crystalline silicon bottom cell.

[0047] The preparation process of the laminated solar cell provided by the present invention can fully utilize the existing crystalline silicon cell production equipment without replacing or adding production equipment, and at the same time simplifies the preparation process of the laminated solar cell, making the preparation more convenient.

[0048] According to an embodiment of the present invention, the preparation of the crystalline silicon bottom cell includes:

[0049] Providing a silicon substrate, and forming a first tunneling oxide layer and a second tunneling oxide layer on a pair of opposite surfaces of the silicon substrate, respectively;

[0050] Depositing a p-poly layer on a surface of the first tunnel oxide layer away from the silicon substrate;

[0051] Depositing an n-poly layer on a surface of the second tunnel oxide layer away from the silicon substrate; the passivation layer is in contact with the n-poly layer;

[0052] and / or, after depositing a p-poly layer on the surface of the first tunneling oxide layer away from the silicon substrate, removing the p-poly layer deposited around the surface of the second tunneling oxide layer away from the silicon substrate;

[0053] After depositing an n-poly layer on the surface of the second tunnel oxide layer away from the silicon substrate, removing the n-poly layer, the BSG layer and the PSG layer deposited around the surface of the p-poly layer away from the silicon substrate;

[0054] and / or, depositing a back passivation layer and a back metal electrode in sequence on a surface of the crystalline silicon bottom cell away from the passivation layer;

[0055] A composite layer, a positive metal electrode and an anti-reflection layer are sequentially deposited on the surface of the antimony sulfide top cell away from the transparent conductive oxide layer.

[0056] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0058] Figure 1 One of the structural schematic diagrams of the stacked solar cell provided by the present invention is shown;

[0059] Figure 2 The second structural schematic diagram of the stacked solar cell provided by the present invention is shown;

[0060] Figure 3 The third structural schematic diagram of the stacked solar cell provided by the present invention is shown;

[0061] Figure 4 The fourth structural schematic diagram of the stacked solar cell provided by the present invention is shown.

[0062] Reference numerals:

[0063] Tandem solar cell 100, crystalline silicon bottom cell 110, silicon substrate 111, first tunneling oxide layer 112, p-poly layer 113, second tunneling oxide layer 114, n-poly layer 115, passivation layer 120, transparent conductive oxide layer 130, first portion 131, second portion 132, antimony sulfide top cell 140, hole transport layer 141, third portion 1411, fourth portion 1412, antimony sulfide layer 142, fifth portion 1421, sixth portion 1422, electron transport layer 143, seventh portion 1431, eighth portion 1432, recombination layer 150, ninth portion 151, tenth portion 152, front metal electrode 160, anti-reflection layer 170, back passivation layer 180, back metal electrode 190. DETAILED DESCRIPTION

[0064] The embodiments of the present invention are described in detail below. The embodiments described below are exemplary and are only used to explain the present invention, and should not be understood as limiting the present invention.

[0065] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not mean that the present disclosure necessarily has the first element, component, region, layer or part.

[0066] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. Further, in the description of the present invention, unless otherwise specified, the meaning of "plurality" is two or more.

[0067] The endpoints and any values ​​of the ranges disclosed in this article are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article.

[0068] In order to make the present invention more easily understood, certain technical and scientific terms are specifically defined below. Unless otherwise clearly defined elsewhere in this document, all other technical and scientific terms used herein have the meanings commonly understood by those skilled in the art to which the present invention belongs.

[0069] In this document, the terms “include” or “comprising” are open expressions, that is, including the contents specified in the present invention but not excluding other contents.

[0070] In the related art, in order to connect antimony sulfide solar cells and silicon solar cells in series, a high work function transition metal oxide layer and a passivation layer can be set between the two sub-cells. However, in this technical solution, the passivation layer needs to contain a metal nanoparticle array, which makes the preparation method more complicated and costly, and is not conducive to large-scale production.

[0071] The present invention proposes a stacked solar cell and a preparation method thereof, wherein the stacked solar cell comprises: a crystalline silicon bottom cell, a passivation layer, a transparent conductive oxide layer and an antimony sulfide top cell stacked in sequence; the passivation layer comprises at least one slotted area; the transparent conductive oxide layer contacts the crystalline silicon bottom cell through the slotted area. The stacked solar cell does not require a passivation layer containing metal nano-array particles, and can realize connecting the antimony sulfide cell and the silicon cell in series. At the same time, by slotting the passivation layer, the transparent conductive oxide layer is in direct contact with the crystalline silicon bottom cell, so that the carriers can be transmitted longitudinally, thereby promoting current transmission and improving the photoelectric conversion efficiency. At the same time, compared with the prior art, the preparation method of the stacked solar cell does not require the addition of metal nano-array particles in the passivation layer, thereby simplifying the preparation process of the stacked solar cell, and can also make full use of the existing crystalline silicon cell production equipment without replacing or adding production equipment.

[0072] According to an embodiment of the present invention, a first aspect of the present invention provides a stacked solar cell, the structure of which is shown in FIG. Figure 1 Among them, the first direction described in the present invention is Figure 1 The first direction is the Z direction, and the second direction is the X direction.

[0073] According to a specific embodiment of the present invention, the stacked solar cell 100 includes a crystalline silicon bottom cell 110, a passivation layer 120, a transparent conductive oxide layer 130, and an antimony sulfide top cell 140 which are stacked in sequence along a first direction;

[0074] The passivation layer 120 includes at least one grooved region arranged along the second direction;

[0075] The transparent conductive oxide layer 130 includes at least one first portion 131 and at least one second portion 132, wherein the second portion 132 corresponds to the groove area one by one and is arranged in the groove area to contact the crystalline silicon bottom cell 110, and the first portion 131 and the second portion 132 are arranged in a stepped manner along the second direction; the first direction is perpendicular to the second direction.

[0076] The stacked solar cell does not need a passivation layer containing metal nano-array particles, and can realize the connection of antimony sulfide cells and silicon cells in series. At the same time, by slotting the passivation layer, the transparent conductive oxide layer is in direct contact with the crystalline silicon bottom cell, so that the carriers can be transmitted vertically, thereby promoting current transmission and improving the photoelectric conversion efficiency. At the same time, compared with the prior art, the preparation method of the stacked solar cell does not need to add metal nano-array particles in the passivation layer, thereby simplifying the preparation process of the stacked solar cell, and can also make full use of the existing crystalline silicon cell production equipment without replacing or adding production equipment.

[0077] According to a specific embodiment of the present invention, the thickness of the second portion 132 of the transparent conductive oxide layer 130 along the first direction is greater than or equal to the thickness of the passivation layer 120 along the first direction.

[0078] According to a specific embodiment of the present invention, the difference between the thickness of the second portion 132 along the first direction and the thickness of the passivation layer 120 does not exceed 10% of the thickness of the crystalline silicon bottom cell 110 along the first direction. When the thickness of the second portion 132 of the transparent conductive oxide layer 130 along the first direction is equal to the thickness of the passivation layer 120 along the first direction, it indicates that the crystalline silicon bottom cell 110 has not been grooved; when the thickness of the second portion 132 of the transparent conductive oxide layer 130 along the first direction is greater than the thickness of the passivation layer 120 along the first direction, it indicates that the crystalline silicon bottom cell 110 has also been grooved, and the groove depth of the crystalline silicon bottom cell 110 (the difference between the thickness of the second portion 132 along the first direction and the thickness of the passivation layer 120) does not exceed 10% of the thickness of the crystalline silicon bottom cell 110 along the first direction. As some specific examples, the groove depth of the crystalline silicon bottom cell 110 is 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, etc. of the thickness of the crystalline silicon bottom cell 110 along the first direction. Thus, the carriers are transported longitudinally.

[0079] Specifically, the thickness of the passivation layer 120 is not particularly limited, and those skilled in the art can select it according to actual needs. As some specific examples, the thickness of the passivation layer 120 is 60-90 nm, such as 60 nm, 70 nm, 80 nm, 90 nm, etc. The thickness of the transparent conductive oxide layer 130 is not particularly limited, and those skilled in the art can select it according to actual needs. As some specific examples, the thickness of the transparent conductive oxide layer 130 is 60-110 nm, such as 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, etc.

[0080] According to a specific embodiment of the present invention, the material of the passivation layer 120 is not limited to aluminum oxide (AlO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), Silicon Carbide (SiC x ).

[0081] According to a specific embodiment of the present invention, the material of the transparent conductive oxide layer 130 includes but is not limited to ITO, IWO, ICO and the like.

[0082] According to a specific embodiment of the present invention, the structure of the crystalline silicon bottom cell 110 is not particularly limited, and it can be a conventional crystalline silicon bottom cell, which can optionally include a p-poly layer 113, a first tunneling oxide layer 112, a silicon substrate 111, a second tunneling oxide layer 114, and an n-poly layer 115 stacked in sequence, wherein the n-poly layer 115 is disposed on the surface of the passivation layer 120 away from the transparent conductive oxide layer 130. Figure 2 .

[0083] Specifically, the doping type of the silicon substrate 111 includes N-type or P-type, and N-type can be selected. The thickness of the silicon substrate 111 is not particularly limited, and those skilled in the art can select it according to actual needs. As some specific examples, the thickness of the silicon substrate 111 is 80-180nm, such as 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, etc. Further, the silicon substrate 111 can be prepared as a double-sided suede structure, a double-sided polished surface structure, or one side is a polished surface and the other side is a suede structure.

[0084] Specifically, the materials of the first tunnel oxide layer 112 and the second tunnel oxide layer 114 may be the same or different, including but not limited to silicon dioxide.

[0085] Specifically, the p-poly layer 113 may be a boron-doped polysilicon layer. The surface concentration of the p-poly layer 113 is 1×10 19 ~2×10 21 cm -3 The thickness of the p-poly layer 113 is not particularly limited, and those skilled in the art may select the thickness according to actual needs. As some specific examples, the thickness of the p-poly layer 113 is 60-700 nm.

[0086] Specifically, the n-poly layer 115 may be a phosphorus-doped polysilicon layer. The thickness of the n-poly layer 115 is not particularly limited, and those skilled in the art may select it according to actual needs. As some specific examples, the thickness of the n-poly layer 115 is 60-150 nm, such as 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, etc.

[0087] According to a specific embodiment of the present invention, the structure of the antimony sulfide top cell 140 is not particularly limited, and it may be a conventional antimony sulfide cell, and may optionally include a hole transport layer 141, an antimony sulfide layer 142, and an electron transport layer 143 stacked in sequence along the first direction;

[0088] The hole transport layer 141 is disposed on a surface of the transparent conductive oxide layer 130 away from the passivation layer 120. Figure 3 .

[0089] According to a specific embodiment of the present invention, the stacked solar cell 100 satisfies at least one of the following conditions:

[0090] (A) the hole transport layer 141 includes at least one third portion 1411 and at least one fourth portion 1412, the fourth portion 1412 corresponds to the groove region one by one, and is disposed in the groove region in contact with the second portion 132 of the transparent conductive oxide layer, and the third portion 1411 and the fourth portion 1412 are arranged in a stepped manner along the second direction;

[0091] (B) the antimony sulfide layer 142 includes at least one fifth portion 1421 and at least one sixth portion 1422, the sixth portion 1422 corresponds to the grooved region one by one, and is disposed in the grooved region in contact with the fourth portion 1412 of the hole transport layer 141, and the fifth portion 1421 and the sixth portion 1422 are arranged in a stepped manner along the second direction;

[0092] (C) The electron transport layer 143 includes at least one seventh portion 1431 and at least one eighth portion 1432, the eighth portion 1432 corresponds to the grooved region one by one, and is arranged in the grooved region to contact the sixth portion 1422 of the antimony sulfide layer 142, and the seventh portion 1431 and the eighth portion 1432 are arranged in a stepped manner along the second direction.

[0093] According to a specific embodiment of the present invention, see Figure 3 , the stacked solar cell 100 further includes:

[0094] A composite layer 150, a positive metal electrode 160 and an anti-reflection layer 170 are sequentially stacked along the first direction;

[0095] The composite layer 150 is disposed on a surface of the antimony sulfide top cell 140 away from the transparent conductive oxide layer 130. According to a specific embodiment of the present invention, the tandem solar cell 100 satisfies at least one of the following conditions:

[0096] (A) the composite layer 150 includes at least one ninth portion 151 and at least one tenth portion 152, the tenth portion 152 corresponds to the grooved region one by one, and is disposed in the grooved region in contact with the eighth portion 1432 of the electron transport layer 143, and the ninth portion 151 and the tenth portion 152 are arranged in a stepped manner along the second direction;

[0097] (B) The positive metal electrode 160 corresponds to the groove area and is disposed in the groove area to contact the tenth portion 152 of the composite layer 150 .

[0098] Specifically, the material of the hole transport layer 141 includes but is not limited to NiO x , PEDOT, PTAA. The thickness is not particularly limited, and those skilled in the art can select it according to actual needs. Along the first direction, the thickness difference between the hole transport layer 141 and the transparent conductive oxide layer 130 does not exceed 10%, that is, the thickness of the hole transport layer 141 can be greater than, equal to or less than the transparent conductive oxide layer 130, but the thickness difference between the two does not exceed 10%.

[0099] Specifically, the thickness of the antimony sulfide layer 142 is not particularly limited, and those skilled in the art can select it according to actual needs. Along the first direction, the thickness difference between the antimony sulfide layer 142 and the hole transport layer 141 does not exceed 10%, that is, the thickness of the antimony sulfide layer 142 can be greater than, equal to or less than the hole transport layer 141, but the thickness difference between the two does not exceed 10%.

[0100] Specifically, the material of the electron transport layer 143 includes but is not limited to C60, SnO xThe thickness is not particularly limited, and those skilled in the art can select it according to actual needs. Along the first direction, the difference in thickness between the electron transport layer 143 and the antimony sulfide layer 142 does not exceed 10%, that is, the thickness of the electron transport layer 143 can be greater than, equal to, or less than the antimony sulfide layer 142, but the difference in thickness between the two does not exceed 10%.

[0101] Specifically, the material of the composite layer 150 includes but is not limited to ITO, IWO, and ICO. The thickness thereof is not particularly limited, and those skilled in the art may select it according to actual needs. Along the first direction, the thickness difference between the composite layer 150 and the electron transport layer 143 does not exceed 10%. That is, the thickness of the composite layer 150 may be greater than, equal to, or less than the electron transport layer 143, but the thickness difference between the two does not exceed 10%.

[0102] Specifically, the material of the positive metal electrode 160 is not particularly limited, and those skilled in the art may select the material according to actual needs.

[0103] Specifically, the material of the anti-reflection layer 170 may be magnesium fluoride. The thickness thereof is not particularly limited, and those skilled in the art may select it according to actual needs. As some specific examples, the thickness of the anti-reflection layer 170 is 5-20 nm, such as 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, etc.

[0104] According to a specific embodiment of the present invention, the stacked solar cell 100 further includes: a back passivation layer 180 and a back metal electrode 190 sequentially stacked along the first direction. Figure 4 .

[0105] Specifically, the back passivation layer 180 is disposed on the surface of the p-poly layer 113 away from the first tunneling oxide layer 112. The material of the back passivation layer 180 can be the same as or different from that of the passivation layer 120, and can be selected from at least one of AlOx, SiNx, SiOxNy, SiOx, and SiCx. Its thickness is not particularly limited, and those skilled in the art can select it according to actual needs. As some specific examples, the thickness of the back passivation layer 180 is 60-90nm, such as 60nm, 70nm, 80nm, 90nm, etc.

[0106] Specifically, the material of the back metal electrode 190 is not particularly limited, and those skilled in the art may select the material according to actual needs.

[0107] According to an embodiment of the present invention, a second aspect of the present invention provides a method for preparing the stacked solar cell according to the first aspect. The preparation method comprises:

[0108] Prepare a crystalline silicon bottom cell 110;

[0109] Depositing a passivation layer 120 on a surface of the crystalline silicon bottom cell 110 along a first direction, and performing a groove process on the passivation layer 120 to form at least one groove region arranged along a second direction;

[0110] Depositing a transparent conductive oxide layer 130 on a surface of the passivation layer 120 away from the crystalline silicon bottom cell 110 to form a first portion 131 in contact with the passivation layer 120 and a second portion 132 in contact with the crystalline silicon bottom cell 110;

[0111] An antimony sulfide top cell 140 is prepared on the surface of the transparent conductive oxide layer 130 away from the crystalline silicon bottom cell 110 .

[0112] According to a specific embodiment of the present invention, the preparation of the crystalline silicon bottom cell 110 includes:

[0113] Providing a silicon substrate 111, and forming a first tunneling oxide layer 112 and a second tunneling oxide layer 114 on a pair of opposite surfaces of the silicon substrate 111 respectively;

[0114] Depositing a p-poly layer 113 on a surface of the first tunnel oxide layer 112 away from the silicon substrate 111;

[0115] An n-poly layer 115 is deposited on a surface of the second tunneling oxide layer 114 away from the silicon substrate 111 ; the n-poly layer 115 is in contact with the passivation layer 120 .

[0116] According to a specific embodiment of the present invention, the silicon substrate 111 may be pre-cleaned, textured or polished, and then the surface of the silicon wafer may be cleaned with concentrated sulfuric acid, ammonia water or hydrochloric acid.

[0117] According to a specific embodiment of the present invention, the first tunnel oxide layer 112 and the second tunnel oxide layer 114 may be formed by tubular low-pressure chemical vapor deposition. When the first tunnel oxide layer 112 and the second tunnel oxide layer 114 are made of the same material, they may be prepared on both sides of the silicon substrate at the same time.

[0118] According to a specific embodiment of the present invention, the p-poly layer 113 may be deposited by first depositing an intrinsic amorphous silicon layer on the surface of the first tunnel oxide layer 112 away from the silicon substrate 111 , and then performing boron diffusion and high-temperature crystallization to obtain the p-poly layer 113 .

[0119] Specifically, the boron diffusion treatment can be performed by placing the silicon wafer after depositing the intrinsic amorphous silicon layer into a tubular diffusion furnace, performing boron doping at high temperature, and then increasing the temperature to achieve crystallization, thereby forming the p-poly layer 113 .

[0120] According to a specific embodiment of the present invention, after the p-poly layer 113 is deposited on the surface of the first tunneling oxide layer 112 away from the silicon substrate 111 , the p-poly layer plated around the surface of the second tunneling oxide layer 114 away from the silicon substrate 111 is removed.

[0121] Specifically, the p-poly layer plated on the other side can be removed by cleaning and etching. Hydrofluoric acid can be used for cleaning, and then a tank cleaning machine can be used to remove the p-poly plated on the front side, or a chain-type single-sided p-poly can be used. At the same time, since the back side is protected by BSG, it will not be removed.

[0122] According to a specific embodiment of the present invention, the n-poly layer 115 may be formed by in-situ doping or two-step deposition using a low pressure chemical vapor deposition method.

[0123] According to a specific embodiment of the present invention, after the n-poly layer 115 is deposited on the surface of the second tunneling oxide layer 114 away from the silicon substrate 111, the n-poly layer, BSG layer and PSG layer plated around the surface of the p-poly layer 113 away from the silicon substrate 111 are removed.

[0124] Specifically, after the n-poly layer 115 is formed, the back oxide layer of the silicon wafer may be removed on one side in a chain manner, and the n-poly layer plated on the back side may be cleaned and etched to remove the layer.

[0125] Specifically, the BSG layer and the PSG layer are removed by performing bath hydrofluoric acid cleaning after removing the plated n-poly layer to remove the front and back oxide layers, and then using concentrated hydrochloric acid cleaning to remove surface impurities.

[0126] According to a specific embodiment of the present invention, when the stacked solar cell includes a back passivation layer, the deposition of the passivation layer and the back passivation layer may be performed after the deposition of the n-poly layer.

[0127] Specifically, the passivation layer and the back passivation layer can be prepared by methods such as tubular plasma enhanced chemical vapor deposition, and then chain high-temperature sintering is performed to passivate the p-poly interface and the crystalline silicon body.

[0128] According to a specific embodiment of the present invention, the method of slotting the passivation layer 120 is not particularly limited, and laser slotting or other methods can be selected, and the slotting is specifically performed by picosecond or nanosecond. The shape of the pattern is not particularly limited, and those skilled in the art can select it according to actual needs, and it can be similar to a normal gate line pattern. The slot width is not particularly limited, and those skilled in the art can select it according to actual needs. As some specific examples, the slot width is 20-60μm, such as 20μm, 30μm, 40μm, 50μm, 60μm, etc.

[0129] According to a specific embodiment of the present invention, the transparent conductive oxide layer 130 may be deposited by physical vapor deposition or the like.

[0130] According to a specific embodiment of the present invention, the preparation of the antimony sulfide top cell 140 includes sequentially preparing a hole transport layer 141, an antimony sulfide layer 142, and an electron transport layer 143 after depositing the transparent conductive oxide layer 130. The hole transport layer 141 and the antimony sulfide layer 142 can be prepared by a solution method, and the electron transport layer 143 can be prepared by a solution method, ALD (atomic layer deposition) or RPD (reactive plasma deposition) and the like.

[0131] According to a specific embodiment of the present invention, after the antimony sulfide top cell 140 is formed, a positive metal electrode 160 and a back metal electrode 190 may be deposited on the front side and the back side of the silicon wafer, respectively.

[0132] Specifically, low-temperature silver paste can be used for screen printing on the front and back sides of silicon wafers. The gate line width is not particularly limited, and those skilled in the art can select it according to actual needs.

[0133] According to a specific embodiment of the present invention, the preparation method may further deposit an anti-reflection layer 170 on the surface of the composite layer 150 away from the electron transport layer 143 .

[0134] The scheme of the present invention will be explained below in conjunction with the embodiments. It will be appreciated by those skilled in the art that the following embodiments are only used to illustrate the present invention and should not be considered as limiting the scope of the present invention. Where specific techniques or conditions are not indicated in the embodiments, the techniques or conditions described in the literature in this area or the product specifications are used. The reagents or instruments used are not indicated by the manufacturer and are all conventional products that can be obtained commercially.

[0135] Example 1

[0136] A method for preparing a stacked solar cell comprises the following steps:

[0137] (1) Select an N-type silicon substrate, pre-clean and texturize the surface of the silicon wafer, and then clean the surface of the silicon wafer with concentrated sulfuric acid, ammonia water, and hydrochloric acid;

[0138] (2) Using a tubular low-pressure chemical vapor deposition method, a 1.5 nm thick tunnel oxide layer SiO2 is first deposited on the back side at about 600°C, followed by a 300 nm thick intrinsic amorphous silicon layer;

[0139] (3) placing the silicon wafer obtained in step (2) into a tubular diffusion furnace, performing boron doping at 890° C., and raising the temperature to 950° C. for advancement and high-temperature crystallization to form a p-poly layer;

[0140] (4) The silicon wafer obtained in step (3) is post-cleaned to remove the front oxide layer, and then a tank cleaning machine is used to remove the p-poly plated on the front side. Since the back side is protected by BSG, it will not be removed;

[0141] (5) After the silicon wafer obtained in step (4) is cleaned again, a front n-poly layer is deposited and in-situ doped using low-pressure chemical vapor deposition to a thickness of about 60 nm;

[0142] (6) performing chain single-sided removal of the back oxide layer, followed by single-sided removal of n-poly;

[0143] (7) Perform tank-type hydrofluoric acid cleaning to remove the front and back oxide layers, and then perform concentrated hydrochloric acid cleaning to remove surface impurities;

[0144] (8) using a tubular plasma enhanced chemical vapor deposition method to deposit AlOx and SiNx films on the front side with a thickness of about 60 nm; and depositing SiNx on the back side with a thickness of about 60 nm;

[0145] (9) Chain sintering at 750 °C to activate H ions in SiNx and passivate the p-poly interface and the crystalline silicon body;

[0146] (10) Directly depositing a conventional antimony sulfide cell, which includes a hole transport layer, an antimony sulfide layer, and an electron transport layer, each layer having a thickness of 60 nm;

[0147] (11) Use low-temperature silver paste for screen printing on the front and back sides, with a grid line width of 26 μm;

[0148] (12) A layer of anti-reflection layer MgF2 is deposited on the front side.

[0149] Example 2

[0150] A method for preparing a stacked solar cell comprises the following steps:

[0151] (1) Select an N-type silicon substrate, pre-clean and texturize the surface of the silicon wafer, and then clean the surface of the silicon wafer with concentrated sulfuric acid, ammonia water, and hydrochloric acid;

[0152] (2) Using a tubular low-pressure chemical vapor deposition method, a 1.5 nm thick tunnel oxide layer SiO2 is first deposited on the back side at about 600°C, followed by a 300 nm thick intrinsic amorphous silicon layer;

[0153] (3) placing the silicon wafer obtained in step (2) into a tubular diffusion furnace, performing boron doping at 890° C., and raising the temperature to 950° C. for advancement and high-temperature crystallization to form a p-poly layer;

[0154] (4) The silicon wafer obtained in step (3) is post-cleaned to remove the front oxide layer, and then a tank cleaning machine is used to remove the p-poly plated on the front side. Since the back side is protected by BSG, it will not be removed;

[0155] (5) After the silicon wafer obtained in step (4) is cleaned again, a front n-poly layer is deposited and in-situ doped using low-pressure chemical vapor deposition to a thickness of about 60 nm;

[0156] (6) performing chain single-sided removal of the back oxide layer, followed by single-sided removal of n-poly;

[0157] (7) Perform tank-type hydrofluoric acid cleaning to remove the front and back oxide layers, and then perform concentrated hydrochloric acid cleaning to remove surface impurities;

[0158] (8) using a tubular plasma enhanced chemical vapor deposition method to deposit AlOx and SiNx films on the front side with a thickness of about 60 nm; and depositing SiNx on the back side with a thickness of about 60 nm;

[0159] (9) Chain sintering at 750 °C to activate H ions in SiNx and passivate the p-poly interface and the crystalline silicon body;

[0160] (10) Using ultraviolet nanosecond laser to laser groove AlOx and SiNx, the groove width is 60 μm, similar to the normal grid line pattern;

[0161] (11) ITO coating is performed by PVD method. At this time, ITO can directly contact the bottom n-poly to enable carriers to be transported vertically. The thickness of ITO is 60nm;

[0162] (12) preparing a hole transport layer, an antimony sulfide layer, and an electron transport layer in sequence by a solution method, each layer having a thickness of 60 nm;

[0163] (13) Use low-temperature silver paste for screen printing on the front and back sides, with a grid line width of 26 μm;

[0164] (14) A layer of anti-reflection layer MgF2 is deposited on the front side.

[0165] Comparative Example 1

[0166] A method for preparing a stacked solar cell comprises the following steps:

[0167] (1) Select an N-type silicon substrate, pre-clean and texturize the surface of the silicon wafer, and then clean the surface of the silicon wafer with concentrated sulfuric acid, ammonia water, and hydrochloric acid;

[0168] (2) Using a tubular low-pressure chemical vapor deposition method, a 1.5 nm thick tunnel oxide layer SiO2 is first deposited on the back side at about 600°C, followed by a 300 nm thick intrinsic amorphous silicon layer;

[0169] (3) placing the silicon wafer obtained in step (2) into a tubular diffusion furnace, performing boron doping at 890° C., and raising the temperature to 950° C. for advancement and high-temperature crystallization to form a p-poly layer;

[0170] (4) The silicon wafer obtained in step (3) is post-cleaned to remove the front oxide layer, and then a tank cleaning machine is used to remove the p-poly plated on the front side. Since the back side is protected by BSG, it will not be removed;

[0171] (5) After the silicon wafer obtained in step (4) is cleaned again, a front n-poly layer is deposited and in-situ doped using low-pressure chemical vapor deposition to a thickness of about 60 nm;

[0172] (6) performing chain single-sided removal of the back oxide layer, followed by single-sided removal of n-poly;

[0173] (7) Perform tank-type hydrofluoric acid cleaning to remove the front and back oxide layers, and then perform concentrated hydrochloric acid cleaning to remove surface impurities;

[0174] (8) using a tubular plasma enhanced chemical vapor deposition method to deposit AlOx and SiNx films on the front side with a thickness of about 60 nm; and depositing SiNx on the back side with a thickness of about 60 nm;

[0175] (9) Chain sintering at 750 °C to activate H ions in SiNx and passivate the p-poly interface and the crystalline silicon body;

[0176] (10) ITO coating is performed by PVD method, and the thickness of ITO is 60 nm;

[0177] (11) preparing a hole transport layer, an antimony sulfide layer, and an electron transport layer in sequence by a solution method, each layer having a thickness of 60 nm;

[0178] (12) Use low-temperature silver paste for screen printing on the front and back sides, with a grid line width of 26 μm;

[0179] (13) A layer of anti-reflection layer MgF2 is deposited on the front side.

[0180] Test Case

[0181] The stacked solar cells prepared in Examples 1-2 and Comparative Example 1 were subjected to performance tests. A steady-state IV tester was used to make the stacked solar cells stably operate at the maximum power point. The electrical performance data at this time were tested. The results are shown in Table 1.

[0182] Table 1

[0183] Voc(V) <![CDATA[Jsc(mA / cm 2 )]]> FF(%) Eff(%) Example 1 2.01 19.8 79 31.44 Example 2 1.99 19.7 79.2 31.05 Comparative Example 1 1.91 18.5 78 27.56

[0184] The results show that compared with conventional stacked solar cells without grooving, the stacked solar cells prepared by the present invention have higher conversion efficiency. At the same time, compared with the prior art, there is no need to add metal nanoarray particles in the passivation layer, which simplifies the preparation process of the stacked solar cells. It can also make full use of the existing crystalline silicon cell production equipment without replacing or adding production equipment, which is conducive to the mass production of stacked solar cells.

[0185] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0186] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A stacked solar cell, characterized in that: include: A crystalline silicon bottom cell, a passivation layer, a transparent conductive oxide layer and an antimony sulfide top cell are sequentially stacked along a first direction; The passivation layer includes at least one grooved region arranged along a second direction, wherein the second direction is perpendicular to the first direction; The transparent conductive oxide layer includes at least one first portion and at least one second portion, the second portion corresponds to the groove area one by one, and is arranged in the groove area to contact the crystalline silicon bottom cell, and the first portion and the second portion are arranged in a stepped manner along the second direction; Wherein, the first direction is the thickness direction of the crystalline silicon bottom cell.

2. The tandem solar cell according to claim 1, characterized in that: A thickness of the second portion of the transparent conductive oxide layer along the first direction is greater than or equal to a thickness of the passivation layer along the first direction.

3. The tandem solar cell according to claim 1, characterized in that: The difference between the thickness of the second portion along the first direction and the thickness of the passivation layer does not exceed 10% of the thickness of the crystalline silicon bottom cell along the first direction.

4. The tandem solar cell according to claim 1, characterized in that: The material of the passivation layer includes at least one of aluminum oxide, silicon nitride, silicon oxynitride, silicon oxide, and silicon carbide.

5. The tandem solar cell according to claim 1, characterized in that: The crystalline silicon bottom cell comprises a p-poly layer, a first tunneling oxide layer, a silicon substrate, a second tunneling oxide layer, and an n-poly layer which are sequentially stacked along the first direction; The n-poly layer is disposed on a surface of the passivation layer away from the transparent conductive oxide layer; and / or, the surface concentration of the p-poly layer is 1×10 19 ~2×10 21 cm -3 .

6. The tandem solar cell according to claim 1, characterized in that: The antimony sulfide top cell comprises a hole transport layer, an antimony sulfide layer, and an electron transport layer stacked in sequence along the first direction; The hole transport layer is disposed on a surface of the transparent conductive oxide layer away from the passivation layer; And / or, the stacked solar cell satisfies at least one of the following conditions: (A) the hole transport layer includes at least one third portion and at least one fourth portion, the fourth portion corresponds to the groove region one by one, and is disposed in the groove region in contact with the second portion of the transparent conductive oxide layer, and the third portion and the fourth portion are arranged in a stepped manner along the second direction; (B) the antimony sulfide layer includes at least one fifth portion and at least one sixth portion, the sixth portion corresponds to the grooved region one by one, and is arranged in the grooved region in contact with the fourth portion of the hole transport layer, and the fifth portion and the sixth portion are arranged in a stepped manner along the second direction; (C) The electron transport layer includes at least one seventh portion and at least one eighth portion, the eighth portion corresponds to the grooved region one by one, and is arranged in the grooved region to contact the sixth portion of the antimony sulfide layer, and the seventh portion and the eighth portion are arranged in a stepped manner along the second direction.

7. The tandem solar cell according to claim 1, characterized in that: The stacked solar cell further comprises: A composite layer, a positive metal electrode and an anti-reflection layer are sequentially stacked along the first direction; The composite layer is disposed on a surface of the antimony sulfide top cell away from the transparent conductive oxide layer; And / or, the stacked solar cell satisfies at least one of the following conditions: (A) the composite layer includes at least one ninth portion and at least one tenth portion, the tenth portion corresponds to the grooved region one by one, and is arranged in the grooved region in contact with the eighth portion of the electron transport layer, and the ninth portion and the tenth portion are arranged in a stepped manner along the second direction; (B) The positive metal electrode corresponds to the grooved region and is disposed in the grooved region in contact with the tenth portion of the composite layer.

8. The tandem solar cell according to claim 6 or 7, characterized in that: The stacked solar cell satisfies at least one of the following conditions: (A) the material of the composite layer includes at least one of ITO, IWO, and ICO; (B) The material of the hole transport layer includes NiO x , PEDOT, PTAA; (C) The material of the electron transport layer includes C60, SnO x At least one of; And / or, the stacked solar cell satisfies at least one of the following conditions: Along the first direction, the difference in thickness between the hole transport layer and the transparent conductive oxide layer does not exceed 10%; The difference in thickness between the antimony sulfide layer and the hole transport layer does not exceed 10%; The difference in thickness between the electron transport layer and the antimony sulfide layer does not exceed 10%; The thickness difference between the composite layer and the electron transport layer does not exceed 10%.

9. The tandem solar cell according to claim 1, characterized in that: The stacked solar cell further comprises: a back passivation layer and a back metal electrode sequentially stacked along the first direction; The back passivation layer is arranged on the surface of the crystalline silicon bottom cell away from the passivation layer; And / or, the material of the back passivation layer includes at least one of aluminum oxide, silicon nitride, silicon oxynitride, silicon oxide, and silicon carbide.

10. A method for preparing a stacked solar cell according to any one of claims 1 to 9, characterized in that: include: Preparation of crystalline silicon bottom cells; Depositing a passivation layer on a surface of the crystalline silicon bottom cell along a first direction, and performing a groove process on the passivation layer to form at least one groove region arranged along a second direction; Depositing a transparent conductive oxide layer on a surface of the passivation layer away from the crystalline silicon bottom cell to form a first portion in contact with the passivation layer and a second portion in contact with the crystalline silicon bottom cell; An antimony sulfide top cell is prepared on the surface of the transparent conductive oxide layer away from the crystalline silicon bottom cell.

11. The preparation method according to claim 10, characterized in that: The preparation of the crystalline silicon bottom cell includes: Providing a silicon substrate, and forming a first tunneling oxide layer and a second tunneling oxide layer on a pair of opposite surfaces of the silicon substrate, respectively; Depositing a p-poly layer on a surface of the first tunnel oxide layer away from the silicon substrate; Depositing an n-poly layer on a surface of the second tunnel oxide layer away from the silicon substrate; the passivation layer is in contact with the n-poly layer; and / or, after depositing a p-poly layer on the surface of the first tunneling oxide layer away from the silicon substrate, removing the p-poly layer deposited around the surface of the second tunneling oxide layer away from the silicon substrate; After depositing an n-poly layer on the surface of the second tunnel oxide layer away from the silicon substrate, removing the n-poly layer, the BSG layer and the PSG layer deposited around the surface of the p-poly layer away from the silicon substrate; and / or, depositing a back passivation layer and a back metal electrode in sequence on a surface of the crystalline silicon bottom cell away from the passivation layer; A composite layer, a positive metal electrode and an anti-reflection layer are sequentially deposited on the surface of the antimony sulfide top cell away from the transparent conductive oxide layer.

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