Single-Photon Avalanche Diode and Its Manufacturing Method, Single-Photon Detector

Abstract

The present invention discloses a single-photon avalanche diode, a manufacturing method thereof, and a single-photon detector, relating to the technical field of optical detection. The single-photon avalanche diode includes a silicon layer and a logic wafer. The silicon layer is etched to form a filling region, and the filling region is filled with silicon dioxide. An avalanche region and a PN junction are provided in the silicon layer. The logic wafer is disposed at the bottom of the silicon layer, and the logic wafer is bonded to the silicon layer. The PN junction is disposed close to the logic wafer, and the avalanche region is disposed between the PN junction and the filling region. By filling the filling region with silicon dioxide that does not have the ability to absorb near-ultraviolet light, when near-ultraviolet light passes through the silicon dioxide and enters the silicon layer, electron-hole pairs are generated by the absorption of the silicon layer. At this time, the distance between the electron-hole pairs and the avalanche region is greatly reduced, so that the number of electron-hole pair recombinations occurring during the migration of multiple electron-hole pairs is reduced, thereby improving the detection efficiency of the entire single-photon avalanche diode.

Description

Technical Field

[0001] The present invention relates to the technical field of optical detection, and particularly relates to a single-photon avalanche diode, a manufacturing method thereof, and a single-photon detector. Background Art

[0002] A single-photon avalanche diode is a photodetector avalanche diode with weak light detection ability. Due to its advantages such as high gain, fast response, and high sensitivity, it is widely used in fields such as Raman spectroscopy, positron emission tomography, and fluorescence lifetime imaging. The working principle of the single-photon avalanche diode for detecting trace photons is as follows: A reverse bias voltage greater than the avalanche breakdown voltage is applied across the single-photon avalanche diode. When photons are incident, valence band electrons absorb the photons and jump to the conduction band, generating electron-hole pairs. The photo-generated electron-hole pairs are accelerated under the action of the applied electric field and obtain sufficient energy. After colliding with the lattice, new electron-hole pairs can be formed. As the new electrons and holes continuously repeat the process of accelerating and colliding with the lattice, the electron-hole pairs increase exponentially, and an avalanche multiplication effect occurs. At this time, the number of carriers in the single-photon avalanche diode increases rapidly, the current increases sharply, and the detection efficiency of the instrument is greatly improved.

[0003] The single-photon avalanche diode has deficiencies in ultraviolet detection. After near-ultraviolet light is absorbed by silicon, the generated electron-hole pairs need to migrate to the avalanche region, and electron-hole pair recombination will occur during the migration process, which will lead to a decrease in detection efficiency.

[0004] Therefore, it is necessary to provide a single-photon avalanche diode, a manufacturing method thereof, and a single-photon detector to solve the above technical problems. Summary of the Invention

[0005] The main object of the present invention is to propose a single-photon avalanche diode, a manufacturing method thereof, and a single-photon detector, aiming to solve the technical problem of the low detection efficiency of the single-photon avalanche diode in the prior art.

[0006] To achieve the above object, according to one aspect of the present invention, the present invention proposes a single-photon avalanche diode, including:

[0007] A silicon layer, a filling area is etched in the silicon layer, silicon dioxide is filled in the filling area, and an avalanche region and a PN junction are provided in the silicon layer;

[0008] A logic wafer, the logic wafer is disposed at the bottom of the silicon layer, and the logic wafer is bonded to the silicon layer, the PN junction is disposed close to the logic wafer, and the avalanche region is disposed between the PN junction and the filling area.

[0009] In one embodiment, a light-trapping structure is formed in the silicon layer, and the light-trapping structure is disposed at the bottom of the filling area.

[0010] In one embodiment, the number of the light trapping structures is plural, and the plural light trapping structures are arranged in an array along the length direction and the width direction of the filling region.

[0011] In one embodiment, the light trapping structure is a conical structure with a pointed head facing the avalanche region.

[0012] In one embodiment, an opening is formed at the top of the silicon layer, and the opening communicates with the filling region.

[0013] In one embodiment, the single-photon avalanche diode further includes a microlens, the microlens is disposed on the top of the silicon layer, the microlens covers the opening, and the microlens is configured to pass incident light through the opening and focus the light to the filling region.

[0014] In one embodiment, a groove is formed on the outer periphery of the silicon layer, the single-photon avalanche diode further includes an isolation layer, the isolation layer is disposed in the groove, and the top and the bottom of the isolation layer are respectively in contact with the microlens and the logic wafer.

[0015] In one embodiment, the single-photon avalanche diode further includes a guard ring, the guard ring surrounds the outer periphery of the avalanche region, the silicon layer is one of P-type and N-type, and the guard ring is the other of P-type and N-type.

[0016] In one embodiment, the filling region is a cylindrical filling region or a cubic filling region.

[0017] According to another aspect of the present invention, the present invention further provides a method for manufacturing a single-photon avalanche diode, the method for manufacturing the single-photon avalanche diode is applied to the single-photon avalanche diode as described above, and the method for manufacturing the single-photon avalanche diode includes the following steps:

[0018] Provide the silicon layer and the logic wafer, implant doping ions in the silicon layer to form the avalanche region and the PN junction, and bond the silicon layer to the logic wafer;

[0019] Grind the side of the silicon layer facing away from the logic wafer to thin the silicon layer;

[0020] Etch the filling region in the silicon layer, and etch a light trapping structure at the bottom of the filling region, fill the filling region with the silicon dioxide, and planarize the surface of the silicon dioxide;

[0021] Etch a groove on the outer periphery of the silicon layer, and fill an isolation layer in the groove;

[0022] Process a microlens on the top of the silicon layer.

[0023] According to another aspect of the present invention, the present invention further provides a single-photon detector, including the single-photon avalanche diode described above.

[0024] In the above solution, the single-photon avalanche diode includes a silicon layer and a logic wafer. The silicon layer is etched to form a filling area filled with silicon dioxide, and an avalanche area and a PN junction are provided in the silicon layer. The logic wafer is disposed at the bottom of the silicon layer and is bonded to the silicon layer. The PN junction is disposed close to the logic wafer, and the avalanche area is disposed between the PN junction and the filling area. Specifically, a silicon substrate is first prepared as the silicon bottom, and then doping ions are implanted into the silicon bottom to form a PN junction and an avalanche area. If the silicon bottom is one of P-type and N-type, the avalanche area will be the other of P-type and N-type. Then, the logic wafer is bonded to the silicon layer, and a filling area is processed on the layer of the silicon layer facing away from the logic wafer, and the filling area is filled with silicon dioxide, thus completing the fabrication of the single-photon avalanche diode. When detecting, incident light of near-ultraviolet light enters the silicon dioxide. Since silicon dioxide has no obvious absorption effect on near-ultraviolet light, silicon dioxide can effectively transmit the near-ultraviolet light into the silicon layer. The incident light is absorbed in the silicon layer to generate electron-hole pairs. These electron-hole pair carriers will migrate in the silicon layer to the avalanche area. The avalanche area is a highly doped area and usually has a relatively high electric field strength. When the electron-hole pairs enter the avalanche area, they will be accelerated and hit other atoms to generate more electron-hole pairs, thereby triggering an avalanche effect, that is, an initial small current is rapidly amplified into a large current, thus generating a current signal. Since a PN junction is provided between the avalanche area and the logic wafer, the PN junction plays a role of isolation and control to ensure that the avalanche process does not affect the normal operation of the logic wafer. The logic wafer acquires the current signal generated by the avalanche effect, is responsible for processing these current signals, and outputs an electrical signal, and then realizes spectral detection through the electrical signal. In the present invention, a filling area is processed in the silicon layer, and the filling area is filled with silicon dioxide that does not have the ability to absorb near-ultraviolet light. In this way, after the near-ultraviolet light passes through the silicon dioxide and enters the silicon layer, it is absorbed by the silicon layer to generate electron-hole pairs. At this time, the distance between the electron-hole pairs and the avalanche area is greatly reduced, so that the number of electron-hole pair recombinations occurring during the migration of multiple electron-hole pairs will be reduced, improving the number of effective carriers reaching the avalanche area, thereby improving the detection efficiency of the entire single-photon avalanche diode. Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0026] Figure 1 Schematic diagram of the structure of the first embodiment of the single-photon avalanche diode provided by the present invention;

[0027] Figure 2 Schematic diagram of the structure of the second embodiment of the single-photon avalanche diode provided by the present invention;

[0028] Figure 3 Schematic diagram of the structure of the third embodiment of the single-photon avalanche diode provided by the present invention;

[0029] Figure 4 Schematic diagram of the structure of the fourth embodiment of the single-photon avalanche diode provided by the present invention;

[0030] Figure 5 Flow chart of the manufacturing method of the single-photon avalanche diode according to the first embodiment of the present invention.

[0031] Explanation of the reference numerals in the drawings:

[0032] 100, single-photon avalanche diode; 1, silicon layer; 2, logic wafer; 11, filling area; 12, avalanche area; 13, PN junction; 14, light trapping structure; 15, opening; 16, microlens; 17, trench; 3, isolation layer.

[0033] The realization, functional features and advantages of the object of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0034] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0035] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present invention, the directional indications are only used to explain the relative positional relationship and movement conditions between components in a specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0036] In addition, if the embodiments of the present invention involve descriptions such as "first" and "second", the descriptions of "first", "second", etc. are for descriptive purposes only, and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, if "and / or" or "and / or" appears throughout the text, its meaning includes three parallel scenarios. Taking "A and / or B" as an example, it includes scenario A, or scenario B, or the scenario where both A and B are satisfied simultaneously. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0037] A single-photon avalanche diode is a type of avalanche photodetector with weak light detection capabilities. Due to its advantages such as high gain, fast response, and high sensitivity, it is widely used in fields such as Raman spectroscopy, positron emission tomography, and fluorescence lifetime imaging. The working principle of a single-photon avalanche diode for detecting trace photons is as follows: A reverse bias voltage greater than the avalanche breakdown voltage is applied across the single-photon avalanche diode. When photons are incident, valence band electrons absorb the photons and jump to the conduction band, generating electron-hole pairs. The photo-generated electron-hole pairs are accelerated under the action of the applied electric field and obtain sufficient energy. After colliding with the lattice, new electron-hole pairs can be formed. As the new electrons and holes continuously repeat the process of accelerating and colliding with the lattice, the electron-hole pairs multiply, and an avalanche multiplication effect occurs. At this time, the number of carriers in the single-photon avalanche diode increases rapidly, the current increases sharply, and the detection efficiency of the instrument is greatly improved.

[0038] The single-photon avalanche diode has deficiencies in ultraviolet detection. After near-ultraviolet light is absorbed by silicon, the generated electron-hole pairs need to migrate to the avalanche region, and electron-hole pair recombination will occur during the migration process, which will lead to a decrease in detection efficiency.

[0039] Please refer to Figure 1, the single-photon avalanche diode 100 includes a silicon layer 1 and a logic wafer 2. The silicon layer 1 is etched to form a filling area 11 filled with silicon dioxide. An avalanche area 12 and a PN junction 13 are provided in the silicon layer 1. The logic wafer 2 is disposed at the bottom of the silicon layer 1 and is bonded to the silicon layer 1. The PN junction 13 is disposed close to the logic wafer 2, and the avalanche area 12 is disposed between the PN junction 13 and the filling area 11. Specifically, a silicon substrate is prepared as the silicon bottom first, and then doping ions are implanted into the silicon bottom to form the PN junction 13 and the avalanche area 12. If the silicon bottom is one of P-type and N-type, then the avalanche area 12 is the other of P-type and N-type. Then, the logic wafer 2 and the silicon layer 1 are bonded to each other. A filling area 11 is processed on the layer of the silicon layer 1 facing away from the logic wafer 2, and the filling area 11 is filled with silicon dioxide, thus completing the fabrication of the single-photon avalanche diode 100. When detecting, incident light of near-ultraviolet light enters the silicon dioxide. Since the silicon dioxide has no obvious absorption effect on the near-ultraviolet light, the silicon dioxide can effectively transmit the near-ultraviolet light into the silicon layer 1. The incident light is absorbed in the silicon layer 1 to generate electron-hole pairs. These electron-hole pair carriers will migrate in the silicon layer 1 to the avalanche area 12. The avalanche area 12 is a highly doped area and usually has a relatively high electric field strength. When the electron-hole pairs enter the avalanche area 12, they will be accelerated and collide with other atoms to generate more electron-hole pairs, thus triggering an avalanche effect, that is, an initial small current is rapidly amplified into a large current, thereby generating a current signal. Since the PN junction 13 is provided between the avalanche area 12 and the logic wafer 2, the PN junction 13 plays a role of isolation and control to ensure that the avalanche process will not affect the normal operation of the logic wafer 2. The logic wafer 2 acquires the current signal generated by the avalanche effect, is responsible for processing these current signals, and outputs an electrical signal, and then realizes spectral detection through the electrical signal. In this embodiment, the filling area 11 is processed in the silicon layer 1, and the filling area 11 is filled with silicon dioxide that does not have the ability to absorb near-ultraviolet light. This enables the near-ultraviolet light to pass through the silicon dioxide and enter the silicon layer 1 and be absorbed by the silicon layer 1 to generate electron-hole pairs. At this time, the distance between the electron-hole pairs and the avalanche area 12 is greatly reduced. In this way, the number of electron-hole pair recombinations occurring during the migration of multiple electron-hole pairs will be reduced, improving the number of effective carriers reaching the avalanche area 12, thereby improving the detection efficiency of the entire single-photon avalanche diode 100.

[0040] Please refer to Figures 2 to 4, in one embodiment, a light trapping structure 14 is formed in the silicon layer 1, and the light trapping structure 14 is disposed at the bottom of the filling region 11. Specifically, the light trapping structure 14 is etched at the bottom of the filling region 11; when detecting, the incident light of near ultraviolet light enters the silicon dioxide. Since the silicon dioxide has no obvious absorption effect on the near ultraviolet light, the silicon dioxide can effectively transmit the near ultraviolet light to the silicon layer 1. The incident light enters the silicon layer 1 from the light trapping structure 14. The light trapping structure 14 reduces the reflectivity of the incident light and increases the optical path of the incident light in the silicon layer 1, so that the absorption rate of the silicon layer 1 for the incident light can be improved, promoting the generation of electron-hole pairs. These electron-hole pair carriers will migrate to the avalanche region 12 in the silicon layer 1. The avalanche region 12 is a highly doped region and usually has a relatively high electric field strength. When the electron-hole pairs enter the avalanche region 12, they will be accelerated and hit other atoms, generating more electron-hole pairs, thus triggering an avalanche effect, that is, an initial small current is quickly amplified into a large current, thereby generating a current signal. Since a PN junction 13 is provided between the avalanche region 12 and the logic wafer 2, the PN junction 13 plays a role of isolation and control, ensuring that the avalanche process will not affect the normal operation of the logic wafer 2. The logic wafer 2 obtains the current signal generated by the avalanche effect, and the logic wafer 2 is responsible for processing these current signals and outputting them, so that the detection of near ultraviolet light can be realized; in this embodiment, by processing and forming the light trapping structure 14 at the bottom of the filling region 11, the light trapping structure 14 reduces the reflectivity of the incident light, thereby improving the absorption rate of the silicon layer 1 for the incident light and promoting the generation of electron-hole pairs.

[0041] Please refer to Figures 2 to 4 , in one embodiment, the light trapping structure 14 is a conical structure with the tip facing the avalanche region 12. By setting the light trapping structure 14 as a conical structure with the tip facing the avalanche region 12, the tip of the conical structure faces the avalanche region 12, which can more effectively reduce the reflection loss of light at the bottom of the filling region 11. After the light enters the filling region 11, through multiple reflections and refractions of the conical structure, it is finally guided to the avalanche region 12, reducing the reflection loss and improving the light absorption rate. The conical structure can also further increase the propagation path of the light in the filling region 11. The light is reflected and refracted multiple times inside the conical structure, extending the optical path length of the light in the silicon layer 1, thereby increasing the probability of photons being absorbed.

[0042] In one embodiment, the number of the light trapping structures 14 is multiple, and the multiple light trapping structures 14 are arranged in an array along the length direction and the width direction of the filling area 11. The multiple conical structures are arranged in an array along the length direction and the width direction of the filling area 11 to form an array structure. This arrangement ensures uniform distribution of light throughout the filling area 11, reduces local hot spots and non-uniform light absorption, and improves the uniformity and reliability of photon detection. The design of the conical structure enables more photons to be effectively collected and guided to the avalanche region 12, further improving the photon collection efficiency of the single-photon avalanche diode 100 and further enhancing the overall detection ability.

[0043] Please refer to Figures 1 to 4 , in one embodiment, an opening 15 is formed at the top of the silicon layer 1, and the opening 15 communicates with the filling area 11. By forming the opening 15 at the top of the silicon layer 1 and connecting the opening 15 with the filling area 11, it is convenient for the operator to fill the filling area 11 with silicon dioxide, greatly reducing the operation difficulty of the operator and improving the operation efficiency.

[0044] Please refer to Figure 3 or Figure 4, in one embodiment, the single-photon avalanche diode 100 further includes a microlens 16. The microlens 16 is disposed on the top of the silicon layer 1, covers the opening 15, and is configured to transmit incident light through the opening 15 and focus it onto the filling region 11. Specifically, a microlens 16 is disposed on the top of the silicon layer 1 to cover the opening 15. When detection is performed, the incident light of near-ultraviolet first enters the microlens 16, and the microlens 16 focuses the incident light and guides it into the filling region 11. Since the filling region 11 is filled with silicon dioxide, and silicon dioxide has no obvious absorption effect on near-ultraviolet light, silicon dioxide can effectively transmit the near-ultraviolet light into the silicon layer 1. The incident light enters the silicon layer 1 from the light trapping structure 14 and is absorbed in the silicon layer 1 to generate electron-hole pairs. These electron-hole pair carriers migrate in the silicon layer 1 to the avalanche region 12, which is a highly doped region and usually has a relatively high electric field strength. When the electron-hole pairs enter the avalanche region 12, they are accelerated and collide with other atoms to generate more electron-hole pairs, thus triggering an avalanche effect, that is, an initial small current is rapidly amplified into a large current, thereby generating a current signal. Since a PN junction 13 is provided between the avalanche region 12 and the logic wafer 2, the PN junction 13 plays a role of isolation and control to ensure that the avalanche process does not affect the normal operation of the logic wafer 2. The logic wafer 2 acquires the current signal generated by the avalanche effect, processes these current signals, and outputs them, thus realizing the detection of near-ultraviolet light. In this embodiment, by providing the microlens 16, the incident light is focused onto the filling region 11 of the single-photon avalanche diode 100, so that more incident light enters the silicon layer 1, which can improve the light collection efficiency and ensure that more photons can reach the silicon layer 1.

[0045] Please refer to Figure 4, in one embodiment, a groove 17 is formed on the outer periphery of the silicon layer 1. The single-photon avalanche diode 100 further includes an isolation layer 3. The isolation layer 3 is disposed in the groove 17, and the top and bottom of the isolation layer 3 are respectively in contact with the microlens 16 and the logic wafer 2. Specifically, a circumferential groove 17 is etched on the outer periphery of the silicon layer 1, and then an insulating material is filled in the groove 17, thus forming the isolation layer 3. The isolation layer 3 serves as a physical barrier, blocking the light propagation path from one single-photon avalanche diode 100 unit to another, which reduces the mutual interference of optical signals between adjacent single-photon avalanche diode 100 units, thereby reducing optical crosstalk. The isolation layer 3 can reflect or absorb part of the light, further reducing the light propagation. The setting of the groove 17 and the isolation layer 3 can also optimize the electric field distribution and reduce the edge effect. The edge effect may cause edge breakdown and non-uniform electric field distribution, thus affecting the performance of the single-photon avalanche diode 100. By reducing the edge effect, it can be ensured that the electric field is more uniform inside the single-photon avalanche diode 100, improving the efficiency of the avalanche effect. The isolation layer 3 can also control the light propagation path, reducing the scattering and refraction of light in the silicon layer 1. This helps to more effectively guide the light to the photosensitive area of the single-photon avalanche diode 100. By reducing the scattering and refraction, it can be ensured that the optical path length of the light in the silicon layer 1 is more controllable, improving the photon absorption rate.

[0046] Furthermore, the isolation layer 3 includes deep trench isolation, shallow trench isolation, metal isolation, and a combined isolation layer 3. The deep trench isolation layer 3 is to etch deeper grooves 17 on the outer periphery of the silicon layer 1, and then fill these grooves 17 with an insulating material (such as silicon dioxide). These deep trench isolation layers 3 can effectively isolate adjacent single-photon avalanche diode 100 units, reducing optical crosstalk.

[0047] The shallow trench isolation layer 3 is to etch shallower grooves 17 on the outer periphery of the silicon layer 1 and fill these grooves 17 with an insulating material (such as silicon dioxide). The shallow trench isolation layer 3 has a poor effect of reducing optical crosstalk compared with the deep trench isolation layer 3, but the manufacturing process is relatively simple and the cost is relatively low.

[0048] The metal isolation layer 3 is usually a metal thin film covering the edge or the periphery of the single-photon avalanche diode 100. The metal layer can effectively reflect and shield optical signals, reducing optical crosstalk. The metal isolation layer 3 may affect the electric field distribution and needs to be carefully designed to avoid negative impacts.

[0049] The combined isolation layer 3 can, on the basis of deep trench isolation, cover a metal isolation layer 3 to further improve the isolation effect. The combined isolation layer 3 combines the advantages of multiple isolation technologies, providing the best isolation effect. However, the process of the combined isolation layer 3 is more complex and the cost is higher.

[0050] In one embodiment, the filling region 11 is a cylindrical filling region 11 or a cubic filling region 11. The shape and structure of the filling region 11 have an important impact on the performance of the single-photon avalanche diode 100. The filling region 11 is used to guide light into the single-photon avalanche diode 100, reduce reflection loss, and improve the light absorption rate. The filling region 11 can be cylindrical or cubic. The cylindrical filling region 11 can more effectively guide light into the single-photon avalanche diode 100, reduce reflection loss, and improve the light absorption rate. The geometric shape of the cylindrical filling region 11 helps to maintain the uniform distribution of light and reduce light scattering and refraction losses. The cubic filling region 11 has a square cross-section perpendicular to the surface of the silicon layer 1. The manufacturing process of the cubic filling region 11 is relatively simple and easy to achieve large-scale production. The cubic filling region 11 can make better use of space. The manufacturing process of the cubic filling region 11 is simple and the cost is low, which is suitable for large-scale production and low-cost applications.

[0051] According to another aspect of the present invention, please refer to Figure 5 , Figure 5 which is a schematic flowchart of the manufacturing method of the single-photon avalanche diode according to the first embodiment of the present invention. The present invention also provides a manufacturing method of a single-photon avalanche diode. The manufacturing method of the single-photon avalanche diode is applied to the single-photon avalanche diode 100 as described above. The manufacturing method of the single-photon avalanche diode includes the following steps:

[0052] S1. Provide the silicon layer 1 and the logic wafer 2, implant doping ions into the silicon layer 1 to form the avalanche region 12 and the PN junction 13, and bond the silicon layer 1 and the logic wafer 2;

[0053] Select a silicon layer 1 and a logic wafer 2, select appropriate doping ions, such as phosphorus, arsenic, boron, etc., use photolithography technology to define the doping region, adjust the implantation energy and dose to ensure that the doping ions penetrate the photoresist and enter the silicon layer 1. After implantation, the silicon layer 1 needs to be annealed to activate the doping ions and repair the damage generated during the implantation process. In this way, the avalanche region 12 and the PN junction 13 are formed by aggregation in the silicon layer 1. If the silicon layer 1 is one of the P-type or N-type layers, then the avalanche region 12 is the other of the P-type or N-type layers. Then, clean the bonding surfaces of the silicon layer 1 and the logic wafer 2 to ensure no pollution, and use technologies such as direct bonding and metal bonding to bond the silicon layer 1 and the logic wafer 2 together. After bonding, perform annealing treatment to enhance the bonding strength.

[0054] S2. Grind the side of the silicon layer 1 facing away from the logic wafer 2 to thin the silicon layer 1;

[0055] The silicon layer 1 is ground using a grinding machine, and the thickness of the silicon layer 1 is controlled during grinding to ensure that the design requirements are met. After completion, the surface of the silicon layer 1 needs to be cleaned to remove residues. The surface of the silicon layer 1 is further planarized using chemical mechanical polishing technology. The polished surface needs to be cleaned to remove residues.

[0056] S3. An implantation region 11 is etched in the silicon layer 1, and a light-trapping structure 14 is etched at the bottom of the implantation region 11. The implantation region 11 is filled with silicon dioxide, and the surface of the silicon dioxide is planarized.

[0057] The patterns of the implantation region 11 and the light-trapping structure 14 are defined in the silicon layer 1 using photolithography technology. A photoresist is coated on the surface of the silicon layer 1, and the required patterns are formed through exposure and development. The implantation region 11 and the light-trapping structure 14 are etched in the silicon layer 1. The silicon dioxide is filled in the implantation region 11 using chemical vapor deposition or spin coating technology, and then the surface of the silicon dioxide is planarized using chemical mechanical polishing technology. The planarized surface needs to be cleaned to remove residues. In this way, the implantation region 11 and the light-trapping structure 14 are processed.

[0058] S4. A trench 17 is etched on the outer periphery of the silicon layer 1, and an isolation layer 3 is filled in the trench 17.

[0059] The pattern of the trench 17 is defined on the outer periphery of the silicon layer 1 using photolithography technology. A photoresist is coated on the surface of the silicon layer 1, and the required patterns are formed through exposure and development. The trench 17 is etched on the outer periphery of the silicon layer 1. During the etching process, it is necessary to ensure that the depth and shape of the trench 17 meet the design requirements according to the design. Then, an isolation material is filled in the trench 17, and the surface of the isolation layer 3 is planarized using chemical mechanical polishing technology. The planarized surface needs to be cleaned to remove residues. In this way, the isolation layer 3 is processed.

[0060] S5. A microlens 16 is processed on the top of the silicon layer 1.

[0061] The pattern of the microlens 16 is defined using photolithography technology. A photoresist is coated on the surface of the silicon layer 1, and the required patterns are formed through exposure and development. The shape of the microlens 16 is etched. A polymer material is deposited in the microlens 16 region using spin coating technology, and the polymer material is formed into the required shape of the microlens 16 through heat treatment. The formed surface needs to be cleaned to remove residues. In this way, the processing of the microlens 16 is completed.

[0062] In this embodiment, a filling region 11 is formed by processing the silicon layer 1, and the filling region 11 is filled with silicon dioxide that does not have the ability to absorb near-ultraviolet light. In this way, when near-ultraviolet light passes through the silicon dioxide and enters the silicon layer 1, it is absorbed by the silicon layer 1 to generate electron-hole pairs. At this time, the distance between the electron-hole pairs and the avalanche region 12 is greatly reduced. In this way, the number of electron-hole pair recombinations that occur during the migration of multiple electron-hole pairs will be reduced, and the number of effective carriers reaching the avalanche region 12 is increased, thereby improving the detection efficiency of the entire single-photon avalanche diode 100.

[0063] According to another aspect of the present invention, the present invention further provides a single-photon detector, including the above-mentioned single-photon avalanche diode 100. Since the single-photon detector includes all the implementation manners of all the embodiments of the above-mentioned single-photon avalanche diode 100, it at least has all the beneficial effects brought by the above-mentioned all implementation manners, which will not be elaborated here one by one.

[0064] The above is only an exemplary implementation manner of the present invention, and does not limit the patent scope of the present invention. Any equivalent structural transformation made by using the content of the specification and drawings of the present invention under the technical concept of the present invention, or direct / indirect application in other related technical fields is included in the patent protection scope of the present invention.

Claims

1. A single photon avalanche diode, characterized in that: include: A silicon layer, wherein the silicon layer is etched to form a filling region, wherein the filling region is filled with silicon dioxide, and wherein an avalanche region and a PN junction are provided in the silicon layer; A logic wafer, wherein the logic wafer is disposed at the bottom of the silicon layer, and the logic wafer and the silicon layer are bonded to each other, the PN junction is disposed close to the logic wafer, and the avalanche region is disposed between the PN junction and the filling region; A light trapping structure is formed in the silicon layer. The light trapping structure is arranged at the bottom of the filling region. The light trapping structure is a conical structure with a pointed end facing the avalanche region.

2. The single photon avalanche diode according to claim 1, characterized in that: There are multiple light trapping structures, and the multiple light trapping structures are arranged in an array along the length direction and the width direction of the filling area.

3. The single photon avalanche diode according to any one of claims 1 or 2, characterized in that: An opening is formed on the top of the silicon layer, and the opening is communicated with the filling area.

4. The single photon avalanche diode according to claim 3, characterized in that: The single-photon avalanche diode further includes a microlens, which is disposed on the top of the silicon layer and covers the opening. The microlens is used to pass the incident light through the opening and focus it onto the filling area.

5. The single photon avalanche diode according to claim 4, characterized in that: A groove is formed on the periphery of the silicon layer. The single-photon avalanche diode further includes an isolation layer, which is arranged in the groove. The top and bottom of the isolation layer are respectively in contact with the microlens and the logic wafer.

6. The single photon avalanche diode according to claim 5, characterized in that: The filling area is a cylindrical filling area or a cubic filling area.

7. A method for manufacturing a single-photon avalanche diode, wherein the method for manufacturing a single-photon avalanche diode is applied to the single-photon avalanche diode according to any one of claims 1 to 6, characterized in that: The method for manufacturing the single photon avalanche diode comprises the following steps: Providing the silicon layer and the logic wafer, implanting doping ions into the silicon layer to form the avalanche region and the PN junction, and bonding the silicon layer to the logic wafer; Grinding a side of the silicon layer away from the logic wafer to thin the silicon layer; Etching the filling area in the silicon layer and etching a light trapping structure at the bottom of the filling area, filling the filling area with the silicon dioxide, and flattening the surface of the silicon dioxide; Etching a groove at the periphery of the silicon layer and filling the groove with an isolation layer; Microlenses are machined on top of the silicon layer.

8. A single photon detector, characterized in that: A single photon avalanche diode comprising any one of claims 1 to 6.

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