A method of manufacturing a back contact cell

Abstract

The application discloses a manufacturing method of a back contact cell, and relates to the technical field of photovoltaics, which aims to improve the working performance of the back contact cell. The manufacturing method of the back contact cell comprises the following steps: providing a semiconductor substrate; forming a first interface passivation layer and a first doped silicon layer in sequence on a first surface of the semiconductor substrate along the thickness direction of the semiconductor substrate; forming an insulating mask pattern on a partial region of the first doped silicon layer away from the semiconductor substrate; removing the first interface passivation layer and the first doped silicon layer exposed outside the insulating mask pattern; performing a texturing treatment on the surface of the region exposed outside the insulating mask pattern and a second surface; forming a first passivation layer on the second surface of the semiconductor substrate; forming a second interface passivation layer and a second doped silicon layer in sequence on the first interface passivation layer and the first doped silicon layer, and on the first surface; and selectively etching the second interface passivation layer and the second doped silicon layer.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and more particularly to a method for manufacturing a back-contact battery. Background Technology

[0002] A solar cell is a device that converts solar energy into electrical energy. Specifically, when a solar cell is in operation, sunlight shines on the semiconductor pn junction, forming new electron-hole pairs. Under the influence of the built-in electric field of the pn junction, photogenerated holes flow to the p-region, and photogenerated electrons flow to the n-region. When the circuit is connected, an electric current is generated. A solar cell where both the positive and negative electrodes are located on the back side of the cell is called a back-contact cell. Compared to double-sided contact solar cells, the front side of a back-contact cell is not obstructed by metal electrodes, resulting in higher light utilization on the light-facing side. Therefore, back-contact cells have higher short-circuit current and photoelectric conversion efficiency, making them one of the current technological directions for achieving high-efficiency crystalline silicon solar cells.

[0003] However, the existing manufacturing process for back contact batteries is relatively complex, which is not conducive to improving the manufacturing efficiency of back contact batteries and reducing manufacturing costs. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a back contact battery, which can improve the manufacturing efficiency of the back contact battery, reduce the manufacturing cost, and improve the conversion efficiency of the back contact battery.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a back-contact battery, the method comprising: First, providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface opposite to each other. Next, along the thickness direction of the semiconductor substrate, a first interface passivation layer and a first doped silicon layer are sequentially formed on the first surface of the semiconductor substrate. Next, an insulating mask pattern is formed on a portion of the first doped silicon layer facing away from the semiconductor substrate. Next, the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern are removed. Next, the area of ​​the first surface exposed outside the insulating mask pattern and the second surface are texturized. Next, a first passivation layer is formed on the second surface of the semiconductor substrate. Next, along the thickness direction of the semiconductor substrate, a second interface passivation layer and a second doped silicon layer are sequentially formed on the first surface. The second doped silicon layer and the first doped silicon layer have opposite conductivity types. Next, a portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer are removed to expose a portion of the first interface passivation layer and the first doped silicon layer.

[0006] With the above technical solution, the stacked first interface passivation layer and first doped silicon layer, as well as the stacked second interface passivation layer and second doped silicon layer, can each constitute a passivation contact structure. This passivation contact structure has excellent interface passivation effect and can achieve selective collection of charge carriers, reduce the carrier recombination rate on the first surface of the semiconductor substrate, and improve the conversion efficiency of the back contact cell. In addition, after removing the first interface passivation layer and first doped silicon layer that are not covered by the insulating mask pattern, the areas on the first surface where the first interface passivation layer and first doped silicon layer are not formed are also exposed. At this point, texturing can be performed simultaneously on the area of ​​the first surface exposed outside the insulating mask pattern and on the second surface. This improves the light-trapping effect of the second surface, and the portion of the second doped silicon layer formed on the area of ​​the first surface exposed outside the insulating mask pattern also exhibits a similar undulating morphology due to the texturing effect. This increases the specific surface area of ​​the second doped silicon layer on the side facing away from the semiconductor substrate, thus also increasing the contact area between the second doped silicon layer and conductive materials (such as transparent conductive layers or electrodes), reducing transmission losses, and further improving the conversion efficiency of the back contact cell. Furthermore, since texturing can be performed simultaneously on the area of ​​the first surface exposed outside the insulating mask pattern and on the second surface, the manufacturing efficiency of the back contact cell can also be improved. Moreover, the second interface passivation layer and the second doped silicon layer also cover a portion of the first interface passivation layer and the first doped silicon layer along the thickness direction of the semiconductor substrate, which can reduce the etching amount of the second interface passivation layer and the second doped silicon layer, increasing etching capacity. Simultaneously, the edges of the first interface passivation layer and the first doped silicon layer are covered by a second interface passivation layer and a second doped silicon layer. This prevents the etchant from affecting the edge portions of the first interface passivation layer and the first doped silicon layer, thereby improving the carrier collection efficiency of the edge portions of the first interface passivation layer and the first doped silicon layer. Furthermore, no isolation trenches are provided between the first interface passivation layer and the first doped silicon layer and the second interface passivation layer and the second doped silicon layer. Therefore, the contact areas between the first interface passivation layer and the first doped silicon layer and the semiconductor substrate, as well as the contact areas between the second interface passivation layer and the second doped silicon layer and the semiconductor substrate, can be maximized. This improves the utilization rate of the semiconductor substrate and thus enhances the photoelectric conversion efficiency.

[0007] As one possible implementation, the texturing process for the area of ​​the first surface exposed outside the insulating mask pattern and the second surface includes: simultaneously removing the insulating mask pattern while texturing the area of ​​the first surface exposed outside the insulating mask pattern and the second surface. Alternatively, the texturing process for the area of ​​the first surface exposed outside the insulating mask pattern and the second surface includes: texturing the area of ​​the first surface exposed outside the insulating mask pattern and the second surface; retaining the insulating mask pattern after texturing.

[0008] With the above technical solution, after removing the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern, the insulating mask pattern, the area of ​​the first surface of the semiconductor substrate exposed outside the insulating mask pattern, and the second surface are all exposed. Therefore, during the texturing process, the texturing solution not only contacts the area of ​​the first surface of the semiconductor substrate exposed outside the insulating mask pattern and the second surface, but also contacts the insulating mask pattern. In this case, the insulating mask pattern can be removed simultaneously with the texturing process, removed after texturing, or retained after texturing. It is evident that whether or not the insulating mask pattern is retained after texturing offers two possible options, which helps reduce material limitations on the insulating mask pattern and also improves the applicability of the manufacturing method provided by this invention in different application scenarios. When the insulating mask pattern is retained, it helps to separate the first doped silicon layer and the second doped silicon layer with the opposite conductivity type, preventing leakage and reducing the forward leakage loss of the back contact battery. When the insulating mask pattern is removed, a diode structure with a high reverse breakdown voltage can be formed between the first doped silicon layer and the second doped silicon layer with the opposite conductivity type, reducing the risk of hot spots on the back contact battery in installation environments with many obstructions such as sand and dust.

[0009] As one possible implementation, the sequential formation of a first interface passivation layer and a first doped silicon layer on a first surface of the semiconductor substrate includes: simultaneously forming the first interface passivation layer and the first doped silicon layer on the first surface of the semiconductor substrate, and forming a first doped silicon glass layer on the side of the first doped silicon layer facing away from the semiconductor substrate; and forming an insulating mask pattern on a portion of the first doped silicon layer facing away from the semiconductor substrate includes: patterning the first doped silicon glass layer to form an insulating mask pattern. In this case, the first doped silicon glass layer can be formed simultaneously with the formation of the first doped silicon layer, eliminating the need for an additional deposition process to form the corresponding insulating mask pattern, thus simplifying the manufacturing process of the back contact battery and improving the manufacturing efficiency of the back contact battery.

[0010] As one possible implementation, forming a first interface passivation layer and a first doped silicon layer sequentially on a first surface of a semiconductor substrate includes: while forming the first interface passivation layer and the first doped silicon layer sequentially on the first surface of the semiconductor substrate, forming a first doped silicon glass layer on the side of the first doped silicon layer away from the semiconductor substrate; and forming an insulating mask pattern on a portion of the side of the first doped silicon layer away from the semiconductor substrate includes: forming an insulating layer on the side of the first doped silicon glass layer away from the semiconductor substrate; and patterning the first doped silicon glass layer and the insulating layer to form an insulating mask pattern.

[0011] When using the above technical solution, compared with a single-layer insulating mask pattern, the insulating mask pattern in this case includes not only the patterned first doped silicon glass layer but also the patterned insulating layer, which is beneficial to improving the protective effect of the insulating mask pattern. Secondly, if the insulating mask pattern is retained after texturing, the insulating mask pattern including the first doped silicon glass layer and the insulating layer also has a high insulation isolation effect, which can further reduce the leakage risk of the overlapping portion of the second doped silicon layer and the first doped silicon layer along the thickness direction of the semiconductor substrate, and further improve the conversion efficiency of the back contact cell.

[0012] As one possible implementation, forming a first interface passivation layer and a first doped silicon layer sequentially on a first surface of a semiconductor substrate includes: while forming the first interface passivation layer and the first doped silicon layer sequentially on the first surface of the semiconductor substrate, forming a first doped silicon glass layer on the side of the first doped silicon layer away from the semiconductor substrate; and forming an insulating mask pattern on a portion of the side of the first doped silicon layer away from the semiconductor substrate includes: removing the first doped silicon glass layer; forming an insulating layer on the side of the first doped silicon layer away from the semiconductor substrate; and patterning the insulating layer to form an insulating mask pattern.

[0013] With the above technical solution, the insulating mask pattern can be directly formed on the side of the first doped silicon glass layer facing away from the semiconductor substrate. Because the insulating material used to fabricate the insulating mask pattern (such as silicon oxide, aluminum oxide, or silicon nitride) may have a passivation effect, it not only provides mask protection and insulation but also directly passivates the side of the first doped silicon layer facing away from the semiconductor substrate. This helps reduce surface defects on that side and further improves the conversion efficiency of the back-contact battery.

[0014] As one possible implementation, a first passivation layer is formed on the second surface of the semiconductor substrate, including: simultaneously forming the first passivation layer on the first surface of the semiconductor substrate while forming the first passivation layer on the second surface of the semiconductor substrate. Next, the first passivation layer is annealed. Then, the first passivation layer located on the first surface of the semiconductor substrate is removed.

[0015] With the above technical solution, a first passivation layer is formed on the first surface while a first passivation layer is formed on the second surface of the semiconductor substrate. The presence of the first passivation layer on the first surface can passivate the side of the first doped silicon layer away from the semiconductor substrate during annealing, reducing surface defects on the side of the first doped silicon layer away from the semiconductor substrate. It also prevents hydrogen from escaping and affecting the passivation effect when the side of the first doped silicon layer away from the semiconductor substrate is exposed during annealing after the insulating mask pattern is removed, thus ensuring that the back contact battery has high conversion efficiency.

[0016] As one possible implementation, the first passivation layer includes an intrinsic silicon passivation layer. In this case, the intrinsic silicon passivation layer has a high hydrogen content, which allows the first passivation layer to have a high passivation effect on the second surface of the semiconductor substrate, further improving the conversion efficiency of the manufactured back contact cell. During the annealing process, the first passivation layer can perform hydrogen implantation (i.e., hydrogen replenishment) on the first doped silicon layer, which can improve the passivation effect of the first doped silicon layer.

[0017] As one possible implementation, after sequentially forming a second interface passivation layer and a second doped silicon layer on the first surface, and before removing portions of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer, the method for back-contact solar cells further includes forming an anti-reflection layer on the side of the first passivation layer facing away from the semiconductor substrate. In this case, the reflectivity of the manufactured back-contact solar cell on the second surface is reduced, further improving the conversion efficiency of the back-contact solar cell.

[0018] As one possible implementation, after texturing the area of ​​the first surface exposed outside the insulating mask pattern and the second surface, and before forming the first passivation layer on the second surface of the semiconductor substrate, a second interface passivation layer and a second doped silicon layer are sequentially formed on the first surface.

[0019] With the above technical solution, the formation sequence of the stacked second interface passivation layer and the second doped silicon layer can be set not only after the formation of at least the first passivation layer, but also after texturing and before the formation of at least the first passivation layer. This adds another optional example to the manufacturing method provided by the present invention, which is beneficial to improving the applicability of the manufacturing method provided by the present invention in different application scenarios. Meanwhile, when the first passivation layer is formed on the second surface of the semiconductor substrate, the first passivation layer may be deposited around the side of the semiconductor substrate and at least a portion of the first surface. Based on this, when the formation sequence of the stacked second interface passivation layer and the second doped silicon layer is set after texturing and before the formation of at least the first passivation layer, it is no longer necessary to remove at least the portion of the first passivation layer deposited around the first surface before forming the stacked second interface passivation layer and the second doped silicon layer, thereby reducing process steps. It can be determined whether to remove the first passivation layer deposited around the first surface after the formation of at least the first passivation layer according to actual needs, reducing manufacturing requirements. Furthermore, in this case, the corresponding structure on the first side can be completed first, and then the corresponding film layer (first passivation layer and antireflection layer) on the second side can be made, reducing the number of times the layers are flipped and reducing the risk of damage.

[0020] As one possible implementation, the first passivation layer includes a second doped silicon glass layer, and the conductivity type of the dopant in the second doped silicon glass layer is the same as that of the first doped silicon layer.

[0021] With the above technical solution, the second doped silicon glass layer has higher light transmittance compared to the intrinsic silicon passivation layer. Therefore, compared to the first passivation layer including the intrinsic silicon passivation layer, when the first passivation layer includes the second doped silicon glass layer, the parasitic absorption of the first passivation layer can be reduced, which is beneficial to improving the light utilization rate of the back contact battery. Furthermore, the second doped silicon glass layer is also doped with a dopant of the same conductivity type as the first doped silicon layer, enabling the first passivation layer to not only chemically passivate one side of the second surface of the semiconductor substrate but also to field passivate the other side. This reduces the carrier recombination rate on the second surface while also improving the carrier collection efficiency of both the first and second doped silicon layers. Compared to the need for separate deposition, the second doped silicon glass layer can be formed through a diffusion process, simplifying the fabrication of the first passivation layer.

[0022] As one possible implementation, a first passivation layer is formed on the second surface of the semiconductor substrate, comprising: forming a first passivation layer and an antireflection layer sequentially stacked along the thickness direction of the semiconductor substrate on the second surface of the semiconductor substrate. In this case, the reflectivity of the back contact cell on the second surface side is reduced, thereby further improving the conversion efficiency of the back contact cell.

[0023] As one possible implementation, after removing portions of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer, the manufacturing method of the back contact battery further includes: forming a transparent conductive layer covering the side of the first doped silicon layer and the second doped silicon layer facing away from the semiconductor substrate. A through-hole isolating trench is formed within the transparent conductive layer to disconnect the portion of the transparent conductive layer corresponding to the first doped silicon layer from the portion corresponding to the second doped silicon layer. Next, a first electrode is formed on the portion of the transparent conductive layer corresponding to the first doped silicon layer, and a second electrode is formed on the portion of the transparent conductive layer corresponding to the second doped silicon layer. In this case, the transparent conductive layer has high carrier transport characteristics, which is beneficial for improving carrier collection efficiency. Furthermore, the transparent conductive layer is disposed between the metal electrode and the semiconductor layer, which helps to reduce the contact barrier and reduce contact resistance.

[0024] As one possible implementation, the thickness of the edge portion of the transparent conductive layer adjacent to the isolation trench gradually decreases towards the isolation trench. In this case, the thickness of the transparent conductive layer near both sides of the isolation trench is smaller. This results in a smaller thickness (and smaller area) of the two opposing portions of the transparent conductive layer used for transporting opposite charge carriers, which helps reduce the risk of leakage and improves the electrical reliability of the back contact battery. Furthermore, this design also facilitates stress release between other structures in the back contact battery and the transparent conductive layer, preventing edge chipping or detachment due to excessive stress during the formation of the transparent conductive layer, thus improving the structural reliability of the manufactured back contact battery.

[0025] As one possible implementation, the second interface passivation layer, the second doped silicon layer, and the transparent conductive layer disposed on the second doped silicon layer, stacked sequentially, all cover a portion of the stacked first interface passivation layer and the first doped silicon layer on the side away from the semiconductor substrate. And / or, the portion of the first interface passivation layer, the first doped silicon layer, the second interface passivation layer, and the second doped silicon layer stacked along the thickness direction of the semiconductor substrate is an overlapping region; at least a portion of the overlapping region is a reverse leakage region, and within the reverse leakage region, the second doped silicon layer is electrically connected to the first doped silicon layer through the second interface passivation layer.

[0026] When the above technical solution is adopted, in the reverse leakage region, the second doped silicon layer can be electrically connected to the first doped silicon layer with the opposite conductivity type through the second interface passivation layer to form a built-in diode structure with a lower reverse breakdown voltage, thereby reducing the risk of hot spots on the back contact battery.

[0027] As one possible implementation, the thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 140 nm.

[0028] With the above technical solution, the presence of the transparent conductive layer can improve the carrier collection efficiency and allow for the thinning of the first doped silicon layer. In other words, without reducing the carrier collection efficiency, the thickness of the first doped silicon layer can be appropriately reduced due to the presence of the transparent conductive layer. Therefore, when the thickness of the first doped silicon layer is within the aforementioned range, its smaller thickness helps reduce parasitic absorption and further improves the operating efficiency of the back contact cell. Furthermore, because the thickness of the first doped silicon layer is smaller, the formation time of the first doped silicon layer can be reduced, improving fabrication efficiency.

[0029] As one possible implementation, the width of the opening region of the second interface passivation layer and the second doped silicon layer is greater than or equal to 250 μm and less than or equal to 400 μm.

[0030] With the above technical solution, it is understood that the first doped silicon layer needs to be electrically connected to the corresponding conductive material through an opening region disposed within the second interface passivation layer and the second doped silicon layer, thereby discharging the collected charge carriers. The charge carriers transported by the conductive material electrically connected to the first doped silicon layer are of the opposite conductivity type to those of the second doped silicon layer. Based on this, compared to the existing back contact battery where the width of the opening region of the second interface passivation layer and the second doped silicon layer is less than 250 μm, the back contact battery formed by the manufacturing method provided by this invention has a wider opening region for exposing the first doped silicon layer. This allows for a larger possible formation range of the corresponding conductive material electrically connected to the first doped silicon layer while preventing short circuits, thereby increasing the contact area between the first doped silicon layer and the corresponding conductive material, reducing transmission losses, and improving the electrical reliability of the manufactured back contact battery. Secondly, when the width of the opening region is less than or equal to 400 μm, a larger portion of the second interface passivation layer and the second doped silicon layer is retained after the opening operation. This reduces the amount of etching while ensuring that the second interface passivation layer and the second doped silicon layer have a certain area ratio on the first side, thus ensuring that the second doped silicon layer has a high current collection efficiency.

[0031] As one possible implementation, the surface of the region where the first interface passivation layer and the first doped silicon layer are disposed in the first surface has a tower-like texture structure. Furthermore, the thickness of the first interface passivation layer on the bottom surface of the tower-like texture structure is less than the thickness of the first interface passivation layer on the sidewalls of the tower-like texture structure.

[0032] With the above technical solution, it is understood that the bottom surface and the side surface of the aforementioned tower-shaped textured structure have different crystal orientations. Specifically, the bottom surface of the tower-shaped textured structure has a

[110] crystal orientation, and the number of dangling bonds on the surface of the

[110] crystal orientation is relatively small; while the side surface of the tower-shaped textured structure has a

[111] crystal orientation, and the number of dangling bonds in the

[111] crystal orientation is relatively large. Based on this, when the thickness of the first interface passivation layer on the bottom surface of the tower-shaped textured structure is less than the thickness of the first interface passivation layer on the side wall of the tower-shaped textured structure, it is beneficial to make the portion of the first interface passivation layer on the side wall of the tower-shaped textured structure have a relatively high passivation effect, satisfying the requirement of the side surface of the tower-shaped textured structure for a high passivation effect, reducing the carrier recombination rate on the side surface of the tower-shaped textured structure, and further improving the working efficiency of the back contact battery.

[0033] As one possible implementation, the thickness of the first interface passivation layer on the bottom surface of the tower-like textured structure is greater than or equal to 0.5 nm and less than or equal to 1.5 nm. In this case, the thickness of the first interface passivation layer on the bottom surface of the tower-like textured structure is within the above range, which helps to prevent a low passivation effect on the semiconductor substrate due to a small thickness of the first interface passivation layer on the bottom surface of the tower-like textured structure. In addition, it also helps to prevent a high tunneling resistance due to a large thickness of the first interface passivation layer on the bottom surface of the tower-like textured structure. This helps to achieve a balance between the passivation effect and tunneling resistance of the portion of the first interface passivation layer on the bottom surface of the tower-like textured structure, thereby reducing the carrier recombination rate on the side of the tower-like textured structure while ensuring that the first doped silicon layer has a high carrier collection efficiency and reducing transmission loss.

[0034] As one possible implementation, the thickness of the first interface passivation layer on the sidewall of the tower-like textured structure is greater than or equal to 0.5 nm and less than or equal to 2 nm. In this case, the thickness of the first interface passivation layer on the sidewall of the tower-like textured structure is within the above range, which helps to prevent the passivation effect from being low due to the small thickness of this part; in addition, it also helps to prevent the tunneling resistance of this part from being high due to the large thickness of the first interface passivation layer on the sidewall of the tower-like textured structure. This helps to achieve a balance between the passivation effect and the tunneling resistance of the part of the first interface passivation layer on the sidewall of the tower-like textured structure, thereby reducing the carrier recombination rate on the side of the tower-like textured structure while ensuring that the first doped silicon layer has a high carrier collection efficiency and reducing transmission loss.

[0035] As one possible implementation, the thickness of the second interface passivation layer is greater than or equal to 3 nm and less than or equal to 16 nm. In this case, the larger thickness of the second interface passivation layer is beneficial for enhancing the isolation effect between the second interface passivation layer and the first doped silicon layer, reducing the risk of leakage. Furthermore, it can also prevent excessive contact resistance due to the excessive thickness of the second interface passivation layer, thus reducing transmission loss.

[0036] As one possible implementation, the first doped silicon layer is a doped polycrystalline silicon layer. The back contact cell also includes an amorphous silicon layer disposed on the side of the first doped silicon layer facing away from the semiconductor substrate. In this case, the amorphous silicon layer can passivate the side of the first doped silicon layer facing away from the semiconductor substrate, reducing the number of surface defects on that side and improving the conversion efficiency of the back contact cell. Furthermore, since the work function difference between the amorphous silicon layer and the transparent conductive layer is smaller than that between the doped polycrystalline silicon layer and the transparent conductive layer (i.e., the contact barrier between the amorphous silicon layer and the transparent conductive layer is smaller), the contact resistance between the amorphous silicon layer and the transparent conductive layer is also smaller. Therefore, compared to the first doped silicon layer directly contacting the transparent conductive layer, placing an amorphous silicon layer on the side of the first doped silicon layer facing away from the semiconductor substrate allows for more reasonable bandgap matching, reduces contact resistance, and enables the back contact cell to effectively convert sunlight into electrical energy, thus improving the photoelectric conversion efficiency of the back contact cell.

[0037] As one possible implementation, removing a portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer includes: using a laser to remove a portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer, and using a laser to process the edge portion of the opening region of the second doped silicon layer so that a hole structure is formed in the edge portion of the second doped silicon layer.

[0038] With the above technical solution, it is understood that the hole structure is a hollow structure. Therefore, when a hole structure is formed in the edge portion of the second doped silicon layer, the leakage risk between the edge portion of the second doped silicon layer and the first doped silicon layer can be reduced, improving the electrical reliability of the back contact cell. In addition, the presence of the hole structure can also increase the undulation of the edge portion of the stacked second interface passivation layer and the second doped silicon layer, thereby enhancing the light trapping effect in this part and helping to improve the bifaciality of the back contact cell.

[0039] As one possible implementation, the first surface includes a first region and a second region. The second region includes a groove. A first interface passivation layer and a first doped silicon layer are located in the first region. A second interface passivation layer and a second doped silicon layer are located in the second region and extend into the first region, partially covering the first interface passivation layer and the first doped silicon layer. The surface of the first region is a polished surface, and the bottom surface of the groove is a textured surface. The thickness of the second doped silicon layer on the textured surface is less than the thickness of the second doped silicon layer on the polished surface.

[0040] With the above technical solution, the presence of the grooves causes the surface of the second region to be offset from the surface of the first region along the thickness direction of the semiconductor substrate. This facilitates at least partial offsetting of the second interface passivation layer and the second doped silicon layer located on the second region from the first interface passivation layer and the first doped silicon layer located on the first region, reducing the risk of leakage. Furthermore, compared to a polished surface, a textured surface has a larger specific surface area. Within the same formation range, the contact area between the portion of the second doped silicon layer on the textured surface and the semiconductor substrate is larger, while the contact area between the portion of the second doped silicon layer on the polished surface and the semiconductor substrate is smaller. Therefore, when the thickness of the second doped silicon layer on the textured surface is smaller, after ensuring sufficient contact area between the portion of the second doped silicon layer on the textured surface and the semiconductor substrate, space can be reserved for reducing the thickness of this portion. This ensures high carrier collection efficiency while reducing the amount of consumables used in manufacturing the portion of the second doped silicon layer on the textured surface. Additionally, the larger thickness of the second doped silicon layer on the polished surface results in a higher field passivation effect, reducing carrier recombination. In this case, the thickness difference between different parts of the second doped silicon layer can be set according to the surface roughness of the first and second regions and actual needs, and no specific limitation is made here.

[0041] As one possible implementation, the first surface includes a first region and a second region. The second region includes a groove. The surface of the first region is polished, and the bottom surface of the groove is textured. A first interface passivation layer and a first doped silicon layer are located in the first region. A second interface passivation layer and a second doped silicon layer are located in the second region and extend from the second region to the first region, partially covering the first interface passivation layer and the first doped silicon layer. The distance from the surface of the semiconductor substrate in the first region to the bottom surface of the groove is greater than or equal to 2 μm and less than or equal to 8 μm.

[0042] By adopting the above technical solution, it is beneficial to prevent the first and second doped silicon layers from being misaligned along the thickness direction of the semiconductor substrate due to the small distance between the surface of the semiconductor substrate in the first region and the bottom surface of the groove, thus ensuring a low risk of leakage between them. Secondly, during the texturing process on the bottom surface of the groove, the semiconductor substrate needs to be etched. Therefore, the distance between the surface of the semiconductor substrate in the first region and the bottom surface of the groove also affects the size of the textured structure on the bottom surface of the groove. Based on this, keeping the distance between the surface of the semiconductor substrate in the first region and the bottom surface of the groove within the above range can also prevent the bottom surface of the groove and the textured structure formed on the second surface from being too small due to the small distance, ensuring that the second surface has a high light trapping effect. At the same time, it is beneficial to increase the specific surface area of ​​the side of the second doped silicon layer away from the semiconductor substrate, further reducing the contact loss between the second doped silicon layer and the corresponding conductive material. In addition, it can also prevent the etching depth of the semiconductor substrate at the groove from being too large due to the large distance between the surface of the semiconductor substrate in the first region and the bottom surface of the groove, ensuring that each part of the semiconductor substrate has a large light absorption depth, thereby enabling the back contact battery to have a high conversion efficiency.

[0043] As one possible implementation, the first surface includes a first region and a second region; the second region includes a groove. A first interface passivation layer and a first doped silicon layer are located in the first region; a second interface passivation layer and a second doped silicon layer are located in the second region, extending from the second region to the first region and covering a portion of the first interface passivation layer and the first doped silicon layer. The second doped silicon layer is a doped amorphous silicon layer. After sequentially forming a stacked second interface passivation layer and a second doped silicon layer along the thickness direction of the semiconductor substrate on the first surface, the method for manufacturing the back contact cell further includes: laser irradiating the second doped silicon layer located on the bottom surface of the groove to crystallize the second doped silicon layer.

[0044] In the above technical solution, the second doped silicon layer is a doped amorphous silicon layer located in the second region including the groove. The bottom surface of the groove is textured, and this textured structure reflects laser light. When the second doped silicon layer on the bottom surface of the groove is irradiated by a laser, the textured structure reflects the laser light, causing the second doped silicon layer to crystallize upon heating. This increases the degree of crystallization of the second doped silicon layer, thereby improving its conductivity, reducing the contact resistance between the second doped silicon layer and the corresponding conductive material, and reducing transmission loss. Attached Figure Description

[0045] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0046] Figure 1 A flowchart illustrating the manufacturing method of a back contact battery provided in an embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 1 ;

[0048] Figure 3 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 2 ;

[0049] Figure 4 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 3 ;

[0050] Figure 5 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 4 ;

[0051] Figure 6 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 5 ;

[0052] Figure 7 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 6 ;

[0053] Figure 8 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 7 ;

[0054] Figure 9 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 8 ;

[0055] Figure 10 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 9 ;

[0056] Figure 11 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 10 ;

[0057] Figure 12 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 10 one;

[0058] Figure 13 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 10 two;

[0059] Figure 14 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 10 three;

[0060] Figure 15 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 10 Four;

[0061] Figure 16 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 10 five;

[0062] Figure 17 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 10 six;

[0063] Figure 18 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 10 seven;

[0064] Figure 19 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 10 eight;

[0065] Figure 20 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 10 Nine;

[0066] Figure 21 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 2 ten;

[0067] Figure 22 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 2 eleven;

[0068] Figure 23 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 2twelve;

[0069] Figure 24 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 2 Thirteen;

[0070] Figure 25 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 2 fourteen;

[0071] Figure 26 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 2 fifteen;

[0072] Figure 27 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 2 sixteen;

[0073] Figure 28 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 2 Seventeen;

[0074] Figure 29 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 2 eighteen;

[0075] Figure 30 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 2 nineteen;

[0076] Figure 31 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 3 ten;

[0077] Figure 32 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 3 eleven;

[0078] Figure 33 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 3 twelve;

[0079] Figure 34 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 3Thirteen;

[0080] Figure 35 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 3 fourteen;

[0081] Figure 36 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 3 fifteen;

[0082] Figure 37 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 3 sixteen;

[0083] Figure 38 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 3 Seventeen;

[0084] Figure 39 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 3 eighteen;

[0085] Figure 40 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 3 nineteen;

[0086] Figure 41 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 4 ten;

[0087] Figure 42 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 4 eleven;

[0088] Figure 43 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 4 twelve;

[0089] Figure 44 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 4 Thirteen;

[0090] Figure 45 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 4fourteen;

[0091] Figure 46 This is a schematic diagram illustrating the manufacturing process of a back contact battery produced using the manufacturing method provided in this embodiment of the invention. Figure 4 fifteen.

[0092] Reference numerals: 11 is a semiconductor substrate, 12 is a first interface passivation layer, 13 is a first doped silicon layer, 14 is a first doped silicon glass layer, 15 is an insulating mask pattern, 16 is an insulating layer, 17 is a first passivation layer, 18 is an anti-reflection layer, 19 is a second interface passivation layer, 20 is a second doped silicon layer, 21 is a transparent conductive layer, 22 is an isolation trench, 23 is a first region, and 24 is a second region. Detailed Implementation

[0093] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0094] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0095] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0096] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0097] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0098] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight shines on the semiconductor pn junction, forming new electron-hole pairs. Under the influence of the built-in electric field of the pn junction, photogenerated holes flow to the p-region, and photogenerated electrons flow to the n-region. When the circuit is connected, an electric current is generated. Solar cells where both the positive and negative electrodes are located on the back side of the cell are called back-contact cells. Compared to double-sided contact solar cells, the front side of a back-contact cell has no metal electrodes to block the light, resulting in higher light utilization on the light-facing side. Therefore, back-contact cells have higher short-circuit current and photoelectric conversion efficiency, making them one of the current technological directions for achieving high-efficiency crystalline silicon solar cells.

[0099] However, the existing manufacturing process for back contact batteries is relatively complex, which is not conducive to improving the manufacturing efficiency of back contact batteries and reducing manufacturing costs.

[0100] To address the aforementioned technical problems, embodiments of the present invention provide a method for manufacturing a back-contact battery. For example... Figure 1As shown, the manufacturing method of the back contact battery provided in this embodiment of the invention includes the following steps: First, a semiconductor substrate is provided. The semiconductor substrate has a first surface and a second surface opposite to each other. Next, along the thickness direction of the semiconductor substrate, a first interface passivation layer and a first doped silicon layer are sequentially formed on the first surface of the semiconductor substrate. Next, an insulating mask pattern is formed on a portion of the first doped silicon layer on the side opposite to the semiconductor substrate. Next, the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern are removed. Next, the area of ​​the first surface not covered by the insulating mask pattern and the second surface are texturized. Next, a first passivation layer is formed on the second surface of the semiconductor substrate. Next, along the thickness direction of the semiconductor substrate, a second interface passivation layer and a second doped silicon layer are sequentially formed on the first surface. The second doped silicon layer and the first doped silicon layer have opposite conductivity types. Next, a portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer are removed to expose a portion of the first interface passivation layer and the first doped silicon layer.

[0101] It should be noted that the manufacturing method provided in this embodiment of the invention does not specifically limit the order of the operation steps of forming a first passivation layer on the second surface of the semiconductor substrate and the operation steps of sequentially forming a second interface passivation layer and a second doped silicon layer on the first surface along the thickness direction of the semiconductor substrate. It is permissible to first form the first passivation layer on the second surface of the semiconductor substrate, and then sequentially form the second interface passivation layer and the second doped silicon layer on the first surface; alternatively, it is permissible to first sequentially form the second interface passivation layer and the second doped silicon layer on the first surface, and then form the first passivation layer on the second surface of the semiconductor substrate.

[0102] With the above technical solution, the stacked first interface passivation layer and first doped silicon layer, as well as the stacked second interface passivation layer and second doped silicon layer, can each constitute a passivation contact structure. This passivation contact structure has excellent interface passivation effect and can achieve selective collection of charge carriers, reduce the carrier recombination rate on the first surface of the semiconductor substrate, and improve the conversion efficiency of the back contact cell. In addition, after removing the first interface passivation layer and first doped silicon layer that are not covered by the insulating mask pattern, the areas on the first surface where the first interface passivation layer and first doped silicon layer are not formed are also exposed. At this point, texturing can be performed simultaneously on the area of ​​the first surface exposed outside the insulating mask pattern and on the second surface. This improves the light-trapping effect of the second surface, and the portion of the second doped silicon layer formed on the area of ​​the first surface exposed outside the insulating mask pattern also exhibits a similar undulating morphology due to the texturing effect. This increases the specific surface area of ​​the second doped silicon layer on the side facing away from the semiconductor substrate, thus also increasing the contact area between the second doped silicon layer and conductive materials (such as transparent conductive layers or electrodes), reducing transmission losses, and further improving the conversion efficiency of the back contact cell. Furthermore, since texturing can be performed simultaneously on the area of ​​the first surface exposed outside the insulating mask pattern and on the second surface, the manufacturing efficiency of the back contact cell can also be improved. Moreover, the second interface passivation layer and the second doped silicon layer also cover a portion of the first interface passivation layer and the first doped silicon layer along the thickness direction of the semiconductor substrate, which can reduce the etching amount of the second interface passivation layer and the second doped silicon layer, increasing etching capacity. Simultaneously, the edges of the first interface passivation layer and the first doped silicon layer are covered by a second interface passivation layer and a second doped silicon layer. This prevents the etchant from affecting the edge portions of the first interface passivation layer and the first doped silicon layer, thereby improving the carrier collection efficiency of the edge portions of the first interface passivation layer and the first doped silicon layer. Furthermore, no isolation trenches are provided between the first interface passivation layer and the first doped silicon layer and the second interface passivation layer and the second doped silicon layer. Therefore, the contact areas between the first interface passivation layer and the first doped silicon layer and the semiconductor substrate, as well as the contact areas between the second interface passivation layer and the second doped silicon layer and the semiconductor substrate, can be maximized. This improves the utilization rate of the semiconductor substrate and thus enhances the photoelectric conversion efficiency.

[0103] The following will be based on Figures 2 to 38 The diagram shows a cross-sectional view of the operation, and illustrates the manufacturing process of the back contact battery provided by the present invention through various embodiments:

[0104] Example 1

[0105] Step 1: Provide a semiconductor substrate. The semiconductor substrate has a first side and a second side facing each other.

[0106] Specifically, the embodiments of the present invention do not impose specific limitations on the material of the semiconductor substrate. The semiconductor substrate can be any semiconductor material such as a silicon substrate, a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate. Furthermore, the conductivity type of the semiconductor substrate can be either N-type or P-type.

[0107] In actual manufacturing processes, after the semiconductor substrate is provided, in some examples, the semiconductor substrate can be pre-cleaned to remove cutting damage on the surface of the semiconductor substrate, as well as organic matter and other contaminants generated during transportation, thereby improving the yield of the manufactured back contact battery.

[0108] Step 2: As Figure 2 As shown, along the thickness direction of the semiconductor substrate 11, a first interface passivation layer 12 and a first doped silicon layer 13 are sequentially formed on the first surface of the semiconductor substrate 11.

[0109] Specifically, the materials of the first interface passivation layer and the first doped silicon layer are not specifically limited in the embodiments of the present invention, and can be set according to actual needs.

[0110] For example, the first interface passivation layer can be an intrinsic silicon layer. The first interface passivation layer and the first doped silicon layer can form a heterogeneous contact structure. In this case, the first interface passivation layer and the first doped silicon layer have a high passivation effect on the corresponding surface of the semiconductor substrate, further reducing the carrier recombination rate on the surface of that region and improving the conversion efficiency of the manufactured back contact battery. The material of the first interface passivation layer and / or the first doped silicon layer can include at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0111] For example, the first interface passivation layer can be a tunneling passivation layer, and the material of the tunneling passivation layer can include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium carbonitride nitride. Secondly, when the first interface passivation layer is a tunneling passivation layer, the first doped silicon layer includes a doped crystalline silicon layer. Specifically, the first doped silicon layer can include a doped polycrystalline silicon layer and / or a doped monocrystalline silicon layer. In this context, since amorphous silicon, nanocrystalline silicon, and microcrystalline silicon readily form polycrystalline silicon or monocrystalline silicon at high temperatures, and the tunneling passivation layer and doped silicon layer exhibit relatively stable chemical properties at high temperatures, forming a first interface passivation layer and a first doped silicon layer with high thermal stability on one side of the first surface of the semiconductor substrate can reduce or even eliminate the impact of laser radiation heat on the first interface passivation layer and the first doped silicon layer during subsequent selective etching of the stacked second interface passivation layer and the second doped silicon layer using laser processing, thereby improving the yield of the back contact battery. Simultaneously, the first interface passivation layer and the first doped silicon layer are less sensitive to high-temperature laser thermal damage, reducing the impact on their passivation effect during laser processing, further increasing the process window and reducing the process difficulty.

[0112] When the first interface passivation layer is a tunneling passivation layer and the first doped silicon layer includes a doped crystalline silicon layer, in the actual manufacturing process, processes such as low-pressure chemical vapor deposition or thermal oxidation can be used to form the first interface passivation layer on the first surface of the semiconductor substrate. Next, in some examples, processes such as chemical vapor deposition can be used to form an intrinsic silicon layer on the first interface passivation layer. Then, processes such as diffusion, ion implantation, or dopant source coating can be used to dope the intrinsic silicon layer, thereby forming a first doped polycrystalline silicon layer.

[0113] In other examples, a doped amorphous silicon layer can be formed on the first interface passivation layer using processes such as chemical vapor deposition; then, the doped amorphous silicon layer is annealed to form a doped polycrystalline silicon layer. In still other examples, a first doped silicon layer, comprising at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon, can be formed directly on the first interface passivation layer using processes such as chemical vapor deposition.

[0114] It should be noted that, as Figure 2 As shown, during the formation of the first interface passivation layer 12 and the first doped silicon layer 13, the first interface passivation layer 12 and the first doped silicon layer 13 are also formed on the side surface and at least a portion of the second surface of the semiconductor substrate 11. Specifically, during the formation of the first doped silicon layer 13, if the semiconductor substrate 11 uses a double-insertion method, the first doped silicon layer 13 will be formed in the edge region of the second surface of the semiconductor substrate 11; if the semiconductor substrate 11 uses a single-insertion method, then... Figure 2 As shown, a first doped silicon layer 13 will be formed on the entire second surface of the semiconductor substrate 11.

[0115] In addition, such as Figure 2 As shown, when the intrinsic silicon layer is doped using a diffusion process, a first doped silicon glass layer 14 is also formed on the side of the first doped silicon layer 13 away from the semiconductor substrate 11 while the first doped silicon layer 13 is being formed.

[0116] Specifically, the embodiments of the present invention do not impose specific limitations on the thickness of the first interface passivation layer and the first doped silicon layer, which can be set according to actual needs.

[0117] For example, the thickness of the first doped silicon layer can be greater than or equal to 30 nm and less than or equal to 150 nm. For instance, the thickness of the first doped silicon layer can be 30 nm, 40 nm, 50 nm, 80 nm, 100 nm, 120 nm, or 150 nm, etc.

[0118] For example, when the first interface passivation layer is a tunneling passivation layer, the thickness of the first interface passivation layer can be greater than or equal to 0.5 nm and less than or equal to 2.5 nm; or, when the first interface passivation layer is an intrinsic silicon layer, the thickness of the first interface passivation layer can be greater than or equal to 4 nm and less than or equal to 18 nm.

[0119] In practical applications, the thickness of each part of the first interface passivation layer can be the same or different. When the thicknesses of each part of the first interface passivation layer are different, in some examples, where the surface of the region where the first interface passivation layer and the first doped silicon layer are located has a tower-like textured structure, the thickness of the first interface passivation layer at the bottom of the tower-like textured structure can be less than the thickness of the first interface passivation layer at the sidewall of the tower-like textured structure. In this case, it is understood that the bottom surface and the side surface of the tower-like textured structure have different crystal orientations. Specifically, the bottom surface of the tower-like textured structure has a

[110] crystal orientation, with a relatively small number of dangling bonds on the surface of the

[110] crystal orientation; while the side surface of the tower-like textured structure has a

[111] crystal orientation, with a relatively large number of dangling bonds on the

[111] crystal orientation. Based on this, when the thickness of the first interface passivation layer on one side of the bottom surface of the tower-shaped texture structure is less than the thickness of the first interface passivation layer on the sidewall of the tower-shaped texture structure, it is beneficial to make the portion of the first interface passivation layer on the sidewall of the tower-shaped texture structure have a relatively high passivation effect, which meets the requirement of the side of the tower-shaped texture structure for a high passivation effect, reduces the carrier recombination rate on the side of the tower-shaped texture structure, and further improves the working efficiency of the manufactured back contact battery.

[0120] The thickness of the first interface passivation layer on the bottom surface of the tower-shaped texture structure and the thickness of the first interface passivation layer on the side wall of the tower-shaped texture structure can be determined according to the requirements of the passivation effect of different areas of the tower-shaped texture structure and the actual manufacturing process, and no specific limitation is made here.

[0121] For example, the thickness of the first interface passivation layer on the bottom surface of the tower-like textured structure can be greater than or equal to 0.5 nm and less than or equal to 1.5 nm. For instance, the thickness of the first interface passivation layer on the bottom surface of the tower-like textured structure can be 0.5 nm, 0.6 nm, 0.8 nm, 1 nm, 1.2 nm, 1.3 nm, or 1.5 nm, etc. In this case, the thickness of the first interface passivation layer on the bottom surface of the tower-like textured structure is within the above range, which helps to prevent a low passivation effect on the semiconductor substrate due to a small thickness of the first interface passivation layer on the bottom surface of the tower-like textured structure. Furthermore, it also helps to prevent a high tunneling resistance due to a large thickness of the first interface passivation layer on the bottom surface of the tower-like textured structure. This helps to achieve a balance between the passivation effect and tunneling resistance of the portion of the first interface passivation layer on the bottom surface of the tower-like textured structure, thereby reducing the carrier recombination rate on the side of the tower-like textured structure while ensuring that the first doped silicon layer has a high carrier collection efficiency and reducing transmission losses.

[0122] For example, the thickness of the first interface passivation layer on the sidewall of the tower-like textured structure can be greater than or equal to 0.5 nm and less than or equal to 2 nm. For instance, the thickness of the first interface passivation layer on the sidewall of the tower-like textured structure can be 0.5 nm, 0.8 nm, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, or 2 nm, etc. In this case, the thickness of the first interface passivation layer on the sidewall of the tower-like textured structure is within the above range, which helps to prevent a low passivation effect due to a small thickness in this part; in addition, it also helps to prevent a high tunneling resistance in this part due to a large thickness of the first interface passivation layer on the sidewall of the tower-like textured structure. This helps to achieve a balance between the passivation effect and tunneling resistance of the portion of the first interface passivation layer on the sidewall of the tower-like textured structure, thereby reducing the carrier recombination rate on the side of the tower-like textured structure while ensuring that the first doped silicon layer has a high carrier collection efficiency and reducing transmission loss.

[0123] Step 3: As Figure 3 As shown, the first doped silicon glass layer is removed. Specifically, in practical applications, the first doped silicon glass layer can be removed using processes such as wet etching (e.g., using hydrofluoric acid solution).

[0124] It should be noted that, in some examples, when the first interface passivation layer formed in the second step is an intrinsic silicon layer, and the first interface passivation layer and the first doped silicon layer constitute a heterogeneous contact structure, the third step may also be omitted.

[0125] Step 4: As Figure 4 As shown, an insulating layer 16 is formed on the side of the first doped silicon layer 13 facing away from the semiconductor substrate 11. Specifically, the insulating layer 16 can be formed on the side of the first doped silicon layer facing away from the semiconductor substrate 11 using processes such as chemical vapor deposition. The material of the insulating layer 16 can include any insulating material with mask protection function, such as alumina and / or silicon nitride, as long as it can be applied to the manufacturing method provided in the embodiments of the present invention. The thickness of the insulating layer 16 can be set according to actual needs.

[0126] It is worth noting that the insulating layer can be directly formed on the side of the first doped silicon layer facing away from the semiconductor substrate. Because the insulating material used to fabricate the insulating layer (such as alumina or silicon nitride) may have passivation properties, it not only provides mask protection and insulation but also directly passivates the side of the first doped silicon layer facing away from the semiconductor substrate. This helps reduce surface defects on that side and further improves the conversion efficiency of the back-contact battery. The insulating layer can also be made of materials with hydrogen-filling capabilities, such as at least one of alumina and silicon nitride, for hydrogen implantation into the first doped silicon layer, especially when the first doped silicon layer is made of doped polycrystalline silicon, to improve the passivation effect of the first doped silicon layer.

[0127] Additionally, it should be noted that, as Figure 4 and Figure 5 As shown, while the insulating layer 16 is formed on one side of the first surface of the semiconductor substrate 11, insulating layers 16 are also formed on the side surface and at least a portion of the second surface of the semiconductor substrate 11. In some examples, the insulating layer 16 formed on the second surface of the semiconductor substrate 11 can be removed after its formation and before subsequent texturing. The insulating layer 16 formed on the side surface of the semiconductor substrate 11 can be entirely retained, partially retained, or completely removed.

[0128] Step 5: As Figure 6 As shown, the insulating layer is patterned to form an insulating mask pattern 15. Specifically, the patterning of the insulating layer can be achieved using photolithography combined with etching, laser irradiation, or chemical paste etching. After patterning, the remaining portion of the insulating layer forms the insulating mask pattern 15.

[0129] Step 6: As Figure 7As shown, the first interface passivation layer 12 and the first doped silicon layer 13 that are not covered by the insulating mask pattern 15 are removed.

[0130] In actual manufacturing processes, other processes such as laser etching or wet etching can be used to remove the first interface passivation layer and the first doped silicon layer that are not covered by the insulating mask pattern. After the removal operation, at least the portion of the first side of the semiconductor substrate exposed outside the insulating mask pattern, and the second side, are exposed (it can be understood that when removing the insulating layer formed on one side of the second side of the semiconductor substrate, the insulating layer formed on at least a portion of the side surface of the semiconductor substrate is also removed, and the area on the side surface without the corresponding insulating layer is also exposed). The etchant and etching conditions used in the wet etching process can be determined according to the actual application scenario, and are not specifically limited here.

[0131] It should be noted that the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern can be removed by an appropriate etching process after the insulating mask pattern is formed. Alternatively, the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern can be removed simultaneously with the patterning of the insulating layer to form the insulating mask pattern. This simplifies the process and improves the fabrication efficiency of back-contact solar cells. For example, a laser can be used to simultaneously remove part of the insulating layer and part of the first interface passivation layer and the first doped silicon layer to ultimately form the insulating mask pattern and the first interface passivation layer and the first doped silicon layer covered by the insulating mask pattern.

[0132] Furthermore, the aforementioned first surface may include a first region and a second region. And, within the first surface, the region covered by the first interface passivation layer and the first doped silicon layer is defined as the first region, and the region not covered by the first interface passivation layer and the first doped silicon layer is defined as the second region. Based on this, after removing the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern, the surface of the first region in the first surface can be flush with the surface of the second region. At this time, along the thickness direction of the semiconductor substrate, the portion of the semiconductor substrate corresponding to the second region also has a larger light absorption depth, which is beneficial for improving the conversion efficiency of the semiconductor substrate. Or, as... Figure 7As shown, the second region 24 may also include a groove, indicating that when removing the first interface passivation layer 12 and the first doped silicon layer 13 not covered by the insulating mask pattern 15, the portions of the first interface passivation layer 12 and the first doped silicon layer 13 located on the second region 24 have been completely removed, preventing short circuits. Simultaneously, the presence of the groove causes the surface of the second region 24 to be offset from the surface of the first region 23 along the thickness direction of the semiconductor substrate 11, thereby facilitating at least partial offsetting of the second interface passivation layer and the second doped silicon layer located on the second region 24 from the first interface passivation layer 12 and the first doped silicon layer 13 located on the first region 23, reducing the risk of leakage. Specifically, the depth of the groove is not specifically limited in this embodiment of the invention and can be determined according to the actual manufacturing process.

[0133] Step 7: As Figure 8 and Figure 9 As shown, the surface of the first side exposed outside the insulating mask pattern 15 and the second side are texturized.

[0134] Specifically, the above texturing process can be performed using techniques such as wet etching. The processing solution and conditions for texturing can be determined based on the actual application scenario, and are not specifically limited here. Figure 8 As shown, after the texturing process, at least the surface of the first side exposed outside the insulating mask pattern 15 and the second side form a texturized surface. Specifically, as... Figure 8 As shown, if the insulating mask pattern 15 covers various regions on the side surface of the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11, then after the texturing process, the surface of the first surface exposed outside the insulating mask pattern 15 and the second surface form a textured surface. Figure 9 As shown, if the insulating mask pattern 15 does not cover the side surface of the semiconductor substrate 11, or only covers a portion of the side surface of the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11, then after the above texturing process, not only will the surface of the area outside the insulating mask pattern 15 on the first side and the second side form a textured surface, but the surface of the area on the side surface of the semiconductor substrate 11 that is not covered by the insulating mask pattern 15 will also form a textured surface.

[0135] In actual manufacturing processes, in some examples, the exposed surfaces of the semiconductor substrate can be polished and cleaned using an alkaline solution. This alkaline solution can be sodium hydroxide or potassium hydroxide, etc. The concentration of the alkaline solution can be 0.1% to 3%. Next, cleaning is performed in a mixed solution comprising KOH, H₂O₂, and H₂O. The ratio of KOH, H₂O₂, and H₂O in the mixed solution is (1:2:5), the cleaning temperature is 65°C, and the cleaning time is 360 s. Then, texturing is performed on the first surface of the semiconductor substrate exposed outside the insulating mask pattern and on the second surface. For example, a solution system of TS53V01:KOH:DIW is used for texturing. The mass percentage concentration of TS53V01 is 0.2% to 1.5%, the mass percentage concentration of KOH is 1% to 3%, and the texturing temperature is 75°C to 85°C. Optionally, a mass percentage concentration of TS53V01 of 0.5% to 1% and a mass percentage concentration of KOH of 1.5% to 2% are used. Then, it was washed again in a mixed solution containing KOH, H2O2, and H2O. The washing temperature was 65℃, and the washing time was 300s.

[0136] It should be noted that the depth of the groove in the second region of the first surface described above is also affected by the texturing process. Optionally, when the surface of the first region is polished and the bottom surface of the groove is textured, the distance from the surface of the semiconductor substrate in the first region to the bottom surface of the groove can be greater than or equal to 2 μm and less than or equal to 8 μm. Specifically, this distance refers to the distance between the surface of the semiconductor substrate in the first region and the base of the pyramid of the textured structure in the bottom surface of the groove. For example, the distance from the surface of the semiconductor substrate in the first region to the bottom surface of the groove can be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 5 μm, 6 μm, 7 μm, or 8 μm, etc. In this case, it is advantageous to prevent the first and second doped silicon layers from being misaligned along the thickness direction of the semiconductor substrate due to a small distance between the surface of the semiconductor substrate in the first region and the bottom surface of the groove, thus ensuring a low risk of leakage between them. Secondly, during the texturing process on the bottom surface of the groove, the semiconductor substrate needs to be etched. Therefore, the distance between the surface of the semiconductor substrate in the first region and the bottom surface of the groove also affects the size of the textured structure on the bottom surface. Based on this, keeping the distance between the surface of the semiconductor substrate in the first region and the bottom surface of the groove within the aforementioned range can also prevent the bottom surface of the groove and the textured structure formed on the second surface from being too small due to a small distance, ensuring a high light trapping effect on the second surface. At the same time, it is beneficial to increase the specific surface area of ​​the side of the second doped silicon layer facing away from the semiconductor substrate, further reducing the contact loss between the second doped silicon layer and the corresponding conductive material. In addition, it can also prevent a large etching depth of the semiconductor substrate at the groove due to a large distance between the surface of the semiconductor substrate in the first region and the bottom surface of the groove, ensuring that each part of the semiconductor substrate has a large light absorption depth, thereby enabling the back contact cell to have a high conversion efficiency.

[0137] Step 8: As Figure 10 and Figure 11 As shown, the insulating mask pattern is removed. Specifically, processes such as wet etching can be used to remove the insulating mask pattern. The etching agent used to remove the insulating mask pattern can be determined based on the material of the insulating mask pattern and the actual requirements; no specific limitations are made here.

[0138] For example, when the insulating mask pattern is made of silicon nitride, the insulating mask pattern can be removed using hydrofluoric acid with a concentration of 5% wt to 10% wt. The removal time can be, for example, 600 s.

[0139] It should be noted that in some examples, step seven can be performed first, followed by step eight; in another example, steps seven and eight can be performed simultaneously, that is, removing the insulating mask pattern while texturing is being done.

[0140] Step 9: As Figure 12As shown, a first passivation layer 17 is formed on the second surface of the semiconductor substrate 11, and a first passivation layer 17 is also formed on the first surface of the semiconductor substrate 11.

[0141] In actual manufacturing processes, chemical vapor deposition (such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) processes can be used to form the aforementioned first passivation layer. The material of this first passivation layer can be selected according to actual needs and is not specifically limited here. For example, the first passivation layer may include aluminum oxide (Al₂O₃). x O) layer. In addition, such as Figure 12 As shown, while the first passivation layer 17 is formed on the second and first surfaces of the semiconductor substrate 11, the first passivation layer 17 can also be formed on the side surface of the semiconductor substrate 11.

[0142] Step 10: As Figure 13 As shown, an antireflection layer is formed on the second surface of the semiconductor substrate 11 to reduce the reflectivity of the back contact battery on one side of the second surface, thereby further improving the conversion efficiency of the back contact battery. The material of the antireflection layer 18 can be determined according to the actual application scenario, and is not specifically limited here. For example, the antireflection layer 18 may include a silicon nitride layer. Secondly, when forming the antireflection layer 18 on the second surface of the semiconductor substrate 11, it is also possible to form the antireflection layer 18 on the side surface of the semiconductor substrate 11 and on at least a portion of the first surface of the semiconductor substrate 11.

[0143] Step 11: Anneal the first passivation layer to activate its passivation effect. During annealing, the presence of the first passivation layer helps prevent hydrogen from escaping from the first doped silicon layer. Simultaneously, hydrogen from the first passivation layer can be injected into the first doped silicon layer, reducing the number of surface defects on the side of the first doped silicon layer facing away from the semiconductor substrate, thus ensuring a high passivation effect on that side.

[0144] Step 12: After annealing and before forming the stacked second interface passivation layer and second doped silicon layer, as follows... Figure 13 and Figure 14 As shown, the antireflective layer 18 deposited around one side of the first surface and the first passivation layer 17 formed on one side of the first surface need to be removed sequentially. At this time, the portions of the first passivation layer 17 and the antireflective layer 18 deposited around the side of the semiconductor substrate 11 can be entirely or partially retained. This removal operation can be performed in a chain cleaning apparatus. After the removal operation and before subsequent operations, the semiconductor substrate 11 can be subjected to metal ion cleaning (i.e., RCA cleaning) to remove contamination and minor scratches caused to the semiconductor substrate 11 within the chain cleaning apparatus. In some embodiments, this cleaning operation may not be performed.

[0145] In some embodiments, step 12 may be omitted.

[0146] Step 13: As Figure 15 As shown, along the thickness direction of the semiconductor substrate 11, a second interface passivation layer 19 and a second doped silicon layer 20 are sequentially formed on the first surface. The second doped silicon layer 20 and the first doped silicon layer 13 have opposite conductivity types.

[0147] In the actual manufacturing process, processes such as plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) can be used to form a second interface passivation layer and a second doped silicon layer stacked sequentially on the first surface. The materials of the second interface passivation layer and the second doped silicon layer can be selected according to actual requirements.

[0148] For example, the second interface passivation layer can be a tunneling passivation layer, and the material of the tunneling passivation layer can include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium carbonitride nitride. Secondly, when the second interface passivation layer is a tunneling passivation layer, the second doped silicon layer includes a doped crystalline silicon layer. Specifically, the second doped silicon layer can include a doped polycrystalline silicon layer and / or a doped monocrystalline silicon layer.

[0149] For example, the second interface passivation layer can be an intrinsic silicon layer. The second interface passivation layer and the second doped silicon layer can form a heterogeneous contact structure. In this case, the second interface passivation layer and the second doped silicon layer have a high passivation effect on the corresponding surface of the semiconductor substrate, further reducing the carrier recombination rate on the surface of that region and improving the conversion efficiency of the manufactured back contact cell. The material of the second interface passivation layer and / or the second doped silicon layer can include at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0150] It should be noted that, as Figure 15 and Figure 16 As shown, during the formation of the second interface passivation layer 19 and the second doped silicon layer 20, a stacked second interface passivation layer 19 and second doped silicon layer 20 are also formed on the side surface of the semiconductor substrate 11 and at least a portion of the second surface. In some examples, such as Figure 19 As shown, processes such as wet etching can be used to remove at least a portion of the second interface passivation layer 19 and the second doped silicon layer 20 deposited around one side of the second surface of the semiconductor substrate 11. The portions of the second interface passivation layer 19 and the second doped silicon layer 20 deposited around the side of the semiconductor substrate 11 can be entirely retained, partially retained, or completely removed.

[0151] As for the conductivity type of the second doped silicon layer, it can be set according to actual needs, as long as the conductivity types of the first doped silicon layer and the second doped silicon layer are opposite.

[0152] Optionally, when the first interface passivation layer is a tunneling passivation layer, the first doped silicon layer is doped polycrystalline silicon, and the second interface passivation layer is an intrinsic silicon layer, forming a heterogeneous contact structure, the conductivity type of the first doped silicon layer can be N-type, and the conductivity type of the second doped silicon layer can be P-type. In this case, compared with P-type doped amorphous silicon, P-type doped microcrystalline silicon, or P-type nanocrystalline silicon materials, P-type doped polycrystalline silicon materials have higher contact resistance with the electrode and poorer field passivation effect. Therefore, setting the conductivity type of the first doped silicon layer to N-type and the conductivity type of the second doped silicon layer to P-type can further improve the field passivation effect of the first doped silicon layer, while reducing the contact resistance between the first doped silicon layer and the electrode, which is beneficial to improving the electrical performance of the manufactured back contact battery.

[0153] The thickness of the second interface passivation layer and the second doped silicon layer can be set according to actual needs, and no specific limit is made here.

[0154] For example, the thickness of the second interface passivation layer can be greater than or equal to 3 nm and less than or equal to 16 nm. For instance, the thickness of the second interface passivation layer can be 3 nm, 5 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, or 16 nm, etc. In this case, it is understood that after texturing, or simultaneously with texturing, the insulating mask pattern is removed, and the second passivation layer and the second doped silicon layer formed on the first surface are directly formed on the semiconductor substrate and the first doped silicon layer. At this time, the overlapping portions of the second doped silicon layer and the first doped silicon layer are separated only by the second interface passivation layer. Based on this, when the thickness of the second interface passivation layer is within the above range, a larger thickness of the second interface passivation layer is beneficial for enhancing the isolation effect of the second interface passivation layer between the first doped silicon layer and the second doped silicon layer overlapping along the thickness direction of the semiconductor substrate, reducing the risk of forward leakage, and improving the conversion efficiency of the manufactured back contact battery. Furthermore, it can also prevent a large contact resistance due to an excessively large thickness of the second interface passivation layer, reducing transmission loss.

[0155] Furthermore, the thickness of each portion of the second interface passivation layer can be the same. In this case, each portion of the second interface passivation layer has a high passivation effect.

[0156] Or, such as Figure 17As shown, the first surface may include a first region 23 and a second region 24. The second region 24 includes a groove. A first interface passivation layer 12 and a first doped silicon layer 13 are located in the first region 23. A second interface passivation layer 19 and a second doped silicon layer 20 are located in the second region 24, and extend to cover a portion of the first interface passivation layer 12 and the first doped silicon layer 13. The surface of the first region 23 is a polished surface, and the bottom surface of the groove is a textured surface. Furthermore, the thickness of the second interface passivation layer 19 on the textured surface can be less than the thickness of the second interface passivation layer 19 on the polished surface. In this case, the presence of the groove causes the surface of the second region 24 to be offset from the surface of the first region 23 along the thickness direction of the semiconductor substrate 11, thereby facilitating at least partial offset between the second interface passivation layer 19 and the second doped silicon layer 20 located on the second region 24 and the first interface passivation layer 12 and the first doped silicon layer 13 located on the first region 23, reducing the risk of leakage. Furthermore, when the thickness of the second interface passivation layer 19 on the textured surface is small, this portion has a lower transmission resistance, which helps reduce transmission loss. Conversely, when the thickness of the second interface passivation layer 19 on the polished surface is larger, it helps improve the passivation and insulation effect of the portion on the polished surface, thereby reducing forward leakage and improving the conversion efficiency of the manufactured back contact battery. In this case, the thickness difference between different portions of the second interface passivation layer 19 can be set according to the surface roughness of the first region 23 and the second region 24, as well as actual requirements, and is not specifically limited here.

[0157] As for the second doped silicon layer, optionally, the thickness of the second doped silicon layer can be greater than or equal to 3 nm and less than or equal to 50 nm. For example, the thickness of the second doped silicon layer can be 3 nm, 5 nm, 8 nm, 10 nm, 20 nm, 30 nm, 40 nm or 50 nm, etc.

[0158] In this design, the thickness of each portion of the second doped silicon layer can be the same. In this case, each portion of the second doped silicon layer has a high field passivation effect.

[0159] Or, such as Figure 16As shown, when the first surface includes the first region 23 and the second region 24, the thickness of the second doped silicon layer 20 on the textured surface can be less than the thickness of the second doped silicon layer 20 on the polished surface. In this case, the textured surface has a larger specific surface area than the polished surface. Within the same formation range, the contact area between the portion of the second doped silicon layer 20 on the textured surface and the semiconductor substrate 11 is larger, while the contact area between the portion of the second doped silicon layer 20 on the polished surface and the semiconductor substrate 11 is smaller. Based on this, when the thickness of the second doped silicon layer 20 on the textured surface is smaller, after ensuring sufficient contact area between the portion of the second doped silicon layer 20 on the textured surface and the semiconductor substrate 11, space can be reserved for reducing the thickness of this portion. This ensures high carrier collection efficiency while reducing the amount of consumables used in manufacturing the portion of the second doped silicon layer 20 on the textured surface. In addition, the larger thickness of the second doped silicon layer 20 on the polished surface results in a higher field passivation effect, reducing carrier recombination. In this case, the thickness difference between different parts of the second doped silicon layer 20 can be set according to the surface roughness of the first region 23 and the second region 24, as well as actual needs, and no specific limitation is made here.

[0160] In addition, in some examples, in actual applications, when the first surface includes the first region and the second region, the second region includes a groove, and the second doped silicon layer is a doped amorphous silicon layer, after the second interface passivation layer and the second doped silicon layer are sequentially formed on the first surface along the thickness direction of the semiconductor substrate, the manufacturing method of the back contact cell may further include a fourteenth step: laser irradiating the second doped silicon layer located on the bottom surface of the groove to crystallize the second doped silicon layer.

[0161] When the above technical solution is adopted, the second doped silicon layer located on the bottom surface of the groove is irradiated with a laser. Under the irradiation of a high-temperature laser, the crystallinity of at least a portion of the second doped silicon layer located on the bottom surface of the groove is increased. Furthermore, it is understood that the lower the crystallinity of the semiconductor layer, the smaller the grains in the semiconductor layer, even exhibiting the disorder of amorphous silicon material. The smaller the grains in the semiconductor layer, the fewer the interfaces between the grains, resulting in a higher resistance at the grain interfaces. Therefore, increasing the crystallinity of at least a portion of the second doped silicon layer located on the bottom surface of the groove is beneficial for improving the conductivity of at least a portion of the second doped silicon layer located on the bottom surface of the groove, reducing the transmission loss between the second doped silicon layer and the corresponding conductive material (such as a transparent conductive layer or conductive electrode), and improving the conversion efficiency of the manufactured back contact battery.

[0162] It should be noted that, in the embodiments of the present invention, a higher degree of crystallization can refer to a higher crystallinity, a larger grain size, and / or a greater number of grains. For example, when the second doped silicon layer is a doped amorphous silicon layer (which may contain a small amount of nanocrystalline silicon, but the content of this nanocrystalline silicon is very small, for example, less than 5%, as is known in the art), at least a portion of the second doped silicon layer located on the bottom surface of the trench will generate lattice-ordered grains, thus increasing its degree of crystallization. The portion of the second doped silicon layer corresponding to the first region has a lower degree of crystallization; this portion with a lower degree of crystallization is still amorphous silicon material and does not contain grains generated after laser or other treatments. In this case, the conductivity of at least a portion of the second doped silicon layer located on the bottom surface of the trench will be higher, which helps to reduce the transmission loss of at least a portion of the second doped silicon layer located on the bottom surface of the trench and reduce the contact resistance between at least a portion of the second doped silicon layer located on the bottom surface of the trench and the transparent conductive layer. The portion of the second doped silicon layer corresponding to the first region has a lower degree of crystallization. This results in a relatively lower conductivity for this portion, which helps reduce the forward leakage current between the second doped silicon layer and the first doped silicon layer, further improving the conversion efficiency of the back-contact battery. Specifically, after crystallization treatment, the crystal type of the second doped silicon layer can remain unchanged, but the degree of crystallization can increase. For example, before and after the crystallization treatment, the crystal type of the second doped silicon layer can both be microcrystalline silicon, with the degree of crystallization increasing from 20% before crystallization treatment to 80% after. Alternatively, the crystal type of the second doped silicon layer can also change after crystallization treatment. For example, before the crystallization treatment, the crystal type of the second doped silicon layer can be amorphous silicon, while after crystallization treatment, the crystal type changes to nanocrystalline silicon or microcrystalline silicon.

[0163] In addition, in the actual manufacturing process, the above-mentioned step fourteen can be omitted.

[0164] Step 15: As Figure 17 As shown, a portion of the second interface passivation layer 19 and the second doped silicon layer 20 located on the first interface passivation layer 12 and the first doped silicon layer 13 are removed to expose a portion of the first interface passivation layer 1212 and the first doped silicon layer 13.

[0165] In actual manufacturing processes, etching methods such as laser etching, etchant etching, or a combination of photolithography and wet etching can be used to selectively etch the stacked second interface passivation layer and the second doped silicon layer. It is understandable that after selective etching, the remaining portions of the second interface passivation layer and the second doped silicon layer will affect the carrier collection efficiency of the second doped silicon layer. Furthermore, the first doped silicon layer needs to be electrically connected to the corresponding conductive material through openings within the second interface passivation layer and the second doped silicon layer to export the collected carriers. The carriers transported by the conductive material electrically connected to the first doped silicon layer are of the opposite conductivity type to those of the second doped silicon layer. Therefore, the width of the openings in the second interface passivation layer and the second doped silicon layer also affects the formation of the conductive material electrically connected to the first doped silicon layer. Thus, the size of the openings can be determined based on the requirements of the carrier collection efficiency of the second doped silicon layer and the manufacturing precision and range of the conductive material electrically connected to the first doped silicon layer in the actual application scenario; no specific limitations are made here.

[0166] For example, the width of the opening region of the second interface passivation layer and the second doped silicon layer can be greater than or equal to 250 μm and less than or equal to 400 μm. For instance, the width of the opening region can be 250 μm, 260 μm, 280 μm, 300 μm, 320 μm, 340 μm, 360 μm, 380 μm, or 400 μm, etc. In this case, compared with the existing back contact battery where the width of the opening region of the second interface passivation layer and the second doped silicon layer is less than 250 μm, the back contact battery formed by the manufacturing method provided by the present invention has a larger opening region for exposing the first doped silicon layer. This facilitates a larger formable range for the corresponding conductive material electrically connected to the first doped silicon layer while preventing short circuits, thereby increasing the contact area between the first doped silicon layer and the corresponding conductive material, reducing transmission loss, and improving the electrical reliability of the manufactured back contact battery. Secondly, when the width of the opening region is less than or equal to 400 μm, a larger portion of the second interface passivation layer and the second doped silicon layer is retained after the opening operation. This reduces the amount of etching while ensuring that the second interface passivation layer and the second doped silicon layer have a certain area ratio on the first side, thus ensuring that the second doped silicon layer has a high current collection efficiency.

[0167] Furthermore, in some examples, during the actual manufacturing process, when using a laser to remove portions of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer, the laser can be used to process the edge portion of the opening region of the second doped silicon layer, thereby forming a porous structure within the edge portion of the second doped silicon layer. Specifically, by adjusting the laser etching parameters, the edge portion of the second doped silicon layer near the opening region is heated under the action of a high-temperature laser, so that after selective etching, a porous structure is formed within the edge portion of the second doped silicon layer. In this case, it is understood that the porous structure is a hollow structure. Therefore, when a porous structure is formed within the edge portion of the second doped silicon layer, the edge structure of the second doped silicon layer becomes loose, which can reduce the leakage risk between the edge portion of the second doped silicon layer and the first doped silicon layer, improving the electrical reliability of the back contact battery. In addition, the presence of the porous structure can also increase the undulation of the edge portion of the stacked second interface passivation layer and the second doped silicon layer, thereby enhancing the light trapping effect in this part and helping to improve the bifaciality of the back contact battery. Specifically, the distribution and size of the holes in the above-mentioned hole structure can be determined according to the actual manufacturing process, and no specific limitations are made here.

[0168] For example, the width of the portion with the porous structure in the second doped silicon layer can be greater than or equal to 0.1 μm and less than or equal to 20 μm. For instance, the width of the portion with the porous structure in the second doped silicon layer can be 0.1 μm, 0.3 μm, 0.5 μm, 0.8 μm, 1 μm, 2 μm, 5 μm, 10 μm, 15 μm, or 20 μm, etc. In this case, when the width of the portion with the porous structure in the second doped silicon layer is within the above range, the carrier flow between the first and second doped silicon layers can be effectively reduced, thus reducing leakage current.

[0169] For example, from a top view of the back contact battery, the shape of the hole structure can be at least one of a circle, an ellipse, or an irregular shape. Furthermore, when the hole structure is at least one of a circle, an ellipse, or an irregular shape, the hole structure can enhance insulation and reduce leakage.

[0170] Step 16: As Figure 18As shown, a transparent conductive layer 21 is formed covering the side of the first doped silicon layer 13 and the second doped silicon layer 20 facing away from the semiconductor substrate 11. A through-hole isolation trench 22 is formed within the transparent conductive layer 21 to disconnect the portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 from the portion corresponding to the second doped silicon layer 20. Specifically, the embodiments of the present invention do not specifically limit the material and thickness of the transparent conductive layer 21, nor the width of the isolation trench 22, as long as they can be applied to the manufacturing method provided in the embodiments of the present invention. Furthermore, the second doped silicon layer and the second interface passivation layer corresponding to the isolation trench can be removed or not. In the case of removing the second doped silicon layer and the second interface passivation layer corresponding to the isolation trench, the portion of the second doped silicon layer near the opening region can also have the aforementioned hole structure; the beneficial effects can be referred to the preceding text and will not be repeated here.

[0171] The transparent conductive layer can be formed using processes such as physical vapor deposition (PVD), and then isolation trenches can be created in the transparent conductive layer using processes such as laser etching or etchant etching. Specifically, when using etchant etching, the etchant can be printed first, and then cured and etched. Next, the etchant needs to be cleaned. Furthermore, the location of the isolation trenches can be determined based on actual needs and manufacturing precision. Optionally, the isolation trenches can be located in the region where the first and second doped silicon layers overlap along the thickness direction of the semiconductor substrate.

[0172] In addition, such as Figure 18 As shown, the thickness of each part of the transparent conductive layer 21 can be approximately the same. Alternatively, the thickness of the edge portion of the transparent conductive layer adjacent to the isolation trench 22 can gradually decrease along the direction close to the isolation trench 22. In this case, the thickness of the transparent conductive layer near both sides of the isolation trench 22 is smaller. At this time, the thickness of the two parts of the transparent conductive layer used for transporting opposite charge carriers is smaller (and the facing area is also smaller), which helps to reduce the risk of leakage and improve the electrical reliability of the back contact battery. The width of the region where the thickness gradually decreases in the transparent conductive layer and the magnitude of the gradual decrease in thickness can be determined according to the etching parameters when the isolation trench 22 is formed in the transparent conductive layer during the actual manufacturing process, and are not specifically limited here. Furthermore, this setting also facilitates stress release between other structures in the back contact battery and the transparent conductive layer, avoiding problems such as edge chipping or detachment due to excessive stress during the formation of the transparent conductive layer, thus improving the structural reliability of the manufactured back contact battery.

[0173] Furthermore, if the back contact battery also includes a transparent conductive layer and the first doped silicon layer includes a doped crystalline silicon layer, the thickness of the first doped silicon layer can be adjusted to reduce the amount of consumables used for the first doped silicon layer.

[0174] Optionally, if the back contact cell also includes a transparent conductive layer and the first doped silicon layer includes a doped crystalline silicon layer, the thickness of the first doped silicon layer can be greater than or equal to 30 nm and less than or equal to 140 nm. For example, the thickness of the first doped silicon layer can be 30 nm, 40 nm, 50 nm, 60 nm, 80 nm, 100 nm, 120 nm, 130 nm, or 140 nm, etc. With this configuration, when the back contact cell includes a transparent conductive layer and the first doped silicon layer includes a doped crystalline silicon layer, since the transparent conductive layer can be responsible for collecting and discharging charge carriers, the thickness requirement of the first doped silicon layer can be appropriately reduced without reducing the charge carrier collection efficiency. Based on this, when the thickness of the first doped silicon layer is within the above range, the thickness of the first doped silicon layer is relatively small, which helps to reduce its own parasitic absorption and further improve the working efficiency of the manufactured back contact cell. In addition, since the thickness of the first doped silicon layer is small, the formation time of the first doped silicon layer can be reduced, improving the manufacturing efficiency.

[0175] Of course, when the back contact battery does not include the above-mentioned transparent conductive layer, or when the back contact battery includes the transparent conductive layer, the thickness of the first doped silicon layer can be set to other suitable values ​​according to different application scenarios.

[0176] In addition, in some examples, such as Figure 18 As shown, the second interface passivation layer 19, the second doped silicon layer 20, and the transparent conductive layer 21 disposed on the second doped silicon layer 20, stacked sequentially, all cover a portion of the stacked first interface passivation layer 12 and first doped silicon layer 13 away from the semiconductor substrate 11. And / or, the portion of the first interface passivation layer 12, the first doped silicon layer 13, the second interface passivation layer 19, and the second doped silicon layer 20 stacked along the thickness direction of the semiconductor substrate 11 is an overlapping region. In the overlapping region, the second interface passivation layer 19 is in direct contact with the first doped silicon layer 13. In the overlapping region, the second doped silicon layer 20 can be electrically isolated from the first doped silicon layer 13 through the second interface passivation layer 19. Alternatively, at least part of the overlapping region can also be a reverse leakage region, and in the reverse leakage region, the second doped silicon layer 20 is electrically connected to the first doped silicon layer 13 through the second interface passivation layer 19. In this case, within the reverse leakage region, the second doped silicon layer 20 can be electrically connected to the second interface passivation layer 19 and the first doped silicon layer 13, which has the opposite conductivity type, to form a built-in diode structure with a lower reverse breakdown voltage, thereby reducing the risk of hot spots on the back contact battery.

[0177] Specifically, along the length of the overlapping region, the reverse leakage region can be continuously or discontinuously distributed. It is understandable that the width of the reverse leakage region along the width of the overlapping region and the length of its continuous distribution along the length of the overlapping region affect the magnitude of the leakage current. Specifically, the larger the width of the reverse leakage region and / or the longer its continuous distribution, the larger the leakage current and the lower the hot spot risk, but the larger the forward leakage current will also be. Based on this, the width of the reverse leakage region and the length of its continuous distribution can be determined according to the hot spot risk and conversion efficiency requirements of the back-contact battery in the actual application scenario; no specific limitations are made here.

[0178] Step 17: As Figure 19 As shown, a first electrode is formed on the portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13, and a second electrode is formed on the portion of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0179] For example, the first and second electrodes described above can be formed using processes such as screen printing and electroplating. Specifically, the materials of the first and second electrodes can include any conductive material such as silver, aluminum, copper, nickel, or titanium, as long as it can be applied to the manufacturing method provided in the embodiments of the present invention.

[0180] It should be noted that, in addition to forming the insulating mask pattern using the method described above, the method of forming the insulating mask pattern in Embodiment 1 of the present invention may also include at least the following two:

[0181] The first method involves forming a first doped silicon glass layer on a portion of the first doped silicon layer away from the semiconductor substrate, simultaneously with the formation of the first doped silicon layer. Based on this, forming an insulating mask pattern on the portion of the first doped silicon layer away from the semiconductor substrate can include: Figure 20 and Figure 21 As shown, the first doped silicon glass layer 14 is patterned to form an insulating mask pattern 15. In this case, compared to the insulating mask pattern formation process described above, steps three and four can be omitted in this first method. Step five described above is replaced by patterning the first doped silicon glass layer.

[0182] Specifically, such as Figure 20 and Figure 21As shown, the first doped silicon glass layer 14 can be patterned by laser irradiation. The density of the area of ​​the first doped silicon glass layer 14 irradiated by the laser decreases, making it easier to etch away. Conversely, the area of ​​the first doped silicon glass layer 14 not irradiated by the laser has higher density and provides mask protection. Of course, other methods can also be used to pattern the first doped silicon glass layer 14. In this case, the first doped silicon glass layer 14 can be formed simultaneously with the first doped silicon layer 13, eliminating the need for an additional deposition process to form the insulating mask pattern 15. This simplifies the manufacturing process of the back contact battery and improves its manufacturing efficiency.

[0183] The second method involves forming a first doped silicon glass layer on a portion of the first doped silicon layer away from the semiconductor substrate, simultaneously with the formation of the first doped silicon layer. Based on this, forming an insulating mask pattern on the portion of the first doped silicon layer away from the semiconductor substrate may also include: such as... Figures 22 to 24 As shown, an insulating layer 16 is formed on the side of the first doped silicon glass layer 14 facing away from the semiconductor substrate 11; and the first doped silicon glass layer 14 and the insulating layer 16 are patterned to form an insulating mask pattern 15. In this second method, the third step can be omitted compared to the insulating mask pattern formation process described above. Furthermore, the fifth step described above needs to be replaced by patterning the first doped silicon glass layer and the insulating layer.

[0184] Specifically, such as Figures 22 to 24 As shown, an insulating layer can be formed on the side of the first doped silicon glass layer 14 away from the semiconductor substrate 11 using processes such as chemical vapor deposition. The material of this insulating layer can include insulating materials with mask protection functions, such as alumina and / or silicon nitride. The thickness of the insulating layer can be set according to actual needs. Next, the first doped silicon glass layer 14 and the insulating layer can be patterned using processes such as photolithography combined with etching, laser irradiation, or chemical paste etching. In this case, compared to a single-layer insulating mask pattern 15, the insulating mask pattern 15 includes not only the patterned first doped silicon glass layer 14 but also the patterned insulating layer, which helps to improve the protective effect of the insulating mask pattern 15.

[0185] Furthermore, in some embodiments, step eight described above may not be performed during the actual manufacturing process. In other words, as... Figure 25As shown, after removing the first interface passivation layer 12 and the first doped silicon layer 13 that are not covered by the insulating mask pattern 15, and before forming the stacked second interface passivation layer 19 and the second doped silicon layer 20, the insulating mask pattern 15 is not removed. At this time, the presence of the insulating mask pattern 15 can separate the first doped silicon layer 13 and the second doped silicon layer 20 along the thickness direction of the semiconductor substrate 11, suppressing forward leakage current, reducing the thickness requirement of the second interface passivation layer 19, reducing the transmission resistance of the second interface passivation layer 19, reducing transmission loss, and improving the carrier collection efficiency of the second doped silicon layer 20, thereby improving the conversion efficiency of the back contact cell.

[0186] In step nine, without performing step eight, the first passivation layer may be formed only on the second surface of the semiconductor substrate. Alternatively, the first passivation layer may be formed on both the first and second surfaces of the semiconductor substrate.

[0187] In some examples, where the first doped silicon layer is a doped polycrystalline silicon layer, the back contact cell may further include an amorphous silicon layer disposed on the side of the first doped silicon layer facing away from the semiconductor substrate. In this case, the amorphous silicon layer can passivate the side of the first doped silicon layer facing away from the semiconductor substrate, reducing the number of surface defects on this side and improving the conversion efficiency of the back contact cell. Furthermore, the presence of the amorphous silicon layer can prevent the etchant used to etch the second interface passivation layer and the second doped silicon layer from affecting the first doped silicon layer, further improving the formation quality of the first doped silicon layer. Furthermore, since the work function difference between the amorphous silicon layer and the transparent conductive layer is smaller than that between the doped polycrystalline silicon layer and the transparent conductive layer, meaning the contact barrier between the amorphous silicon layer and the transparent conductive layer is smaller than that between the doped polycrystalline silicon layer and the transparent conductive layer, the contact resistance between the amorphous silicon layer and the transparent conductive layer is smaller than that between the doped polycrystalline silicon layer and the transparent conductive layer. Therefore, compared to the first doped silicon layer directly contacting the transparent conductive layer, setting an amorphous silicon layer on the side of the first doped silicon layer away from the semiconductor substrate can achieve more reasonable bandgap matching, reduce contact resistance, and enable the back contact battery to effectively convert sunlight into electrical energy, thereby improving the photoelectric conversion efficiency of the back contact battery.

[0188] Specifically, the aforementioned amorphous silicon layer is formed when the second interface passivation layer and the second doped silicon layer are removed by laser. The high-temperature laser modifies the surface of the first doped silicon layer, resulting in the amorphous silicon layer. Furthermore, the amorphous silicon layer can be located on a portion of the bottom of the opening region of the second interface passivation layer and the second doped silicon layer, or it can cover all areas at the bottom of the opening region.

[0189] In addition, the amorphous silicon layer can be continuously distributed in the opening region of the second interface passivation layer and the second doped silicon layer, and is disposed on the side of the first doped silicon layer away from the semiconductor substrate; or it can be distributed intermittently, for example, in a dispersed dotted distribution.

[0190] Example 2

[0191] This embodiment 2 only details the steps that differ from those in embodiment 1. For steps that are the same, please refer to the explanation of embodiment 1 above; these will not be repeated in embodiment 2. The difference between embodiment 2 and embodiment 1 is that in step eight, the first passivation layer formed in embodiment 2 includes an intrinsic silicon passivation layer, and the antireflection layer is formed after the formation of the stacked second interface passivation layer and the second doped silicon layer. Embodiment 2 will be described in detail below:

[0192] Step 1: Provide a semiconductor substrate. The semiconductor substrate has a first side and a second side facing each other.

[0193] Step 2: As Figure 2 As shown, along the thickness direction of the semiconductor substrate 11, a first interface passivation layer 12 and a first doped silicon layer 13 are sequentially formed on the first surface of the semiconductor substrate 11.

[0194] Step 3: As Figure 3 As shown, the first doped silicon glass layer is removed.

[0195] Step 4: As Figure 4 and Figure 5 As shown, an insulating layer 16 is formed on the side of the first doped silicon layer 13 that is away from the semiconductor substrate 11.

[0196] Step 5: As Figure 6 As shown, the insulating layer is patterned to form an insulating mask pattern 15.

[0197] Step 6: As Figure 7 As shown, the first interface passivation layer 12 and the first doped silicon layer 13 that are not covered by the insulating mask pattern 15 are removed.

[0198] Step 7: As Figure 8 and Figure 9 As shown, the surface of the first side exposed outside the insulating mask pattern 15 and the second side are texturized.

[0199] In the manufacturing method provided in Example 2, the operations in steps one through seven are the same as those in steps one through seven of the manufacturing method provided in Example 1, and can be referred to the description in Example 1 above, which will not be repeated here. After the texturing process, the insulating mask pattern 15 in the manufacturing method provided in Example 2 is retained and is not removed.

[0200] Step 8: As Figure 26 As shown, a first passivation layer 17 is formed on the second surface of the semiconductor substrate 11. The first passivation layer 17 includes an intrinsic silicon passivation layer. In this case, the intrinsic silicon passivation layer has a high hydrogen content, which allows the first passivation layer 17 to have a high passivation effect on the second surface of the semiconductor substrate 11, further improving the conversion efficiency of the manufactured back contact battery. During annealing, the first passivation layer can perform hydrogen implantation (i.e., hydrogen replenishment) on the first doped silicon layer, thereby improving the passivation effect of the first doped silicon layer. Furthermore, the intrinsic silicon passivation layer is manufactured at a relatively low temperature, eliminating the need for high-temperature annealing activation, which helps reduce the manufacturing cost of the back contact battery.

[0201] In addition, in step eight of the manufacturing method provided in Example 2, the first passivation layer may be formed only on the second surface. Alternatively, while forming the first passivation layer on one side of the second surface, the first passivation layer may also be deposited around the side surface of the semiconductor substrate and at least a portion of the area on the first surface.

[0202] Step 9: As Figure 27 As shown, along the thickness direction of the semiconductor substrate 11, a second interface passivation layer 19 and a second doped silicon layer 20 are formed sequentially on the first surface. The second doped silicon layer 20 and the first doped silicon layer 13 have opposite conductivity types.

[0203] In the manufacturing method provided in Example 2, the operation of the ninth step is the same as that of the manufacturing method provided in Example 1, and can be referred to the description in Example 1 above, which will not be repeated here. Furthermore, when the first passivation layer is an intrinsic silicon passivation layer and the second interface passivation layer is an intrinsic silicon layer, the manufacturing method provided in this embodiment of the invention does not specifically limit the formation order of the first passivation layer and the second interface passivation layer. It is permissible to form the first passivation layer first, followed by the second interface passivation layer; or it is permissible to form the second interface passivation layer first, followed by the first passivation layer.

[0204] Step 10: As Figure 28 As shown, an antireflective layer is formed on the second surface of the semiconductor substrate 11 to reduce the reflectivity of the back contact battery on one side of the second surface, thereby further improving the conversion efficiency of the back contact battery. The material of the antireflective layer 18 can be determined according to the actual application scenario, and is not specifically limited here. For example, the antireflective layer 18 may include a silicon nitride layer. Secondly, when the antireflective layer 18 is formed on the second surface of the semiconductor substrate 11, it is also possible that the antireflective layer 18 is also formed on the side surface of the semiconductor substrate 11 and on at least a portion of the first surface of the semiconductor substrate 11. Therefore, before performing the operation steps, a process such as wet etching can be used to remove the antireflective layer 18 that is deposited on at least a portion of the first surface of the semiconductor substrate 11. After removing the dewrap, the antireflective layer 18 on the side surface of the semiconductor substrate 11 can be completely or partially retained.

[0205] Furthermore, in practical applications, in some examples of the manufacturing method provided in Embodiment 2, the first surface may also include the aforementioned first region and second region, and the second region may include a groove. In this case, when the second doped silicon layer is a doped amorphous silicon layer, after the second interface passivation layer and the second doped silicon layer are sequentially formed on the first surface along the thickness direction of the semiconductor substrate, the manufacturing method of the back contact battery may further include an eleventh step: laser irradiating the second doped silicon layer located on the bottom surface of the groove to crystallize the second doped silicon layer. The method, degree, and effect of this crystallization treatment can be referred to above, and will not be repeated here. In addition, the above-mentioned eleventh step may also be omitted.

[0206] Step 12: As Figure 29 As shown, a portion of the second interface passivation layer 19 and the second doped silicon layer 20 located on the first interface passivation layer 12 and the first doped silicon layer 13 are removed to expose a portion of the first interface passivation layer 1212 and the first doped silicon layer 13.

[0207] Step 13: As Figure 30 and Figure 31 As shown, a transparent conductive layer 21 is formed covering the side of the first doped silicon layer 13 and the second doped silicon layer 20 facing away from the semiconductor substrate 11. A through-hole isolation trench 22 is formed in the transparent conductive layer 21 to disconnect the portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 from the portion of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0208] Step 14: As Figure 32 As shown, a first electrode is formed on the portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13, and a second electrode is formed on the portion of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0209] In the manufacturing method provided in Example 2, the operations of steps 12 to 14 are the same as those of steps 15 to 17 in the manufacturing method provided in Example 1 when the insulating mask pattern is retained after the texturing process. Please refer to the description in Example 1 above, and it will not be repeated here.

[0210] It should be noted that, in addition to forming the insulating mask pattern using the method described above, the method of forming the insulating mask pattern in Embodiment 2 of the present invention may also include at least the following two:

[0211] The first method involves forming a first doped silicon glass layer on a portion of the first doped silicon layer away from the semiconductor substrate, simultaneously with the formation of the first doped silicon layer. Based on this, forming an insulating mask pattern on the portion of the first doped silicon layer away from the semiconductor substrate can include: Figure 20 and Figure 21 As shown, the first doped silicon glass layer 14 is patterned to form an insulating mask pattern 15. In this case, compared to the insulating mask pattern formation process described above, steps three and four can be omitted in this first method. Step five described above is replaced by patterning the first doped silicon glass layer.

[0212] The second method involves forming a first doped silicon glass layer on a portion of the first doped silicon layer away from the semiconductor substrate, simultaneously with the formation of the first doped silicon layer. Based on this, forming an insulating mask pattern on the portion of the first doped silicon layer away from the semiconductor substrate may also include: such as... Figures 22 to 24 As shown, an insulating layer 16 is formed on the side of the first doped silicon glass layer 14 facing away from the semiconductor substrate 11; and the first doped silicon glass layer 14 and the insulating layer 16 are patterned to form an insulating mask pattern 15. In this second method, the third step can be omitted compared to the insulating mask pattern formation process described above. Furthermore, the fifth step described above needs to be replaced by patterning the first doped silicon glass layer and the insulating layer.

[0213] The specific formation process of the first and second insulating mask patterns described above can be referred to in Example 1, and will not be repeated here.

[0214] In addition, in the actual manufacturing process, the insulating mask pattern can be removed at the same time as or after the seventh step and before the eighth step.

[0215] Furthermore, in some embodiments, where the first doped silicon layer is a doped polycrystalline silicon layer, the back contact cell may further include an amorphous silicon layer disposed on the side of the first doped silicon layer facing away from the semiconductor substrate. In this case, the amorphous silicon layer can passivate the side of the first doped silicon layer facing away from the semiconductor substrate, reducing the number of surface defects on that side and improving the conversion efficiency of the back contact cell. Secondly, the presence of the amorphous silicon layer can also prevent the etchant used to etch the second interface passivation layer and the second doped silicon layer from affecting the first doped silicon layer, further improving the formation quality of the first doped silicon layer. Furthermore, since the work function difference between the amorphous silicon layer and the transparent conductive layer is smaller than that between the doped polycrystalline silicon layer and the transparent conductive layer, meaning the contact barrier between the amorphous silicon layer and the transparent conductive layer is smaller than that between the doped polycrystalline silicon layer and the transparent conductive layer, the contact resistance between the amorphous silicon layer and the transparent conductive layer is smaller than that between the doped polycrystalline silicon layer and the transparent conductive layer. Therefore, compared to the first doped silicon layer directly contacting the transparent conductive layer, setting an amorphous silicon layer on the side of the first doped silicon layer away from the semiconductor substrate can achieve more reasonable bandgap matching, reduce contact resistance, and enable the back contact battery to effectively convert sunlight into electrical energy, thereby improving the photoelectric conversion efficiency of the back contact battery.

[0216] Specifically, the aforementioned amorphous silicon layer is formed when the second interface passivation layer and the second doped silicon layer are removed by laser. The high-temperature laser modifies the surface of the first doped silicon layer, resulting in the amorphous silicon layer. Furthermore, the amorphous silicon layer can be located on a portion of the bottom of the opening region of the second interface passivation layer and the second doped silicon layer, or it can cover all areas at the bottom of the opening region.

[0217] In addition, the amorphous silicon layer can be continuously distributed in the opening region of the second interface passivation layer and the second doped silicon layer, and is disposed on the side of the first doped silicon layer away from the semiconductor substrate; or it can be distributed intermittently, for example, in a dispersed dotted distribution.

[0218] Example 3

[0219] This embodiment 3 only details the steps that differ from those in embodiment 1. For steps that are the same, please refer to the explanation of embodiment 1 above; these will not be repeated in embodiment 3. The difference between embodiment 3 and embodiment 1 is that in embodiment 3, a stacked second interface passivation layer and a second doped silicon layer are formed first, followed by the formation of the first passivation layer and the antireflection layer. Embodiment 3 will be described in detail below:

[0220] Step 1: Provide a semiconductor substrate. The semiconductor substrate has a first side and a second side facing each other.

[0221] Step 2: As Figure 2As shown, along the thickness direction of the semiconductor substrate 11, a first interface passivation layer 12 and a first doped silicon layer 13 are sequentially formed on the first surface of the semiconductor substrate 11.

[0222] Step 3: As Figure 3 As shown, the first doped silicon glass layer is removed.

[0223] Step 4: As Figure 4 and Figure 5 As shown, an insulating layer 16 is formed on the side of the first doped silicon layer 13 that is away from the semiconductor substrate 11.

[0224] Step 5: As Figure 6 As shown, the insulating layer 16 is patterned to form an insulating mask pattern 15.

[0225] Step 6: As Figure 7 As shown, the first interface passivation layer 12 and the first doped silicon layer 13 that are not covered by the insulating mask pattern 15 are removed.

[0226] Step 7: As Figure 11 and Figure 12 As shown, the surface of the first side exposed outside the insulating mask pattern 15 and the second side are texturized.

[0227] Step 8: As Figure 8 and Figure 9 As shown, the insulating mask pattern is removed.

[0228] In the manufacturing method provided in Example 3, the operations of the first to eighth steps are the same as those of the first to eighth steps in the manufacturing method provided in Example 1, and will not be repeated here.

[0229] Step 9: As Figure 33 As shown, along the thickness direction of the semiconductor substrate 11, a second interface passivation layer 19 and a second doped silicon layer 20 are formed sequentially on the first surface. The second doped silicon layer 20 and the first doped silicon layer 13 have opposite conductivity types.

[0230] Step 10: As Figure 34 As shown, a first passivation layer 17 is formed on the second surface of the semiconductor substrate 11, and a first passivation layer 17 is also formed on the first surface of the semiconductor substrate 11.

[0231] Step 11: As Figure 35 As shown, an antireflection layer is formed on the second surface of the semiconductor substrate 11.

[0232] In the manufacturing method provided in Example 3, the methods in which the corresponding structures are formed in steps nine to eleven are the same as those in steps nine, ten, and twelfth of the manufacturing method provided in Example 1, and will not be repeated here.

[0233] Step 12: Use laser annealing to process the first passivation layer disposed on the second surface of the semiconductor substrate to activate the passivation performance of the first passivation layer.

[0234] It should be noted that in the manufacturing method provided in Example 1, annealing is required after forming the first passivation layer (or forming the first passivation layer and the antireflection layer) to activate the passivation performance. In contrast, the manufacturing method provided in Example 3 activates the passivation performance of the first passivation layer (or forming the first passivation layer and the antireflection layer) through laser processing after its formation. This laser annealing process uses a relatively low temperature, which reduces the impact of high temperatures on the formed structure and helps to lower manufacturing costs.

[0235] Step 13: As Figure 36 As shown, the antireflective layer 18 deposited around one side of the first surface and the first passivation layer 17 formed on one side of the first surface need to be removed sequentially. At this time, the portions of the first passivation layer 17 and the antireflective layer 18 deposited around the side of the semiconductor substrate 11 can be entirely or partially retained. This removal operation can be performed in a chain cleaning apparatus. After the removal operation and before subsequent operations, the semiconductor substrate 11 can be subjected to metal ion cleaning (i.e., RCA cleaning) to remove contamination and minor scratches caused to the semiconductor substrate 11 within the chain cleaning apparatus. In some embodiments, this cleaning operation may not be performed.

[0236] In some examples, step thirteen may be omitted.

[0237] Step 14: As Figure 37 As shown, a portion of the second interface passivation layer 19 and the second doped silicon layer 20 located on the first interface passivation layer 12 and the first doped silicon layer 13 are removed to expose a portion of the first interface passivation layer 12 and the first doped silicon layer 13.

[0238] Step 15: As Figure 38 As shown, a transparent conductive layer 21 is formed covering the side of the first doped silicon layer 13 and the second doped silicon layer 20 facing away from the semiconductor substrate 11. A through-hole isolation trench 22 is formed in the transparent conductive layer 21 to disconnect the portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 from the portion of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0239] Step 16: As Figure 39 As shown, a first electrode is formed on the portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13, and a second electrode is formed on the portion of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0240] In the manufacturing method provided in Example 3, steps fourteen through sixteen are the same as steps fifteen through seventeen in the manufacturing method provided in Example 1, and will not be described again here.

[0241] It is worth noting that, unlike the manufacturing method provided in Embodiment 1, the manufacturing method provided in Embodiment 3 involves texturing the surface of the area exposed outside the insulating mask pattern on the first side and the second side, and forming a stacked second interface passivation layer and a second doped silicon layer on the first side before forming the first passivation layer on the second side of the semiconductor substrate. In this case, another optional example can be added to the manufacturing method provided by the embodiments of the present invention, which is beneficial to improving the applicability of the manufacturing method provided by the embodiments of the present invention in different application scenarios. At the same time, when the first passivation layer is formed on the second side of the semiconductor substrate, the first passivation layer may be deposited around the side of the semiconductor substrate and at least a portion of the first side. Based on this, when the formation sequence of the stacked second interface passivation layer and the second doped silicon layer is set after the texturing process and before at least the first passivation layer is formed, it is no longer necessary to remove at least the portion of the first passivation layer deposited around the first side before forming the stacked second interface passivation layer and the second doped silicon layer, thereby reducing the number of process steps. It can be determined whether to remove the first passivation layer deposited around the first side after at least the first passivation layer is formed according to actual needs, thereby reducing manufacturing requirements. Furthermore, in this case, the corresponding structure on the first side can be fabricated first, followed by the corresponding film layers (first passivation layer and antireflection layer) on the second side, reducing the number of flipping operations and lowering the risk of damage. Additionally, when the material of the second doped silicon layer includes at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon, the structure on the first side is fabricated first, followed by the structure on the second side. Moreover, amorphous silicon, microcrystalline silicon, and nanocrystalline silicon have relatively poor thermal stability compared to polycrystalline silicon and monocrystalline silicon; therefore, only locally processed laser annealing can be used, and rapid annealing is not feasible.

[0242] It should be noted that, in addition to forming the insulating mask pattern using the method described above, the method of forming the insulating mask pattern in Embodiment 3 of the present invention may also include at least the following two:

[0243] The first method involves forming a first doped silicon glass layer on a portion of the first doped silicon layer away from the semiconductor substrate, simultaneously with the formation of the first doped silicon layer. Based on this, forming an insulating mask pattern on the portion of the first doped silicon layer away from the semiconductor substrate can include: Figure 20 and Figure 21As shown, the first doped silicon glass layer 14 is patterned to form an insulating mask pattern 15. In this case, compared to the insulating mask pattern formation process described above, steps three and four can be omitted in this first method. Step five described above is replaced by patterning the first doped silicon glass layer.

[0244] The second method involves forming a first doped silicon glass layer on a portion of the first doped silicon layer away from the semiconductor substrate, simultaneously with the formation of the first doped silicon layer. Based on this, forming an insulating mask pattern on the portion of the first doped silicon layer away from the semiconductor substrate may also include: such as... Figures 22 to 24 As shown, an insulating layer 16 is formed on the side of the first doped silicon glass layer 14 facing away from the semiconductor substrate 11; and the first doped silicon glass layer 14 and the insulating layer 16 are patterned to form an insulating mask pattern 15. In this second method, the third step can be omitted compared to the insulating mask pattern formation process described above. Furthermore, the fifth step described above needs to be replaced by patterning the first doped silicon glass layer and the insulating layer.

[0245] The specific formation process of the first and second insulating mask patterns described above can be referred to in Example 1, and will not be repeated here.

[0246] Furthermore, in actual manufacturing processes, step eight above may not be performed. In other words, as... Figure 39 As shown, after removing the first interface passivation layer 12 and the first doped silicon layer 13 that are not covered by the insulating mask pattern 15, and before forming the stacked second interface passivation layer 19 and the second doped silicon layer 20, the insulating mask pattern 15 is not removed. At this time, the presence of the insulating mask pattern 15 can separate the first doped silicon layer 13 and the second doped silicon layer 20 along the thickness direction of the semiconductor substrate 11, suppressing forward leakage current, reducing the thickness requirement of the second interface passivation layer 19, reducing the transmission resistance of the second interface passivation layer 19, reducing transmission loss, and improving the carrier collection efficiency of the second doped silicon layer 20, thereby improving the conversion efficiency of the back contact cell.

[0247] In step ten, without performing step eight, the first passivation layer may be formed only on the second surface of the semiconductor substrate. Alternatively, the first passivation layer may be formed on both the first and second surfaces of the semiconductor substrate.

[0248] In some embodiments, where the first doped silicon layer is a doped polycrystalline silicon layer, the back contact cell may further include an amorphous silicon layer disposed on the side of the first doped silicon layer facing away from the semiconductor substrate. In this case, the amorphous silicon layer can passivate the side of the first doped silicon layer facing away from the semiconductor substrate, reducing the number of surface defects on this side and improving the conversion efficiency of the back contact cell. Furthermore, the presence of the amorphous silicon layer can prevent the etchant used to etch the second interface passivation layer and the second doped silicon layer from affecting the first doped silicon layer, further improving the formation quality of the first doped silicon layer. Furthermore, since the work function difference between the amorphous silicon layer and the transparent conductive layer is smaller than that between the doped polycrystalline silicon layer and the transparent conductive layer, meaning the contact barrier between the amorphous silicon layer and the transparent conductive layer is smaller than that between the doped polycrystalline silicon layer and the transparent conductive layer, the contact resistance between the amorphous silicon layer and the transparent conductive layer is smaller than that between the doped polycrystalline silicon layer and the transparent conductive layer. Therefore, compared to the first doped silicon layer directly contacting the transparent conductive layer, setting an amorphous silicon layer on the side of the first doped silicon layer away from the semiconductor substrate can achieve more reasonable bandgap matching, reduce contact resistance, and enable the back contact battery to effectively convert sunlight into electrical energy, thereby improving the photoelectric conversion efficiency of the back contact battery.

[0249] Specifically, the aforementioned amorphous silicon layer is formed when the second interface passivation layer and the second doped silicon layer are removed by laser. The high-temperature laser modifies the surface of the first doped silicon layer, resulting in the amorphous silicon layer. Furthermore, the amorphous silicon layer can be located on a portion of the bottom of the opening region of the second interface passivation layer and the second doped silicon layer, or it can cover all areas at the bottom of the opening region.

[0250] In addition, the amorphous silicon layer can be continuously distributed in the opening region of the second interface passivation layer and the second doped silicon layer, and is disposed on the side of the first doped silicon layer away from the semiconductor substrate; or it can be distributed intermittently, for example, in a dispersed dotted distribution.

[0251] Example 4

[0252] This embodiment 4 only details the steps that differ from those in embodiment 1. For steps that are the same, please refer to the explanation of embodiment 1 above; these will not be repeated in embodiment 4. The difference between embodiment 4 and embodiment 1 is that the first passivation layer formed in step eight of embodiment 4 includes a second doped silicon glass layer and / or an alumina layer. Embodiment 4 will be described in detail below:

[0253] Step 1: Provide a semiconductor substrate. The semiconductor substrate has a first side and a second side facing each other.

[0254] Step 2: As Figure 2As shown, along the thickness direction of the semiconductor substrate 11, a first interface passivation layer 12 and a first doped silicon layer 13 are sequentially formed on the first surface of the semiconductor substrate 11.

[0255] Step 3: As Figure 3 As shown, the first doped silicon glass layer is removed.

[0256] Step 4: As Figure 4 and Figure 5 As shown, an insulating layer 16 is formed on the side of the first doped silicon layer 13 that is away from the semiconductor substrate 11.

[0257] Step 5: As Figure 6 As shown, the insulating layer 16 is patterned to form an insulating mask pattern 15.

[0258] Step 6: As Figure 7 As shown, the first interface passivation layer 12 and the first doped silicon layer 13 that are not covered by the insulating mask pattern 15 are removed.

[0259] Step 7: As Figure 8 and Figure 9 As shown, the surface of the first side exposed outside the insulating mask pattern 15 and the second side are texturized.

[0260] Step 8: As Figure 26 As shown, a first passivation layer 17 is formed on the second surface of the semiconductor substrate 11.

[0261] The first passivation layer can include any passivating film layer such as a second doped silicon glass layer and / or an alumina layer, as long as it can be applied to the manufacturing method provided in this embodiment of the invention. The dopant in the second doped silicon glass layer has the same conductivity type as the first doped silicon layer. In this case, compared to the intrinsic silicon passivation layer, the second doped silicon glass layer and the alumina layer have higher light transmittance. Therefore, compared to the first passivation layer including an intrinsic silicon passivation layer, when the first passivation layer includes a second doped silicon glass layer and / or an alumina layer, the parasitic absorption of the first passivation layer can be reduced, which is beneficial to improving the light utilization rate of the back contact battery. Furthermore, the second doped silicon glass layer is also doped with a dopant of the same conductivity type as the first doped silicon layer, so that the first passivation layer can not only chemically passivate one side of the second surface of the semiconductor substrate, but also field passivate one side of the second surface of the semiconductor substrate. This reduces the carrier recombination rate on the second surface and also helps to improve the carrier collection efficiency of the first and second doped silicon layers. Compared to the need for separate deposition, the second doped silicon glass layer can be formed through a diffusion process, which simplifies the fabrication of the first passivation layer.

[0262] Furthermore, when the first passivation layer is a second doped silicon glass layer, the first passivation layer can be formed on both the second and first sides of the semiconductor substrate. When the first passivation layer is an aluminum oxide layer, the first passivation layer can be formed only on the second side, without forming it on the first side.

[0263] Step 9: As Figure 40 As shown, an antireflection layer is formed on the second surface of the semiconductor substrate 11.

[0264] Step 10: Use laser annealing to process the first passivation layer on the second surface of the semiconductor substrate to activate its passivation properties.

[0265] Step 11: As Figure 41 As shown, the antireflective layer 18 coated around one side of the first surface and the first passivation layer 17 formed on one side of the first surface are removed in sequence.

[0266] Step 12: As Figure 42 and Figure 43 As shown, along the thickness direction of the semiconductor substrate 11, a second interface passivation layer 19 and a second doped silicon layer 20 are sequentially formed on the first surface. The second doped silicon layer 20 and the first doped silicon layer 13 have opposite conductivity types.

[0267] Step 13: As Figure 44 As shown, a portion of the second interface passivation layer 19 and the second doped silicon layer 20 located on the first interface passivation layer 12 and the first doped silicon layer 13 are removed to expose a portion of the first interface passivation layer 12 and the first doped silicon layer 13.

[0268] Step 14: As Figure 45 As shown, a transparent conductive layer 21 is formed covering the side of the first doped silicon layer 13 and the second doped silicon layer 20 facing away from the semiconductor substrate 11. A through-hole isolation trench 22 is formed in the transparent conductive layer 21 to disconnect the portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 from the portion of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0269] Step 15: As Figure 46 As shown, a first electrode is formed on the portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13, and a second electrode is formed on the portion of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0270] Except for retaining the insulating mask pattern after the seventh step and the first passivation layer may also include a second doped silicon glass layer, the operations of the first to fifteenth steps in the manufacturing method provided in Example 4 are the same as the operations of the first to seventh steps and the ninth to seventeenth steps in the manufacturing method provided in Example 1, and will not be repeated here.

[0271] It should be noted that, in addition to forming the insulating mask pattern using the method described above, the method of forming the insulating mask pattern in Embodiment 4 of the present invention may also include at least the following two:

[0272] The first method involves forming a first doped silicon glass layer on a portion of the first doped silicon layer away from the semiconductor substrate, simultaneously with the formation of the first doped silicon layer. Based on this, forming an insulating mask pattern on the portion of the first doped silicon layer away from the semiconductor substrate can include: Figure 20 and Figure 21 As shown, the first doped silicon glass layer 14 is patterned to form an insulating mask pattern 15. In this case, compared to the insulating mask pattern formation process described above, steps three and four can be omitted in this first method. Step five described above is replaced by patterning the first doped silicon glass layer.

[0273] The second method involves forming a first doped silicon glass layer on a portion of the first doped silicon layer away from the semiconductor substrate, simultaneously with the formation of the first doped silicon layer. Based on this, forming an insulating mask pattern on the portion of the first doped silicon layer away from the semiconductor substrate may also include: such as... Figures 22 to 24 As shown, an insulating layer 16 is formed on the side of the first doped silicon glass layer 14 facing away from the semiconductor substrate 11; and the first doped silicon glass layer 14 and the insulating layer 16 are patterned to form an insulating mask pattern 15. In this second method, the third step can be omitted compared to the insulating mask pattern formation process described above. Furthermore, the fifth step described above needs to be replaced by patterning the first doped silicon glass layer and the insulating layer.

[0274] The specific formation process of the first and second insulating mask patterns described above can be referred to in Example 1, and will not be repeated here.

[0275] Alternatively, in the actual manufacturing process, the insulating mask pattern can be removed during or after step seven, but before step eight. In this case, during step eight, while forming the first passivation layer on the second surface of the semiconductor substrate, a first passivation layer can also be formed on the first surface. This allows for hydrogen implantation of the first doped silicon layer through the first passivation layer, reducing the number of defects on the side of the first doped silicon layer facing away from the semiconductor substrate.

[0276] Furthermore, in some embodiments, where the first doped silicon layer is a doped polycrystalline silicon layer, the back contact cell may further include an amorphous silicon layer disposed on the side of the first doped silicon layer facing away from the semiconductor substrate. In this case, the amorphous silicon layer can passivate the side of the first doped silicon layer facing away from the semiconductor substrate, reducing the number of surface defects on that side and improving the conversion efficiency of the back contact cell. Secondly, the presence of the amorphous silicon layer can also prevent the etchant used to etch the second interface passivation layer and the second doped silicon layer from affecting the first doped silicon layer, further improving the formation quality of the first doped silicon layer. Furthermore, since the work function difference between the amorphous silicon layer and the transparent conductive layer is smaller than that between the doped polycrystalline silicon layer and the transparent conductive layer, meaning the contact barrier between the amorphous silicon layer and the transparent conductive layer is smaller than that between the doped polycrystalline silicon layer and the transparent conductive layer, the contact resistance between the amorphous silicon layer and the transparent conductive layer is smaller than that between the doped polycrystalline silicon layer and the transparent conductive layer. Therefore, compared to the first doped silicon layer directly contacting the transparent conductive layer, setting an amorphous silicon layer on the side of the first doped silicon layer away from the semiconductor substrate can achieve more reasonable bandgap matching, reduce contact resistance, and enable the back contact battery to effectively convert sunlight into electrical energy, thereby improving the photoelectric conversion efficiency of the back contact battery.

[0277] Specifically, the aforementioned amorphous silicon layer is formed when the second interface passivation layer and the second doped silicon layer are removed by laser. The high-temperature laser modifies the surface of the first doped silicon layer, resulting in the amorphous silicon layer. Furthermore, the amorphous silicon layer can be located on a portion of the bottom of the opening region of the second interface passivation layer and the second doped silicon layer, or it can cover all areas at the bottom of the opening region.

[0278] In addition, the amorphous silicon layer can be continuously distributed in the opening region of the second interface passivation layer and the second doped silicon layer, and is disposed on the side of the first doped silicon layer away from the semiconductor substrate; or it can be distributed intermittently, for example, in a dispersed dotted distribution.

[0279] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0280] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A method for manufacturing a back-contact battery, characterized in that, include: Provide a semiconductor substrate; The semiconductor substrate has a first side and a second side opposite to each other; Along the thickness direction of the semiconductor substrate, a first interface passivation layer and a first doped silicon layer are sequentially formed on the first surface of the semiconductor substrate; An insulating mask pattern is formed on a portion of the first doped silicon layer on the side opposite to the semiconductor substrate; Remove the first interface passivation layer and the first doped silicon layer that are not covered by the insulating mask pattern; The area of ​​the first surface exposed outside the insulating mask pattern and the second surface are texturized. While forming a first passivation layer on the second surface of the semiconductor substrate, the first passivation layer is also formed on the entire first surface of the semiconductor substrate. The first passivation layer is used to improve the hydrogen passivation effect of the first doped silicon layer; An antireflection layer is formed on the side of the first passivation layer located on the second surface of the semiconductor substrate that is away from the semiconductor substrate; After forming the antireflection layer, the first passivation layer located on the first surface of the semiconductor substrate is removed; After removing the first passivation layer located on the first surface of the semiconductor substrate, a second interface passivation layer and a second doped silicon layer are sequentially formed on the first surface along the thickness direction of the semiconductor substrate; the second doped silicon layer and the first doped silicon layer have opposite conductivity types. Remove portions of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer to expose portions of the first interface passivation layer and the first doped silicon layer.

2. The method for manufacturing a back contact battery according to claim 1, characterized in that, The texturing process for the area of ​​the first surface exposed outside the insulating mask pattern and the second surface includes: performing the texturing process on the area of ​​the first surface exposed outside the insulating mask pattern and the second surface; Remove the insulating mask pattern; Alternatively, the texturing process for the area of ​​the first surface exposed outside the insulating mask pattern and the second surface includes: performing the texturing process on the area of ​​the first surface exposed outside the insulating mask pattern and the second surface; retaining the insulating mask pattern after the texturing process.

3. The method for manufacturing a back contact battery according to claim 1 or 2, characterized in that, The step of sequentially forming a first interface passivation layer and a first doped silicon layer on the first surface of the semiconductor substrate includes: while sequentially forming the first interface passivation layer and the first doped silicon layer on the first surface of the semiconductor substrate, forming a first doped silicon glass layer on the side of the first doped silicon layer away from the semiconductor substrate. The step of forming an insulating mask pattern on a portion of the first doped silicon layer away from the semiconductor substrate includes: patterning the first doped silicon glass layer to form the insulating mask pattern. Alternatively, the step of sequentially forming a first interface passivation layer and a first doped silicon layer on the first surface of the semiconductor substrate includes: while sequentially forming the first interface passivation layer and the first doped silicon layer on the first surface of the semiconductor substrate, forming a first doped silicon glass layer on the side of the first doped silicon layer away from the semiconductor substrate. The step of forming an insulating mask pattern on a portion of the first doped silicon layer away from the semiconductor substrate includes: forming an insulating layer on the side of the first doped silicon glass layer away from the semiconductor substrate; and patterning the first doped silicon glass layer and the insulating layer to form the insulating mask pattern. Alternatively, the step of sequentially forming a first interface passivation layer and a first doped silicon layer on the first surface of the semiconductor substrate includes: while sequentially forming the first interface passivation layer and the first doped silicon layer on the first surface of the semiconductor substrate, forming a first doped silicon glass layer on the side of the first doped silicon layer away from the semiconductor substrate. The step of forming an insulating mask pattern on a portion of the first doped silicon layer away from the semiconductor substrate includes: removing the first doped silicon glass layer; forming an insulating layer on the side of the first doped silicon layer away from the semiconductor substrate; and patterning the insulating layer to form the insulating mask pattern.

4. The method for manufacturing a back contact battery according to claim 1, characterized in that, The first passivation layer includes an intrinsic amorphous silicon layer.

5. The method for manufacturing a back contact battery according to claim 1, characterized in that, The first passivation layer includes a second doped silicon glass layer, and the conductivity type of the dopant in the second doped silicon glass layer is the same as that of the first doped silicon layer.

6. The method for manufacturing a back contact battery according to claim 1, characterized in that, After removing a portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer, the manufacturing method of the back contact cell further includes: A transparent conductive layer is formed covering the side of the first doped silicon layer and the second doped silicon layer away from the semiconductor substrate; a through-hole is formed in the transparent conductive layer to disconnect the portion of the transparent conductive layer corresponding to the first doped silicon layer from the portion of the transparent conductive layer corresponding to the second doped silicon layer. A first electrode is formed on the portion of the transparent conductive layer corresponding to the first doped silicon layer, and a second electrode is formed on the portion of the transparent conductive layer corresponding to the second doped silicon layer.

7. The method for manufacturing a back contact battery according to claim 6, characterized in that, The thickness of the edge portion of the transparent conductive layer adjacent to the isolation trench gradually decreases in the direction close to the isolation trench.

8. The method for manufacturing a back contact battery according to claim 6 or 7, characterized in that, The second interface passivation layer and the second doped silicon layer, which are stacked sequentially, and the transparent conductive layer disposed on the second doped silicon layer, all cover a portion of the stacked first interface passivation layer and the first doped silicon layer away from the semiconductor substrate.

9. The method for manufacturing a back contact battery according to claim 1, characterized in that, The thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 140 nm; And / or, the width of the opening region of the second interface passivation layer and the second doped silicon layer is greater than or equal to 250 μm and less than or equal to 400 μm.

10. The method for manufacturing a back contact battery according to claim 1, characterized in that, In the first surface, the region where the first interface passivation layer and the first doped silicon layer are disposed has a tower-based texture structure. The thickness of the first interface passivation layer at the bottom surface of the tower-shaped texture structure is less than the thickness of the first interface passivation layer at the sidewall of the tower-shaped texture structure.

11. The method for manufacturing a back contact battery according to claim 1, characterized in that, The thickness of the second interface passivation layer is greater than or equal to 3 nm and less than or equal to 16 nm.

12. The method for manufacturing a back contact battery according to claim 1, characterized in that, The first doped silicon layer is a doped polycrystalline silicon layer; The back contact battery also includes an amorphous silicon layer, which is located in the opening region between the second interface passivation layer and the second doped silicon layer, and is disposed on the side of the first doped silicon layer away from the semiconductor substrate.

13. The method for manufacturing a back contact battery according to claim 1, characterized in that, The removal of a portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer includes: A portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer is removed using a laser, and the edge portion of the opening region of the second doped silicon layer is processed using a laser to form a hole structure in the edge portion of the opening region of the second doped silicon layer.

14. The method for manufacturing a back contact battery according to claim 1, characterized in that, The first surface includes a first region and a second region; the second region includes a groove; The first interface passivation layer and the first doped silicon layer are located in the first region; the second interface passivation layer and the second doped silicon layer are located in the second region, and extend to cover a portion of the first interface passivation layer and the first doped silicon layer in the first region. The surface of the first region is a polished surface, and the bottom surface of the groove is a textured surface; the thickness of the second doped silicon layer on the textured surface is less than the thickness of the second doped silicon layer on the polished surface.

15. The method for manufacturing a back contact battery according to claim 1, characterized in that, The first surface includes a first area and a second area; the second area includes a groove; the surface of the first area is a polished surface, and the bottom surface of the groove is a velvety surface; The first interface passivation layer and the first doped silicon layer are located in the first region; the second interface passivation layer and the second doped silicon layer are located in the second region and extend from the second region to the first region, covering a portion of the first interface passivation layer and the first doped silicon layer. The distance from the surface of the semiconductor substrate in the first region to the bottom surface of the groove is greater than or equal to 2 μm and less than or equal to 8 μm.

16. The method for manufacturing a back contact battery according to claim 1, wherein the first surface includes a first region and a second region; the second region includes a groove; The first interface passivation layer and the first doped silicon layer are located in the first region; the second interface passivation layer and the second doped silicon layer are located in the second region and extend from the second region to the first region, covering a portion of the first interface passivation layer and the first doped silicon layer. The second doped silicon layer is a doped amorphous silicon layer; After forming a second interface passivation layer and a second doped silicon layer sequentially on the first surface along the thickness direction of the semiconductor substrate, the manufacturing method of the back contact cell further includes: The second doped silicon layer located on the bottom surface of the groove is subjected to laser irradiation to crystallize the second doped silicon layer.

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