Light emitting diode capable of improving stress and preparation method thereof

Abstract

The embodiment of the invention provides a light emitting diode for improving stress and a preparation method thereof, and belongs to the technical field of semiconductors. The preparation method comprises the following steps: sequentially forming a buffer layer and a filling layer on a substrate; alternately performing a plurality of cooling growth stages and a plurality of heating growth stages to form a first insertion layer on the filling and leveling layer, in the cooling growth stages, forming a first sub-layer at a first temperature, the first temperature being lower than the growth temperature of the filling and leveling layer; in the heating growth stage, a second sub-layer is formed at a second temperature, and the second temperature is higher than the first temperature; and sequentially forming a first semiconductor layer, a light-emitting layer and a second semiconductor layer on the first insertion layer, wherein the second temperature is lower than the growth temperature of the first semiconductor layer. According to the embodiment of the invention, the radiation recombination efficiency of current carriers can be improved, and the luminous efficiency of an LED is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a light emitting diode with improved stress and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) has been widely used in various light source fields such as backlight, lighting, and landscaping due to its small size, long service life, rich colors, and low energy consumption.

[0003] In the related art, a method for preparing an LED includes: forming a buffer layer, a fill layer, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence on a substrate.

[0004] However, there is a large lattice mismatch between the substrate and the semiconductor material, which will generate stress. In addition, the high-temperature growth of the filling layer is also prone to introduce stress. These stresses will accumulate in the first semiconductor layer and extend upward to the light-emitting layer, affecting the quality of the light-emitting layer, thereby reducing the radiation recombination efficiency of electrons and holes in the light-emitting layer and affecting the luminous efficiency of the LED. Summary of the invention

[0005] The embodiment of the present disclosure provides a light-emitting diode with improved stress and a method for manufacturing the same, which can improve the radiation recombination efficiency of carriers and improve the luminous efficiency of LEDs. The technical solution is as follows:

[0006] On the one hand, a method for preparing a light-emitting diode is provided, comprising: forming a buffer layer and a leveling layer on a substrate in sequence; alternating multiple temperature-dropping growth stages and multiple temperature-increasing growth stages to form a first insertion layer on the leveling layer, wherein, in the temperature-dropping growth stage, a first sublayer is formed at a first temperature, and the first temperature is lower than the growth temperature of the leveling layer; in the temperature-increasing growth stage, a second sublayer is formed at a second temperature, and the second temperature is higher than the first temperature; and forming a first semiconductor layer, a light-emitting layer, and a second semiconductor layer in sequence on the first insertion layer, and the second temperature is lower than the growth temperature of the first semiconductor layer.

[0007] Optionally, the difference between the second temperature and the first temperature is 20°C to 50°C.

[0008] Optionally, the first temperature is 1020°C to 1050°C, and the second temperature is 1040°C to 1070°C.

[0009] Optionally, forming the first insertion layer on the leveling layer further comprises: before alternating the multiple temperature reduction growth stages and the multiple temperature increase growth stages, forming a third sublayer at a third temperature, wherein the third temperature is greater than the first temperature and less than the second temperature.

[0010] Optionally, the difference between the third temperature and the first temperature is 30°C to 60°C.

[0011] Optionally, the thickness of the third sublayer is greater than the thickness of the first sublayer, and greater than the thickness of the second sublayer.

[0012] Optionally, the method also includes: before forming the light-emitting layer, forming a second insertion layer on the first semiconductor layer in the following manner: forming a fourth sublayer at a fourth temperature, the fourth temperature being lower than the growth temperature of the first semiconductor layer; forming a fifth sublayer at a fifth temperature, the fifth temperature being lower than the fourth temperature; and forming a sixth sublayer at a sixth temperature, the sixth temperature being lower than the fifth temperature and higher than the growth temperature of the light-emitting layer.

[0013] Optionally, the difference between the fourth temperature and the fifth temperature is 10°C to 40°C, and the difference between the fifth temperature and the sixth temperature is 20°C to 50°C.

[0014] Optionally, the fourth temperature is 1030°C to 1060°C, the fifth temperature is 1020°C to 1050°C, and the sixth temperature is 1000°C to 1040°C.

[0015] On the other hand, a light-emitting diode is provided, comprising a substrate, a buffer layer, a filling layer, a first insertion layer, a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked in sequence; the first insertion layer comprises a plurality of first sublayers and a plurality of second sublayers stacked alternately, the first sublayer is formed at a first temperature, the first temperature is lower than the growth temperature of the filling layer, the second sublayer is formed at a second temperature, the second temperature is higher than the first temperature and lower than the growth temperature of the first semiconductor layer.

[0016] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0017] In the disclosed embodiment, since the growth temperature of the filling layer is generally high, a cooling growth stage is performed after the filling layer is formed, and the first sublayer is formed at a first temperature lower than the growth temperature of the filling layer, which can reduce the stress introduced when the filling layer is grown at high temperature. Then a heating growth stage is performed, and the second sublayer is formed at a second temperature greater than the growth temperature of the first sublayer and less than the growth temperature of the first semiconductor layer. This can stabilize the strain of the first sublayer and ensure that the quality of the first sublayer and the second sublayer is good. In addition, since the growth temperature of the first semiconductor layer is also high, the second temperature is closer to the growth temperature of the first semiconductor layer relative to the first temperature, which is conducive to reducing the probability of LED cracking caused by stress mutation caused by temperature mutation when the first semiconductor layer is subsequently formed. By alternating multiple cooling growth stages and multiple heating growth stages, the stress is released stably multiple times, and the first insertion layer can effectively reduce the probability of stress extending upward to the first semiconductor layer and the light-emitting layer, thereby improving the radiation recombination efficiency of carriers and improving the luminous efficiency of the LED. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a flow chart of a method for preparing an LED provided by an embodiment of the present disclosure;

[0020] Figure 2 is a flow chart of another method for preparing an LED provided by an embodiment of the present disclosure;

[0021] Figure 3 It is a schematic diagram of the structure of an LED provided in an embodiment of the present disclosure.

[0022] Reference numerals:

[0023] 10: substrate; 20: buffer layer; 30: filling layer; 40: first insertion layer; 41: first sublayer; 42: second sublayer; 43: third sublayer; 50: first semiconductor layer; 60: light emitting layer; 70: second semiconductor layer; 80: second insertion layer; 81: fourth sublayer; 82: fifth sublayer; 83: sixth sublayer; 90: electron blocking layer. DETAILED DESCRIPTION

[0024] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0025] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" and similar words mean that the elements or objects appearing before "include" include the elements or objects listed after "include" and their equivalents, and do not exclude other elements or objects. Words such as "connect" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0026] Figure 1 FIG. 1 is a flow chart of a method for preparing an LED provided by an embodiment of the present disclosure. Figure 1 As shown, the preparation method comprises:

[0027] In step S101, a buffer layer and a fill layer are sequentially formed on a substrate.

[0028] In step S102, a plurality of temperature reduction growth stages and a plurality of temperature increase growth stages are performed alternately to form a first insertion layer on the leveling layer.

[0029] In the cooling growth stage, a first sublayer is formed at a first temperature which is lower than the growth temperature of the filling layer; in the heating growth stage, a second sublayer is formed at a second temperature which is higher than the first temperature.

[0030] In step S103 , a first semiconductor layer, a light emitting layer and a second semiconductor layer are sequentially formed on the first insertion layer.

[0031] The second temperature is lower than the growth temperature of the first semiconductor layer.

[0032] In the disclosed embodiment, since the growth temperature of the filling layer is generally high, a cooling growth stage is performed after the filling layer is formed, and the first sublayer is formed at a first temperature lower than the growth temperature of the filling layer, which can reduce the stress introduced when the filling layer is grown at high temperature. Then a heating growth stage is performed, and the second sublayer is formed at a second temperature greater than the growth temperature of the first sublayer and less than the growth temperature of the first semiconductor layer. This can stabilize the strain of the first sublayer and ensure that the quality of the first sublayer and the second sublayer is good. In addition, since the growth temperature of the first semiconductor layer is also high, the second temperature is closer to the growth temperature of the first semiconductor layer relative to the first temperature, which is conducive to reducing the probability of LED cracking caused by stress mutation caused by temperature mutation when the first semiconductor layer is subsequently formed. By alternating multiple cooling growth stages and multiple heating growth stages, the stress is released stably multiple times, and the first insertion layer can effectively reduce the probability of stress extending upward to the first semiconductor layer and the light-emitting layer, thereby improving the radiation recombination efficiency of carriers and improving the luminous efficiency of the LED.

[0033] Figure 2 FIG. 1 is a flow chart of another method for preparing an LED provided by an embodiment of the present disclosure. Figure 2 As shown, the preparation method comprises:

[0034] In step S201 , a buffer layer is formed on a substrate.

[0035] Optionally, the substrate may be a sapphire substrate, which is a transparent substrate with good light transmittance, high mechanical strength, and easy to handle and clean.

[0036] For example, the substrate may be a patterned sapphire substrate having a plurality of protrusions arranged in an array on its surface.

[0037] In other embodiments, the substrate may also be a Si substrate or a SiC substrate, which is not limited in the present disclosure.

[0038] Optionally, the buffer layer includes at least one of a GaN layer, an AlN layer and an AlGaN layer.

[0039] Exemplarily, the buffer layer includes a stacked low-temperature GaN layer and a high-temperature GaN layer.

[0040] Figure 3 Schematic diagram of the structure of an LED provided by an embodiment of the present disclosure. Figure 3As shown, in a metal-organic chemical vapor deposition (MOCVD) reaction chamber, the temperature of the reaction chamber can be controlled to be 530°C to 560°C to grow a low-temperature GaN layer, and then the temperature of the reaction chamber can be controlled to be 1000°C to 1100°C to grow a high-temperature GaN layer to form a buffer layer 20 on the substrate 10. The buffer layer 20 is beneficial to reducing the lattice mismatch and thermal mismatch between the substrate 10 and the semiconductor material, thereby ensuring good quality of the LED.

[0041] In step S202 , a fill layer is formed on the buffer layer.

[0042] Optionally, the filling layer 30 is a GaN layer.

[0043] For example, the temperature of the reaction chamber can be controlled to be 1090° C. to 1120° C. to grow a GaN layer to form a leveling layer 30 on the buffer layer 20. The leveling layer 30 is used to level the surface of the buffer layer 20 away from the substrate 10, which is conducive to ensuring good crystal quality.

[0044] In step S203 , a first insertion layer is formed on the leveling layer.

[0045] The step S203 includes: performing multiple cooling growth stages and multiple heating growth stages alternately. In the cooling growth stage, the first sublayer 41 is formed at a first temperature, which is lower than the growth temperature of the fill layer 30; in the heating growth stage, the second sublayer 42 is formed at a second temperature, which is higher than the first temperature and lower than the growth temperature of the first semiconductor layer 50.

[0046] Exemplarily, the second temperature is lower than the growth temperature of the leveling layer 30 .

[0047] In other embodiments, the second temperature may also be greater than or equal to the growth temperature of the filling layer 30 , which is not limited in the present disclosure.

[0048] Optionally, the first insertion layer 40 is a GaN layer.

[0049] Optionally, the difference between the second temperature and the first temperature is 20° C. to 50° C. When the difference between the second temperature and the first temperature is within this range, the alternating cooling growth stage and heating growth stage can effectively reduce the stress caused by lattice mismatch, high temperature growth and temperature mutation, and ensure the good quality of the first sublayer 41 and the second sublayer 42.

[0050] For example, the difference between the second temperature and the first temperature may be 20° C., 40° C., 50° C., etc.

[0051] Optionally, the first temperature is 1020° C. to 1050° C. If the first temperature is too low, the difference between the temperature of the cooling growth stage and the growth temperature of the filling layer 30 may be too large, causing a sudden change in stress due to the sudden change in temperature; if the first temperature is too high, the effect of reducing stress in the cooling growth stage may be affected. The first temperature within this range can effectively reduce the stress introduced during the high-temperature growth of the filling layer 30 without causing a sudden change in stress.

[0052] For example, the first temperature may be 1020° C., 1040° C., 1050° C., or the like.

[0053] Optionally, the second temperature is 1040° C. to 1070° C. If the second temperature is too low, the effect of releasing stress in the temperature increase growth stage is poor; if the second temperature is too high, the temperature change from the temperature decrease growth stage to the temperature increase growth stage may be too large, causing stress mutation. When the second temperature is within this range, the stress of the first sublayer 41 during low-temperature growth can be effectively reduced after the temperature decrease growth stage, the strain of the first sublayer 41 can be stabilized, the quality of the first sublayer 41 and the second sublayer 42 can be ensured to be good, and it is helpful to reduce the probability of LED cracking caused by stress mutation caused by temperature mutation when the first semiconductor layer 50 is subsequently formed.

[0054] Exemplarily, the second temperature is 1040°C, 1060°C, 1070°C, etc.

[0055] It should be noted that the first temperature and the second temperature range are overlapped, and it is sufficient to ensure that the first temperature is lower than the second temperature.

[0056] like Figure 3 As shown, the first insertion layer 40 of the LED includes two first sub-layers 41 and second sub-layers 42 that are alternately stacked.

[0057] Exemplarily, the first sub-layer 41 and the second sub-layer 42 are made of the same material, both of which are GaN layers.

[0058] Exemplarily, the formation of the first sublayer 41 in the cooling growth stage and the formation of the second sublayer 42 in the heating growth stage differ only in temperature conditions and growth time, and other growth conditions may be the same, for example, pressure conditions, Ga source type, Ga source flow rate, N source type and N source flow rate and other growth conditions may be the same.

[0059] In other embodiments, in addition to the differences in temperature conditions and growth time for forming the first sublayer 41 in the cooling growth stage and the second sublayer 42 in the heating growth stage, other growth conditions may also be different. For example, growth conditions such as pressure conditions, Ga source flow rate, N source flow rate and growth rate may also be different, and the present disclosure does not impose any restrictions on this.

[0060] Optionally, along the direction from the leveling layer 30 to the first semiconductor layer 50 , the thicknesses of the first first sub-layer 41 , the first second sub-layer 42 , the second first sub-layer 41 and the second second sub-layer 42 are all different.

[0061] Exemplarily, the thickness of the first first sublayer 41 is greater than the thickness of the second first sublayer 41, and the thickness of the first second sublayer 42 is greater than the thickness of the second second sublayer 42. In this way, the first sublayer 41 with a larger thickness and the second sublayer 42 with a larger thickness are formed in the first cooling growth stage and the first heating growth stage after the high-temperature growth of the filling layer 30, respectively, which can effectively reduce the stress introduced when the high-temperature growth of the filling layer 30 is grown, and ensure that the quality of the first sublayer 41 and the second sublayer 42 is good. The first sublayer 41 with a smaller thickness and the second sublayer 42 with a smaller thickness are formed in the second cooling growth stage and the second heating growth stage, respectively, which can shorten the time for forming the first insertion layer 40 while ensuring that the stress is released stably multiple times, thereby improving the preparation efficiency.

[0062] Exemplarily, the thickness of the first sub-layer 41 is 30 nm to 60 nm.

[0063] Exemplarily, the thickness of the first second sub-layer 42 is 35 nm to 70 nm.

[0064] Exemplarily, the thickness of the second first sub-layer 41 is 20 nm to 50 nm.

[0065] Exemplarily, the thickness of the second second sub-layer 42 is 25 nm to 50 nm.

[0066] Optionally, the growth time of the first first sublayer 41 is greater than the growth time of the second first sublayer 41, and the growth time of the first second sublayer 42 is greater than the growth time of the second second sublayer 42. In this way, it is helpful to reduce the stress introduced by long-term high-temperature growth or long-term low-temperature growth, and it is helpful to improve the preparation efficiency.

[0067] Optionally, the growth time of the first sub-layer 41 is 1 min to 3 min.

[0068] Optionally, the growth time of the first second sub-layer 42 is 1 min to 3 min.

[0069] Optionally, the growth time of the second first sub-layer 41 is 1 min to 2 min.

[0070] Optionally, the growth time of the second second sub-layer 42 is 1 min to 2 min.

[0071] In other embodiments, the thickness of the first sublayer 41 is the same, and the thickness of the second sublayer 42 is the same; or, the growth time of the first sublayer 41 is the same, and the growth time of the second sublayer 42 is the same; or, the first insertion layer 40 includes more first sublayers 41 and more second sublayers 42 that are alternately stacked, etc., and the present disclosure is not limited to this.

[0072] Optionally, step S203 further includes: before performing multiple temperature-lowering growth stages and multiple temperature-raising growth stages alternately, forming a third sublayer 43 at a third temperature, wherein the third temperature is greater than the first temperature and less than the second temperature. In this way, adding a temperature-lowering growth process between forming the filling layer 30 and performing the temperature-lowering growth stage can play a transitional role, which is beneficial to effectively releasing stress and preventing stress mutation after the filling layer 30 is formed at a high temperature.

[0073] Optionally, the difference between the third temperature and the first temperature is 30° C. to 60° C. In this way, an additional cooling growth between the filling layer 30 and the first sublayer 41 to form the third sublayer 43 can reduce the stress introduced by the high-temperature formation of the filling layer 30, and the growth of the first sublayer 41 will not cause stress mutations and cause LED cracks.

[0074] Optionally, the third temperature is 1050° C. to 1080° C. When the third temperature is within this range, the third sublayer 43 can play a role in preventing stress mutation caused by temperature mutation during the intermediate cooling process, effectively reducing stress and reducing the probability of stress extending upward.

[0075] Exemplarily, the third sub-layer 43 is made of the same material as the first sub-layer 41 and the second sub-layer 42 , that is, a GaN layer.

[0076] Optionally, the thickness of the third sublayer 43 is greater than the thickness of the first sublayer 41, and greater than the thickness of the second sublayer 42. In this way, by forming the third sublayer 43 with a larger thickness between the leveling layer 30 and the first first sublayer 41, it is beneficial to effectively release the stress after the leveling layer 30 is formed at a high temperature.

[0077] Exemplarily, the thickness of the third sublayer 43 is 40 nm to 80 nm.

[0078] It should be noted that the thickness of the third sublayer 43 overlaps with the thickness range of the first sublayer 41 and the second sublayer 42 , and the thickness of the third sublayer 43 is ensured to be greater than the thickness of the first sublayer 41 and greater than the thickness of the second sublayer 42 .

[0079] Optionally, the growth time of the third sub-layer 43 is 2 min to 3 min.

[0080] In step S204 , a first semiconductor layer is formed on the first insertion layer.

[0081] Optionally, the first semiconductor layer 50 may be an N-type GaN layer.

[0082] Exemplarily, the first semiconductor layer 50 is a Si-doped GaN layer.

[0083] Exemplarily, the temperature of the reaction chamber may be controlled to be 950° C. to 1150° C. to grow an N-type GaN layer to form the first semiconductor layer 50 on the first insertion layer 40 .

[0084] In step S205 , a second insertion layer is formed on the first semiconductor layer.

[0085] Optionally, step S205 includes: forming a fourth sublayer 81 at a fourth temperature, which is lower than the growth temperature of the first semiconductor layer 50; forming a fifth sublayer 82 at a fifth temperature, which is lower than the fourth temperature; and forming a sixth sublayer 83 at a sixth temperature, which is lower than the fifth temperature and higher than the growth temperature of the light-emitting layer 60. In this way, it is ensured that more stress is not introduced when forming the second insertion layer 80, and the stress of the first semiconductor layer 50 grown at high temperature is stably released, reducing the probability of cracks caused by stress mutation due to excessive temperature difference, improving the reliability of the LED, and effectively reducing the probability of stress extending to the light-emitting layer 60, thereby improving the radiation recombination efficiency of carriers and improving the luminous efficiency of the LED.

[0086] Optionally, the second insertion layer 80 is an N-type GaN layer.

[0087] Exemplarily, the second insertion layer 80 is a Si-doped GaN layer.

[0088] Optionally, the difference between the fourth temperature and the fifth temperature is 10°C to 40°C.

[0089] Optionally, the difference between the fifth temperature and the sixth temperature is 20°C to 50°C.

[0090] In this way, in the process of forming the second insertion layer 80, the temperature difference of each cooling growth is small in the process of forming the fourth sublayer 81, the fifth sublayer 82 and the sixth sublayer 83 through three coolings, the stress can be released stably, and there will be no stress mutation between different sublayers due to temperature mutation.

[0091] Optionally, the fourth temperature is 1030°C to 1060°C.

[0092] Illustratively, the fourth temperature may be 1030° C., 1050° C., 1060° C., or the like.

[0093] Optionally, the fifth temperature is 1020°C to 1050°C.

[0094] Illustratively, the fifth temperature may be 1020° C., 1040° C., 1050° C., or the like.

[0095] Optionally, the sixth temperature is 1000°C to 1040°C.

[0096] Illustratively, the sixth temperature may be 1000° C., 1020° C., 1040° C., or the like.

[0097] In this way, the fourth sublayer 81, the fifth sublayer 82 and the sixth sublayer 83 can release the stress stably multiple times, and the sixth temperature is closer to the growth temperature of the light-emitting layer 60, which can further reduce the probability of stress extending upward to the light-emitting layer 60 and improve the radiation recombination efficiency of carriers.

[0098] It should be noted that the fourth temperature, the fifth temperature and the sixth temperature ranges mentioned above overlap, and it is sufficient to ensure that the fifth temperature is lower than the fourth temperature and the sixth temperature is lower than the fifth temperature.

[0099] Exemplarily, the fourth sublayer 81 , the fifth sublayer 82 , and the sixth sublayer 83 are made of the same material, which is a Si-doped GaN layer.

[0100] Exemplarily, the thickness of the fourth sublayer 81 is 30 nm to 60 nm.

[0101] Exemplarily, the thickness of the fifth sublayer 82 is 20 nm to 50 nm.

[0102] Exemplarily, the thickness of the sixth sublayer 83 is 10 nm to 50 nm.

[0103] Optionally, the growth time of the fourth sub-layer 81 is 1.5 min to 3 min.

[0104] Optionally, the growth time of the fifth sublayer 82 is 1 min to 2 min.

[0105] Optionally, the growth time of the sixth sub-layer 83 is 0.5 min to 2 min.

[0106] In other embodiments, the number of sub-layers of the second insertion layer 80 may be more or less, and the present disclosure is not limited thereto.

[0107] In step S206 , a light emitting layer is formed on the second insertion layer.

[0108] Optionally, the light-emitting layer 60 is a multi-quantum well layer, including multiple pairs of quantum well layers and quantum barrier layers stacked alternately. According to the different light-emitting wavelength ranges of the LED, the light-emitting layer 60 can be made of different materials. For example, the light-emitting layer 60 of the blue-green LED can be made of multiple pairs of InGaN layers and GaN layers stacked alternately, and the light-emitting layer 60 of the red LED can be made of multiple pairs of InGaAs layers and GaAs layers stacked alternately.

[0109] Exemplarily, the light emitting layer 60 includes 6 to 12 pairs of alternately stacked InGaN layers and GaN layers, for example, 9 pairs of alternately stacked InGaN layers and GaN layers, and other pairs, which are not limited in the present disclosure.

[0110] Exemplarily, the growth temperature of the quantum well layer is 700°C to 850°C.

[0111] Exemplarily, the growth temperature of the quantum barrier layer is 850°C to 950°C.

[0112] In step S207 , an electron blocking layer is formed on the light emitting layer.

[0113] Optionally, the electron blocking layer 90 is a P-type AlGaN layer.

[0114] Exemplarily, the electron blocking layer 90 is a Mg-doped AlGaN layer.

[0115] For example, the temperature of the reaction chamber can be controlled to be 1000° C. to 1100° C., and the Mg-doped AlGaN layer can be grown to form an electron blocking layer 90 on the light-emitting layer 60. The electron blocking layer 90 can block electrons and reduce the probability of electrons escaping from the light-emitting layer 60 to the second semiconductor layer 70, thereby improving the radiation recombination efficiency of carriers and improving the luminous efficiency of the LED.

[0116] In step S208 , a second semiconductor layer is formed on the electron blocking layer.

[0117] Optionally, the second semiconductor layer 70 may be a P-type GaN layer.

[0118] Exemplarily, the second semiconductor layer 70 is a Mg-doped GaN layer.

[0119] For example, the temperature of the reaction chamber may be controlled to be 950° C. to 1050° C. to grow a P-type GaN layer to form the second semiconductor layer 70 on the electron blocking layer 90 .

[0120] It should be noted that Figure 3 The film layer structure of the LED shown and the material of the above film layer are only used as an example. In other embodiments, the LED may also include more or fewer film layer structures, and the materials of each film layer can be selected according to actual needs, etc., and there is no limitation on this publicly.

[0121] like Figure 3 As shown, the present disclosure also provides an LED, which adopts Figure 1 or Figure 2 Prepared according to the preparation method shown.

[0122] like Figure 3As shown, the LED includes a substrate 10, a buffer layer 20, a fill layer 30, a first insertion layer 40, a first semiconductor layer 50, a light emitting layer 60 and a second semiconductor layer 70 which are stacked in sequence.

[0123] Among them, the first insertion layer 40 includes a plurality of first sublayers 41 and a plurality of second sublayers 42 alternately stacked, the first sublayer 41 is formed at a first temperature, the first temperature is lower than the growth temperature of the filling layer 30, and the second sublayer 42 is formed at a second temperature, the second temperature is greater than the first temperature and lower than the growth temperature of the first semiconductor layer 50.

[0124] The beneficial effects of the embodiments of the present disclosure can be seen in Figure 1 The relevant embodiments of the preparation method will not be described in detail here.

[0125] like Figure 3 As shown, the first insertion layer 40 includes a third sublayer 43 , a first sublayer 41 , a second sublayer 42 , a first sublayer 41 , and a second sublayer 42 which are sequentially stacked in a direction away from the leveling layer 30 .

[0126] Optionally, the LED further includes a second insertion layer 80 , which is located between the first semiconductor layer 50 and the light emitting layer 60 .

[0127] Exemplarily, the second insertion layer 80 includes a fourth sublayer 81 , a fifth sublayer 82 , and a sixth sublayer 83 which are sequentially stacked in a direction away from the first semiconductor layer 50 .

[0128] Optionally, the LED further includes an electron blocking layer 90 , which is located between the light emitting layer 60 and the second semiconductor layer 70 .

[0129] Optionally, the material, thickness, number of cycles and growth temperature of each layer can be found in Figures 1 to 3 The detailed description of the embodiments related to the preparation method is omitted here.

[0130] The above description does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of the technical solution of the present disclosure.

Claims

1. A method for preparing a light emitting diode, characterized in that: include: A buffer layer (20) and a leveling layer (30) are sequentially formed on a substrate (10); Alternating between a plurality of temperature-lowering growth stages and a plurality of temperature-raising growth stages to form a first insertion layer on the fill layer (30), wherein in the temperature-lowering growth stage, a first sublayer (41) is formed at a first temperature, the first temperature being lower than the growth temperature of the fill layer (30); and in the temperature-raising growth stage, a second sublayer (42) is formed at a second temperature, the second temperature being higher than the first temperature; A first semiconductor layer (50), a light-emitting layer (60) and a second semiconductor layer (70) are sequentially formed on the first insertion layer (40), and the second temperature is lower than the growth temperature of the first semiconductor layer (50).

2. The preparation method according to claim 1, characterized in that: The difference between the second temperature and the first temperature is 20°C to 50°C.

3. The preparation method according to claim 2, characterized in that: The first temperature is 1020°C to 1050°C, and the second temperature is 1040°C to 1070°C.

4. The preparation method according to any one of claims 1 to 3, characterized in that: The step of forming a first insertion layer (40) on the leveling layer (30) further comprises: Before the plurality of temperature-lowering growth stages and the plurality of temperature-increasing growth stages are alternately performed, a third sublayer (43) is formed at a third temperature, wherein the third temperature is greater than the first temperature and less than the second temperature.

5. The preparation method according to claim 4, characterized in that: The difference between the third temperature and the first temperature is 30° C. to 60° C.

6. The preparation method according to claim 4, characterized in that: The thickness of the third sub-layer (43) is greater than the thickness of the first sub-layer (41), and greater than the thickness of the second sub-layer (42).

7. The preparation method according to any one of claims 1 to 3 and claims 5 to 6, characterized in that: The method further comprises: Before forming the light-emitting layer (60), a second insertion layer (80) is formed on the first semiconductor layer (50) in the following manner: forming a fourth sublayer (81) at a fourth temperature, the fourth temperature being lower than the growth temperature of the first semiconductor layer (50); forming a fifth sublayer (82) at a fifth temperature, the fifth temperature being lower than the fourth temperature; and forming a sixth sublayer (83) at a sixth temperature, the sixth temperature being lower than the fifth temperature and higher than the growth temperature of the light-emitting layer (60).

8. The preparation method according to claim 7, characterized in that: A difference between the fourth temperature and the fifth temperature is 10°C to 40°C, and a difference between the fifth temperature and the sixth temperature is 20°C to 50°C.

9. The preparation method according to claim 8, characterized in that: The fourth temperature is 1030°C to 1060°C, the fifth temperature is 1020°C to 1050°C, and the sixth temperature is 1000°C to 1040°C.

10. A light emitting diode, characterized in that: It comprises a substrate (10), a buffer layer (20), a fill layer (30), a first insertion layer (40), a first semiconductor layer (50), a light-emitting layer (60) and a second semiconductor layer (70) which are stacked in sequence; The first insertion layer (40) comprises a plurality of first sublayers (41) and a plurality of second sublayers (42) stacked alternately, wherein the first sublayers (41) are formed at a first temperature, which is lower than the growth temperature of the filling layer (30), and the second sublayers (42) are formed at a second temperature, which is higher than the first temperature and lower than the growth temperature of the first semiconductor layer (50).

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