Light-emitting diode chip with composite current blocking layer and preparation method of light-emitting diode chip

Abstract

The invention provides a light emitting diode chip with a composite current blocking layer and a preparation method thereof, and belongs to the technical field of semiconductors. The light-emitting diode chip comprises an epitaxial layer and a composite current blocking layer. The composite current blocking layer is located on one side of the epitaxial layer, the composite current blocking layer comprises a first current blocking layer and a second current blocking layer which are sequentially stacked, and the etching angle of a channel of the light-emitting diode chip is 60-80 degrees. The light emitting efficiency of the light emitting diode chip can be effectively improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a light emitting diode chip with a composite current blocking layer and a preparation method thereof. Background Art

[0002] A light emitting diode (LED) is a semiconductor diode that can convert electrical energy into light energy.

[0003] In the related art, the light-emitting diode chip is an important component of the light-emitting diode. The light-emitting diode chip mainly includes an epitaxial layer and an electrode. In order to avoid the current crowding effect around the electrode due to the area with high current density being mainly concentrated under and near the electrode, which affects the light-emitting and heat-generating uniformity of the light-emitting diode chip and the stability and reliability of far-field emission. Usually, a current blocking layer is set between the electrode and the epitaxial layer, thereby reducing the current density under and near the electrode, alleviating the current crowding effect, and facilitating the diffusion of more current, thereby improving the internal quantum efficiency and light extraction efficiency of the light-emitting diode chip.

[0004] However, the current blocking layer and the epitaxial layer described in the related art have a small etching angle after mesa etching, which is not conducive to the emission of light from the epitaxial layer, thereby reducing the light output rate of the light emitting diode chip. Summary of the invention

[0005] The embodiment of the present disclosure provides a light emitting diode chip with a composite current blocking layer and a preparation method thereof, which can effectively improve the light extraction efficiency of the light emitting diode chip. The technical solution is as follows:

[0006] In one aspect, an embodiment of the present disclosure provides a light-emitting diode chip, comprising an epitaxial layer and a composite current blocking layer;

[0007] The composite current blocking layer is located on one side of the epitaxial layer, and the composite current blocking layer includes a first current blocking layer and a second current blocking layer stacked in sequence. The etching angle of the channel of the light emitting diode chip is 60-80°.

[0008] In another implementation of the present disclosure, the first current blocking layer is an Al2O3 film;

[0009] The second current blocking layer is a SiO2 thin film.

[0010] In another implementation of the present disclosure, the thickness of the first current blocking layer is

[0011] The thickness of the second current blocking layer is

[0012] On the other hand, the embodiment of the present disclosure provides a method for preparing a light-emitting diode chip, which is used to prepare the light-emitting diode chip described in the previous aspect, and the preparation method comprises:

[0013] preparing an epitaxial layer;

[0014] Sequentially preparing a first current blocking layer and a second current blocking layer on one side of the epitaxial layer to prepare a composite current blocking layer, wherein an etching rate of the first current blocking layer is lower than an etching rate of the second current blocking layer;

[0015] Through photolithography, the channel pattern is produced;

[0016] Based on the channel pattern, the composite current blocking layer and the epitaxial layer are etched to obtain a channel terrace, and the etching angle of the channel is 60-80°.

[0017] In an implementation of the present disclosure, the etching rate of the first current blocking layer is 40% to 60% lower than the etching rate of the second current blocking layer.

[0018] In one implementation of the present disclosure, preparing the first current blocking layer includes:

[0019] The temperature in the chamber of the atomic layer deposition equipment is set to 180-260°C;

[0020] The first precursor and the second precursor are introduced alternately for multiple times to deposit the first current blocking layer, wherein the first precursor is H2O, and the second precursor is TMA.

[0021] In one implementation of the present disclosure, preparing the first current blocking layer further includes:

[0022] After the first precursor is introduced and before the second precursor is introduced, N2 is introduced for flushing;

[0023] After the second precursor is introduced and before the first precursor is introduced, N2 is introduced for flushing.

[0024] In one implementation of the present disclosure, preparing the second current blocking layer includes:

[0025] The temperature in the chamber of the plasma enhanced chemical vapor deposition equipment is set to 200-260°C, the pressure in the chamber is set to 80-100Pa, and the upper radio frequency power is set to 70-90W;

[0026] N2 is used as a carrier gas, and Si source gas and O source gas are introduced to deposit the second current blocking layer.

[0027] In one implementation of the present disclosure, preparing the second current blocking layer further includes:

[0028] SiH4 is used as the Si source gas, and the flow rate is set to 100-140 sccm;

[0029] N2O is used as the O source gas, and the flow rate is set to 1600-2000 sccm.

[0030] In one implementation of the present disclosure, preparing the second current blocking layer further includes:

[0031] The flow rate of the carrier gas is set to 500-700 sccm.

[0032] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0033] The light-emitting diode chip includes an epitaxial layer and a composite current blocking layer. The composite current blocking layer is located on one side of the epitaxial layer and can play a role of current blocking, avoiding the current crowding effect, thereby improving the light emission and heat generation uniformity of the light-emitting diode chip, thereby improving the internal quantum efficiency and light extraction efficiency of the light-emitting diode chip. In addition, since the composite current blocking layer includes a first current blocking layer and a second current blocking layer stacked in sequence, when etching the channel table, the etching rate of the first current blocking layer and the etching rate of the second current blocking layer are different, which will increase the etching angle of the channel to 60-80°, and the larger etching angle of the channel is conducive to the light being emitted from the epitaxial layer, thereby improving the light extraction efficiency of the light-emitting diode chip.

[0034] That is to say, by providing the composite current blocking layer, the composite current blocking layer not only ensures its own current blocking function, but also plays a role in increasing the etching angle of the channel, thereby effectively improving the light extraction efficiency of the light emitting diode chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 is a structural schematic diagram of a light-emitting diode chip provided by an embodiment of the present disclosure;

[0037] Figure 2 is a flow chart of a method for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0038] Figure 3 It is a flow chart of another method for preparing a light emitting diode chip provided in an embodiment of the present disclosure.

[0039] The symbols in the figure mean the following:

[0040] 1. Epitaxial layer;

[0041] 11. first semiconductor layer; 12. active layer; 13. second semiconductor layer;

[0042] 2. Composite current blocking layer;

[0043] 21. a first current blocking layer; 22. a second current blocking layer;

[0044] 3. Substrate;

[0045] 4. Transparent conductive layer;

[0046] 5. Insulation layer;

[0047] 6. P-type electrode;

[0048] 7. N-type electrode.

[0049] The above drawings have shown clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0051] In order to better illustrate the light-emitting diode chip with a composite current blocking layer provided by the embodiment of the present disclosure, the role of the current blocking layer in the light-emitting diode chip in the related art is first described.

[0052] In the related art, for upright blue-green LED chips, due to the insulating properties of the sapphire substrate, the N-type electrode and the P-type electrode are both located on the same side of the epitaxial layer. As a result, the current needs to move laterally. Since the conductivity of the Mg-doped P-type GaN layer is much lower than that of the N-type GaN layer, the resistance of the current flowing laterally at the P-type GaN layer is relatively high, resulting in a concentrated area of ​​high current density below or near the P-type electrode, resulting in a current crowding effect, which greatly affects the light emission and heat generation uniformity of the LED chip and the stability and reliability of the far-field emission. In addition, the current crowding effect will also cause the internal quantum efficiency of the LED chip to decrease due to excessive current density in some parts.

[0053] In order to solve the above problems, in the relevant technology, a current blocking layer is set between the P-type electrode and the epitaxial layer, thereby reducing the current density below and near the P-type electrode, alleviating the current crowding effect, and facilitating the diffusion of more current, thereby improving the internal quantum efficiency and light extraction efficiency of the light-emitting diode chip.

[0054] The embodiment of the present disclosure provides a light emitting diode chip, Figure 1 is a schematic diagram of the structure of the light emitting diode chip, combined with Figure 1 In this embodiment, the light emitting diode chip includes an epitaxial layer 1 and a composite current blocking layer 2 .

[0055] The composite current blocking layer 2 is located on one side of the epitaxial layer 1 , and the composite current blocking layer 2 includes a first current blocking layer 21 and a second current blocking layer 22 which are stacked in sequence.

[0056] It is worth noting that the etching rate of the first current blocking layer 21 is lower than the etching rate of the second current blocking layer 22 , which means that under the same etching conditions, the etching speed of the first current blocking layer 21 is slower than the etching speed of the second current blocking layer 22 .

[0057] The light-emitting diode chip includes an epitaxial layer 1 and a composite current blocking layer 2. The composite current blocking layer 2 is located on one side of the epitaxial layer 1 and can play a role in current blocking, thereby avoiding the current crowding effect, thereby improving the light emission and heat generation uniformity of the light-emitting diode chip, and further improving the internal quantum efficiency and light extraction efficiency of the light-emitting diode chip. In addition, since the composite current blocking layer 2 includes a first current blocking layer 21 and a second current blocking layer 22 stacked in sequence, when etching the channel table, the etching rate of the first current blocking layer 21 and the etching rate of the second current blocking layer 22 are different, thereby increasing the etching angle a of the channel table to 60-80°, and the larger etching angle a of the channel table is conducive to the light being emitted from the epitaxial layer 1, thereby improving the light extraction efficiency of the light-emitting diode chip.

[0058] That is to say, by providing the composite current blocking layer 2, the composite current blocking layer 2 not only ensures its own current blocking function, but also increases the etching angle a of the channel terrace, thereby effectively improving the light extraction efficiency of the LED chip.

[0059] In this embodiment, the etching rate of the first current blocking layer 21 is lower than the etching rate of the second current blocking layer 22 .

[0060] Exemplarily, the etching rate of the first current blocking layer 21 is 40% to 60% lower than the etching rate of the second current blocking layer 22 .

[0061] In the above implementation, the etching rate relationship between the first current blocking layer 21 and the second current blocking layer 22 is designed to be the above ratio, which can ensure that the etching angle a of the channel terrace can be improved on the one hand, and on the other hand, can also ensure the etching efficiency of the composite current blocking layer 2.

[0062] It is worth noting that, assuming that the etching rate of the first current blocking layer 21 is 50% lower than the etching rate of the second current blocking layer 22, the etching rate of the first current blocking layer 21 is x, and the etching rate of the second current blocking layer 22 is y, then x and y satisfy the following relationship: y=x(1-50%).

[0063] In this embodiment, the etching rate of the first current blocking layer 21 is 50% lower than the etching rate of the second current blocking layer 22 .

[0064] In the above implementation, the etching rate relationship between the first current blocking layer 21 and the second current blocking layer 22 is designed to be the above ratio, which can ensure that the etching angle a of the channel terrace can be improved on the one hand, and on the other hand, can also ensure the etching efficiency of the composite current blocking layer 2.

[0065] Of course, in other embodiments, the etching rate relationship value between the first current blocking layer 21 and the second current blocking layer 22 can also be selected as other values ​​within the above numerical range, such as 55%, etc., and the present disclosure does not limit this.

[0066] In this embodiment, the first current blocking layer 21 is an Al2O3 film, and the second current blocking layer 22 is a SiO2 film.

[0067] In the above implementation, the first current blocking layer 21 is designed as an Al2O3 film, and the second current blocking layer 22 is designed as a SiO2 film. On the one hand, it can meet the functional effect of current blocking, and on the other hand, it can meet the etching rate of the first current blocking layer 21, which is 40% to 60% lower than the etching rate of the second current blocking layer 22, thereby facilitating increasing the etching angle a of the channel table.

[0068] In other embodiments, the first current blocking layer 21 and the second current blocking layer 22 may also be other thin film layers, such as any two of the following thin film layers: TiO2 thin film, HfO2 thin film, Ta2O5 thin film, ZrO thin film, AlN thin film, TiN thin film, SiNx thin film, etc. It is only necessary that the etching rate of the first current blocking layer 21 is lower than the etching rate of the second current blocking layer 22.

[0069] In this embodiment, the thickness of the first current blocking layer 21 is The thickness of the second current blocking layer 22 is

[0070] In the above implementation, since the etching rate of the first current blocking layer 21 is low, the thickness of the first current blocking layer 21 is designed to be relatively small, which can be beneficial to improving the overall etching efficiency of the composite current blocking layer 2. In addition, the thickness of the first current blocking layer 21 and the second current blocking layer 22 is designed to be the above values, which can ensure the etching time of the channel mesa, so that after the etching of the channel mesa is completed, the etching angle a of the obtained channel mesa can be significantly increased.

[0071] The composite current blocking layer 2 is introduced above, and the other thin film layers of the light emitting diode chip are introduced below.

[0072] See again Figure 1 In this embodiment, the epitaxial layer 1 includes a first semiconductor layer 11, an active layer 12 and a second semiconductor layer 13 stacked in sequence. The first semiconductor layer 11 is of a first conductivity type, and the second semiconductor layer 13 is of a second conductivity type, and the second conductivity type is different from the first conductivity type.

[0073] When the light emitting diode chip is working, electron transition occurs between the first semiconductor layer 11 and the second semiconductor layer 13 , so that the active layer 12 emits light.

[0074] Exemplarily, the first semiconductor layer 11 is an N-type gallium nitride layer, the active layer 12 is a quantum well layer, and the second semiconductor layer 13 is a P-type gallium nitride layer.

[0075] In this embodiment, the light emitting diode chip further includes a substrate 3 , which can provide a basis for the growth of the epitaxial layer 1 .

[0076] Exemplarily, the substrate 3 is a sapphire substrate, a silicon wafer substrate, or other light emitting diode chip substrate materials.

[0077] Of course, in other embodiments, the light emitting diode chip may not have the substrate 3, and the present disclosure does not limit this.

[0078] In this embodiment, the light emitting diode chip further includes a transparent conductive layer 4 , and the transparent conductive layer 4 covers one side of the epitaxial layer 1 and the current blocking layer.

[0079] The transparent conductive layer 4 is transparent and conductive. When the active layer 12 emits light, the light can pass through the transparent conductive layer 4 smoothly without being absorbed or scattered, thereby improving the light extraction efficiency of the light emitting diode chip and further improving the light emitting brightness of the light emitting diode chip. At the same time, the transparent conductive layer 4 is conductive and can provide current for the epitaxial layer 1.

[0080] Exemplarily, the transparent conductive layer 4 is an indium tin oxide ITO layer, and the transparent conductive layer 4 is formed by sputtering on the epitaxial layer 1 using magnetron sputtering technology. ITO has both optical transparency and high conductivity. When the active layer 12 emits light, the light can pass through the transparent conductive layer 4 smoothly. The high conductivity ensures that the current can be effectively transferred to the active layer 12, thereby improving the luminous efficiency of the light-emitting diode chip.

[0081] In this embodiment, the light emitting diode chip further comprises an insulating layer 5, which is SiO2 and covers the epitaxial layer 1 and the transparent conductive layer 4. The insulating layer 5 is used for insulating protection to avoid unnecessary short circuit between the epitaxial layer 1 and the transparent conductive layer 4.

[0082] In this embodiment, the light emitting diode chip further includes a P-type electrode 6 and an N-type electrode 7 .

[0083] The P-type electrode 6 sequentially penetrates the insulating layer 5 , the transparent conductive layer 4 and the composite current blocking layer 2 to contact the second semiconductor layer 13 , and the N-type electrode 7 penetrates the insulating layer 5 to contact the first semiconductor layer 11 .

[0084] Exemplarily, the material of the P-type electrode 6 and the N-type electrode 7 is one or a combination of metals such as Cr, Al, AlCu, Ti, Ni, Pt, and Au.

[0085] Figure 2 is a flow chart of a method for preparing a light emitting diode chip provided by an embodiment of the present disclosure, for preparing Figure 1 The light emitting diode chip shown in this embodiment is prepared by a method comprising:

[0086] Step 201: Prepare an epitaxial layer 1.

[0087] Step 202 : sequentially preparing a first current blocking layer 21 and a second current blocking layer 22 on one side of the epitaxial layer 1 to prepare a composite current blocking layer 2 , wherein the etching rate of the first current blocking layer 21 is lower than that of the second current blocking layer 22 .

[0088] Step 203: Produce channel patterns through photolithography.

[0089] Step 204: Based on the channel pattern, the composite current blocking layer 2 and the epitaxial layer 1 are etched to obtain a channel terrace, and the etching angle of the channel is 60-80°.

[0090] A composite current blocking layer 2 is prepared on one side of the epitaxial layer 1. The composite current blocking layer 2 can play a role of current blocking, avoiding the current crowding effect, thereby improving the light emission and heat generation uniformity of the light-emitting diode chip, and further improving the internal quantum efficiency and light extraction efficiency of the light-emitting diode chip. In addition, since the composite current blocking layer 2 includes a first current blocking layer 21 and a second current blocking layer 22 stacked in sequence, and the etching rate of the first current blocking layer 21 is different from the etching rate of the second current blocking layer 22, when etching the channel table, the photoresist is used as a soft mask, and the composite current blocking layer 2 is used as a hard-soft film, which will increase the etching angle a of the channel table, and the larger etching angle a of the channel table is conducive to the light being emitted from the epitaxial layer 1, thereby improving the light extraction efficiency of the light-emitting diode chip.

[0091] That is to say, by providing the composite current blocking layer 2, the composite current blocking layer 2 not only ensures its own current blocking function, but also increases the etching angle a of the channel terrace, thereby effectively improving the light extraction efficiency of the LED chip.

[0092] Figure 3 is a flow chart of another method for preparing a light emitting diode chip provided in an embodiment of the present disclosure. In this embodiment, the preparation method includes:

[0093] Step 301: Provide a substrate 3.

[0094] Exemplarily, the substrate 3 is a sapphire substrate 3 , a silicon wafer substrate 3 , or other light emitting diode chip substrate 3 materials.

[0095] Step 302: Prepare an epitaxial layer 1.

[0096] Exemplarily, a metal-organic chemical vapor deposition (MOCVD) technique is used to sequentially grow a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13. The first semiconductor layer 11 has a first conductivity type, and the second semiconductor layer 13 has a second conductivity type different from the first conductivity type. Energy transition occurs between the first semiconductor layer 11 and the second semiconductor layer 13, and the active layer 12 emits light.

[0097] Exemplarily, the first semiconductor layer 11 is an N-type gallium nitride layer, the active layer 12 is a quantum well layer, and the second semiconductor layer 13 is a P-type gallium nitride layer.

[0098] Step 303 : preparing a first current blocking layer 21 on one side of the epitaxial layer 1 .

[0099] Exemplarily, step 303 includes the following steps:

[0100] Step 3031: Set the temperature in the chamber of the atomic layer deposition (ALD) device to 180-260°C.

[0101] Exemplarily, the temperature in the chamber of the atomic layer deposition equipment is set to 200-220°C.

[0102] Step 3032: Introduce the first precursor.

[0103] Exemplarily, the first precursor is gaseous H2O, which is used to provide an O source.

[0104] Step 3033: Introduce N2 for flushing.

[0105] Step 3034: Introduce the second precursor.

[0106] Exemplarily, the second precursor is gaseous TMA (trimethylaluminum), which is used to provide an Al source.

[0107] Step 3035: Introduce N2 for flushing.

[0108] Repeat steps 3032 to 3035 until the growth is obtained. The first current blocking layer 21 is formed.

[0109] Step 304 : preparing a second current blocking layer 22 on one side of the first current blocking layer 21 .

[0110] Exemplarily, step 304 includes the following steps:

[0111] Step 3041: Set the chamber temperature of the plasma enhanced chemical vapor deposition (PECVD) equipment to 200-260° C., the chamber pressure to 80-100 Pa, and the upper RF power to 70-90 W.

[0112] Exemplarily, the model of the plasma enhanced chemical vapor deposition equipment is E550.

[0113] Step 3042 : Using N 2 as a carrier gas, introducing Si source gas and O source gas to deposit a second current blocking layer 22 .

[0114] Exemplarily, the flow rate of the carrier gas is set to 500-700 sccm, SiH 4 is used as the Si source gas, the flow rate is set to 100-140 sccm, and N 2 O is used as the O source gas, the flow rate is set to 1600-2000 sccm.

[0115] In this embodiment, the flow rate of the carrier gas is set to 600 sccm, the flow rate of the Si source gas is set to 120 sccm, and the flow rate of the O source gas is set to 1800 sccm.

[0116] Step 305: fabricate a channel pattern through a photolithography process.

[0117] In the above implementation, the photoresist forming the channel pattern is used as a soft mask in the subsequent step 306 .

[0118] Step 306: Based on the channel pattern, the composite current blocking layer 2 and the epitaxial layer 1 are etched to obtain a channel terrace.

[0119] In the above implementation, the photoresist is used as a soft mask, and the composite current blocking layer 2 is used as a hard-soft film, which increases the etching angle a of the channel terrace. A larger etching angle a of the channel terrace is conducive to the light being emitted from the epitaxial layer 1, thereby improving the light extraction efficiency of the light-emitting diode chip.

[0120] Exemplarily, the etching angle a of the channel terrace is 60° to 80°.

[0121] Step 307: growing a transparent conductive layer 4.

[0122] Exemplarily, a layer of indium tin oxide (ITO) film is deposited by magnetron sputtering technology or electron beam evaporation process, and a part of the ITO film is removed by photolithography and chemical wet etching process to form the transparent conductive layer 450 .

[0123] Step 308: Prepare an insulating layer 5.

[0124] Exemplarily, the insulating layer 5 is a DBR layer or a SiO2 layer, wherein the DBR layer is prepared by an optical coating machine, and the SiO2 layer is deposited by a PECVD (plasma enhanced chemical vapor deposition) device.

[0125] Step 309 : etching a first through hole and a second through hole in the insulating layer 5 .

[0126] Step 310: Prepare a P-type electrode 6 to pass through the first through hole to connect to the second semiconductor layer 13, and prepare an N-type electrode 7 to pass through the second through hole to connect to the first semiconductor layer 11.

[0127] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0128] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode chip, characterized in that: It comprises an epitaxial layer (1) and a composite current blocking layer (2); The composite current blocking layer (2) is located on one side of the epitaxial layer (1), the composite current blocking layer (2) comprises a first current blocking layer (21) and a second current blocking layer (22) stacked in sequence, and the etching angle of the channel of the light-emitting diode chip is 60-80°.

2. The light emitting diode chip according to claim 1, characterized in that: The first current blocking layer (21) is an Al2O3 thin film; The second current blocking layer (22) is a SiO2 thin film.

3. The light emitting diode chip according to claim 1, characterized in that: The thickness of the first current blocking layer (21) is The thickness of the second current blocking layer (22) is 4. A method for preparing a light emitting diode chip, characterized in that: For preparing the light emitting diode chip according to claim 1, the preparation method comprises: Preparing an epitaxial layer (1); A first current blocking layer (21) and a second current blocking layer (22) are sequentially prepared on one side of the epitaxial layer (1) to prepare a composite current blocking layer (2), wherein the etching rate of the first current blocking layer (21) is lower than the etching rate of the second current blocking layer (22); Through photolithography, the channel pattern is produced; Based on the channel pattern, the composite current blocking layer (2) and the epitaxial layer (1) are etched to obtain a channel terrace, and the etching angle of the channel is 60-80°.

5. The preparation method according to claim 4, characterized in that: The etching rate of the first current blocking layer (21) is 40% to 60% lower than the etching rate of the second current blocking layer (22).

6. The preparation method according to claim 4, characterized in that: The first current blocking layer (21) is prepared, comprising: The temperature in the chamber of the atomic layer deposition equipment is set to 180-260°C; The first precursor and the second precursor are introduced alternately multiple times to deposit the first current blocking layer (21), wherein the first precursor is H2O and the second precursor is TMA.

7. The preparation method according to claim 6, characterized in that: The method of preparing the first current blocking layer (21) further comprises: After the first precursor is introduced and before the second precursor is introduced, N2 is introduced for flushing; After the second precursor is introduced and before the first precursor is introduced, N2 is introduced for flushing.

8. The preparation method according to claim 4, characterized in that: The second current blocking layer (22) is prepared, comprising: The temperature in the chamber of the plasma enhanced chemical vapor deposition equipment is set to 200-260°C, the pressure in the chamber is set to 80-100Pa, and the upper radio frequency power is set to 70-90W; N2 is used as a carrier gas, and Si source gas and O source gas are introduced to deposit the second current blocking layer (22).

9. The preparation method according to claim 8, characterized in that: The method of preparing the second current blocking layer (22) further comprises: SiH4 is used as the Si source gas, and the flow rate is set to 100-140 sccm; N2O is used as the O source gas, and the flow rate is set to 1600-2000 sccm.

10. The preparation method according to claim 8, characterized in that: The method of preparing the second current blocking layer (22) further comprises: The flow rate of the carrier gas is set to 500-700 sccm.

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