Light emitting diode for improving electrode loosening and preparation method thereof

Abstract

The invention provides a light-emitting diode for improving electrode loosening and a preparation method thereof, and belongs to the technical field of photoelectron manufacturing. The light-emitting diode comprises an epitaxial layer, a transparent conductive layer, a passivation layer and a bonding pad, the transparent conductive layer is located on the surface of the epitaxial layer, the passivation layer is located on the surface of the epitaxial layer and covers the transparent conductive layer, the transparent conductive layer is provided with a first through hole exposing the epitaxial layer, and the bonding pad is located in the first through hole. And / or the passivation layer is provided with a second through hole for exposing the epitaxial layer; a barrier layer is arranged in the first through hole and / or the second through hole, the barrier layer is provided with a hollow, and the bonding pad is located on the surface, away from the epitaxial layer, of the barrier layer and electrically connected with the epitaxial layer through the hollow. According to the embodiment of the invention, the problem of electrode routing failure can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode with improved electrode loosening and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) is an extremely influential new product in the optoelectronics industry. It has the characteristics of small size, long service life, rich colors and low energy consumption. It is widely used in lighting, display screens, signal lights, backlight sources, toys and other fields.

[0003] In the related art, the light-emitting diode includes: an epitaxial layer, a transparent conductive layer, a pad and a finger bar, wherein the transparent conductive layer is located on the surface of the epitaxial layer and has a through hole. One end of the finger bar is connected to the pad, which is located in the through hole and electrically connected to the epitaxial layer. The finger bar is located on the transparent conductive layer, and the pad is used to connect to an external power source and transmit current to various areas of the epitaxial layer through the finger bar.

[0004] Since the pads are mostly made of metal, they absorb light. To prevent the pads from absorbing light, a passivation layer is usually set between the pads and the epitaxial layer. The passivation layer is mostly a silicon oxide layer, and the refractive index of the passivation layer and the epitaxial layer is different, so that the path of the light incident on the passivation layer will change, allowing part of the light to be refracted, thereby preventing the light from being absorbed by the pads. However, the direct connection between the pads and the passivation layer can easily lead to the problem of the pads loosening, causing the electrode wire to fail. Summary of the invention

[0005] The embodiment of the present disclosure provides a light-emitting diode with improved electrode loosening and a method for manufacturing the same, which can improve the problem of electrode wire failure. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode, which includes an epitaxial layer, a transparent conductive layer, a passivation layer and a pad, wherein the transparent conductive layer is located on the surface of the epitaxial layer, the passivation layer is located on the surface of the epitaxial layer and covers the transparent conductive layer, the transparent conductive layer has a first through hole exposing the epitaxial layer, and / or the passivation layer has a second through hole exposing the epitaxial layer; a blocking layer is arranged in the first through hole and / or the second through hole, the blocking layer has a hollow, the pad is located on the surface of the blocking layer away from the epitaxial layer, and is electrically connected to the epitaxial layer through the hollow.

[0007] Optionally, the blocking layer includes: a blocking block and a blocking ring, the blocking block is located inside the blocking ring, and the blocking block and the blocking ring are arranged concentrically, and the annular gap between the blocking block and the blocking ring is the hollowing.

[0008] Optionally, the orthographic projections of the pad and the blocking block on the surface of the epitaxial layer are circular, and the projection diameter of the blocking block is less than 0.75 times the projection diameter of the pad.

[0009] Optionally, the orthographic projection of the pad on the surface of the epitaxial layer is a circle, and the orthographic projection of the blocking ring on the surface of the epitaxial layer is a circular ring; the inner diameter of the blocking ring projection is greater than 0.8 times the diameter of the pad projection, and the inner diameter of the blocking ring projection is less than 0.9 times the diameter of the pad projection; the outer diameter of the blocking ring projection is greater than the diameter of the pad projection, and the outer diameter of the blocking ring projection is less than 1.1 times the diameter of the pad projection.

[0010] Optionally, the blocking layer includes a plurality of blocking blocks, and the plurality of blocking blocks are arranged at intervals in the first through hole and / or the second through hole.

[0011] Optionally, the orthographic projection of the pad on the surface of the epitaxial layer is a circle, and the orthographic projections of the plurality of blocking blocks on the surface of the epitaxial layer are arranged in a circular array with the center of the pad as the center.

[0012] Optionally, the orthographic projection of the blocking block on the surface of the epitaxial layer is a circle, the diameter of the blocking block projection is greater than or equal to (D-14) / 7, and the diameter of the blocking block projection is less than or equal to (D-4) / 3, and the diameter of the pad projection is D, expressed in microns.

[0013] Optionally, a distribution density of the blocking blocks in an edge region of the first through hole and / or the second through hole is smaller than a distribution density of the blocking blocks in a central region of the first through hole.

[0014] Optionally, a distribution density of the blocking blocks in a region of the first through hole close to the second through hole is greater than a distribution density of the blocking blocks in a region of the first through hole far from the second through hole.

[0015] On the other hand, the embodiment of the present disclosure also provides a method for preparing a light-emitting diode, the preparation method comprising: forming an epitaxial layer; forming a transparent conductive layer on the surface of the epitaxial layer, the transparent conductive layer having a first through hole exposing the epitaxial layer; forming a passivation layer on the surfaces of the transparent conductive layer and the epitaxial layer, the surface of the passivation layer having a via hole exposing the first through hole, and / or the passivation layer having a second through hole exposing the epitaxial layer; forming a blocking layer in the first through hole and / or the second through hole, the blocking layer having a hollow; forming a pad on the surface of the blocking layer away from the epitaxial layer, so that the pad is electrically connected to the epitaxial layer through the hollow.

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] In the light-emitting diode provided by the embodiment of the present disclosure, the transparent conductive layer is located on the surface of the epitaxial layer, and the transparent conductive layer has a first through hole exposing the epitaxial layer, a barrier layer is arranged in the first through hole, the barrier layer has a hollow, and the pad is arranged on the surface of the barrier layer away from the epitaxial layer, and is electrically connected to the epitaxial layer through the hollow. In this way, the hollow is arranged on the surface of the barrier layer, so that the pad can be embedded in the hollow and electrically connected to the epitaxial layer, which not only meets the electrical connection requirements of the pad and the epitaxial layer, but also enables the pad and the barrier layer to adopt an embedded matching of a concave-convex structure, thereby effectively improving the connection reliability of the pad and the barrier layer, preventing the pad from easily loosening from the epitaxial layer, and improving the problem of electrode wire failure.

[0018] In addition, a barrier layer is provided between the epitaxial layer and the pad, and the contact area between the pad and the barrier layer can be increased, thereby forming an omnidirectional reflector with good reflectivity, reducing the light absorbed by the pad and improving the light output rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 is a top view of a light emitting diode provided by an embodiment of the present disclosure;

[0021] Figure 2 yes Figure 1 An AA cross-sectional view is provided;

[0022] Figure 3 yes Figure 1 A partial enlarged view of location M is provided;

[0023] Figure 4 is a top view of a light emitting diode provided by an embodiment of the present disclosure;

[0024] Figure 5 yes Figure 4 A BB cross-section diagram is provided;

[0025] Figure 6 yes Figure 4 A local magnified image of N locations is provided;

[0026] Figure 7 is a schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0027] Figure 8 is a schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0028] Fig. 9 is a schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0029] Fig.10 is a schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0030] Fig.11 is a relationship diagram between the contact area between a pad and a barrier layer and the photoelectric performance provided by an embodiment of the present disclosure;

[0031] Fig.12 It is a flow chart of a method for preparing a light emitting diode provided in an embodiment of the present disclosure.

[0032] The descriptions of the marks in the figure are as follows:

[0033] 10. Substrate;

[0034] 20. epitaxial layer; 21. first semiconductor layer; 22. multi-quantum well layer; 23. second semiconductor layer;

[0035] 30. transparent conductive layer; 31. first through hole; 32. second through hole;

[0036] 41, blocking layer; 410, hollowing; 411, blocking block; 412, blocking ring;

[0037] 42. passivation layer; 421. second through hole;

[0038] 501, n-type pad; 502, p-type pad;

[0039] 51. Solder pad; 52. Finger bar. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0041] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0042] Figure 1 It is a top view of a light emitting diode provided by an embodiment of the present disclosure. Figure 2 yes Figure 1 An AA cross-section diagram is provided. Figure 1 , 2 As shown, the light-emitting diode includes an epitaxial layer 20, a transparent conductive layer 30, a passivation layer 42 and a pad 51, wherein the transparent conductive layer 30 is located on the surface of the epitaxial layer 20, the passivation layer 42 is located on the surface of the epitaxial layer 20 and covers the transparent conductive layer 30, the transparent conductive layer 30 has a first through hole 31 exposing the epitaxial layer 20, and / or the passivation layer 42 has a second through hole 32 exposing the epitaxial layer 20.

[0043] like Figure 2 As shown, a barrier layer 41 is disposed in the first through hole 31 and / or the second through hole 32, the barrier layer 41 has a hollow 410, and the pad includes a pad 51, the pad 51 is located on the surface of the barrier layer 41 away from the epitaxial layer 20, and the pad 51 is electrically connected to the epitaxial layer 20 through the hollow 410.

[0044] In the light-emitting diode provided by the embodiment of the present disclosure, the transparent conductive layer 30 is located on the surface of the epitaxial layer 20, and the transparent conductive layer 30 has a first through hole 31 exposing the epitaxial layer 20, and a barrier layer 41 is arranged in the first through hole 31, and the barrier layer 41 has a hollow 410, and the pad 51 is arranged on the surface of the barrier layer 41 away from the epitaxial layer 20, and is electrically connected to the epitaxial layer 20 through the hollow 410. In this way, the hollow 410 is arranged on the surface of the barrier layer 41, so that the pad 51 can be embedded in the hollow 410 and electrically connected to the epitaxial layer 20, which not only meets the electrical connection requirements of the pad 51 and the epitaxial layer 20, but also enables the pad 51 and the barrier layer 41 to adopt an embedded matching of a concave-convex structure, thereby effectively improving the connection reliability of the pad 51 and the barrier layer 41, preventing the pad 51 from being easily loosened from the epitaxial layer 20, and improving the problem of electrode wire failure.

[0045] Furthermore, by providing a barrier layer 41 between the epitaxial layer 20 and the pad 51 , the contact area between the pad 51 and the barrier layer 41 can be increased, thereby forming an omnidirectional reflector with good reflectivity, reducing light absorption by the pad 51 and improving light extraction efficiency.

[0046] In one implementation of the present disclosure, Figure 3 yes Figure 1 The local enlarged picture of M is provided. Figure 2 , 3 As shown, the blocking layer 41 includes: a blocking block 411 and a blocking ring 412 . The blocking block 411 is located inside the blocking ring 412 , and the blocking block 411 and the blocking ring 412 are arranged concentrically. The annular gap between the blocking block 411 and the blocking ring 412 is hollow 410 .

[0047] By setting the barrier layer 41 into concentrically distributed barrier blocks 411 and barrier rings 412, an annular gap is formed on the barrier layer 41, so that the pad 51 above the barrier layer 41 can be embedded in the annular gap, thereby improving the connection reliability between the pad 51 and the barrier layer 41, and preventing the pad 51 from easily loosening from the epitaxial layer 20.

[0048] Optionally, the orthographic projections of the pad 51 and the blocking block 411 on the surface of the epitaxial layer 20 are circular, and the projection diameter of the blocking block 411 is less than 0.75 times the projection diameter of the pad 51 .

[0049] Since the diameter of the blocking block 411 is too large, the contact area between the pad 51 and the barrier layer 41 will be larger, which will affect the connection reliability of the pad 51 and cause the pad 51 to become loose. Therefore, the diameter of the blocking block 411 is controlled to be less than 0.75 times the diameter of the pad 51, so as to reserve a large enough area so that the blocking block 411 does not contact the pad 51, and the pad 51 can be embedded in the hollow 410 of the barrier layer 41, thereby improving the connection reliability between the pad 51 and the barrier layer 41.

[0050] Exemplarily, the projected diameter of the blocking block 411 is equal to 0.3 times the projected diameter of the pad 51 .

[0051] Optionally, the orthographic projection of the pad 51 on the surface of the epitaxial layer 20 is a circle, and the orthographic projection of the barrier ring 412 on the surface of the epitaxial layer 20 is a circular ring.

[0052] like Figure 3 As shown, the inner diameter of the projection of the blocking ring 412 is greater than 0.8 times the diameter of the projection of the pad 51 , and the inner diameter of the projection of the blocking ring 412 is less than 0.9 times the diameter of the projection of the pad 51 .

[0053] This can avoid the inner diameter of the blocking ring 412 being too small, which would make the distance between the blocking ring 412 and the blocking block 411 too small, and increase the difficulty of corroding the annular gap between the blocking ring 412 and the blocking block 411; it can also avoid the inner diameter of the blocking ring 412 being too large, which would make only a very small edge area of ​​the pad 51 overlap on the blocking ring 412, affecting the connection reliability of the pad 51. In addition, in the process of corroding the barrier layer 41, there is actually an over-corrosion phenomenon, so if the inner diameter of the blocking ring 412 is too large, it will also cause the edge of the pad 51 to be unable to overlap on the barrier layer 41, which is not conducive to improving the connection reliability of the pad 51.

[0054] like Figure 3 As shown, the outer diameter of the projection of the blocking ring 412 is greater than the diameter of the projection of the pad 51 , and the outer diameter of the projection of the blocking ring 412 is less than 1.1 times the diameter of the projection of the pad 51 .

[0055] Since there is actually an over-corrosion phenomenon during the corrosion of the barrier layer 41, setting the outer diameter of the barrier ring 412 within the above range can prevent the outer diameter of the barrier ring 412 from being too small. After excessive corrosion, the edge area of ​​the pad 51 is not in contact with the barrier ring 412, so that the light at the edge area of ​​the pad is absorbed, resulting in a reduction in light extraction rate. At the same time, it can also prevent the outer diameter of the barrier ring 412 from being too large, which causes the edge area of ​​the pad 51 to be blocked by the barrier block 411, resulting in excessive current blocking and poor current diffusion.

[0056] Alternatively, if Figure 2 As shown, the passivation layer 42 is located outside the first through hole 31 and on the surface of the epitaxial layer 20, and the passivation layer 42 covers the transparent conductive layer 30. The passivation layer 42 has a second through hole 421 exposing the transparent conductive layer 30, the inner diameter of the second through hole 421 is larger than the inner diameter of the first through hole 31, and the first through hole 31 and the second through hole 421 are concentrically distributed.

[0057] Exemplarily, the inner diameter of the second through hole 421 is greater than 1.17 times the diameter of the pad 51 , and the inner diameter of the second through hole 421 is less than 1.21 times the diameter of the pad 51 .

[0058] By setting the inner diameter of the second through hole 421 within the above range, it is prevented that the inner diameter of the second through hole 421 is too small, which may easily overlap with the outer diameter of the blocking ring 412, resulting in the gap between the passivation layer 42 and the blocking ring 412 not being corroded cleanly when the passivation layer 42 is corroded, and it is difficult to form the second through hole 421; it is also prevented that the inner diameter of the second through hole 421 is too large, which may make the area of ​​the passivation layer 42 too small, causing the problem of water absorption failure of the light-emitting diode.

[0059] Alternatively, if Figure 1 As shown, the light emitting diode further includes a finger bar 52, one end of which is connected to the pad 51. The finger bar 52 covers the surface of the transparent conductive layer 30 away from the epitaxial layer 20.

[0060] The pad 51 is used to connect to an external power source so that the external power source can inject current into the pad 51. The finger bar 52 is used to allow the current in the pad 51 to expand laterally along the finger bar 52. The finger bar 52 is stacked on the transparent conductive layer 30 and is electrically connected to the epitaxial layer 20 through the transparent conductive layer 30, so that the current on the finger bar 52 can be more easily injected downward into the epitaxial layer 20.

[0061] Alternatively, if Figure 2 As shown, the light emitting diode includes a substrate 10 , and an epitaxial layer 20 is located on the surface of the substrate 10 .

[0062] For example, the substrate may be a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.

[0063] Alternatively, if Figure 2 As shown, the epitaxial layer 20 includes a first semiconductor layer 21 , a multi-quantum well layer 22 , and a second semiconductor layer 23 which are sequentially stacked on the substrate 10 .

[0064] One of the first semiconductor layer and the second semiconductor layer is a p-type layer, and the other of the first semiconductor layer and the second semiconductor layer is an n-type layer.

[0065] Exemplarily, the first semiconductor layer is an n-type layer, and the second semiconductor layer is a p-type layer.

[0066] Optionally, the first semiconductor layer is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0067] Optionally, the multi-quantum well layer includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the multi-quantum well layer may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0068] As an example, in the embodiment of the present disclosure, the multi-quantum well layer includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0069] Optionally, the thickness of the multi-quantum well layer may be 150 nm to 200 nm.

[0070] Optionally, the second semiconductor layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0071] Optionally, the light emitting diode further includes an AlN buffer layer and a u-type GaN layer, the AlN buffer layer and the u-type GaN layer are sequentially stacked on the substrate, and the epitaxial layer 20 is located on the u-type GaN layer.

[0072] Optionally, the transparent conductive layer 30 may be an indium tin oxide (ITO) layer. The ITO layer has good transmittance and low resistivity. Using the ITO layer as the transparent conductive layer 30 can allow more light to be transmitted from the transparent conductive layer 30, thereby ensuring the light output effect; at the same time, due to the low resistivity, it is also convenient for carrier conduction and improves injection efficiency.

[0073] For example, the transparent conductive layer 30 may be an indium zinc oxide (IZO) layer. The IZO layer has good transmittance and low resistivity. Using the IZO layer as the transparent conductive layer 30 can allow more light to be transmitted from the transparent conductive layer 30, thereby ensuring the light output effect; at the same time, due to the low resistivity, it is also convenient for carrier conduction and improves injection efficiency.

[0074] As an example, the thickness of the transparent conductive layer 30 may be 200 angstroms to 5000 angstroms. For example, the thickness of the transparent conductive layer 30 is 2000 angstroms.

[0075] Optionally, the passivation layer 42 may be at least one of a silicon oxide layer, an aluminum oxide layer, and a silicon nitride layer.

[0076] Exemplarily, the barrier layer 41 and the passivation layer 42 are made of the same film material. The barrier layer 41 and the passivation layer 42 can be formed in the first through hole 31 , on the surface of the transparent conductive layer 30 and on the surface of the epitaxial layer 20 by a single patterning process.

[0077] Optionally, the thickness of the passivation layer 42 may be 800 angstroms to 3000 angstroms.

[0078] Alternatively, the pad may include a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.

[0079] In another implementation of the present disclosure, Figure 4 It is a top view of a light emitting diode provided by an embodiment of the present disclosure. Figure 5 yes Figure 4 A BB cross-section diagram is provided. Figure 3 , 4 As shown, the blocking layer 41 includes a plurality of blocking blocks 411 , and the plurality of blocking blocks 411 are arranged in the first through hole 31 and / or the second through hole 32 at intervals.

[0080] By setting the blocking layer 41 into a plurality of spaced blocking blocks 411, the gaps between the blocking blocks 411 form a hollow 410, so that the pad 51 above the blocking layer 41 can be embedded in the gap between the blocking blocks 411, thereby improving the connection reliability between the pad 51 and the blocking layer 41 and preventing the pad 51 from easily loosening from the epitaxial layer 20.

[0081] Figure 6 yes Figure 4 A local magnified image of N locations is provided. Figure 6 As shown, the orthographic projection of the pad 51 on the surface of the epitaxial layer 20 is a circle, and the orthographic projections of the plurality of blocking blocks 411 on the surface of the epitaxial layer 20 are arranged in a circular array with the center of the pad 51 as the center.

[0082] The blocking blocks 411 are arranged in a circular array so that the blocking blocks 411 are more evenly distributed in the first through hole 31. While the blocking blocks 411 fill the first through hole 31, gaps of various shapes can be formed between adjacent blocking blocks 411, so that the pads 51 can be embedded in these gaps of various shapes, which can effectively improve the connection reliability between the pads 51 and the blocking layer 41.

[0083] Exemplarily, the blocking block 411 can be centered at the center of the solder pad 51, and the spacing angle between adjacent blocking blocks 411 spaced circumferentially can be controlled to be 60°, and the spacing between adjacent blocking blocks 411 spaced radially can be controlled to be the diameter of the blocking block 411 + 2, so that a plurality of blocking blocks 411 are arranged at intervals in a circular array.

[0084] Optionally, the orthographic projection of the blocking block 411 on the surface of the epitaxial layer 20 is a circle, the diameter of the projection of the blocking block 411 is greater than or equal to (D-14) / 7, and the diameter of the projection of the blocking block 411 is less than or equal to (D-4) / 3, and the diameter of the projection of the pad 51 is D, in micrometers.

[0085] In the disclosed embodiment, the diameter of the blocking block 411 can be designed according to the wire bonding requirements of the solder pad of the light emitting diode and the photoelectric performance requirements.

[0086] Figure 7 Schematic diagram of a light emitting diode provided by an embodiment of the present disclosure. Figure 7 As shown, the diameter of the blocking block 411 can be designed to be the minimum diameter, that is, the diameter of the blocking block 411 is (D-14) / 7, at which time the blocking blocks 411 are more densely distributed, and more small-sized gaps are reserved between the blocking blocks 411, so that the pads 51 can be embedded in these small-sized gaps. In this way, the stability of the bonding of the pads 51 can be ensured, that is, the pads 51 can be more stably connected to the epitaxial layer 20.

[0087] Figure 8 Schematic diagram of a light emitting diode provided by an embodiment of the present disclosure. Figure 8 As shown, the diameter of the blocking block 411 can be set to a maximum diameter, so that the blocking block 411 occupies more space in the first through hole 31, so that more light can be refracted through the blocking block 411 and prevented from being absorbed by the pad 51, thereby improving the light-emitting effect of the light-emitting diode.

[0088] Fig. 9 Schematic diagram of a light emitting diode provided by an embodiment of the present disclosure. Fig. 9 As shown, the distribution density of the blocking blocks 411 in the edge area of ​​the first through hole 31 and / or the second through hole 32 is less than the distribution density of the blocking blocks 411 in the central area of ​​the first through hole 31 .

[0089] The distribution density may refer to the number of blocking blocks 411 distributed in a unit area.

[0090] In the embodiment of the present disclosure, the distribution density of the blocking blocks 411 in the edge region of the first through hole 31 is less than the distribution density of the blocking blocks 411 in the central region of the first through hole 31. This indicates that the distribution spacing of the blocking blocks 411 in the edge region of the first through hole 31 is larger, so that the blocking blocks 411 are distributed more sparsely, while the distribution spacing of the blocking blocks 411 in the central region of the first through hole 31 is smaller, so that the blocking blocks 411 are distributed more densely.

[0091] Since the edge area of ​​the pad 51 usually has poor connection stability with the blocking block 411, the blocking blocks 411 are distributed more sparsely in the edge area of ​​the first through hole 31, and more densely in the central area of ​​the first through hole 31. This makes the pad 51 less in contact with the blocking block 411 in the edge area of ​​the first through hole 31, and makes the pad 51 more in contact with the epitaxial layer 20 in the edge area of ​​the first through hole 31, so as to improve the connection reliability between the pad 51 and the blocking block 411 in the edge area.

[0092] It should be noted that the orthographic projection of the blocking block 411 on the surface of the epitaxial layer 20 may be a circle, a polygon, an ellipse or other irregular shapes, and the embodiment of the present disclosure does not limit this.

[0093] Alternatively, if Figure 5 As shown, the light emitting diode comprises a substrate, and an epitaxial layer 20 is located on the surface of the substrate.

[0094] For example, the substrate may be a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.

[0095] Optionally, the epitaxial layer 20 includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer sequentially stacked on the substrate.

[0096] One of the first semiconductor layer and the second semiconductor layer is a p-type layer, and the other of the first semiconductor layer and the second semiconductor layer is an n-type layer.

[0097] Exemplarily, the first semiconductor layer is an n-type layer, and the second semiconductor layer is a p-type layer.

[0098] Optionally, the first semiconductor layer is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0099] Optionally, the multi-quantum well layer includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the multi-quantum well layer may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0100] As an example, in the embodiment of the present disclosure, the multi-quantum well layer includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0101] Optionally, the thickness of the multi-quantum well layer may be 150 nm to 200 nm.

[0102] Optionally, the second semiconductor layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0103] Optionally, the transparent conductive layer 30 may be an ITO layer or an IZO layer.

[0104] As an example, the thickness of the transparent conductive layer 30 may be 200 angstroms to 5000 angstroms. For example, the thickness of the transparent conductive layer 30 is 2000 angstroms.

[0105] Optionally, the passivation layer 42 may be at least one of a silicon oxide layer, an aluminum oxide layer, and a silicon nitride layer.

[0106] Exemplarily, the barrier layer 41 and the passivation layer 42 are made of the same film material. The barrier layer 41 and the passivation layer 42 can be formed in the first through hole 31 , on the surface of the transparent conductive layer 30 and on the surface of the epitaxial layer 20 by a single patterning process.

[0107] Optionally, the thickness of the passivation layer 42 may be 800 angstroms to 3000 angstroms.

[0108] Alternatively, if Figure 5 As shown, the surface of the second semiconductor layer has a groove exposing the second semiconductor layer.

[0109] In the embodiment of the present disclosure, the light emitting diode includes an n-type pad 501 and a p-type pad 502, that is, the pad includes an n-type pad 501 and a p-type pad 502. The n-type pad 501 and the p-type pad 502 are arranged on the surface of the epitaxial layer 20 at intervals.

[0110] Exemplarily, the first semiconductor layer is an n-type layer, and the second semiconductor layer is a p-type layer. The n-type pad 501 is located on the surface of the second semiconductor layer, and the p-type pad 502 is located in the groove and is electrically connected to the first semiconductor layer.

[0111] like Figure 5 As shown, a barrier layer 41 is disposed in the groove and in the first through hole 31 of the transparent conductive layer 30. That is, the passivation layer 42 is located on the surface of the second semiconductor layer and extends into the groove.

[0112] like Figure 5 As shown, the n-type pad 501 is located in the groove and on the surface of the barrier layer 41 in the groove, and is connected to the first semiconductor layer through the hollow 410 of the barrier layer 41 .

[0113] like Figure 5 As shown, the transparent conductive layer 30 is located on the surface of the second semiconductor layer, and the p-type pad 502 is located in the first through hole 31 of the transparent conductive layer 30 . A barrier layer 41 is provided in the first through hole 31 , and is connected to the second semiconductor layer through the hollow 410 of the barrier layer 41 .

[0114] The barrier layer 41 in the groove may have the same structure as the barrier layer 41 in the first through hole 31 , which will not be elaborated in the embodiment of the present disclosure.

[0115] Fig.10 Schematic diagram of a light emitting diode provided by an embodiment of the present disclosure. Fig.10 As shown, the distribution density of the blocking blocks 411 in the area of ​​the first through hole 31 close to the second through hole 32 is greater than the distribution density of the blocking blocks 411 in the area of ​​the first through hole 31 far from the second through hole 32 .

[0116] After the light-emitting diode is powered on, the current at the locations of the pad 51 of the p-type pad 502 and the finger bar 52 of the n-type pad 501 is relatively concentrated. Therefore, the blocking blocks 411 in the area closest to the pad 51 of the p-type pad 502 and the finger bar 52 of the n-type pad 501 are distributed more densely, so that the current in the area of ​​the pad 51 of the p-type pad 502 close to the finger bar 52 of the n-type pad 501 can be guided to the area far away from the p-type pad 502 through the densely distributed blocking blocks 411, thereby reducing current congestion and facilitating light emission.

[0117] At the same time, the blocking blocks 411 in the area of ​​the pad 51 of the p-type pad 502 away from the finger strip 52 of the n-type pad 501 are distributed more sparsely, so that the pad 51 distributed in this area is easier to contact the epitaxial layer 20, thereby improving the stability of the pad bonding.

[0118] The light-emitting diode provided in the embodiment of the present disclosure has a blocking layer arranged below the pad, and a hollowing out is arranged on the blocking layer, so that the pad can contact the epitaxial layer through the hollowing out, while also increasing the contact area between the pad and the blocking layer. This can form an omnidirectional reflector with good reflectivity, reduce the light absorbed by the pad, and thus improve the light output rate.

[0119] Table 1 below is a table showing the difference in photoelectric performance of a light emitting diode provided by an embodiment of the present disclosure. As shown in Table 7, when the contact area between the pad and the barrier layer increases, the photoelectric performance of the light emitting diode will also be improved accordingly.

[0120] Table 1

[0121]

[0122] According to the data provided in Table 1, the fitting curve of the relationship between the contact area between the pad and the barrier layer and the photoelectric performance is y=0.0087x.

[0123] Fig.11 is a graph showing the relationship between the contact area between the pad and the barrier layer and the photoelectric performance provided by an embodiment of the present disclosure. Fig.11 When the contact area between the pad and the barrier layer increases by 15%, the photoelectric performance of the light-emitting diode can be increased by about 0.22%. It can be seen that the light-emitting diode provided by the embodiment of the present disclosure can not only improve the photoelectric performance of the light-emitting diode, but also prevent the pad from being easily loosened from the epitaxial layer, thereby improving the problem of electrode wire failure.

[0124] Fig.12 FIG. 1 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure. Fig.12 As shown, the preparation method comprises:

[0125] S11: forming an epitaxial layer.

[0126] The epitaxial layer includes a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer stacked in sequence.

[0127] S12: forming a transparent conductive layer on the surface of the epitaxial layer.

[0128] The transparent conductive layer has a first through hole exposing the epitaxial layer.

[0129] S13: forming a passivation layer on the surfaces of the transparent conductive layer and the epitaxial layer.

[0130] The surface of the passivation layer has a via hole exposing the first through hole, and / or the passivation layer has a second through hole exposing the epitaxial layer.

[0131] S14: forming a barrier layer in the first through hole and / or the second through hole, wherein the barrier layer has a hollow portion.

[0132] S15: forming a pad on a surface of the barrier layer away from the epitaxial layer, so that the pad is electrically connected to the epitaxial layer through the hollowing.

[0133] In the light-emitting diode prepared by the preparation method, the transparent conductive layer is located on the surface of the epitaxial layer, and the transparent conductive layer has a first through hole exposing the epitaxial layer, a barrier layer is arranged in the first through hole, the barrier layer has a hollow, and the pad is arranged on the surface of the barrier layer away from the epitaxial layer, and is electrically connected to the epitaxial layer through the hollow. In this way, the hollow is arranged on the surface of the barrier layer, so that the pad can be embedded in the hollow and electrically connected to the epitaxial layer, which not only meets the electrical connection requirements of the pad and the epitaxial layer, but also enables the pad and the barrier layer to adopt an embedded matching of a concave-convex structure, thereby effectively improving the connection reliability of the pad and the barrier layer, preventing the pad from easily loosening from the epitaxial layer, and improving the problem of electrode wire failure.

[0134] In addition, a barrier layer is provided between the epitaxial layer and the pad, and the contact area between the pad and the barrier layer can be increased, thereby forming an omnidirectional reflector with good reflectivity, reducing the light absorbed by the pad and improving the light output rate.

[0135] The epitaxial layer formed in step S11 is located on the substrate.

[0136] The substrate is a sapphire substrate, a silicon substrate or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0137] As an example, in the embodiment of the present disclosure, the substrate is a sapphire substrate. The sapphire substrate is a commonly used substrate with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a sapphire flat sheet substrate.

[0138] The sapphire substrate may be pre-treated, placed in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber, and baked for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0139] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0140] Before step S11 , the method may include: sequentially forming an AlN buffer layer and a u-type GaN layer on the sapphire substrate by using MOCVD technology.

[0141] Growing an epitaxial layer on the substrate in step S12 may include: sequentially forming a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer on the sapphire substrate by MOCVD technology.

[0142] Exemplarily, the epitaxial layer includes an n-type GaN layer, a multi-quantum well layer, and an n-type GaN layer stacked in sequence.

[0143] Optionally, the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0144] The growth temperature of the n-type GaN layer may be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer may be 100 torr to 300 torr.

[0145] Optionally, the multi-quantum well layer includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. Wherein, the multi-quantum well layer may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0146] When growing multi-quantum well layers, the pressure of the MOCVD reaction chamber is controlled at 200 torr. When growing InGaN quantum well layers, the temperature of the reaction chamber is 760°C to 780°C. When growing GaN quantum barrier layers, the temperature of the reaction chamber is 860°C to 890°C.

[0147] As an example, in the embodiment of the present disclosure, the multi-quantum well layer includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0148] Optionally, the thickness of the multi-quantum well layer may be 150 nm to 200 nm.

[0149] Optionally, the p-type GaN layer may have a thickness of 0.5 μm to 3 μm.

[0150] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer may be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer may be 800° C. to 1000° C.

[0151] Step S12 may include: forming a transparent conductive layer on the surface of the second semiconductor layer.

[0152] The transparent conductive layer has a first through hole exposing the second semiconductor layer.

[0153] Exemplarily, the transparent conductive layer is an indium tin oxide layer or an indium zinc oxide layer.

[0154] Exemplarily, the thickness of the transparent conductive layer may be 200 angstroms to 5000 angstroms. For example, the thickness of the transparent conductive layer is 2000 angstroms.

[0155] Step S13 may include: forming a passivation layer on a surface of the second semiconductor layer away from the first semiconductor layer and in the groove.

[0156] Specifically, it may include: forming a passivation layer on the surface of the p-type GaN layer, the surface of the transparent conductive layer, and in the groove.

[0157] Exemplarily, the passivation layer may be a silicon oxide layer, and the thickness of the passivation layer may be 800 angstroms to 3000 angstroms.

[0158] The barrier layer in step S14 and the passivation layer in step S13 can be prepared by a single patterning process to save preparation costs and improve preparation efficiency.

[0159] The silicon oxide layer is prepared by a one-time patterning process, and the portion of the silicon oxide layer located in the first through hole of the transparent conductive layer and the portion of the passivation layer located in the groove serve as a barrier layer.

[0160] Optionally, a portion of the silicon oxide layer stacked on the surface of the transparent conductive layer and a portion on the groove wall of the groove are a passivation layer.

[0161] Step S15 may include: forming a pad on the surface of the barrier layer away from the epitaxial layer, electrically connecting the pad to the epitaxial layer through hollowing, forming a finger on the transparent conductive layer, connecting one end of the finger to the pad, and obtaining the pad.

[0162] The pad located in the groove is an n-type pad, and the pad located on the second semiconductor layer is a p-type pad.

[0163] Illustratively, the pad may be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.

[0164] Finally, the sapphire substrate can be cut and scratched by invisible cutting, which can effectively reduce the loss of brightness. Then, the light-emitting diode is obtained by testing.

[0165] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light emitting diode comprises an epitaxial layer (20), a transparent conductive layer (30), a passivation layer (42) and a pad (51), wherein the transparent conductive layer (30) is located on the surface of the epitaxial layer (20), the passivation layer (42) is located on the surface of the epitaxial layer (20) and covers the transparent conductive layer (30), the transparent conductive layer (30) has a first through hole (31) exposing the epitaxial layer (20), and / or the passivation layer (42) has a second through hole (32) exposing the epitaxial layer (20); A barrier layer (41) is arranged in the first through hole (31) and / or the second through hole (32), the barrier layer (41) has a hollow (410), the pad is located on a surface of the barrier layer (41) away from the epitaxial layer (20), and is electrically connected to the epitaxial layer (20) through the hollow (410).

2. The light emitting diode according to claim 1, characterized in that: The blocking layer (41) comprises: a blocking block (411) and a blocking ring (412); the blocking block (411) is located inside the blocking ring (412), and the blocking block (411) and the blocking ring (412) are arranged concentrically; and an annular gap between the blocking block (411) and the blocking ring (412) is the hollowing (410).

3. The light emitting diode according to claim 2, characterized in that: The orthographic projections of the pad (51) and the blocking block (411) on the surface of the epitaxial layer (20) are circular, and the projection diameter of the blocking block (411) is less than 0.75 times the projection diameter of the pad (51).

4. The light emitting diode according to claim 2, characterized in that: The orthographic projection of the pad (51) on the surface of the epitaxial layer (20) is a circle, and the orthographic projection of the blocking ring (412) on the surface of the epitaxial layer (20) is a circular ring; The inner diameter of the projection of the blocking ring (412) is greater than 0.8 times the diameter of the projection of the pad (51), and the inner diameter of the projection of the blocking ring (412) is less than 0.9 times the diameter of the projection of the pad (51); The outer diameter of the projection of the blocking ring (412) is greater than the diameter of the projection of the pad (51), and the outer diameter of the projection of the blocking ring (412) is less than 1.1 times the diameter of the projection of the pad (51).

5. The light emitting diode according to claim 1, characterized in that: The blocking layer (41) comprises a plurality of blocking blocks (411), and the plurality of blocking blocks (411) are arranged at intervals in the first through hole (31) and / or the second through hole (32).

6. The light emitting diode according to claim 5, characterized in that: The orthographic projection of the pad (51) on the surface of the epitaxial layer (20) is circular, and the orthographic projections of the plurality of blocking blocks (411) on the surface of the epitaxial layer (20) are arranged in a circular array with the center of the pad (51) as the center.

7. The light emitting diode according to claim 5 or 6, characterized in that: The orthographic projection of the blocking block (411) on the surface of the epitaxial layer (20) is circular, the diameter of the projection of the blocking block (411) is greater than or equal to (D-14) / 7, and the diameter of the projection of the blocking block (411) is less than or equal to (D-4) / 3, and the diameter of the projection of the pad (51) is D, in micrometers.

8. The light emitting diode according to claim 5 or 6, characterized in that: The distribution density of the blocking blocks (411) in the edge area of ​​the first through hole (31) and / or the second through hole (32) is smaller than the distribution density of the blocking blocks (411) in the central area of ​​the first through hole (31).

9. The light emitting diode according to claim 5 or 6, characterized in that: The distribution density of the blocking blocks (411) in a region of the first through hole (31) close to the second through hole (32) is greater than the distribution density of the blocking blocks (411) in a region of the first through hole (31) far from the second through hole (32).

10. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: forming an epitaxial layer; forming a transparent conductive layer on a surface of the epitaxial layer, wherein the transparent conductive layer has a first through hole exposing the epitaxial layer; forming a passivation layer on the surfaces of the transparent conductive layer and the epitaxial layer, wherein the surface of the passivation layer has a via hole exposing the first through hole, and / or the passivation layer has a second through hole exposing the epitaxial layer; forming a barrier layer in the first through hole and / or the second through hole, wherein the barrier layer has hollowing; A pad is formed on a surface of the barrier layer away from the epitaxial layer, so that the pad is electrically connected to the epitaxial layer through the hollowing.

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