Active bidirectional phase shift network based on phase inversion variable gain amplifier

Abstract

The invention discloses an active bidirectional phase-shifting network based on a phase-reversal variable gain amplifier. The phase-shifting network comprises a first input / output port (1), a quadrature coupler (2), a first Balun network (3), a bidirectional phase-reversal variable gain amplifier network (4), a second Balun network (5), a power divider (6) and a second input / output port (7) which are connected in sequence, wherein the first input / output port (1), the quadrature coupler (2), the first Balun network (3), the bidirectional phase-reversal variable gain amplifier network (4), the second Balun network (5), the power divider (6) and the second input / output port (7) are connected in sequence; and the first Balun network (3), the bidirectional phase inversion variable gain amplifier network (4) and the second Balun network (5) are divided into two groups, namely an I-path group and a Q-path group. Switching of signal directions and selection of phase quadrants are achieved by controlling the bias voltage of the phase inversion variable gain amplifier, meanwhile, signals are amplified through a transconductance stage transistor in the phase inversion variable gain amplifier, and the insertion loss of a phase-shifting network is effectively reduced.

Description

Technical Field

[0001] The present invention belongs to microwave and millimeter wave communication, and in particular relates to an active bidirectional vector modulation phase shift network based on a phase reversal variable gain amplifier (VGA). Background Art

[0002] With the rapid development of wireless communication technology, especially in the application of 5G and future 6G technology, the demand for high-speed data transmission and high-frequency communication is growing. Phased array is a communication system architecture that effectively improves the communication rate. The phase-shifting network that realizes phase adjustment is an important component of the phased array. Phase-shifting networks can be divided into active and passive types according to their structure. In the millimeter wave frequency band, traditional passive phase-shifting networks can no longer meet the requirements of modern phased array systems due to their high insertion loss, large size and low efficiency. Therefore, the research and development of new active phase-shifting networks has become a hot issue in the field of wireless communications.

[0003] Vector modulation phase shifter is a commonly used active phase shift network architecture. The active phase shift network of this architecture achieves precise phase shifting by synthesizing the amplitude and phase of two orthogonal signals independently adjusted by a variable gain amplifier. Active vector modulation phase shifters have a small insertion loss in the millimeter wave terahertz frequency band, thereby alleviating the pressure on the link budget and reducing the link complexity. At the same time, active vector modulation phase shifters can be phase calibrated after tape-out, and the phase shift accuracy of the phase shift network can be improved by increasing the resolution of the digital-to-analog converter.

[0004] However, existing active vector modulation phase shifters are mostly built based on variable gain amplifiers with fixed directivity, which limits them to unidirectional phase control, which imposes certain restrictions on their application in time division multiplexing systems. Therefore, it is necessary to adjust the architecture of the amplitude control unit to realize a bidirectional phase shifting network. The phase reversal variable gain amplifier can be used as a gain control unit of the active vector modulation phase shifter due to its stable output impedance, and can cover the full 360° phase without adding an additional phase inverter to the RF path, with a relatively low system complexity. The bidirectional design of the control unit based on the phase reversal variable gain amplifier is a feasible solution.

[0005] Currently, researchers are exploring the use of advanced semiconductor processes, such as SiGe BiCMOS processes, to realize high-performance active phase-shifting networks. These processes can achieve low-cost, low-insertion-loss, and highly integrated phase-shifting networks to meet the needs of modern phased array systems. Summary of the invention

[0006] Technical problem: The present invention aims to provide an active bidirectional phase-shifting network based on a phase-reversal variable gain amplifier, which uses a bidirectional phase-reversal variable gain amplifier as a bidirectional amplitude control unit of an orthogonal signal, thereby realizing an active impedance network with lower loss bidirectional phase adjustment function.

[0007] Technical solution: The present invention discloses an active bidirectional phase-shifting network based on a phase-reversal variable gain amplifier, comprising a first input-output port, an orthogonal coupler, a first balun network, a bidirectional phase-reversal variable gain amplifier network, a second balun network, a power divider, and a second input-output port connected in sequence; the first balun network, the bidirectional phase-reversal variable gain amplifier network, and the second balun network are divided into two groups, namely an I-path group and a Q-path group.

[0008] The bidirectional phase-reversal variable gain amplifier network includes two identical bidirectional phase-reversal variable gain amplifiers, an I path and a Q path, each bidirectional phase-reversal variable gain amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first VGA input-output differential port, and a second VGA input-output differential port; the emitter of the first transistor, the emitter of the second transistor, and the collector of the fifth transistor are connected, the emitter of the third transistor, the emitter of the fourth transistor, and the collector of the sixth transistor are connected; the emitter of the seventh transistor, the emitter of the eighth transistor, and the collector of the eleventh transistor are connected, and the emitter of the ninth transistor, the emitter of the tenth transistor, and the collector of the twelfth transistor are connected.

[0009] One end of the first capacitor is connected to the collector of the first transistor, the collector of the fourth transistor, and the + end of the first VGA input-output differential port, and the other end of the first capacitor is connected to the base of the eleventh transistor; one end of the second capacitor is connected to the collector of the second transistor, the collector of the third transistor, and the - end of the second VGA input-output differential port, and the other end of the second capacitor is connected to the base of the twelfth transistor.

[0010] One end of the third capacitor is connected to the collector of the eighth transistor, the collector of the ninth transistor, and the + end of the second VGA input-output differential port, and the other end of the third capacitor is connected to the base of the fifth transistor; one end of the fourth capacitor is connected to the collector of the seventh transistor, the collector of the tenth transistor, and the - end of the second VGA input-output differential port, and the other end of the fourth capacitor is connected to the base of the sixth transistor.

[0011] The base of the first transistor is connected to the output end of the first AND gate through a resistor, the base of the second transistor is connected to the output end of the second AND gate through a resistor, the base of the third transistor is connected to the output end of the third AND gate through a resistor, the base of the fourth transistor is connected to the output end of the fourth AND gate through a resistor, the base of the seventh transistor is connected to the output end of the fifth AND gate through a resistor, the base of the eighth transistor is connected to the output end of the sixth AND gate through a resistor, the base of the ninth transistor is connected to the output end of the seventh AND gate through a resistor, and the base of the tenth transistor is connected to the output end of the eighth AND gate through a resistor.

[0012] The two input terminals of the first AND gate are respectively connected to the direction selection voltage Rx and quadrant selection voltage quad The two input terminals of the second AND gate are connected to the direction selection voltage Rx and quadrant selection voltage , the two input terminals of the third AND gate are connected to the direction selection voltage Rx and quadrant selection voltage quad , the two input terminals of the fourth AND gate are connected to the direction selection voltage Rx and quadrant selection voltage The two input terminals of the fifth AND gate are connected to the direction selection voltage and quadrant selection voltage quad The two input terminals of the sixth AND gate are connected to the direction selection voltage and quadrant selection voltage The two input terminals of the seventh AND gate are connected to the direction selection voltage and quadrant selection voltage quad The two input terminals of the eighth AND gate are connected to the direction selection voltage and quadrant selection voltage .

[0013] The direction selection voltage Rx There are only two states, 0 or 1. When the state is 1, it is in the forward working mode, and when the state is 0, it is in the reverse working mode; the quadrant selection voltage quad has only two states, 0 or 1, for realizing quadrant switching.

[0014] The bases of the fifth transistor and the sixth transistor are connected to the forward gain control voltage V fw , the bases of the eleventh transistor and the twelfth transistor are connected to the reverse gain control voltage V bw , when the direction selection voltage Rx When it is 1, the forward gain control voltage V fw The voltage value is adjustable, the reverse gain control voltage V bw The voltage value is 0V; when the direction selection voltage Rx When it is 0, the reverse gain control voltage V bw The voltage value is adjustable, the positive gain control voltage V fw The voltage value is 0V.

[0015] In the forward working mode of the phase-shifting network, the signal is input into the orthogonal coupler from the first input / output port to generate two signals, I and Q, which enter the I group and Q group of the first balun network respectively to generate four differential signals, I+, I-, Q+, and Q-; wherein the two differential signals, I+ and I-, enter the I group of the bidirectional phase-reversal variable gain amplifier network, and enter the second balun network after being amplified by the I bidirectional phase-reversal variable gain amplifier network to complete the matching and differential power synthesis of the I path; the two differential signals, Q+ and Q-, enter the Q group of the bidirectional phase-reversal variable gain amplifier network, and enter the second balun network after being amplified by the Q bidirectional phase-reversal variable gain amplifier network to complete the matching and differential power synthesis of the Q path; the I signal and the Q signal are input into the power divider to complete the orthogonal power synthesis, and then output through the second input / output port.

[0016] In the reverse working mode of the phase-shifting network, the signal is input into the power divider from the second input / output port to generate two in-phase signals, which enter the I-group and Q-group of the second balun network respectively to generate four differential signals, which are also recorded as I+, I-, Q+, and Q- respectively; among which the I+ and I- differential signals enter the I-group of the bidirectional phase-reversal variable gain amplifier network, and enter the first balun network after being amplified by the I-bidirectional phase-reversal variable gain amplifier network to complete the matching and differential power synthesis of the I-path; the Q+ and Q- differential signals enter the Q-group of the bidirectional phase-reversal variable gain amplifier network, and enter the first balun network after being amplified by the Q-bidirectional phase-reversal variable gain amplifier network to complete the matching and differential power synthesis of the Q-path; the I-path signal and the Q-path signal are input into the orthogonal coupler to complete the orthogonal power synthesis, and are output via the first input / output port.

[0017] The direction selection voltage of the I path and the Q path in the bidirectional phase reversal variable gain amplifier network Rx Keep consistent, I and Q quadrant selection voltage quad , forward gain control voltage V fw , reverse gain control voltage V bw Each one is independent.

[0018] Beneficial effect: The active bidirectional phase-shifting network based on the phase-reversal variable gain amplifier described in the present invention uses a bidirectional phase-reversal variable gain amplifier as a bidirectional amplitude control unit of an orthogonal signal, and utilizes the gain of the amplifier transconductance stage while realizing bidirectional phase shifting, so that the bidirectional phase-shifting active impedance network has lower network loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the overall structure of the phase shift network in a specific implementation manner of the present invention; Figure 2 It is a schematic diagram of the structure of a single-channel bidirectional phase-reversal variable gain amplifier in a specific implementation manner of the present invention; Figure 3 It is a constellation diagram of all states scanned and 64 selected states at 130 GHz in the forward working state of the phase shift network in the specific implementation mode of the present invention; Figure 4 It is a constellation diagram of all states scanned and 64 selected states at 130 GHz in the reverse working state of the phase shift network in the specific implementation mode of the present invention; Figure 5 It is an insertion loss diagram of the phase shift network in the forward and reverse working states in a specific implementation manner of the present invention.

[0020] In the figure, there are: a first input-output port 1, an orthogonal coupler 2, a first balun network 3, a bidirectional phase-reversal variable gain amplifier network 4, a second balun network 5, a power divider 6, and a second input-output port 7; a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12; A first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; A first VGA input-output differential port VGAIO1, a second VGA input-output differential port VGAIO2; A first AND gate and1, a second AND gate and2, a third AND gate and3, a fourth AND gate and4, a fifth AND gate and5, a sixth AND gate and6, a seventh AND gate and7, and an eighth AND gate and8. DETAILED DESCRIPTION

[0021] In order to further illustrate the technical solution disclosed by the present invention, the technical solution of the present invention is further elaborated below in combination with specific implementation methods and drawings.

[0022] like Figure 1, this specific embodiment discloses an active bidirectional vector modulation phase shift network based on a phase reversal variable gain amplifier, the phase shift network comprises a first input-output port 1, an orthogonal coupler 2, a first balun network 3, a bidirectional phase reversal variable gain amplifier network 4, a second balun network 5, a power divider 6, and a second input-output port 7 connected in sequence; The first balun network 3, the bidirectional phase-reversal variable gain amplifier network 4, and the second balun network 5 can all be divided into two groups, namely an I-path group and a Q-path group.

[0023] In the forward working mode, the signal is input into the orthogonal coupler 2 from the first input / output port 1, generating two signals, I and Q, which enter the I group and Q group of the first balun network 3 respectively, generating four signals, I+, I-, Q+, Q-. Among them, the two differential signals of I+ and I- enter the I group of the bidirectional phase-reversal variable gain amplifier network 4, and enter the second balun network 5 after amplification by the I bidirectional phase-reversal VGA network, completing the matching and differential power synthesis of the I path; the two differential signals of Q+ and Q- enter the Q group of the bidirectional phase-reversal variable gain amplifier network 4, and enter the second balun network 5 after amplification by the Q bidirectional phase-reversal VGA network, completing the matching and differential power synthesis of the Q path. The I signal and the Q signal are input into the power divider 6, completing the orthogonal power synthesis, and output through the second input / output port 7.

[0024] In the reverse working mode, the signal is input into the power divider 6 from the second input / output port 7, generating two in-phase signals, which enter the I-channel group and the Q-channel group of the second balun network 5 respectively, generating four differential signals, which are also recorded as I+, I-, Q+, and Q-. The I+ and I- differential signals enter the I-channel group of the bidirectional phase-reversal variable gain amplifier network 4, and enter the first balun network 3 after being amplified by the I-channel bidirectional phase-reversal VGA network, completing the matching and differential power synthesis of the I-channel; the Q+ and Q- differential signals enter the Q-channel group of the bidirectional phase-reversal variable gain amplifier network 4, and enter the first balun network 3 after being amplified by the Q-channel bidirectional phase-reversal VGA network, completing the matching and differential power synthesis of the Q-channel. The I-channel signal and the Q-channel signal are input into the orthogonal coupler 2, completing the orthogonal power synthesis, and are output through the first input / output port 1.

[0025] like Figure 2As shown, this specific embodiment discloses an active bidirectional vector modulation phase-shift network based on a phase-reversal variable gain amplifier, wherein the bidirectional phase-reversal variable gain amplifier network 4 includes two identical bidirectional phase-reversal VGAs, an I path and a Q path, each bidirectional phase-reversal VGA includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11 and a twelfth transistor M12, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; a first VGA input-output differential port VGAIO1, and a second VGA input-output differential port VGAIO2.

[0026] The emitter of the first transistor M1, the emitter of the second transistor M2, and the collector of the fifth transistor M5 are connected; the emitter of the third transistor M3, the emitter of the fourth transistor M4, and the collector of the sixth transistor M6 are connected; the emitter of the seventh transistor M7, the emitter of the eighth transistor M8, and the collector of the eleventh transistor M11 are connected; the emitter of the ninth transistor M9, the emitter of the tenth transistor M10, and the collector of the twelfth transistor M12 are connected.

[0027] One end of the first capacitor C1 is connected to the collector of the first transistor M1, the collector of the fourth transistor M4, and the + end of the first VGA input-output differential port VGAIO1, and the other end of the first capacitor C1 is connected to the base of the eleventh transistor M11; one end of the second capacitor C2 is connected to the collector of the second transistor M2, the collector of the third transistor M3, and the - end of the second VGA input-output differential port VGAIO2, and the other end of the second capacitor C2 is connected to the base of the twelfth transistor M12.

[0028] One end of the third capacitor C3 is connected to the collector of the eighth transistor M8, the collector of the ninth transistor M9, and the + end of the second VGA input-output differential port VGAIO2, and the other end of the third capacitor C3 is connected to the base of the fifth transistor M5; one end of the fourth capacitor C4 is connected to the collector of the seventh transistor M7, the collector of the tenth transistor M10, and the - end of the second VGA input-output differential port VGAIO2, and the other end of the fourth capacitor C4 is connected to the base of the sixth transistor M6.

[0029] The base of the first transistor M1 is connected to the output end of the first AND gate and1 through a resistor, the base of the second transistor M2 is connected to the output end of the second AND gate and2 through a resistor, the base of the third transistor M3 is connected to the output end of the third AND gate and3 through a resistor, the base of the fourth transistor M4 is connected to the output end of the fourth AND gate and4 through a resistor, the base of the seventh transistor M7 is connected to the output end of the fifth AND gate and5 through a resistor, the base of the eighth transistor M8 is connected to the output end of the sixth AND gate and6 through a resistor, the base of the ninth transistor M9 is connected to the output end of the seventh AND gate and7 through a resistor, and the base of the tenth transistor M10 is connected to the output end of the eighth AND gate and8 through a resistor.

[0030] The two input ends of the first AND gate and1 are respectively connected to the direction selection voltage Rx and the quadrant selection voltage quad, the two input ends of the second AND gate and2 are respectively connected to the direction selection voltage Rx and the quadrant selection voltage quad, the two input ends of the third AND gate and3 are respectively connected to the direction selection voltage Rx and the quadrant selection voltage quad, the two input ends of the fourth AND gate and4 are respectively connected to the direction selection voltage Rx and the quadrant selection voltage, the two input ends of the fifth AND gate and5 are respectively connected to the direction selection voltage and the quadrant selection voltage quad, the two input ends of the sixth AND gate and6 are respectively connected to the direction selection voltage and the quadrant selection voltage, the two input ends of the seventh AND gate and7 are respectively connected to the direction selection voltage and the quadrant selection voltage quad, and the two input ends of the eighth AND gate and8 are respectively connected to the direction selection voltage and the quadrant selection voltage.

[0031] Furthermore, the direction selection voltage Rx has only two states, 0 or 1. When the state is 1, it is in the forward working mode, and when the state is 0, it is in the reverse working mode; the quadrant selection voltage quad has only two states, 0 or 1, for realizing quadrant switching.

[0032] The bases of the fifth transistor M5 and the sixth transistor M6 are connected to the forward gain control voltage Vfw, and the bases of the eleventh transistor M11 and the twelfth transistor M12 are connected to the reverse gain control voltage Vbw. When the direction selection voltage Rx is 1, the voltage value of the forward gain control voltage Vfw is adjustable, and the voltage value of the reverse gain control voltage Vbw is 0V; when the direction selection voltage Rx is 0, the voltage value of the reverse gain control voltage Vbw is adjustable, and the voltage value of the forward gain control voltage Vfw is 0V.

[0033] In the active bidirectional phase-shifting network based on a phase-reversal variable gain amplifier described in the present invention, the orthogonal coupler 2 may use an orthogonal coupling device such as a Lange coupler.

[0034] In the active bidirectional phase-shifting network based on a phase-reversal variable gain amplifier described in the present invention, the first balun network 3 and the second balun network 5 can use balanced-unbalanced conversion devices such as Marchand balun and transformer balun.

[0035] In order to verify the feasibility of the active bidirectional phase-shifting network based on the phase-reversal variable gain amplifier provided by the present invention, a commercial electromagnetic simulation software is first used to simulate a disclosed active bidirectional vector modulation phase-shifting network based on the phase-reversal VGA. Figure 3-Figure 5 Relevant simulation results are given respectively, and the results show that the phase shift network achieves 360° six-bit phase shift in both forward and reverse directions at 130GHz, and the insertion loss is less than 15dB in the 120-140GHz frequency band.

[0036] The simulation results verify the feasibility of the present invention as an active bidirectional phase-shift impedance network, and it has low network loss. At the same time, the present invention can be integrated into a time-division multiplexed phased array system as a phase-shift network for each channel to achieve array beamforming.

[0037] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An active bidirectional phase shifting network based on a phase-reversal variable gain amplifier, characterized in that The phase shift network comprises a first input-output port (1), an orthogonal coupler (2), a first balun network (3), a bidirectional phase-reversal variable gain amplifier network (4), a second balun network (5), a power divider (6), and a second input-output port (7) which are connected in sequence; the first balun network (3), the bidirectional phase-reversal variable gain amplifier network (4), and the second balun network (5) are divided into two groups, namely an I-path group and a Q-path group.

2. The active bidirectional phase shift network based on a phase-reversal variable gain amplifier according to claim 1, characterized in that: The bidirectional phase-reversal variable gain amplifier network (4) comprises two identical bidirectional phase-reversal variable gain amplifiers, an I path and a Q path, each of which comprises a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4), a fifth transistor (M5), a sixth transistor (M6), a seventh transistor (M7), an eighth transistor (M8), a ninth transistor (M9), a tenth transistor (M10), an eleventh transistor (M11) and a twelfth transistor (M12), a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), A first VGA input / output differential port (VGAIO1), a second VGA input / output differential port (VGAIO2); an emitter of the first transistor (M1), an emitter of the second transistor (M2), and a collector of the fifth transistor (M5) are connected; an emitter of the third transistor (M3), an emitter of the fourth transistor (M4), and a collector of the sixth transistor (M6) are connected; an emitter of the seventh transistor (M7), an emitter of the eighth transistor (M8), and a collector of the eleventh transistor (M11) are connected; an emitter of the ninth transistor (M9), an emitter of the tenth transistor (M10), and a collector of the twelfth transistor (M12) are connected.

3. The active bidirectional phase shift network based on a phase-reversal variable gain amplifier according to claim 2, characterized in that: One end of the first capacitor (C1) is connected to the collector of the first transistor (M1), the collector of the fourth transistor (M4), and the + end of the first VGA input-output differential port (VGAIO1), and the other end of the first capacitor (C1) is connected to the base of the eleventh transistor (M11); one end of the second capacitor (C2) is connected to the collector of the second transistor (M2), the collector of the third transistor (M3), and the - end of the second VGA input-output differential port (VGAIO2), and the other end of the second capacitor (C2) is connected to the base of the twelfth transistor (M12); One end of the third capacitor (C3) is connected to the collector of the eighth transistor (M8), the collector of the ninth transistor (M9), and the + end of the second VGA input-output differential port (VGAIO2), and the other end of the third capacitor (C3) is connected to the base of the fifth transistor (M5); one end of the fourth capacitor (C4) is connected to the collector of the seventh transistor (M7), the collector of the tenth transistor (M10), and the - end of the second VGA input-output differential port (VGAIO2), and the other end of the fourth capacitor (C4) is connected to the base of the sixth transistor (M6).

4. The active bidirectional phase shift network based on a phase-reversal variable gain amplifier according to claim 2, characterized in that: The base of the first transistor (M1) is connected to the output end of the first AND gate (and1) through a resistor, the base of the second transistor (M2) is connected to the output end of the second AND gate (and2) through a resistor, the base of the third transistor (M3) is connected to the output end of the third AND gate (and3) through a resistor, the base of the fourth transistor (M4) is connected to the output end of the fourth AND gate (and4) through a resistor, the base of the seventh transistor (M7) is connected to the output end of the fifth AND gate (and5) through a resistor, the base of the eighth transistor (M8) is connected to the output end of the sixth AND gate (and6) through a resistor, the base of the ninth transistor (M9) is connected to the output end of the seventh AND gate (and7) through a resistor, and the base of the tenth transistor (M10) is connected to the output end of the eighth AND gate (and8) through a resistor.

5. The active bidirectional phase shift network based on a phase-reversal variable gain amplifier according to claim 4, characterized in that: The two input terminals of the first AND gate (and1) are respectively connected to the direction selection voltage Rx and quadrant selection voltage quad The two input terminals of the second AND gate (and2) are connected to the direction selection voltage Rx and quadrant selection voltage The two input terminals of the third AND gate (and3) are connected to the direction selection voltage Rx and quadrant selection voltage quad The two input terminals of the fourth AND gate (and4) are connected to the direction selection voltage Rx and quadrant selection voltage The two input terminals of the fifth AND gate (and5) are connected to the direction selection voltage and quadrant selection voltage quad The two input terminals of the sixth AND gate (and6) are connected to the direction selection voltage and quadrant selection voltage The two input terminals of the seventh AND gate (and7) are connected to the direction selection voltage and quadrant selection voltage quad The two input terminals of the eighth AND gate (and8) are connected to the direction selection voltage and quadrant selection voltage .

6. The active bidirectional phase shift network based on a phase-reversal variable gain amplifier according to claim 5, characterized in that: The direction selection voltage Rx There are only two states, 0 or 1. When the state is 1, it is in the forward working mode, and when the state is 0, it is in the reverse working mode; the quadrant selection voltage quad has only two states, 0 or 1, for realizing quadrant switching.

7. The active bidirectional phase shift network based on a phase-reversal variable gain amplifier according to claim 2 or 5, characterized in that: The bases of the fifth transistor (M5) and the sixth transistor (M6) are connected to the forward gain control voltage V fw , the bases of the eleventh transistor (M11) and the twelfth transistor (M12) are connected to the reverse gain control voltage V bw , when the direction selection voltage Rx When it is 1, the forward gain control voltage V fw The voltage value is adjustable, the reverse gain control voltage V bw The voltage value is 0V; when the direction selection voltage Rx When it is 0, the reverse gain control voltage V bw The voltage value is adjustable, the positive gain control voltage V fw The voltage value is 0V.

8. The active bidirectional phase shift network based on a phase-reversal variable gain amplifier according to claim 6, characterized in that: In the forward working mode of the phase shift network, a signal is inputted into the orthogonal coupler (2) from the first input / output port (1), generating two signals, I and Q, which respectively enter the I group and Q group of the first balun network (3), generating four differential signals, I+, I-, Q+, and Q-. The two differential signals I+ and I- enter the I-channel group of the bidirectional phase-reversal variable gain amplifier network (4), and after being amplified by the I-channel bidirectional phase-reversal variable gain amplifier network (4), enter the second balun network (5), completing the matching and differential power synthesis of the I-channel; the two differential signals Q+ and Q- enter the Q-channel group of the bidirectional phase-reversal variable gain amplifier network (4), and after being amplified by the Q-channel bidirectional phase-reversal variable gain amplifier network (4), enter the second balun network (5), completing the matching and differential power synthesis of the Q-channel; the I-channel signal and the Q-channel signal are input into the power divider (6), completing the orthogonal power synthesis, and then output through the second input and output port (7).

9. The active bidirectional phase shift network based on phase reversal variable gain amplifier according to claim 6, characterized in that: When the phase shift network is in reverse working mode, the signal is input into the power divider (6) from the second input / output port (7), generating two in-phase signals, which respectively enter the I-channel group and the Q-channel group of the second balun network (5), generating four differential signals, which are also respectively recorded as I+, I-, Q+, and Q-; The two differential signals I+ and I- enter the I-channel group of the bidirectional phase-reversal variable gain amplifier network (4), and after being amplified by the I-channel bidirectional phase-reversal variable gain amplifier network, enter the first balun network (3), completing the matching and differential power synthesis of the I-channel; the two differential signals Q+ and Q- enter the Q-channel group of the bidirectional phase-reversal variable gain amplifier network (4), and after being amplified by the Q-channel bidirectional phase-reversal variable gain amplifier network, enter the first balun network (3), completing the matching and differential power synthesis of the Q-channel; the I-channel signal and the Q-channel signal are input into the orthogonal coupler (2), completing the orthogonal power synthesis, and are output via the first input-output port (1).

10. The active bidirectional phase shift network based on a phase-reversal variable gain amplifier according to claim 8 or 9, characterized in that: The direction selection voltage of the I path and the Q path in the bidirectional phase reversal variable gain amplifier network (4) Rx Keep consistent, I and Q quadrant selection voltage quad , forward gain control voltage V fw , reverse gain control voltage V bw Each one is independent.

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