Hybrid control variable gain amplifier without decoder and circuit thereof

Abstract

The invention discloses a hybrid control variable gain amplifier without a decoder and a circuit of the hybrid control variable gain amplifier. The hybrid control variable gain amplifier comprises an OPA amplifier and two CMOS arrays connected with the OPA amplifier through a switch C1 and a switch C2. The hybrid control variable gain amplifier is switched from an analog control mode to a digital control mode by closing the switches C1 and C2. According to the circuit of the hybrid control variable gain amplifier without the decoder, circuits of two groups of CMOS arrays are respectively connected with a circuit of an OPA amplifier through a switch C1 and a switch C2; a circuit of the CMOS array is formed by connecting circuits of n + 1 gain blocks in parallel. A decoding module is not needed, delay can be effectively reduced in application needing extremely high-speed response, and compared with a traditional hybrid control variable gain amplifier, the hybrid control variable gain amplifier has the advantages of being relatively simple in structure, low in complexity, higher in analog control flexibility and wide in application.

Description

Technical Field

[0001] The present invention belongs to the technical field of control and regulation of amplifiers, and particularly relates to a hybrid-control variable gain amplifier without a decoder and its circuit. Background Art

[0002] A variable gain amplifier (VGA), as the name implies, can dynamically adjust its gain according to changes in external conditions, usually by adjusting voltage or current to change the gain. Based on different gain control principles, variable gain amplifiers are mainly divided into two control methods: variable gain amplifiers based on analog control methods and variable gain amplifiers based on digital control methods. A variable gain amplifier that simultaneously has analog control functions and digital control functions is usually referred to as a hybrid-control variable gain amplifier (Hybrid-Control VGA).

[0003] For a traditional hybrid-control variable gain amplifier, a decoding module is used to convert a digital control signal into an analog control signal, thereby achieving precise adjustment of the amplifier gain. Figure 1 shows the overall architecture of a traditional hybrid-control variable gain amplifier. After a binary digital signal is input into the decoder module, the decoder decodes the digital control signal into an analog control signal to drive the internal transconductance unit (gm CELLS) to adjust the gain to achieve digital control functions. When all digital control codes are set to 0, analog control functions can be achieved. This design that requires a DECODE decoder module increases the integration complexity of the chip, which will lead to an increase in chip area and power consumption. Moreover, since the digital control signal needs to go through a decoding process, it will also introduce a certain delay. At the same time, the decoding process of the decoder module is fixed, and users cannot directly adjust the internal decoding logic. Summary of the Invention

[0004] In order to effectively solve the above problems existing in the prior art, the present invention provides a hybrid-control variable gain amplifier without a decoder. Without the need for a DECODE decoding module, the gain is adjusted by controlling a CMOS array with a digital signal, which enables the digital signal to directly control the adjustment of the gain without the need to add a decoding module.

[0005] The present invention provides a hybrid control variable gain amplifier without a decoder, which at least includes an OPA amplifier, two CMOS arrays, and switches C1 and C2 that connect the two CMOS arrays to the OPA amplifier respectively; the switch C1 controls the closing of the connection between the CMOS array of the upper circuit and the OPA amplifier, and the switch C2 controls the closing of the connection between the CMOS array of the lower circuit and the OPA amplifier; the hybrid control variable gain amplifier switches from the analog control mode to the digital control mode by closing the switches C1 and C2.

[0006] Furthermore, each CMOS array includes logic units, and each logic unit at least includes a block structure composed of a pair of NMOS transistors and a PMOS transistor; one logic unit constitutes a gain block in the hybrid control variable gain amplifier.

[0007] The present invention provides a circuit of the aforementioned hybrid control variable gain amplifier without a decoder. The circuit is formed by connecting the circuits of two CMOS arrays to the circuit of the OPA amplifier through switches C1 and C2 respectively; the circuit of each CMOS array is formed by the circuits of gain blocks connected in parallel.

[0008] Furthermore, use the gain block to represent the th gain block in the CMOS array, ; the circuit of the gain block at least includes a CMOS single-pole double-throw switch, a PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The CMOS single-pole double-throw switch is used to connect the input digital control signal to the gates of the first NMOS transistor or the second NMOS transistor respectively, and controls the generation of positive and negative high and low levels respectively, including the positive high level , and the negative low level ; When at the high level , the first NMOS transistor connected to the high-level power supply voltage works to generate a current ; when at the low level , the second NMOS transistor connected to the bias voltage works to generate a current , where ; the represents the current or the current of the gain block in the CMOS array of the upper or lower circuit.

[0009] Compared with the prior art, the hybrid control variable gain amplifier without a decoder provided by the present invention has the following beneficial effects: (1) Compared with the traditional hybrid control variable gain amplifier, the hybrid control variable gain amplifier designed by the present invention does not require a decoding module, and in applications that require extremely high-speed response, the delay can be effectively reduced.

[0010] (2) Compared with the traditional hybrid control variable gain amplifier, the hybrid control variable gain amplifier and its circuit designed by the present invention have the advantages of relatively simple structure and low complexity. Specifically, according to the number of bits of the input signal, a corresponding number of gain block circuits with relatively simple structures are set. When regulating the summing current, no additional decoding process and relatively complex decoding circuit modules are required, reducing the circuit complexity.

[0011] (3) Compared with the traditional hybrid control variable gain amplifier, the hybrid control variable gain amplifier and its circuit designed by the present invention have higher analog control flexibility. Specifically, the decoding process of the DECODE module with a traditional structure is fixed, and users cannot directly adjust the internal decoding logic, which cannot meet the requirements when a more flexible analog control method is needed. However, the present invention realizes digital deconstruction through a CMOS array, and switches the analog control mode and digital control mode through CMOS, facilitating the design of the deconstruction of the required logic and mode switching according to specific requirements, with better flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments or example embodiments of the present invention, where the graphic shapes and relative sizes representing circuit elements do not serve as features limiting the protection scope of the present invention, and are only used to illustrate the structure, connection relationship, and function of the products protected by the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the structures shown in these drawings.

[0013] Figure 1 It is a schematic diagram of a traditional hybrid control variable gain amplifier in the background technology of the present invention, where is the digital input signal received by the DECODE decoder module, is the transconductance unit, where and are the input signals, and are the output signals; Figure 2Schematic diagram of a hybrid control variable gain amplifier without a decoder in the first embodiment of the present invention, where is the sum current of the upper two paths, is the sum current of the lower path, C1 is the switch controlling the upper path, and C2 is the switch controlling the lower path; Figure 3 CMOS array circuit diagram of a hybrid control variable gain amplifier without a decoder in the second embodiment of the present invention, where and are high and low levels in a one-to-one positive and negative manner, represents the current obtained correspondingly from the upper or lower gain blocks 0, 1, …, gain block ; Figure 4 Circuit diagram of the gain block in the CMOS array in the second embodiment of the present invention, where is the high-level power supply voltage connected to the source of the first NMOS transistor, is the bias voltage connected to the source of the second NMOS transistor, NM1 is the first NMOS transistor, NM2 is the second NMOS transistor, and PM is the PMOS transistor, is the common node of the input digital control signal, is the node where the input digital control signal is connected to the gate of the first NMOS transistor after passing through a single-pole double-throw switch, is the node where the input digital control signal is connected to the gate of the second NMOS transistor after passing through a single-pole double-throw switch, At and At are high and low levels in a one-to-one positive and negative manner, represents the current of the upper gain block or the current of the lower gain block ; Figure 5 Simplified circuit diagram of the OPA amplifier in the second embodiment of the present invention, where PM1 is the first PMOS transistor and PM2 is the second PMOS transistor, is the sum current after the gain provided by the upper CMOS array for the first PMOS transistor, is the sum current after the gain provided by the lower CMOS array for the second PMOS transistor, is the bias current connecting the gate of the transistor and the positive power supply, is the drain load resistor, is the output load resistor; Figure 6This is the circuit diagram of a CMOS single-pole double-throw switch in the circuit of a hybrid control variable gain amplifier without a decoder in the third embodiment of the present invention. Among them, Control is the input port of the digital control signal, and In is the input port of the CMOS single-pole double-throw switch input signal or the input port of, Out1 is the output port with the same high and low output levels as the same, and Out2 is the output port with high and low output levels opposite to the opposite; is the power supply voltage; Figure 7 This is the complete circuit diagram of the hybrid control variable gain amplifier circuit without a decoder in the third embodiment of the present invention. Among them, is the MOS transistor that acts as a switch in the up or down circuit, and A is the high and low level input port that controls the MOS transistor to act as a switch; MOS transistors that implement different functions in the circuit structure. Each dashed box is the circuit of the gain block in the CMOS array. Specific implementation manners

[0014] In order to make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. For example, words such as "up", "down", "left", "right", "both sides", etc. used to describe directions are only used to describe the corresponding positions and connection relationships in the accompanying drawings of the present invention when referring to the product structure and component connection manners of the present invention, and should not be used to limit the product or the product structure characteristics of the present invention itself.

[0015] The present invention will be further described in detail below with reference to the specification drawings and specific embodiments.

[0016] In the first embodiment, the present invention discloses a hybrid control variable gain amplifier without a decoder to solve problems such as high power consumption and complex integration in the traditional structure circuit. As Figure 2 shown, the hybrid control variable gain amplifier without a decoder includes at least an OPA amplifier, two CMOS arrays, and switches C1 and C2 that connect the two CMOS arrays to the OPA amplifier respectively; the hybrid control variable gain amplifier switches from the analog control mode to the digital control mode by closing switches C1 and C2; switch C1 controls the closing of the up circuit, and switch C2 controls the closing of the down circuit.

[0017] Further, each CMOS array includes A logic unit, each logic unit includes at least a block structure composed of a pair of NMOS transistors and a PMOS transistor; one logic unit constitutes a gain block in a hybrid control variable gain amplifier.

[0018] The second embodiment of the present invention provides a hybrid control variable gain amplifier circuit without a decoder. Specifically, FIG. 3 shows the circuit diagram of the CMOS array in the hybrid control variable gain amplifier without a decoder of the first embodiment. As Figure 3 shown, first design the circuit of the gain blocks, and after parallel connection, form the circuit of the entire CMOS array; the th gain block, denoted as gain block , . As Figure 4 shown, the circuit of gain block includes a CMOS single-pole double-throw switch, a PMOS transistor, and two NMOS transistors. Among them, through the CMOS single-pole double-throw switch, are respectively connected to the gates of an NMOS transistor (the first NMOS transistor) and another NMOS transistor (the second NMOS transistor), and are used to control the generation of positive and negative high and low levels of a one-bit digital control signal and . Specifically, when the digital control signal is input, if , through the CMOS single-pole double-throw switch, the common node of the input is connected to the gate of the first NMOS transistor through node , the second NMOS transistor is cut off, and a positive high level and a low level are generated (logically , ); if , through the CMOS single-pole double-throw switch, the common node of the input is connected to the gate of the second NMOS transistor through node , the first NMOS transistor is cut off, and an inverted low level and a high level are generated (logically , ). When is at a high level, the first NMOS transistor connected to the high-level power supply voltage works, and a current is generated ( represents the current of the upper path gain block or the lower path gain block The current is larger; when is at a low level, the second NMOS transistor connected to the bias voltage operates to generate a current which is smaller; here, due to .

[0019] Specifically, when the decoderless hybrid control variable gain amplifier is operating, first, the digital control signal , , through the single-pole double-throw switch set in the CMOS array, generates a high and a low level with opposite polarities and , where the is the inverted digital signal. Then, the high and low levels and are used to adjust the switching state of the current source in the control gain block . As shown in Figure 4 , when is at a high level, the first NMOS transistor connected to forms a conducting current source, and at this time, the gain block outputs a relatively large current ( or ); when is at a low level, the second NMOS transistor connected to forms a conducting current source, and at this time, the gain block outputs a relatively small current ( or ). The gain block regulates the output currents and in this way, so as to adjust Figure 3 the upper two summing currents and the lower summing current . Finally, and are connected to the OPA amplifier to participate in the regulation of the amplifier gain.

[0020] Furthermore, the simplified circuit of the OPA amplifier is as shown in Figure 5 , and it includes two PMOS transistors: the first PMOS transistor and the second PMOS transistor. Among them, is the input signal of the non-inverting input terminal, is the input signal of the inverting input terminal; the non-inverting input terminal is connected to the gate of the first PMOS transistor, and the inverting input terminal is connected to the gate of the second PMOS transistor, which is used to receive the differential signal and convert it into a current signal; is the sum current after gain provided by the CMOS array of the upper circuit for the first PMOS transistor, is the sum current after gain provided by the CMOS array of the lower circuit for the second PMOS transistor; is the bias current, connecting the drain of the transistor and the positive power supply; is the drain load resistor, with both ends respectively connected to the drains of the first and second PMOS transistors, converting the drain current into a voltage for setting the quiescent operating point of the OPA amplifier; is the output load resistor, with one end connected to the drain of the transistor and the other end connected to the negative power supply (ground); and are the output signals. Assume that the transconductance of the first PMOS transistor and the second PMOS transistor on both sides is , then the initial equivalent transconductance of this amplifier, and the initial amplification factor . It can be seen that the amplification factor is positively correlated with . When is connected, can be increased to . Using the OPA amplifier, a current signal with an amplification factor of can be obtained, where , that is, by controlling the size of the current signal through the digital control signal, the gain size of the amplifier is controlled.

[0021] The hybrid control variable gain amplifier circuit without a decoder provided by the third embodiment of the present invention is as shown in Figure 7 . Specifically, Figure 6 shows the circuit diagram of the CMOS single-pole double-throw switch in the gain block of this embodiment. The CMOS single-pole double-throw switch includes two pairs of inverter structures, where is the power supply voltage, providing the operating voltage for the circuit; the digital control signal is input from the Control port. Since the source voltage level of the NMOS transistor follows the gate voltage level, the level output from the Out1 end is the same as . Similarly, , after passing through the inverter, the level output from the Out2 end is opposite to . The input of the In port of the CMOS single-pole double-throw switch is (or ), and the input of the Control port is the digital control signal , and the obtained high and low levels are output from Out1 and Out2 respectively. Figure 7 shows the complete hybrid control variable gain amplifier circuit without a decoder, where The transistor functions as a switch. When port A is at a high level, the transistor conducts, allowing the current generated by the gain block to flow through. And It causes the current mirror to flow into the amplifier composed of ; And And And is a current source in the form of a transistor, which can increase the equivalent transconductance of the amplifier composed of They form a cascode output circuit. The MOS transistor controlled by port A functions as a switch. When A is connected to a low level or not powered, the circuit is in the analog control mode. When connected to a high level, the circuit is in the digital control mode. The gain block within the dashed box can control the summing current. From the amplification factor of the amplifier, it can be seen that at this time, the adjustment of the gain can be achieved through a digital signal, realizing the function of a hybrid control variable gain amplifier without a decoding module.

[0022] Compared with the prior art, the hybrid control variable gain amplifier and its circuit provided by the present invention without a decoder have the following beneficial effects: (1) Compared with the traditional hybrid control variable gain amplifier, the present invention does not require a decoding module, which can effectively reduce the delay, thus meeting the application requirements of gain amplifiers that require extremely high-speed response.

[0023] (2) Compared with the traditional hybrid control variable gain amplifier, the present invention has the advantages of relatively simple structure and low complexity. Specifically, according to the number of bits of the input signal, a corresponding number of gain block circuits with relatively simple structures are set to achieve the regulation of the summing current, without the need for additional decoding processes and relatively complex decoding circuit modules, reducing the circuit complexity.

[0024] (3) Compared with the traditional hybrid control variable gain amplifier, the present invention has higher analog control flexibility. Specifically, the decoding process of the DECODE module with a traditional structure is fixed, and users cannot directly adjust the internal decoding logic. In some special applications, a more flexible analog control method may be required. The present invention realizes digital deconstruction through a CMOS array and switches between the analog control mode and the digital control mode through CMOS, facilitating the design of the deconstruction method of the required logic and the mode switching method according to specific requirements, and thus having better flexibility.

[0025] Matters not described in the present invention are well-known technologies.

[0026] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered that the scope described in this specification is covered.

[0027] The above-described embodiments merely represent several implementation manners of the present invention, and their descriptions are relatively specific and detailed. However, it should not be construed as a limitation on the scope of the invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention.

Claims

1. A hybrid control variable gain amplifier without a decoder, characterized in that, The hybrid control variable gain amplifier includes at least an OPA amplifier, two CMOS arrays, and switches C1 and C2 that connect the two CMOS arrays to the OPA amplifier respectively; the switch C1 controls the closing of the connection between the CMOS array of the upper circuit and the OPA amplifier, and the switch C2 controls the closing of the connection between the CMOS array of the lower circuit and the OPA amplifier; the hybrid control variable gain amplifier switches from the analog control mode to the digital control mode by closing the switches C1 and C2.

2. The hybrid control variable gain amplifier without a decoder according to claim 1, wherein Each CMOS array includes logic units, and each logic unit includes at least a block structure formed by a pair of NMOS transistors and a PMOS transistor; one logic unit constitutes one gain block in the hybrid control variable gain amplifier.

3. A circuit of a hybrid control variable gain amplifier without a decoder as described in claim 2, characterized in that, The circuits of two CMOS arrays are respectively connected to the circuit of the OPA amplifier through switch C1 and switch C2; the circuit of each CMOS array is formed by the circuits of a plurality of gain blocks connected in parallel.

4. The circuit of the hybrid control variable gain amplifier without a decoder according to claim 3, wherein Using a gain block to represent the th gain block in the CMOS array, ; the circuit of the gain block at least includes a CMOS single-pole double-throw switch, a PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The CMOS single-pole double-throw switch is used to connect the input digital control signal to the gates of the first NMOS transistor or the second NMOS transistor respectively, and control the generation of high and low levels that are positive and negative respectively, including a positive high level , and a negative low level ; High level When it is at high level, the first NMOS transistor connected to the high-level power supply voltage works to generate a current ; when it is at low level the second NMOS transistor connected to the bias voltage works to generate a current , because then ; the represents the current or the current of the gain block in the CMOS array of the up-path or down-path circuit.

5. The circuit of the hybrid control variable gain amplifier without a decoder according to claim 4, wherein The circuit of the OPA amplifier includes at least a first PMOS transistor and a second PMOS transistor, and also includes a non-inverting input terminal and an inverting input terminal for an input signal, and obtains a summing current from the CMOS array of the upper circuit or the lower circuit respectively or a current input terminal, a load resistor with both ends respectively connected to the drains of the first PMOS transistor and the second PMOS transistor and two output load resistors ; for each one end is connected to the drain of the PMOS transistor, and the other end is connected to the negative power supply; The load resistor , which is used to convert the drain current into a voltage and set the quiescent operating point of the OPA amplifier; The output load resistor , for outputting a signal.

6. The circuit of the hybrid control variable gain amplifier without a decoder according to claim 5, characterized in that Assume that the transconductances of the first PMOS transistor and the second PMOS transistor are both . Then, when the summing current or is connected to the current input terminal, the initial equivalent transconductance of the OPA amplifier is . Calculate the initial amplification factor , which is positively correlated with .

7. The circuit of the hybrid control variable gain amplifier without a decoder according to claim 4, characterized in that, Gain block The circuit of the CMOS single-pole double-throw switch described in [reference], includes at least two inverter structures, power supply voltage , input signal or signal input port In of [[input signal]], digital control signal digital signal input port Control of [[digital control signal]], output ports Out1 with the same level and output port Out2 with the opposite level ; The power supply voltage provides the working voltage for the circuit; Digital control signal When input from the Control port, since the source voltage of the NMOS transistor follows the gate voltage, the level output from the Out1 terminal is the same as the same, while after passing through the inverter, the level output from the Out2 terminal is opposite to the opposite.

8. The circuit of the hybrid control variable gain amplifier without a decoder according to claim 7, characterized in that, including a transistor for connecting a CMOS array switch, a port A for inputting a high level or a low level, and a transistor ; wherein, the transistor forms an OPA amplifier, and the input current mirror flows into the OPA amplifier formed by the transistor through the transistor and ; the transistor forms an OPA amplifier together with the transistor and and and are current sources in the form of transistors for increasing the equivalent transconductance of the OPA amplifier formed by the transistor ; the transistor forms a cascode output circuit; When the port A is connected to a low level or not powered, the circuit is in the analog control mode; when the port A is at a high level, the circuit is in the digital control mode, and the transistor conducts to allow the current generated by the gain block to flow through.

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