A successive approximation-pipelined hybrid analog-to-digital converter and a timing control method

Abstract

The present invention discloses a successive approximation - pipelined hybrid analog - to - digital converter and a timing control method. The successive approximation - pipelined hybrid analog - to - digital converter includes a first - stage analog - to - digital converter, a residue amplifier, a second - stage analog - to - digital converter, and a timing circuit module; the timing circuit module is configured to sequentially obtain a sampling clock signal and a first flag signal indicating that the first - stage analog - to - digital converter has completed quantization from the timing output terminal of the first - stage analog - to - digital converter, obtain a second flag signal indicating that the second - stage analog - to - digital converter has completed quantization from the timing output terminal of the second - stage analog - to - digital converter, generate an amplification clock signal according to the sampling clock signal, the first flag signal, and the second flag signal, and output the amplification clock signal to the timing control terminal of the residue amplifier; the residue amplifier is configured to perform residue amplification according to the amplification clock signal. The present invention realizes reducing the bit error rate of the successive approximation - pipelined hybrid analog - to - digital converter while improving the linearity.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of analog integrated circuit design, and in particular, to a successive approximation - pipelined hybrid analog - to - digital converter and a timing control method. Background Art

[0002] The successive approximation - pipelined hybrid analog - to - digital converter has the characteristics of low power consumption of the successive approximation analog - to - digital converter and high throughput and low noise of the pipelined analog - to - digital converter, and is widely used in the fields of wired and wireless communications.

[0003] Compared with the traditional pipelined analog - to - digital converter (Pipeline ADC), the difference of the successive approximation - pipelined hybrid analog - to - digital converter is that each stage adopts a successive approximation structure. Since the use of additional comparators and subtraction circuits is avoided, it ensures smaller power consumption and area, and reduces the circuit complexity of the analog - to - digital converter. At the same time, due to the reduction of the total number of stages, it is also beneficial for the analog - to - digital converter to achieve higher linearity. Compared with the traditional successive approximation register analog - to - digital converter (SAR ADC for short), the speed and accuracy are greatly improved. However, in the existing successive approximation - pipelined hybrid analog - to - digital converters, there are asynchronous clocks for the first SAR ADC and the second SAR ADC at two levels respectively, and there is also a clock for the inter - stage amplifier. If the timing design does not match, there are problems of high bit error rate and low linearity. Summary of the Invention

[0004] The present invention provides a successive approximation - pipelined hybrid analog - to - digital converter and a timing control method, so as to reduce the bit error rate of the successive approximation - pipelined hybrid analog - to - digital converter and improve the linearity at the same time.

[0005] In a first aspect, the embodiments of the present invention provide a successive approximation - pipelined hybrid analog - to - digital converter. The successive approximation - pipelined hybrid analog - to - digital converter includes a first - stage analog - to - digital converter, a residue amplifier, a second - stage analog - to - digital converter, and a timing circuit module; the input end of the first - stage analog - to - digital converter is connected to an input signal, the output end of the first - stage analog - to - digital converter is connected to the input end of the residue amplifier, and the output end of the residue amplifier is connected to the input end of the second - stage analog - to - digital converter;

[0006] The timing circuit module is respectively connected to the timing output end of the first-stage analog-to-digital converter, the timing control end of the residual amplifier, and the timing output end of the second-stage analog-to-digital converter; the timing circuit module is configured to sequentially obtain a sampling clock signal and a first flag signal indicating that the first-stage analog-to-digital converter has completed quantization from the timing output end of the first-stage analog-to-digital converter, obtain a second flag signal indicating that the second-stage analog-to-digital converter has completed quantization from the timing output end of the second-stage analog-to-digital converter, generate an amplification clock signal according to the sampling clock signal, the first flag signal, and the second flag signal, and output the amplification clock signal to the timing control end of the residual amplifier;

[0007] The residual amplifier is configured to perform residual amplification on the input signal that has been quantized by the first-stage analog-to-digital converter according to the amplification clock signal.

[0008] In a second aspect, an embodiment of the present invention further provides a timing control method for a successive approximation-pipelined hybrid analog-to-digital converter. The timing control method for the successive approximation-pipelined hybrid analog-to-digital converter is applied to the successive approximation-pipelined hybrid analog-to-digital converter described in any embodiment of the present invention, and includes:

[0009] Sequentially obtain a sampling clock signal and a first flag signal indicating that the first-stage analog-to-digital converter has completed quantization from the timing output end of the first-stage analog-to-digital converter, and obtain a second flag signal indicating that the second-stage analog-to-digital converter has completed quantization from the timing output end of the second-stage analog-to-digital converter; generate an amplification clock signal according to the sampling clock signal, the first flag signal, and the second flag signal, and output the amplification clock signal to the timing control end of the residual amplifier.

[0010] The present invention provides a successive approximation - pipelined hybrid analog - to - digital converter and a timing control method. The successive approximation - pipelined hybrid analog - to - digital converter includes a first - stage analog - to - digital converter, a residue amplifier, a second - stage analog - to - digital converter, and a timing circuit module. The timing circuit module obtains a sampling clock signal, a first flag signal indicating that the first - stage analog - to - digital converter has completed quantization, and a second flag signal indicating that the second - stage analog - to - digital converter has completed quantization. Thus, it is determined that the first - stage analog - to - digital converter has completed sampling according to the sampling clock signal, and it is determined that the first - stage analog - to - digital converter and the second - stage analog - to - digital converter have completed quantization according to the first flag signal and the second flag signal. An amplification clock signal is generated according to the sampling clock signal, the first flag signal, and the second flag signal to determine that the residue amplifier can perform residue amplification, enabling the residue amplifier to perform residue amplification after the first - stage analog - to - digital converter has completed sampling and after the first - stage analog - to - digital converter and the second - stage analog - to - digital converter have completed quantization. This avoids the error - code problem caused by the residue amplifier starting to work before the first - stage analog - to - digital converter has completed quantization, and also avoids the problem that the first - stage analog - to - digital converter has completed quantization very early while the residue amplifier has not yet performed residue amplification. While reducing the error rate of the successive approximation - pipelined hybrid analog - to - digital converter, it can also improve the linearity of the successive approximation - pipelined hybrid analog - to - digital converter. Brief Description of the Drawings

[0011] Figure 1 It is the overall timing diagram of a traditional successive approximation - pipelined hybrid analog - to - digital converter.

[0012] Figure 2 It is the structural schematic diagram of a successive approximation - pipelined hybrid analog - to - digital converter provided by an embodiment of the present invention.

[0013] Figure 3 It is the structural schematic diagram of another successive approximation - pipelined hybrid analog - to - digital converter provided by an embodiment of the present invention.

[0014] Figure 4 It is the structural schematic diagram of the first timing circuit provided by an embodiment of the present invention.

[0015] Figure 5 It is the partial timing diagram of the successive approximation - pipelined hybrid analog - to - digital converter provided by an embodiment of the present invention.

[0016] Figure 6 It is the structural schematic diagram of the second timing circuit provided by an embodiment of the present invention.

[0017] Figure 7 It is the overall timing diagram of the successive approximation - pipelined hybrid analog - to - digital converter provided by an embodiment of the present invention.

[0018] Figure 8 It is the structural schematic diagram of the third timing circuit provided by an embodiment of the present invention.

[0019] Figure 9 This is a flowchart of a timing control method for a successive approximation - pipelined hybrid analog - to - digital converter provided by an embodiment of the present invention.

[0020] Figure 10 This is a flowchart of another timing control method for a successive approximation - pipelined hybrid analog - to - digital converter provided by an embodiment of the present invention. Detailed implementation manners

[0021] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for the sake of description, only parts related to the present invention rather than all structures are shown in the accompanying drawings.

[0022] In the prior art, in the field of wired and wireless communications, radio frequency direct sampling schemes use analog - to - digital converters (ADCs) to directly sample high - frequency signals to replace traditional down - mixing structures. Due to the wide application of this structure, medium - high - precision ADCs with gigahertz speeds have become one of the current research hotspots. Pipelined - structure analog - to - digital converters are the conventional choice at this speed and precision. However, with the development and progress of technology, in nanoscale processes, pipelined analog - to - digital converters are becoming increasingly difficult to design due to their parallel design method and the problem of operational amplifier gain highly dependent on gate length. The difference between a successive approximation - pipelined hybrid analog - to - digital converter and a traditional pipelined ADC is that each stage adopts a successive approximation structure. By avoiding the use of additional comparators and subtraction circuits, it ensures lower power consumption and area, reducing the circuit complexity of the ADC. At the same time, since the total number of stages is reduced, it is also beneficial for the ADC to achieve higher linearity. Compared with traditional SAR ADCs, it significantly improves speed and precision. In addition, this structure also retains the potential to further improve speed by using a time - interleaved structure. This structure breaks the limitation that successive approximation (SAR) analog - to - digital converters cannot be applied to high - sampling - rate and high - resolution scenarios, and still maintains good power efficiency, and is relatively simple to design in nanoscale processes.

[0023] In a successive approximation - pipelined hybrid analog - to - digital converter, timing design is particularly important because the overall successive approximation - pipelined hybrid analog - to - digital converter includes asynchronous clocks for both the first SAR ADC and the second SAR ADC at two levels, as well as the clock for the inter - stage amplifier. If the timing design does not match, it will cause the problem of increased bit error rate of the chip in extreme environments.

[0024] The architecture of the traditional successive approximation - pipelined hybrid analog - to - digital converter samples in half a cycle and amplifies in the other half cycle. Therefore, the overall timing is divided into two equal parts. The successive approximation - pipelined analog - to - digital converter can also be designed using this timing. Figure 1 It is the overall timing diagram of the traditional successive approximation - pipelined hybrid analog - to - digital converter, as Figure 1 shown. φ1 is the overall sampling timing signal of the traditional successive approximation - pipelined hybrid analog - to - digital converter, and φ2 is the working timing signal of the inter - stage amplifier of the traditional successive approximation - pipelined hybrid analog - to - digital converter. In the sampling timing signal diagram of φ1, the S / H stage at time T1 is the sampling stage of the successive approximation - pipelined hybrid analog - to - digital converter. In the working timing signal diagram of φ2, the residual amplification stage at time T2 is the residual amplification stage of the inter - stage amplifier of the successive approximation - pipelined hybrid analog - to - digital converter. The second - stage SAR quantization in φ2 is the quantization stage of the second SAR ADC. One cycle of φ1 and φ2 is T1 + T2 time. The quantization stage of the first SAR ADC is after the sampling stage and before the residual amplification stage of the inter - stage amplifier, that is, the first - stage SAR quantization in φ1. Among them, the residual amplification time is the second - stage sampling time.

[0025] However, the traditional successive approximation - pipelined hybrid analog - to - digital converter has three potential problems: 1. In the architecture of the successive approximation - pipelined hybrid analog - to - digital converter, an input reference signal with a duty cycle not equal to 50% (usually 12.5%) is required. If this timing is adopted, an additional signal with a duty cycle of 50% is required to control the overall circuit. 2. If a fixed duty cycle is adopted, it may cause the residual amplifier to start working before the first - stage SAR ADC has completed quantization, and the residual amplification error will lead to an increase in the bit error rate. 3. If the first - stage SAR ADC finishes working very early, there will be a certain idle time. The first - stage SAR is not working, and the residual amplifier is not working either, which may reduce the linearity of the overall ADC.

[0026] Therefore, the embodiment of the present invention proposes a successive approximation - pipelined hybrid analog - to - digital converter, which can reduce the bit error rate and improve the linearity at the same time.

[0027] Figure 2 It is the structural schematic diagram of a successive approximation - pipelined hybrid analog - to - digital converter provided by the embodiment of the present invention. Refer to Figure 2, the successive approximation - pipelined hybrid analog - to - digital converter includes a first - stage analog - to - digital converter 110, a residue amplifier 120, a second - stage analog - to - digital converter 130, and a timing circuit module 140; the input terminal of the first - stage analog - to - digital converter 110 is connected to an input signal, the output terminal of the first - stage analog - to - digital converter 110 is connected to the input terminal of the residue amplifier 120, and the output terminal of the residue amplifier 120 is connected to the input terminal of the second - stage analog - to - digital converter 130.

[0028] The timing circuit module 140 is respectively connected to the timing output terminal of the first - stage analog - to - digital converter 110, the timing control terminal of the residue amplifier 120, and the timing output terminal of the second - stage analog - to - digital converter 130; the timing circuit module 140 is configured to sequentially obtain a sampling clock signal and a first flag signal indicating that the first - stage analog - to - digital converter 110 has completed quantization from the timing output terminal of the first - stage analog - to - digital converter 110, obtain a second flag signal indicating that the second - stage analog - to - digital converter 130 has completed quantization from the timing output terminal of the second - stage analog - to - digital converter 130, generate an amplification clock signal according to the sampling clock signal, the first flag signal, and the second flag signal, and output the amplification clock signal to the timing control terminal of the residue amplifier 120.

[0029] The residue amplifier 120 is configured to perform residue amplification on the input signal that has been quantized by the first - stage analog - to - digital converter 110 according to the amplification clock signal.

[0030] Among them, the first - stage analog - to - digital converter 110 and the second - stage analog - to - digital converter 130 are SAR ADCs. The first - stage analog - to - digital converter 110 quantizes the input signal under the control of the asynchronous clock of the first - stage analog - to - digital converter 110, and the second - stage analog - to - digital converter 130 quantizes the input signal under the control of the asynchronous clock of the second - stage analog - to - digital converter 130 for the sampling clock signal. The sampling clock signal is the overall sampling clock of the successive approximation - pipelined hybrid analog - to - digital converter. When the sampling clock signal is at a high level, the first - stage analog - to - digital converter 110 samples. When the sampling clock signal changes from a high level to a low level, the sampling of the first - stage analog - to - digital converter is completed. Therefore, it can be determined whether the first - stage analog - to - digital converter has completed sampling according to the sampling clock signal. When the first - stage analog - to - digital converter 110 has completed quantization, the asynchronous clock of the first - stage analog - to - digital converter 110 changes from a high level to a low level, and at this time, a high - level first flag signal is generated. When the first flag signal is at a high level, it is determined that the first - stage analog - to - digital converter 110 has completed quantization; when the asynchronous clock of the second - stage analog - to - digital converter 130 changes from a high level to a low level, a high - level second flag signal is generated at this time. When the second flag signal is at a high level, the second - stage analog - to - digital converter 130 has completed quantization.

[0031] Specifically, the sequential circuit module 140 is respectively connected to the sequential output terminal of the first-stage analog-to-digital converter 110, the sequential control terminal of the residual amplifier 120, and the sequential output terminal of the second-stage analog-to-digital converter 130. The sequential circuit module 140 can sequentially obtain the sampling clock signal and the first flag signal from the sequential output terminal of the first-stage analog-to-digital converter 110, and obtain the second flag signal from the sequential output terminal of the second-stage analog-to-digital converter 130. Thus, it is determined that the first-stage analog-to-digital converter 110 has completed sampling according to the sampling clock signal, and it is determined that the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 have completed quantization according to the first flag signal and the second flag signal. Thus, it can be determined that the residual amplifier 120 can perform residual amplification according to the sampling clock signal, the first flag signal, and the second flag signal, thereby generating an amplified clock signal. Optionally, when the sampling clock signal is at a low level and the first flag signal and the second flag signal are obtained, that is, after the first-stage analog-to-digital converter 110 has completed sampling and the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 have completed quantization, an amplified clock signal is generated. After generating the amplified clock signal, the residual amplifier 120 performs residual amplification on the input signal that has been quantized by the first-stage analog-to-digital converter 110 according to the amplified clock signal, avoiding the error code problem caused by the residual amplifier 120 starting to work before the first-stage analog-to-digital converter 110 has completed quantization, and also avoiding the problem that the first-stage analog-to-digital converter 110 has completed quantization very early while the residual amplifier 120 has not yet performed residual amplification. It realizes reducing the error code rate of the successive approximation-pipelined hybrid analog-to-digital converter and can also improve the linearity of the successive approximation-pipelined hybrid analog-to-digital converter.

[0032] In addition, by determining the amplified clock signal of the residual amplifier 120 through the sampling clock signal, the first flag signal, and the second flag signal, it is ensured that the residual amplifier 120 starts to work immediately at the next moment after the first-stage analog-to-digital converter 110 has completed quantization. It not only avoids the error code problem that may occur in the first half of the sampling clock signal time in the traditional 50% duty cycle clock control method, where the first-stage analog-to-digital converter 110 has not completed quantization, but also ensures that the residual amplifier 120 starts to work immediately after the first-stage analog-to-digital converter 110 has completed quantization, saving cycle time and reducing the bandwidth pressure on the residual amplifier 120. At the same time, the second-stage analog-to-digital converter 130 performs quantization sampling on the input signal under the control of the asynchronous clock of the second-stage analog-to-digital converter 130. Using the second flag signal indicating that the second-stage analog-to-digital converter 130 has completed quantization as a condition for generating the amplified clock signal of the residual amplifier 120 can ensure that the residual amplifier 120 is turned on only after both the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 have completed their work. Therefore, the successive approximation-pipelined hybrid analog-to-digital converter in the embodiment of the present invention does not require an additional clock while the internal functions are closed-loop and no error code will occur.

[0033] In an embodiment of the present invention, a successive approximation - pipelined hybrid analog - to - digital converter is provided. The successive approximation - pipelined hybrid analog - to - digital converter includes a first - stage analog - to - digital converter, a residue amplifier, a second - stage analog - to - digital converter, and a timing circuit module. The timing circuit module acquires a sampling clock signal, a first flag signal indicating that the first - stage analog - to - digital converter has completed quantization, and a second flag signal indicating that the second - stage analog - to - digital converter has completed quantization. Thus, it is determined that the first - stage analog - to - digital converter has completed sampling according to the sampling clock signal, and it is determined that the first - stage analog - to - digital converter and the second - stage analog - to - digital converter have completed quantization according to the first flag signal and the second flag signal. Thereby, it can be determined that the residue amplifier can perform residue amplification according to the sampling clock signal, the first flag signal, and the second flag signal, so as to generate an amplified clock signal, and the residue amplifier performs residue amplification on the input signal that has been quantized by the first - stage analog - to - digital converter according to the amplified clock signal. This avoids the error - code problem caused by the residue amplifier starting to work before the first - stage analog - to - digital converter has completed quantization, and also avoids the problem that the first - stage analog - to - digital converter has completed quantization very early while the residue amplifier has not yet performed residue amplification. While reducing the error - code rate of the successive approximation - pipelined hybrid analog - to - digital converter, the linearity of the successive approximation - pipelined hybrid analog - to - digital converter can also be improved.

[0034] Figure 3 FIG. is a schematic structural diagram of another successive approximation - pipelined hybrid analog - to - digital converter provided by an embodiment of the present invention. Refer to Figure 3 , the timing circuit module 140 includes a first timing circuit 141 and a second timing circuit 142; the input end of the first timing circuit 141 is respectively connected to the timing output ends of the first - stage analog - to - digital converter 110 and the second - stage analog - to - digital converter 130, and the output end of the first timing circuit 141 is connected to the input end of the second timing circuit 142; the first timing circuit 141 is configured to acquire the sampling clock signal, the first flag signal, and the second flag signal, generate an intermediate timing signal according to the sampling clock signal, the first flag signal, and the second flag signal, and send the intermediate timing signal to the second timing circuit 142.

[0035] The input end of the second timing circuit 142 is further connected to the timing output end of the first - stage analog - to - digital converter 110, and the output end of the second timing circuit 142 is connected to the timing control end of the residue amplifier 120. The second timing circuit 142 is configured to generate an amplified clock signal according to the first flag signal and the intermediate timing signal, and output the amplified clock signal to the timing control end of the residue amplifier 120.

[0036] Specifically, when the first timing circuit 141 obtains that the sampling clock signal is at a low level and obtains the first flag signal and the second flag signal, that is, when the first-stage analog-to-digital converter 110 finishes sampling and both the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 finish quantization, it immediately generates an intermediate timing signal. When the second timing circuit 142 obtains the intermediate timing signal or the first flag signal, it generates an amplification clock signal, thereby realizing generating the amplification clock signal according to the first flag signal and the intermediate timing signal, ensuring that the residue amplifier 120 immediately starts working at the next moment after both the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 complete quantization. This not only avoids the problem of error codes caused by the first-stage analog-to-digital converter 110 not completing quantization in the first half of the sampling clock signal time that may occur in the traditional 50% duty cycle clock control method, but also ensures that the residue amplifier 120 immediately starts working after the first-stage analog-to-digital converter 110 completes quantization, saving cycle time and reducing the bandwidth pressure on the residue amplifier 120.

[0037] Further, Figure 4 is a schematic structural diagram of the first timing circuit provided by an embodiment of the present invention. Figure 5 is a partial timing diagram of the successive approximation-pipelined hybrid analog-to-digital converter provided by an embodiment of the present invention. Refer to Figures 3 - 5 , the first timing circuit 141 includes a three-input AND gate 1411 and a NOT gate 1412. The first input terminal of the three-input AND gate 1411 is connected to the first flag signal CMPOK_SAR1, the second input terminal of the three-input AND gate 1411 is connected to the second flag signal CMPOK_SAR2, the third input terminal of the three-input AND gate 1411 is connected to the output terminal of the NOT gate 1412, and the output terminal of the three-input AND gate 1411 is connected to the input terminal of the second timing circuit 142; the input terminal of the NOT gate 1412 is connected to the sampling clock signal CLK_SAMPLE.

[0038] Among them, the three-input AND gate 1411 outputs high only when all its inputs are high. Only when both the first flag signal CMPOK_SAR1 and the second flag signal CMPOK_SAR2 are at a high level and the sampling clock signal CLK_SAMPLE is at a low level, the three-input AND gate 1411 outputs a high-level intermediate timing signal CLK_SAMPLE2, which can greatly reduce the error rate caused by the metastability of the comparator in the first-stage analog-to-digital converter 110. At the same time, it can also save cycle time to reduce the bandwidth pressure on the residue amplifier 120.

[0039] Specifically, the NOT gate 1412 can reverse the input high and low states. When the sampling clock signal CLK_SAMPLE is at a low level, a high-level signal can be output through the NOT gate 1412 to the third input terminal of the three-input AND gate 1411. The first flag signal CMPOK_SAR1 is at a high level after the first-stage analog-to-digital converter 110 completes quantization, and the second flag signal CMPOK_SAR2 is at a high level after the second-stage analog-to-digital converter 130 completes quantization. Therefore, when both the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 complete quantization and the successive approximation-pipelined hybrid analog-to-digital converter finishes sampling, an intermediate timing signal CLK_SAMPLE2 can be generated through the three-input AND gate 1411. Then, a reset clock signal and an amplification clock signal are generated according to the intermediate timing signal CLK_SAMPLE2 to reset and amplify the residual of the residual amplifier 120.

[0040] Optionally, as Figure 4 shown, the first timing circuit 141 further includes a delay unit 1413; the input terminal of the delay unit 1413 is connected to the first flag signal CMPOK_SAR1 after the first-stage analog-to-digital converter 110 completes quantization, and the output terminal of the delay unit 1413 is connected to the first input terminal of the three-input AND gate 1411; the delay unit 1413 is configured to delay the first flag signal CMPOK_SAR1 by a preset time and then input it to the first input terminal of the three-input AND gate 1411.

[0041] Specifically, the delay unit 1413 delays the first flag signal CMPOK_SAR1 by a preset time and then inputs it to the first input terminal of the three-input AND gate 1411. Exemplarily, the preset time is 30*10 -12 s. By delaying the first flag signal CMPOK_SAR1 by a preset time and then inputting it to the first input terminal of the three-input AND gate 1411, after the first timing circuit 141 receives the first flag signal CMPOK_SAR1, the three-input AND gate 1411 can be delayed by a preset time to generate the intermediate timing signal CLK_SAMPLE2, thereby further ensuring that an amplification clock signal is generated after the first-stage analog-to-digital converter 110 completes quantization, enabling the residual amplifier 120 to perform residual amplification, and further ensuring that the successive approximation-pipelined hybrid analog-to-digital converter does not produce error codes.

[0042] Furthermore, Figure 6 is a schematic structural diagram of the second timing circuit provided by the embodiment of the present invention. Refer to Figure 3 and Figure 6, the second timing circuit 142 includes an OR gate 1421. The first input terminal of the OR gate 1421 is connected to the first flag signal CMPOK_SAR1. The second input terminal of the OR gate 1421 is connected to the output terminal generated by the first timing circuit 141. The output terminal of the OR gate 1421 is connected to the timing control terminal of the residue amplifier 120.

[0043] Specifically, the first input terminal of the OR gate 1421 is connected to the first flag signal CMPOK_SAR1, and the second input terminal of the OR gate 1421 is connected to the intermediate timing signal CLK_SAMPLE2. The OR gate 1421 outputs a low level only when all inputs are low. When the first flag signal CMPOK_SAR1 is at a high level, or when the intermediate timing signal CLK_SAMPLE2 is at a high level, or when both the first flag signal CMPOK_SAR1 and the intermediate timing signal CLK_SAMPLE2 are at high levels, the output terminal of the OR gate 1421 outputs the amplified clock signal CLK_AMP at a high level to the timing control terminal of the residue amplifier 120, so that the residue amplifier 120 performs residue amplification on the input signal after being quantized by the first-stage analog-to-digital converter 110 according to the amplified clock signal CLK_AMP, avoiding the error code problem caused by the residue amplifier 120 starting to work before the first-stage analog-to-digital converter 110 has completed quantization, and also avoiding the problem that the first-stage analog-to-digital converter 110 has completed quantization very early while the residue amplifier 120 has not yet performed residue amplification. It realizes reducing the error code rate of the successive approximation - pipelined hybrid analog-to-digital converter and can also improve the linearity of the successive approximation - pipelined hybrid analog-to-digital converter.

[0044] Furthermore, Figure 7 is the overall timing diagram of the successive approximation - pipelined hybrid analog-to-digital converter provided by the embodiment of the present invention. Continuing to refer to Figure 3 and Figure 7 , the timing circuit module 140 includes a third timing circuit 143; the first input terminal of the third timing circuit 143 is connected to the timing output terminal of the first-stage analog-to-digital converter 110, and the second input terminal of the third timing circuit 143 is connected to the output terminal of the first timing circuit 141; the third timing circuit 143 is used to generate a reset clock signal CLK_AMP_RST according to the intermediate flag signal CLK5 and the intermediate timing signal CLK_SAMPLE2 during the quantization process of the first-stage analog-to-digital converter 110, and output the reset clock signal CLK_AMP_RST to the timing control terminal of the residue amplifier 120; wherein, the intermediate flag signal CLK5 during the quantization process of the first-stage analog-to-digital converter 110 is generated at the last rising edge in one cycle of the asynchronous clock signal CLK_ASY_SAR1 of the first-stage analog-to-digital converter 110; the residue amplifier 120 is used to perform reset according to the reset clock signal CLK_AMP_RST.

[0045] Among them, the intermediate flag signal CLK5 in the quantization process of the first-stage analog-to-digital converter 110 is generated at the last rising edge in one cycle of the asynchronous clock signal of the first-stage analog-to-digital converter 110, that is, the intermediate flag signal CLK5 is the latch signal of the last rising edge in one cycle of the asynchronous clock signal of the first-stage analog-to-digital converter 110.

[0046] Specifically, the first input end of the third timing circuit 143 is connected to the timing output end of the first-stage analog-to-digital converter 110 for obtaining the intermediate flag signal CLK5 in the quantization process of the first-stage analog-to-digital converter 110. The second input end of the third timing circuit 143 is connected to the output end of the first timing circuit 141 for obtaining the intermediate timing signal CLK_SAMPLE2. Refer to Figure 7 , the third timing circuit 143 generates a reset clock signal CLK_AMP_RST through the intermediate flag signal CLK5 and the intermediate timing signal CLK_SAMPLE2, so that the reset clock signal CLK_AMP_RST and the amplification clock signal CLK_AMP do not overlap at all, thereby preventing the information amount stored on the capacitor of the first-stage analog-to-digital converter 110 from being released by the reset circuit of the residue amplifier 120. The specific principle is to turn off the reset circuit of the residue amplifier 120 at the rising edge of the last asynchronous clock of the first-stage analog-to-digital converter 110. At this time, the residue amplifier 120 has completed the reset.

[0047] Furthermore, Figure 8 is a schematic structural diagram of the third timing circuit provided by the embodiment of the present invention. Refer to Figure 8 , the third timing circuit 143 includes a NOR gate 1431. The first input end of the NOR gate 1431 is connected to the intermediate flag signal CLK5 in the quantization process of the first-stage analog-to-digital converter 110, and the second input end of the NOR gate is connected to the output end of the first timing circuit 141; the third timing circuit 143 is used to generate a reset clock signal CLK_AMP_RST according to the intermediate flag signal CLK5 and the intermediate timing signal CLK_SAMPLE2 in the quantization process of the first-stage analog-to-digital converter 110, and output the reset clock signal CLK_AMP_RST to the timing control end of the residue amplifier 120.

[0048] Among them, the NOR gate 1431 will output high only when all inputs are low. When both the intermediate flag signal CLK5 and the intermediate timing signal CLK_SAMPLE2 in the quantization process of the first-stage analog-to-digital converter 110 are low, the third timing circuit 143 generates a reset clock signal CLK_AMP_RST.

[0049] Specifically, to avoid the non - overlapping of the reset clock signal CLK_AMP_RST and the amplified clock signal CLK_AMP, when the amplified clock signal CLK_AMP is at a low level, the reset clock signal CLK_AMP_RST needs to be at a high level, so as to ensure that the reset of the residual amplifier 120 and the residual amplification are carried out at different times, preventing the information stored on the capacitors of the first - stage analog - to - digital converter 110 from being released by the reset circuit of the residual amplifier 120.

[0050] In addition, as Figure 2 and Figure 7As shown, the reset clock signal CLK_AMP_RST and the amplification clock signal CLK_AMP of the residual amplifier 120 do not overlap, which can prevent the information stored on the capacitors of the first-stage analog-to-digital converter 110 from being released by the reset circuit of the residual amplifier 120. The specific principle is that the reset circuit of the residual amplifier 120 is turned off at the rising edge t1 of the last asynchronous clock of the first-stage analog-to-digital converter 110. At this time, the residual amplifier 120 has completed the reset. When the first-stage analog-to-digital converter 110 completes quantization and generates a high-level first flag signal CMPOK_SAR1, the first flag signal CMPOK_SAR1 and the intermediate timing signal CLK_SAMPLE2 can cause the amplification clock signal CLK_AMP to start rising at time t2 through the OR gate 1421, generating a high-level amplification clock signal CLK_AMP, and the residual amplification of the residual amplifier 120 begins. During the residual amplification process of the residual amplifier 120, the amplification clock signal CLK_AMP is at a high level. Exemplarily, at time t3 during the residual amplification process of the residual amplifier 120, the amplification clock signal CLK_AMP, the first flag signal CMPOK_SAR1, the second flag signal CMPOK_SAR2, the intermediate timing signal CLK_SAMPLE2, and the intermediate flag signal CLK5 are all at a high level. By controlling the working timing of the residual amplifier 120, it can be ensured that the residual amplifier 120 starts working immediately at the next moment after the first-stage analog-to-digital converter 110 completes quantization. This not only avoids the problem of bit errors caused by the first-stage analog-to-digital converter 110 not completing quantization in the first half of the sampling clock signal CLK_SAMPLE that may occur in the traditional 50% duty cycle clock control method, but also ensures that the residual amplifier 120 starts working immediately after the first-stage analog-to-digital converter 110 completes quantization, reducing the bandwidth pressure on the residual amplifier 120. At the same time, an asynchronous signal CLK_ASY_SAR2 is added to control the operation of the second-stage analog-to-digital converter 130. The second flag signal CMPOK_SAR2 indicating the completion of quantization of the second-stage analog-to-digital converter 130 is added to the three-input AND gate 1411, so it can be ensured that the residual amplifier 120 is turned on only after both the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 have completed their operations. Therefore, the successive approximation-pipelined hybrid analog-to-digital converter according to the embodiments of the present invention does not require an additional clock while the internal functions are closed-loop, and there will be no bit error situation. While reducing the bit error rate of the successive approximation-pipelined hybrid analog-to-digital converter, it can also improve the linearity of the successive approximation-pipelined hybrid analog-to-digital converter.

[0051] Embodiments of the present invention provide a successive approximation - pipelined hybrid analog - to - digital converter, which avoids the error code problem caused by the residue amplifier starting to work before the first - stage analog - to - digital converter finishes quantization, and also avoids the problem that the first - stage analog - to - digital converter finishes quantization very early while the residue amplifier has not yet performed residue amplification. It realizes reducing the error rate of the successive approximation - pipelined hybrid analog - to - digital converter and can also improve the linearity of the successive approximation - pipelined hybrid analog - to - digital converter.

[0052] Embodiments of the present invention also provide a timing control method for a successive approximation - pipelined hybrid analog - to - digital converter. The timing control method for the successive approximation - pipelined hybrid analog - to - digital converter is applied to the successive approximation - pipelined hybrid analog - to - digital converter in any embodiment of the present invention. Figure 9 It is a flowchart of a timing control method for a successive approximation - pipelined hybrid analog - to - digital converter provided by embodiments of the present invention. Refer to Figure 9 , and the timing control method for the successive approximation - pipelined hybrid analog - to - digital converter includes:

[0053] S110: Sequentially obtain a sampling clock signal and a first flag signal indicating that the first - stage analog - to - digital converter has completed quantization from the timing output terminal of the first - stage analog - to - digital converter, and obtain a second flag signal indicating that the second - stage analog - to - digital converter has completed quantization from the timing output terminal of the second - stage analog - to - digital converter.

[0054] Specifically, referring to Figure 2 , it is determined that the first - stage analog - to - digital converter 110 has completed sampling according to the sampling clock signal, and it is determined that the first - stage analog - to - digital converter 110 and the second - stage analog - to - digital converter 130 have completed quantization according to the first flag signal and the second flag signal. Thus, it can be determined that the residue amplifier 120 can perform residue amplification according to the sampling clock signal, the first flag signal, and the second flag signal, thereby generating an amplified clock signal.

[0055] S120: Generate an amplified clock signal according to the sampling clock signal, the first flag signal, and the second flag signal, and output the amplified clock signal to the timing control terminal of the residue amplifier.

[0056] Specifically, when the sampling clock signal is at a low level and the first flag signal and the second flag signal are obtained, that is, when the first-stage analog-to-digital converter 110 finishes sampling and the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 finish quantization, an amplified clock signal is generated. After generating the amplified clock signal, the residual amplifier 120 performs residual amplification on the input signal that has been quantized by the first-stage analog-to-digital converter 110 according to the amplified clock signal, avoiding the error code problem caused by the residual amplifier 120 starting to work before the first-stage analog-to-digital converter 110 finishes quantization, and also avoiding the problem that the first-stage analog-to-digital converter 110 finishes quantization very early while the residual amplifier 120 still has not performed residual amplification, ensuring that the residual amplifier 120 starts to work immediately at the next moment after the first-stage analog-to-digital converter 110 finishes quantization, achieving the reduction of the error rate of the successive approximation - pipelined hybrid analog-to-digital converter and also improving the linearity of the successive approximation - pipelined hybrid analog-to-digital converter.

[0057] An embodiment of the present invention provides a timing control method for a successive approximation - pipelined hybrid analog-to-digital converter. By obtaining the sampling clock signal, the first flag signal indicating that the first-stage analog-to-digital converter finishes quantization, and the second flag signal indicating that the second-stage analog-to-digital converter finishes quantization, it is determined that the first-stage analog-to-digital converter finishes sampling according to the sampling clock signal, and it is determined that the first-stage analog-to-digital converter and the second-stage analog-to-digital converter finish quantization according to the first flag signal and the second flag signal. Thus, it can be determined that the residual amplifier can perform residual amplification according to the sampling clock signal, the first flag signal, and the second flag signal, thereby generating an amplified clock signal, and the residual amplifier performs residual amplification on the input signal that has been quantized by the first-stage analog-to-digital converter according to the amplified clock signal, avoiding the error code problem caused by the residual amplifier starting to work before the first-stage analog-to-digital converter finishes quantization, and also avoiding the problem that the first-stage analog-to-digital converter finishes quantization very early while the residual amplifier still has not performed residual amplification, achieving the reduction of the error rate of the successive approximation - pipelined hybrid analog-to-digital converter and also improving the linearity of the successive approximation - pipelined hybrid analog-to-digital converter.

[0058] Further, Figure 10 is a flowchart of another timing control method for a successive approximation - pipelined hybrid analog-to-digital converter provided by an embodiment of the present invention. Refer to Figure 10 , generating an amplified clock signal according to the sampling clock signal, the first flag signal, and the second flag signal includes:

[0059] S210. Generate an intermediate timing signal according to the sampling clock signal, the first flag signal, and the second flag signal.

[0060] Specifically, refer to Figures 3 - 5, only when both the first flag signal CMPOK_SAR1 and the second flag signal CMPOK_SAR2 are at high level and the sampling clock signal CLK_SAMPLE is at low level, will the three-input AND gate 1411 output a high-level intermediate timing signal CLK_SAMPLE2. The intermediate timing signal can be used to generate non-overlapping amplified clock signals and reset clock signals, thereby greatly reducing the bit error rate caused by comparator metastability in the first-stage analog-to-digital converter 110. At the same time, it can also save cycle time to reduce the bandwidth pressure on the residue amplifier 120.

[0061] S220. Generate an amplified clock signal according to the first flag signal and the intermediate timing signal, and output the amplified clock signal to the timing control terminal of the residue amplifier.

[0062] Specifically, referring to Figure 3 and Figure 6 , when the first flag signal CMPOK_SAR1 is at high level, or the intermediate timing signal CLK_SAMPLE2 is at high level, or both the first flag signal CMPOK_SAR1 and the intermediate timing signal CLK_SAMPLE2 are at high level, the output terminal of the OR gate 1421 outputs a high-level amplified clock signal CLK_AMP to the timing control terminal of the residue amplifier 120, so that the residue amplifier 120 performs residue amplification on the input signal after quantization by the first-stage analog-to-digital converter 110 according to the amplified clock signal CLK_AMP, avoiding the bit error problem caused by the residue amplifier 120 starting to work before the first-stage analog-to-digital converter 110 has completed quantization, and at the same time avoiding the problem that the first-stage analog-to-digital converter 110 has completed quantization very early while the residue amplifier 120 has not yet performed residue amplification. While reducing the bit error rate of the successive approximation - pipelined hybrid analog-to-digital converter, it can also improve the linearity of the successive approximation - pipelined hybrid analog-to-digital converter.

[0063] Optionally, after generating the intermediate timing signal according to the sampling clock signal, the first flag signal and the second flag signal, it further includes:

[0064] Generate a reset clock signal according to the intermediate flag signal and the intermediate timing signal during the quantization process of the first-stage analog-to-digital converter, and output the reset clock signal to the timing control terminal of the residue amplifier.

[0065] Specifically, referring to Figure 3 and Figure 7, a reset clock signal CLK_AMP_RST is generated through an intermediate flag signal CLK5 and an intermediate timing signal CLK_SAMPLE2, and the residue amplifier 120 is reset according to the reset clock signal CLK_AMP_RST. The reset clock signal CLK_AMP_RST and the amplification clock signal CLK_AMP of the residue amplifier 120 do not overlap at all, thereby preventing the amount of information stored on the capacitor of the first-stage analog-to-digital converter 110 from being released by the reset circuit of the residue amplifier 120.

[0066] The embodiment of the present invention provides a timing control method for a successive approximation-pipelined hybrid analog-to-digital converter, which avoids the error code problem caused by the residue amplifier starting to work before the first-stage analog-to-digital converter in the successive approximation-pipelined hybrid analog-to-digital converter has completed quantization, and also avoids the problem that the first-stage analog-to-digital converter has completed quantization very early while the residue amplifier has not yet performed residue amplification. While reducing the error rate of the successive approximation-pipelined hybrid analog-to-digital converter, it can also improve the linearity of the successive approximation-pipelined hybrid analog-to-digital converter.

[0067] Note that the above is only a preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments here, and various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, it can also include more other equivalent embodiments, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A successive approximation-pipeline hybrid analog-to-digital converter, characterized in that: The successive approximation-pipeline hybrid analog-to-digital converter comprises a first-stage analog-to-digital converter, a residual amplifier, a second-stage analog-to-digital converter and a timing circuit module; the input end of the first-stage analog-to-digital converter is connected to an input signal, the output end of the first-stage analog-to-digital converter is connected to the input end of the residual amplifier, and the output end of the residual amplifier is connected to the input end of the second-stage analog-to-digital converter; The timing circuit module is connected to the timing output terminal of the first-stage analog-to-digital converter, the timing control terminal of the residual amplifier, and the timing output terminal of the second-stage analog-to-digital converter respectively; the timing circuit module is used to sequentially obtain a sampling clock signal and a first flag signal of quantization completed by the first-stage analog-to-digital converter from the timing output terminal of the first-stage analog-to-digital converter, obtain a second flag signal of quantization completed by the second-stage analog-to-digital converter from the timing output terminal of the second-stage analog-to-digital converter, generate an amplified clock signal according to the sampling clock signal, the first flag signal, and the second flag signal, and output the amplified clock signal to the timing control terminal of the residual amplifier; The residual amplifier is used to perform residual amplification on the input signal after quantization by the first-stage analog-to-digital converter according to the amplified clock signal; The sequential circuit module includes a first sequential circuit and a second sequential circuit; The input end of the first sequential circuit is connected to the timing output end of the first-stage analog-to-digital converter and the timing output end of the second-stage analog-to-digital converter respectively, and the output end of the first sequential circuit is connected to the input end of the second sequential circuit; The first sequential circuit is used to obtain the sampling clock signal, the first flag signal and the second flag signal, generate an intermediate sequential signal according to the sampling clock signal, the first flag signal and the second flag signal, and send the intermediate sequential signal to the second sequential circuit; The input end of the second timing circuit is also connected to the timing output end of the first-stage analog-to-digital converter, and the output end of the second timing circuit is connected to the timing control end of the residual amplifier. The second timing circuit is used to generate the amplified clock signal according to the first flag signal and the intermediate timing signal, and output the amplified clock signal to the timing control end of the residual amplifier.

2. The successive approximation-pipeline hybrid analog-to-digital converter according to claim 1, characterized in that: The first sequential circuit includes a three-input AND gate and a NOT gate, wherein the first input of the three-input AND gate is connected to the first flag signal, the second input of the three-input AND gate is connected to the second flag signal, the third input of the three-input AND gate is connected to the output of the NOT gate, and the output of the three-input AND gate is connected to the input of the second sequential circuit; the input of the NOT gate is connected to the sampling clock signal.

3. The successive approximation-pipeline hybrid analog-to-digital converter according to claim 2, characterized in that: The first sequential circuit further includes a delay unit; The input end of the delay unit is connected to the first flag signal quantized by the first-stage analog-to-digital converter, and the output end of the delay unit is connected to the first input end of the three-input AND gate; The delay unit is used to delay the first flag signal by a preset time and then input the first flag signal to the first input terminal of the three-input AND gate.

4. The successive approximation-pipeline hybrid analog-to-digital converter according to claim 2, characterized in that: The second timing circuit includes an OR gate, a first input end of the OR gate is connected to the first flag signal, a second input end of the OR gate is connected to an output end generated by the first timing circuit, and an output end of the OR gate is connected to a timing control end of the residual amplifier.

5. The successive approximation-pipeline hybrid analog-to-digital converter according to claim 1, characterized in that: The sequential circuit module includes a third sequential circuit; The first input end of the third sequential circuit is connected to the sequential output end of the first-stage analog-to-digital converter, and the second input end of the third sequential circuit is connected to the output end of the first sequential circuit; The third timing circuit is used to generate a reset clock signal according to the intermediate flag signal of the quantization process of the first-stage analog-to-digital converter and the intermediate timing signal, and output the reset clock signal to the timing control terminal of the residual amplifier; wherein the intermediate flag signal of the quantization process of the first-stage analog-to-digital converter is generated at the last rising edge in one cycle of the asynchronous clock signal of the first-stage analog-to-digital converter; The residual amplifier is used for being reset according to the reset clock signal.

6. The successive approximation-pipeline hybrid analog-to-digital converter according to claim 5, characterized in that: The third sequential circuit comprises a NOR gate, a first input end of the NOR gate is connected to the intermediate flag signal of the quantization process of the first-stage analog-to-digital converter, and a second input end of the NOR gate is connected to the output end of the first sequential circuit; The third timing circuit is used to generate the reset clock signal according to the intermediate flag signal of the quantization process of the first-stage analog-to-digital converter and the intermediate timing signal, and output the reset clock signal to the timing control terminal of the residual amplifier.

7. A timing control method for a successive approximation-pipeline hybrid analog-to-digital converter, characterized in that: The timing control method of the successive approximation-pipeline hybrid analog-to-digital converter is applied to the successive approximation-pipeline hybrid analog-to-digital converter according to any one of claims 1 to 6, and the timing control method comprises: Acquire a sampling clock signal and a first flag signal indicating that quantization of the first-stage analog-to-digital converter is completed from a timing output terminal of the first-stage analog-to-digital converter, and acquire a second flag signal indicating that quantization of the second-stage analog-to-digital converter is completed from a timing output terminal of the second-stage analog-to-digital converter; An amplified clock signal is generated according to the sampling clock signal, the first flag signal and the second flag signal, and the amplified clock signal is output to a timing control terminal of the residual amplifier.

8. The timing control method of the successive approximation-pipeline hybrid analog-to-digital converter according to claim 7, characterized in that: The step of generating an amplified clock signal according to the sampling clock signal, the first flag signal and the second flag signal comprises: generating an intermediate timing signal according to the sampling clock signal, the first flag signal and the second flag signal; The amplified clock signal is generated according to the first flag signal and the intermediate timing signal, and the amplified clock signal is output to the timing control terminal of the residual amplifier.

9. The timing control method of the successive approximation-pipeline hybrid analog-to-digital converter according to claim 8, characterized in that: After the intermediate timing signal is generated according to the sampling clock signal, the first flag signal and the second flag signal, the method further includes: A reset clock signal is generated according to the intermediate flag signal of the quantization process of the first-stage analog-to-digital converter and the intermediate timing signal, and the reset clock signal is output to the timing control terminal of the residual amplifier.

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