A universal ultra-wideband reconfigurable receiving chip

Abstract

The present invention provides a general-purpose ultra-wideband reconfigurable receiving chip, including: multiple frequency conversion channels, used to mix and amplify radio frequency signals of different frequency bands, and output the processed radio frequency signals; orthogonal generation circuit, used to provide local oscillator signals for frequency conversion channels; radio frequency switch module, electrically connected to the frequency conversion channel, used to select different links for radio frequency signals of different frequency bands. By designing multiple frequency conversion channels in the chip structure and adopting reconfigurable design of link and unit layers, coverage of the 0.8~40GHz ultra-wideband is achieved; by integrating multiple circuit modules such as broadband low-noise amplifiers, orthogonal mixers, switch selection modules and baseband amplifiers, multifunctional receiving processing such as amplification, frequency conversion, filtering, and attenuation of radio frequency input signals is achieved; multiple working modes and parameter settings are flexibly configured through the SPI interface, thereby achieving the effect of taking into account ultra-wideband, multi-function and high flexibility in chip architecture.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a universal ultra-wideband reconfigurable receiving chip. Background Art

[0002] With the rapid development of technologies such as 5G, satellite communications, and radar, equipment is moving towards broadband, miniaturization, multi-functions, and low cost. A radio device often needs to support multiple frequency bands and multiple operating modes covering ultra-wide frequency bands.

[0003] However, traditional radio equipment usually only supports specific narrower operating frequency bands. If traditional equipment integration solutions are adopted, when the equipment operates in different frequency bands, its transceiver links need to be integrated with multiple narrowband RF transceiver chips respectively, resulting in high system complexity, poor flexibility, high cost and large size, making it extremely difficult to achieve integrated integration.

[0004] The ultra-wideband reconfigurable RF front-end transceiver chip is the core component of a multi-functional integrated terminal, with the advantages of flexible reconstruction, high integration, low cost and small size.

[0005] In order to realize ultra-wideband, flexible and configurable, multi-functional integrated radio equipment, one of the key challenges is to develop ultra-wideband reconfigurable receiving chips.

[0006] At present, the research on reconfigurable receiver chips in China is mainly focused on unit module circuits. There are still few existing single-chip reconfigurable receiver chips. The latest single-chip RF reconfigurable receiver chip reported in 2024 has a narrow bandwidth, an operating frequency range of only 5-16GHz, not exceeding four times the frequency band, and a single chip architecture with poor flexibility. A single-chip ultra-wideband multifunctional reconfigurable receiver chip that fully covers the L-Ka band is still blank.

[0007] The present disclosure also provides a universal ultra-wideband reconfigurable receiving chip, whose operating frequency covers an ultra-wide frequency band of 0.8-40GHz, and realizes a series of receiving processes such as amplification, frequency conversion, filtering, and attenuation of ultra-wide frequency band RF input signals. It has the advantages of flexible reconstruction, high integration and small size, and strongly supports the development of radio equipment towards broadband, miniaturization, multi-function and low cost. Summary of the invention

[0008] In a first aspect of the present disclosure, a universal ultra-wideband reconfigurable receiving chip is provided, the chip comprising:

[0009] A first frequency conversion channel, the first frequency conversion channel comprising a first noise amplifier, a first orthogonal mixer, and a first baseband amplifier electrically connected in sequence, for mixing and amplifying a radio frequency signal in a first frequency band, and outputting the processed radio frequency signal, wherein the first frequency band includes a frequency band with an operating frequency of 0.8 to 2 GHz;

[0010] A second frequency conversion channel, the second frequency conversion channel comprising a second noise amplifier, a second orthogonal mixer, and a second baseband amplifier electrically connected in sequence, for mixing and amplifying a radio frequency signal in a second frequency band, and outputting the processed radio frequency signal, wherein the second frequency band includes a frequency band with an operating frequency of 2 to 6 GHz;

[0011] a third frequency conversion channel, the third frequency conversion channel comprising a third noise amplifier, a third orthogonal mixer, a third orthogonal synthesizer and a first intermediate frequency amplifier electrically connected in sequence, for mixing and amplifying a radio frequency signal in a third frequency band, and outputting the processed radio frequency signal, the third frequency band comprising a frequency band with an operating frequency of 6 to 18 GHz;

[0012] a fourth frequency conversion channel, the fourth frequency conversion channel comprising a fourth noise amplifier, a fourth orthogonal mixer, a fourth orthogonal synthesizer and a second intermediate frequency amplifier electrically connected in sequence, for mixing and amplifying a radio frequency signal in a fourth frequency band, and outputting the processed radio frequency signal, the fourth frequency band comprising a frequency band with an operating frequency of 18 to 40 GHz;

[0013] The chip further comprises:

[0014] a first orthogonal generation circuit, the first orthogonal generation circuit being electrically connected to the first orthogonal mixer and the second orthogonal mixer respectively, and being used to provide a local oscillator signal for the orthogonal frequency conversion of the first frequency conversion channel and the second frequency conversion channel;

[0015] a second orthogonal generation circuit, the second orthogonal generation circuit being electrically connected to the third orthogonal mixer and the fourth orthogonal mixer respectively, and being used for providing a local oscillator signal for the orthogonal frequency conversion of the third frequency conversion channel and the fourth frequency conversion channel;

[0016] A radio frequency switch module, the radio frequency switch module is electrically connected to the third frequency conversion channel and the fourth frequency conversion channel respectively, and is used to select different links for the radio frequency signal of the third frequency band and the radio frequency signal of the fourth frequency band;

[0017] A fifth frequency conversion channel, the fifth frequency conversion channel is electrically connected to the radio frequency switch module, and includes a fifth orthogonal mixer, a third baseband amplifier and a fourth baseband amplifier, and the fifth orthogonal mixer is electrically connected to the first orthogonal generation circuit.

[0018] In combination with the first aspect, the first orthogonal mixer is further electrically connected to the second baseband amplifier, and the second orthogonal mixer is further electrically connected to the first baseband amplifier.

[0019] Preferably, the local oscillator frequency range provided by the first orthogonal generation circuit includes 3.2~12GHz.

[0020] Preferably, the local oscillator frequency range provided by the second orthogonal generation circuit includes 20~36GHz.

[0021] Preferably, the frequency range of the RF signal output by the first frequency conversion channel and the second frequency conversion channel includes 10K~100MHz.

[0022] Preferably, the frequency range of the radio frequency signal output by the fifth frequency conversion channel includes 10K~500MHz.

[0023] Furthermore, the optional links of the RF switch module include:

[0024] The switch end of the RF switch module and its output port constitute a first link, and the frequency range of the RF signal output by the first link includes 3~4GHz;

[0025] A second link formed by a switch end of the radio frequency switch module, the fifth orthogonal mixer, and the third baseband amplifier or the fourth baseband amplifier;

[0026] A third link consisting of the switch end of the RF switch module and its output port, the off-chip filter, the input port of the RF switch module, the fifth orthogonal mixer, and the third baseband amplifier or the fourth baseband amplifier;

[0027] The fourth link is formed by the switch end and input port of the RF switch module, the fifth orthogonal mixer, and the third baseband amplifier or the fourth baseband amplifier, and the fourth link includes an operating frequency in the frequency band of 3 to 4 GHz.

[0028] Furthermore, the intermediate frequency amplifier includes a first-stage filter, a second-stage filter and a differential common-source amplifier electrically connected in sequence,

[0029] The first-stage filter is used for primary filtering and gain control, the second-stage filter is used for secondary filtering and gain control, and the frequency of the primary filtering is lower than the frequency of the secondary filtering;

[0030] The differential common-source amplifier includes a fixed resistance load for providing output impedance and adjusting gain.

[0031] Furthermore, the baseband amplifier includes a notch filter, an attenuator, a differential amplifier and a DC compensation circuit which are electrically connected in sequence.

[0032] Furthermore, the chip further comprises:

[0033] A power management module including a DC offset cancellation circuit and a bandgap voltage reference for providing a stable voltage and eliminating DC offsets in the signal;

[0034] The serial peripheral interface module configures the chip's operating mode, frequency band, and gain through the SPI interface.

[0035] Beneficial effects: The present invention achieves coverage of an ultra-wide frequency band of 0.8 to 40 GHz by designing a variety of frequency conversion channels in the chip structure and adopting a reconfigurable design of the link and unit layers; by integrating a variety of core functional circuit modules such as a broadband low-noise amplifier, an orthogonal mixer, an intermediate frequency amplifier, a switch selection module, and a baseband amplifier, multifunctional receiving and processing such as amplification, frequency conversion, filtering, and attenuation of the RF input signal is achieved; a variety of operating modes and parameter settings are flexibly configured through the SPI interface, thereby achieving the effect of taking into account ultra-wideband, multi-functions, and high flexibility in the chip architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of the structure of an ultra-wideband reconfigurable receiving chip according to an embodiment of the present disclosure;

[0037] Figure 2 is a schematic structural diagram of an intermediate frequency amplifier according to an embodiment of the present disclosure;

[0038] Figure 3 It is a schematic diagram of the structure of the baseband amplifier of the embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the embodiments of the present disclosure.

[0040] The terms used in the disclosed embodiments are only for the purpose of describing specific embodiments and are not intended to limit the disclosed embodiments. The singular forms of "a", "said" and "the" used in the disclosed embodiments and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0041] It should be understood that although the terms first, second, third, etc. may be used to describe various information in the disclosed embodiments, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the disclosed embodiments, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0042] The ultra-wideband reconfigurable receiving chip is mainly composed of a broadband low-noise amplifier, an orthogonal mixer, an orthogonal synthesizer, an intermediate frequency filter, an intermediate frequency amplifier, a baseband amplifier, an orthogonal signal generator, an RF switch selection module, a power management module (DCOC, BGR) and an SPI module.

[0043] The chip adopts a zero-IF architecture, and the overall working frequency band is divided into multiple frequency conversion channels. Complex connections and merging are achieved through low-loss RF switches, which effectively reduces the layout area while achieving a compromise optimization between signal attenuation when turned on and isolation when disconnected.

[0044] After the RF signal enters the receiving chip through the antenna and front-end circuit, it enters the input port of the corresponding frequency band according to the frequency of the received signal. Considering the frequency band requirements of different application scenarios, the receiving chip is divided into four frequency conversion channels, which support 0.8~40G RF signal input in total.

[0045] refer to Figure 1 The four frequency band links that can receive signals are the first frequency conversion channel 110, the second frequency conversion channel 120, the third frequency conversion channel 130 and the fourth frequency conversion channel 140, all of which are single-ended input ports with impedance matching of 50 ohm and input standing wave ratio less than 2.0.

[0046] The first frequency conversion channel 110 includes a first noise amplifier 111, a first orthogonal mixer 112, and a first baseband amplifier 113 which are electrically connected in sequence, and is used to mix and amplify the radio frequency signal of the first frequency band (0.8-2 GHz), and output the processed radio frequency signal.

[0047] The second frequency conversion channel 120 includes a second noise amplifier 121, a second orthogonal mixer 122, and a second baseband amplifier 123 which are electrically connected in sequence, and is used to mix and amplify the RF signal in the second frequency band (2-6 GHz), and output the processed RF signal.

[0048] The third frequency conversion channel 130 includes a third noise amplifier 131, a third orthogonal mixer 132, a third orthogonal synthesizer 133 and a first intermediate frequency amplifier 134 which are electrically connected in sequence, and is used to mix and amplify the radio frequency signal in the third frequency band (6-18 GHz), and output the processed radio frequency signal.

[0049] The fourth frequency conversion channel 140 includes a fourth noise amplifier 141, a fourth orthogonal mixer 142, a fourth orthogonal synthesizer 143 and a second intermediate frequency amplifier 144 which are electrically connected in sequence, and is used to mix and amplify the radio frequency signal in the fourth frequency band (18~40GHz), and output the processed radio frequency signal.

[0050] The chip also includes:

[0051] A first orthogonal generation circuit 150, the first orthogonal generation circuit 150 is electrically connected to the first orthogonal mixer 112 and the second orthogonal mixer 122, respectively, and is used to provide a local oscillator signal for the orthogonal frequency conversion of the first frequency conversion channel 110 and the second frequency conversion channel 120;

[0052] A second orthogonal generation circuit 160, the second orthogonal generation circuit 160 is electrically connected to the third orthogonal mixer 132 and the fourth orthogonal mixer 142 respectively, and is used to provide a local oscillator signal for the orthogonal frequency conversion of the third frequency conversion channel 130 and the fourth frequency conversion channel 140;

[0053] The RF switch module 170 is electrically connected to the third frequency conversion channel 130 and the fourth frequency conversion channel 140, respectively, and is used to select different links for the RF signal of the third frequency band and the RF signal of the fourth frequency band;

[0054] The fifth frequency conversion channel 180 is electrically connected to the RF switch module 170 , and includes a fifth orthogonal mixer 181 , a third baseband amplifier 182 and a fourth baseband amplifier 183 . The fifth orthogonal mixer 181 is electrically connected to the first orthogonal generation circuit 150 .

[0055] Among them, after the single-ended input signal of each frequency conversion channel enters the chip, it passes through the first-stage low-noise amplifier inside it to realize the conversion of single-ended signal into differential signal while completing the low-noise signal amplification of the corresponding frequency band.

[0056] The second orthogonal generation circuit 160 provides a local oscillator signal for the first orthogonal down-conversion of the third frequency conversion channel 130 and the fourth frequency conversion channel 140. The first orthogonal generation circuit 150 provides a local oscillator for the second orthogonal down-conversion of the third frequency conversion channel 130, the fourth frequency conversion channel 140 and the fifth frequency conversion channel 180, and provides a local oscillator for the first orthogonal down-conversion of the first frequency conversion channel 110 and the second frequency conversion channel 120. The local oscillator frequency ranges corresponding to the first orthogonal generation circuit 150 and the second orthogonal generation circuit 160 are 20-36 GHz and 3.2-12 GHz, respectively.

[0057] The local oscillator ports are also single-ended interfaces, with impedance matching of 50ohm and input standing wave ratio less than 2.0. After the local oscillator signal enters the chip, it first passes through the orthogonal local oscillator signal generator to convert the single-ended signal into a differential signal, and finally uses the differential signal to generate an orthogonal local oscillator signal. The orthogonal local oscillator generation circuit used here will naturally divide the signal into two frequencies, so the orthogonal local oscillator signal generator will output a four-way divided orthogonal signal.

[0058] In addition, the first orthogonal mixer 112 is also electrically connected to the second baseband amplifier 123, and the second orthogonal mixer 122 is also electrically connected to the first baseband amplifier 113. The first frequency conversion channel 110 and the second frequency conversion channel 120 share a pair of orthogonal baseband output ports.

[0059] The third frequency conversion channel 130 and the fourth frequency conversion channel 140 share a pair of orthogonal baseband output ports. The output ports are all differential 100 ohm impedance matching, the frequency conversion method is orthogonal down conversion, and the output signal bandwidth is half of the input signal bandwidth.

[0060] When the received signal enters the first frequency conversion channel 110, it is first amplified by the first noise amplifier 111, then down-converted by the first orthogonal mixer 112, and finally directly amplified by the first baseband amplifier 113 or the second baseband amplifier 123 to generate an orthogonal baseband output signal. The I and Q output signals are both 10K~100MHz, and the actual output bandwidth is 200MHz.

[0061] When the received signal enters the second frequency conversion channel 120, it is first amplified by the second noise amplifier 121, then down-converted by the second orthogonal mixer 122, and finally directly amplified by the first baseband amplifier 113 or the second baseband amplifier 123 to generate an orthogonal baseband output signal. The I and Q output signals are both 10K~100MHz, and the actual output bandwidth is 200MHz.

[0062] When the received signal enters the third frequency conversion channel 130, it is first amplified by the third noise amplifier 131, which is a high-frequency, broadband, low-noise amplifier, and then the third orthogonal mixer 132 performs the first orthogonal down-conversion, and outputs fixed intermediate frequency signals containing two I signals and two Q signals, respectively, with a frequency of 3~4GHz, and then passes through the third orthogonal synthesizer 133 to generate a synthesized I signal and a synthesized Q signal. The I / Q signal passes through the first intermediate frequency amplifier 134 and enters the RF switch module 170.

[0063] When the received signal enters the fourth frequency conversion channel 140, it is first amplified by the fourth noise amplifier 141, which is a high-frequency, broadband, low-noise amplifier, and then the fourth orthogonal mixer 142 performs the first orthogonal down-conversion, and outputs fixed intermediate frequency signals containing two I signals and two Q signals, respectively, with a frequency of 3~4GHz, and then passes through the fourth orthogonal synthesizer 143 to generate a synthesized I signal and a synthesized Q signal. The I / Q signal passes through the second intermediate frequency amplifier 144 and enters the RF switch module 170.

[0064] The I / Q signals entering the RF switch module 170 are controlled by SPI, and multiple RF signals are aggregated into one channel to achieve the purpose of multiplexing the intermediate frequency amplifier, the second orthogonal down-conversion and the baseband amplifier, which can effectively reduce the chip area, reduce costs, and reduce the connection complexity of the second down-conversion circuit.

[0065] When the radio frequency signals aggregated into one path pass through the radio frequency switch module 170, there are four selectable link channels:

[0066] 1) First link: The signal can be directly output to the outside of the chip through the differential 100ohm impedance through the switch selection. At this time, the output port can provide a differential output signal of 3~4GHz, and the output 100ohm impedance matching is provided by an intermediate frequency amplifier covering 3~4GHz.

[0067] 2) Second link: directly connected to the fifth orthogonal mixer 181 for the second down-conversion, and finally providing a 10K~500MHz orthogonal baseband output signal. The fifth orthogonal mixer 181 adopts direct down-conversion, and the output signal bandwidth is half of the input signal bandwidth. The generated baseband signal will enter the baseband amplifier 182 or baseband amplifier 183 and output. The baseband amplifier 182 or baseband amplifier 183 can use an attenuator and an adjustable load network to provide adjustable gain and 3dB bandwidth.

[0068] 3) Third link: The signal is directly output to the outside of the chip through the differential 100ohm impedance through the switch selection. At this time, the output port can provide a 3~4GHz intermediate frequency differential output signal. Then the 3~4GHz intermediate frequency signal passes through the filter outside the chip (not shown in the figure), and then input into the chip, and through the switch selection, it directly goes to the fifth orthogonal mixer 181 for the second down-conversion. The subsequent signal path is the same as 2), which will not be repeated here.

[0069] 4) Fourth link: The intermediate frequency signal is input from the input port through an off-chip differential 100ohm to the fifth orthogonal mixer 181 for the second down-conversion. The input signal is a filtered 3~4GHz intermediate frequency signal. After the second orthogonal down-conversion is completed, the generated baseband signal enters the baseband amplifier 182 or the baseband amplifier 183 and is output.

[0070] Finally, the output port of the fifth frequency conversion channel 180 can provide an orthogonal baseband output signal of 10K~500MHz, the I-channel and Q-channel output signals are both 10K~500MHz, and the actual output bandwidth is 1GHz.

[0071] It should be noted that the frequency conversion channels described in the above chip architecture can be added, deleted or adjusted according to the actual working conditions. Specifically, the number of frequency conversion channels can be greater than or equal to 1 to meet the needs of different application scenarios. For example, in some narrowband application scenarios, only a single frequency conversion channel is required to meet the performance indicators, thereby simplifying chip design and reducing manufacturing costs. In ultra-wideband application scenarios, multiple frequency conversion channels can be added to support signal processing in more frequency bands and achieve higher system function integration.

[0072] Furthermore, based on the above chip architecture, the following structural variations can be performed to meet diverse needs:

[0073] Link splitting and multiplexing: For input signals of different frequency bands, the existing links can be further subdivided. For example, the low-band link can be split into smaller sub-band links, each sub-band corresponding to an independent low-noise amplifier and mixer, thereby achieving more refined frequency band processing. At the same time, in order to save chip area, some amplifiers and mixers can be reused by adding broadband RF switch modules.

[0074] Multi-stage down-conversion structure: In some ultra-wideband applications, the architecture of two-stage orthogonal down-conversion can be expanded to three or more stages of orthogonal down-conversion. By adding one or more stages of mixers and corresponding local oscillator signal generation modules, the frequency band selection flexibility and image suppression capability can be further improved to adapt to more complex signal environments.

[0075] Dynamic adjustability of gain and bandwidth: Further optimize the link performance of core functional circuit modules such as baseband amplifiers in the existing link architecture, so that key performance parameters such as gain and bandwidth can be dynamically adjusted according to working conditions. For example, the gain step of the baseband amplifier can be expanded to 1dB / step or smaller to meet more precise signal adjustment needs.

[0076] Expanded frequency band range: In response to future high-frequency application needs, ultra-high frequency links supporting millimeter wave bands can be added on the basis of the existing link architecture. For example, new links covering 40~100GHz can be added to further expand the application range of the chip and adapt to cutting-edge technology scenarios such as 5G, 6G and satellite communications.

[0077] Enhanced design of off-chip signal interaction: To meet the needs of complex signal processing, more off-chip signal interaction interfaces can be introduced in the switch selection module. For example, more input / output ports can be added on the basis of the existing IF interface to support multi-level interaction with external filters or signal processing units while ensuring signal isolation and reliability.

[0078] For further reference, Figure 2 The intermediate frequency amplifier includes a first-stage filter 210, a second-stage filter 220, and a differential common source amplifier 230 electrically connected in sequence, wherein the first-stage filter is used for primary filtering and gain control, and the second-stage filter is used for secondary point filtering and gain control, and the frequency of the first-stage filter is less than the frequency of the second-stage filter.

[0079] The differential common-source amplifier includes a fixed resistance load for providing output impedance and adjusting gain.

[0080] Specifically, the first-stage filter 210 is a 3 GHz gain adjustable filter, and the second-stage filter 220 is a 4 GHz gain adjustable filter. Both adopt a differential common source and common gate structure, and adjust the gain and frequency respectively by controlling the load resistance and capacitance, and jointly complete the 3~4 GHz filtering.

[0081] The differential common source amplifier 230 is a differential common source structure, which is mainly used to control the overall gain. Different from the first two amplifiers, the differential common source amplifier 230 uses a fixed resistance load, preferably provides a 100 ohm output impedance, and uses an adjustable tail current source to achieve adjustable gain.

[0082] For further reference, Figure 3 The baseband amplifier includes a notch filter 310, an attenuator 320, a differential amplifier 330 and a DC compensation circuit 340 which are electrically connected in sequence.

[0083] An LC resonant circuit is added to the notch filter 310 to eliminate the local oscillator signal leaking into the baseband during the mixing process through the resonant circuit.

[0084] In order to realize 2dB attenuation step control, an attenuator 320 of resistor divider type with precisely controllable attenuation is added to the baseband circuit to perform gain control to ensure that the gain step is 2dB / step.

[0085] At the same time, the circuit structure was optimized, and DC coupling was adopted between amplifiers to adapt to the zero intermediate frequency working mode.

[0086] The circuit is added with an automatic and coded controlled DC offset compensation circuit 340. At the same time, in order to improve the output linearity, the output stage of the circuit is optimized to increase the maximum output power.

[0087] Continue to refer Figure 1 The chip also includes:

[0088] A power management module, including a DC offset elimination circuit DCOC and a reference voltage source BGR, for providing a stable voltage and eliminating DC offsets in the signal;

[0089] The serial peripheral interface module configures the chip's operating mode, frequency band, gain and other parameters through the SPI interface.

[0090] BGR is a reference voltage source used to provide a stable reference voltage.

[0091] DCOC, as a DC offset cancellation circuit, is used to detect and eliminate the DC offset component in the signal, thereby ensuring accurate transmission and reception of the signal. This circuit is particularly suitable for ultra-wideband receiving chips because it can help improve the efficiency and reliability of data transmission.

[0092] The SPI module uses a typical three-wire SPI interface, which can flexibly configure the chip operating mode, signal operating frequency range, and link overall gain and linearity according to different application scenarios.

[0093] The SPI module contains four data interfaces, three unidirectional input ports and one bidirectional data port, and contains a total of 62 readable and writable registers for controlling the working state of the chip. By changing the register control code, the specific RF signal frequency, gain, working bandwidth and other indicators can be flexibly switched, thus having the ability to reconfigure the working state and functions of the chip.

[0094] The universal ultra-wideband reconfigurable receiving chip provided by the present invention realizes coverage of the ultra-wideband frequency band of 0.8~40GHz by designing multiple frequency conversion channels in the chip structure and adopting reconfigurable design of link and unit layers; realizes multifunctional receiving processing such as amplification, frequency conversion, filtering and attenuation of RF input signals by integrating multiple circuit modules such as broadband low-noise amplifier, orthogonal mixer, switch selection module and baseband amplifier; and flexibly configures multiple working modes and parameter settings through the SPI interface, thereby achieving the effect of taking into account ultra-wideband, multi-function and high flexibility in chip architecture.

[0095] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should all be included in the protection scope of the present disclosure.

Claims

1. A universal ultra-wideband reconfigurable receiving chip, characterized in that: The chip comprises: A first frequency conversion channel, the first frequency conversion channel comprising a first noise amplifier, a first orthogonal mixer, and a first baseband amplifier electrically connected in sequence, for mixing and amplifying a radio frequency signal in a first frequency band, and outputting the processed radio frequency signal, wherein the first frequency band includes a frequency band with an operating frequency of 0.8 to 2 GHz; A second frequency conversion channel, the second frequency conversion channel comprising a second noise amplifier, a second orthogonal mixer, and a second baseband amplifier electrically connected in sequence, for mixing and amplifying a radio frequency signal in a second frequency band, and outputting the processed radio frequency signal, wherein the second frequency band includes a frequency band with an operating frequency of 2 to 6 GHz; a third frequency conversion channel, the third frequency conversion channel comprising a third noise amplifier, a third orthogonal mixer, a third orthogonal synthesizer and a first intermediate frequency amplifier electrically connected in sequence, for mixing and amplifying a radio frequency signal in a third frequency band, and outputting the processed radio frequency signal, the third frequency band comprising a frequency band with an operating frequency of 6 to 18 GHz; a fourth frequency conversion channel, the fourth frequency conversion channel comprising a fourth noise amplifier, a fourth orthogonal mixer, a fourth orthogonal synthesizer and a second intermediate frequency amplifier electrically connected in sequence, for mixing and amplifying a radio frequency signal in a fourth frequency band, and outputting the processed radio frequency signal, the fourth frequency band comprising a frequency band with an operating frequency of 18 to 40 GHz; The chip further comprises: a first orthogonal generation circuit, the first orthogonal generation circuit being electrically connected to the first orthogonal mixer and the second orthogonal mixer respectively, and being used to provide a local oscillator signal for the orthogonal frequency conversion of the first frequency conversion channel and the second frequency conversion channel; a second orthogonal generation circuit, the second orthogonal generation circuit being electrically connected to the third orthogonal mixer and the fourth orthogonal mixer respectively, and being used for providing a local oscillator signal for the orthogonal frequency conversion of the third frequency conversion channel and the fourth frequency conversion channel; A radio frequency switch module, the radio frequency switch module is electrically connected to the third frequency conversion channel and the fourth frequency conversion channel respectively, and is used to select different links for the radio frequency signal of the third frequency band and the radio frequency signal of the fourth frequency band; A fifth frequency conversion channel, the fifth frequency conversion channel is electrically connected to the radio frequency switch module, and includes a fifth orthogonal mixer, a third baseband amplifier and a fourth baseband amplifier, and the fifth orthogonal mixer is electrically connected to the first orthogonal generation circuit.

2. The ultra-wideband reconfigurable receiving chip according to claim 1, characterized in that: The first orthogonal mixer is also electrically connected to the second baseband amplifier, and the second orthogonal mixer is also electrically connected to the first baseband amplifier.

3. The ultra-wideband reconfigurable receiving chip according to claim 1, characterized in that: The local oscillator frequency range provided by the first orthogonal generation circuit includes 3.2~12GHz.

4. The ultra-wideband reconfigurable receiving chip according to claim 1, characterized in that: The local oscillator frequency range provided by the second orthogonal generation circuit includes 20~36GHz.

5. The ultra-wideband reconfigurable receiving chip according to claim 1, characterized in that: The frequency range of the RF signal output by the first frequency conversion channel and the second frequency conversion channel includes 10K~100MHz.

6. The ultra-wideband reconfigurable receiving chip according to claim 1, characterized in that: The frequency range of the radio frequency signal output by the fifth frequency conversion channel includes 10K~500MHz.

7. The ultra-wideband reconfigurable receiving chip according to claim 1, characterized in that: The optional links of the RF switch module include: The switch end of the RF switch module and its output port constitute a first link, and the frequency range of the RF signal output by the first link includes 3~4GHz; A second link formed by a switch end of the radio frequency switch module, the fifth orthogonal mixer, and the third baseband amplifier or the fourth baseband amplifier; A third link consisting of the switch end of the RF switch module and its output port, the off-chip filter, the input port of the RF switch module, the fifth orthogonal mixer, and the third baseband amplifier or the fourth baseband amplifier; The fourth link is formed by the switch end and input port of the RF switch module, the fifth orthogonal mixer, and the third baseband amplifier or the fourth baseband amplifier, and the fourth link includes an operating frequency in the frequency band of 3 to 4 GHz.

8. The ultra-wideband reconfigurable receiving chip according to claim 1, characterized in that: The intermediate frequency amplifier includes a first-stage filter, a second-stage filter, and a differential common-source amplifier which are electrically connected in sequence. The first-stage filter is used for primary filtering and gain control, the second-stage filter is used for secondary filtering and gain control, and the frequency of the primary filtering is lower than the frequency of the secondary filtering; The differential common-source amplifier includes a fixed resistance load for providing output impedance and adjusting gain.

9. The ultra-wideband reconfigurable receiving chip according to claim 1, characterized in that: The baseband amplifier includes a notch filter, an attenuator, a differential amplifier and a DC compensation circuit which are electrically connected in sequence.

10. The ultra-wideband reconfigurable receiving chip according to claim 1, characterized in that: The chip further comprises: A power management module including a DC offset cancellation circuit and a bandgap voltage reference for providing a stable voltage and eliminating DC offsets in the signal; The serial peripheral interface module configures the chip's operating mode, frequency band, and gain through the SPI interface.

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