Broadband satellite on-board switching system based on multi-port dynamic allocation of shared multi-queues

Abstract

The present invention provides a broadband satellite on-board switching system based on multi-port dynamic allocation and shared multi-queues, comprising: an input processing unit, configured to receive on-board data of multiple ports and perform cache scheduling on the on-board data; an output processing unit, configured to receive the data output by the input processing unit and transmit it to the corresponding port for output; the input processing unit includes a plurality of input processing sub-units, and the input processing sub-unit includes: an on-board data combining processing module, configured to obtain the on-board data input by the corresponding port and perform detection and combining processing on the on-board data; a multi-port dynamic allocation and shared multi-queue module, configured to perform on the on-board data after combining processing, allocate the on-board data according to the cache status; a data block processing module, configured to perform block processing and information extraction on the allocated on-board data to obtain an on-board data block, a destination port, and priority information; a queue cache scheduling module, configured to perform caching and scheduling on the on-board data according to the destination port and priority information.

Description

Technical Field

[0001] The present invention relates to the technical field of broadband satellite on-board switching, and particularly to a broadband satellite on-board switching system based on multi-port dynamic allocation and shared multi-queues. Background Art

[0002] In recent years, with the continuous development of satellite communication systems, the number of broadband satellite nodes has been increasing continuously, the amount of data transmitted by on-board links has increased significantly, and the data exchange and transmission capacity of on-board links are facing challenges. How to achieve reliable and effective on-board data exchange has become the focus of research. In a broadband satellite on-board switching system, according to different switching objects, it is divided into two categories: channelized switching (belonging to circuit switching) and packet switching. Channelized switching uses frequency band shifting to achieve switching between different beams and different frequency sub-channels; packet switching mainly includes asynchronous transfer mode switching and Internet protocol switching, and completes the switching of user service data in the digital domain;

[0003] Currently, the mainstream on-board data packet switching method is the switching method based on the Crossbar architecture. This method mainly combines multi-port on-board data and stores it in a shared buffer area, and then outputs it through the Crossbar cross matrix; with the continuous increase in the number of ports and the continuous improvement of on-board data bandwidth, higher requirements are put forward for the switching capacity and transmission rate of the on-board switching system; currently, the on-board storage resources and computing capabilities of broadband satellites are limited and cannot meet the needs of large-scale on-board data storage, so higher requirements are put forward for the cache utilization rate of the on-board switching method; with the continuous increase in the number of broadband satellite nodes, the types of data packet services carried are also increasing, so higher requirements are put forward for the scheduling algorithm of the on-board switching system; the existing broadband satellite on-board switching system cannot dynamically allocate subsequent cache space, resulting in low cache space utilization rate of the existing on-board switching system. Summary of the Invention

[0004] In view of the deficiencies in the prior art, the present invention provides a broadband satellite on-board switching system based on multi-port dynamic allocation and shared multi-queues, which solves the problems existing in the prior art.

[0005] According to an embodiment of the present invention, a broadband satellite on-board switching system based on multi-port dynamic allocation and shared multi-queues includes:

[0006] An input processing unit, configured to receive on-board data of multiple ports and perform cache scheduling on the on-board data;

[0007] An output processing unit, configured to receive the data output by the input processing unit and transmit it to the corresponding port for output;

[0008] Among them, the input processing unit includes several input processing sub-units, and the input processing sub-units include: an on-board data multiplexing processing module, a multi-port dynamic allocation shared multi-queue module, a data block processing module, and a queue cache scheduling module;

[0009] The on-board data multiplexing processing module is used to obtain the on-board data input from the corresponding port, detect the on-board data, and perform multiplexing processing on the on-board data from several ports through fair polling;

[0010] The multi-port dynamic allocation shared multi-queue module is used to obtain the cache status and read the on-board data after the on-board data multiplexing processing module, and allocate the on-board data according to the cache status;

[0011] The data block processing module is used to perform block processing and information extraction on the allocated on-board data to obtain on-board data blocks, destination ports, and priority information;

[0012] The queue cache scheduling module is used to cache and schedule the on-board data according to the destination port and priority information.

[0013] As an embodiment of the present invention, the on-board data multiplexing processing module includes several mac_r modules and a fair poller;

[0014] The on-board data multiplexing processing module performs the following operations:

[0015] The mac_r module obtains the on-board data input from the corresponding port, performs frame header detection on the on-board data, and determines whether the frame header of the on-board data conforms to a preset format; if not, discard the on-board data;

[0016] If it conforms, perform CRC check and frame length detection on the on-board data, and determine whether the CRC check result and the data length conform to a preset format; if not, discard the on-board data; if it conforms, cache the on-board data in the mac_r module;

[0017] The fair poller sequentially reads the on-board data in the mac_r module in the manner of fair polling to obtain multiplexed on-board data.

[0018] As an embodiment of the present invention, the multi-port dynamic allocation shared multi-queue module performs the following operations:

[0019] Read the multiplexed on-board data output from the previous-level on-board data multiplexing processing module;

[0020] Obtain the cache status of the data block buffer area of the input processing sub-unit where the multi-port dynamic allocation shared multi-queue module is located, and the idle time of the on-board data multiplexing processing module of other input processing sub-units; among them, the cache status includes: unable to continue storing and can continue storing;

[0021] When there is an input processing sub - unit with idle time greater than the preset idle time, send the on - board data to this input processing sub - unit for processing;

[0022] When there is no input processing sub - unit with idle time greater than the preset idle time, determine whether to send the on - board data to other input processing sub - units for processing according to the cache status; if the cache status is that it cannot store any more, send the on - board data to other input processing sub - units for processing; if the cache status is that it can continue to store, do not send the on - board data to other input processing sub - units for processing.

[0023] As an embodiment of the present invention, the data block processing module performs the following operations:

[0024] Perform bit - width conversion and information extraction processing on the on - board data to obtain the converted data stream, destination port, and priority information;

[0025] Perform block - processing on the converted data stream to obtain on - board data blocks.

[0026] As an embodiment of the present invention, the queue cache scheduling module includes: a data block buffer, a multicast counter, a block number queue, a queue scheduling module, and a priority queue;

[0027] The block number queue is used to assign block numbers to the on - board data blocks input to the queue scheduling module;

[0028] The queue scheduling module is used to control the data block buffer to cache the received on - board data blocks, and when receiving a read request from the output processing unit, schedule and output the on - board data blocks;

[0029] The data block buffer is used to store the on - board data blocks, and when receiving an output instruction from the queue scheduling module, output the on - board data block corresponding to the block number;

[0030] The priority queue module is used to store the block numbers according to the destination port and priority information, and when receiving an output instruction from the queue scheduling module, select and output the block number in a certain priority queue corresponding to the destination port according to the scheduling strategy; among them, there are priority queue groups corresponding to several destination ports in the priority queue module, each priority queue group consists of 8 different priority queues; each priority queue is set with an initial weight value.

[0031] As an embodiment of the present invention, the queue scheduling module performs the following operations:

[0032] When receiving an on - board data block, determine the multicast count value based on the destination port information;

[0033] The control block number queue assigns a block number to each on-board data block, sends the on-board data block to the data block buffer for storage according to the address corresponding to the block number, sends the assigned block number to the priority queue module for storage, and sends the multicast count value to the multicast counter for storage;

[0034] When the output request of the output processing unit is received and the fair polling reaches the corresponding destination port at the same time, obtain the scheduling parameter information input from the outside, select the preset priority queue scheduling algorithm according to the scheduling parameter information to schedule the stored block numbers, and send an output instruction to the data block buffer to control the data block buffer to output the on-board data block corresponding to the block number;

[0035] Decrease by 1 the multicast count value corresponding to the block number stored in the multicast counter; among them, when the multicast count value corresponding to the block number stored in the multicast counter becomes 0, recycle the block number to the block number queue.

[0036] As an embodiment of the present invention, the scheduling parameter information includes: a first scheduling parameter and a second scheduling parameter; the preset priority queue scheduling algorithms include: strict priority and adaptive weighted scheduling algorithm;

[0037] Obtain the scheduling parameter information input from the outside, and select the preset priority queue scheduling algorithm according to the scheduling parameter information to schedule the stored block numbers, including:

[0038] If the scheduling parameter information is the first scheduling parameter, schedule the on-board data according to the strict priority algorithm and the priority information;

[0039] If the scheduling parameter information is the second scheduling parameter, schedule the on-board data according to the adaptive weighted scheduling algorithm.

[0040] As an embodiment of the present invention, scheduling the on-board data according to the adaptive weighted scheduling algorithm includes:

[0041] When there is no priority queue with a weight value of 0 in the priority queue group of the destination port, poll the priority queues of the destination port until a block number is output from the priority queue, and then subtract 1 from the weight value of this priority queue and stop polling; among them, during the polling process, when the priority queue with a non-zero weight value has no block number, continue to poll to the next priority queue;

[0042] When there is a priority queue with a weight value of 0 in the priority queue group of the destination port and there are block numbers in the priority queues with non-zero weight values, poll the priority queues of the destination port until a block number is output from a priority queue, and then subtract 1 from the weight value of this priority queue; among them, during the polling process, when polling to the priority queue with a weight value of 0, do not output the block number and continue to poll to the next priority queue;

[0043] When there is a priority queue with a weight value of 0 in the priority queue group of the destination port, and the priority queue with a weight value of 0 has a block number while the priority queues with non-zero weight values do not have block numbers, poll the priority queues of the destination port until a priority queue outputs a block number. The weight value of this priority queue remains unchanged. Among them, during the polling process, when polling to a priority queue with a weight value of 0, output the block number.

[0044] Among them, after the destination port outputs a block number and receives an output request again, poll the priority queues of the destination port, starting from the next priority queue after the priority queue that output the block number last time. Continuously poll the priority queues of the destination port until the weight values of all priority queues become 0, then calculate and update the initial weight value of each priority queue for the next cycle. The calculation formula is as follows:

[0045]

[0046] Among them, K 1 represents the initial weight value of the next cycle, K 0 represents the initial weight value of the current cycle, and n represents the number of response output requests after the weight value of the priority queue becomes 0 within one cycle.

[0047] The present invention also provides a broadband satellite on-board switching method based on multi-port dynamic allocation of shared multi-queues, including the following steps:

[0048] Receive on-board data of multiple ports and perform cache scheduling on the on-board data.

[0049] Receive the data after cache scheduling and transfer it to the corresponding port for output.

[0050] Receiving on-board data of multiple ports and performing cache scheduling on the on-board data includes:

[0051] Obtain the on-board data input by the corresponding port and perform detection and multiplexing processing on the on-board data.

[0052] Obtain the cache status and read the on-board data after multiplexing processing, and allocate the on-board data according to the cache status.

[0053] Perform block processing and information extraction on the allocated on-board data to obtain on-board data blocks, destination ports, and priority information.

[0054] Perform caching and scheduling on the on-board data according to the destination port and priority information.

[0055] A broadband satellite on - board switching device based on multi - port dynamic allocation of shared multi - queues is used to implement the above - mentioned broadband satellite on - board switching system based on multi - port dynamic allocation of shared multi - queues.

[0056] Compared with the prior art, the present invention has the following beneficial effects: Through the multi - port dynamic allocation of shared multi - queue module, according to the idle time of the on - board data multiplexing processing module of the input processing sub - unit and the cache status of the data buffer, it is determined whether to allocate the on - board data to other input processing sub - units for processing, realizing the dynamic allocation of data cache space and improving the cache utilization rate of the entire on - board switching system. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is a schematic structural diagram of an embodiment of the present invention;

[0058] Figure 2 It is a schematic structural diagram of an input processing sub - unit of another embodiment of the present invention;

[0059] Figure 3 It is a logical schematic diagram of a multi - queue dynamic allocation module of another embodiment of the present invention;

[0060] Figure 4 It is a schematic structural diagram of a queue cache scheduling module of another embodiment of the present invention;

[0061] Figure 5 It is an internal framework diagram of a priority queue module of another embodiment of the present invention;

[0062] Figure 6 It is a flowchart for calculating the initial weight value of a computational priority queue of another embodiment of the present invention;

[0063] Figure 7 It is a schematic diagram of an output processing unit of another embodiment of the present invention;

[0064] Figure 8 It is a schematic diagram of a device of another embodiment of the present invention;

[0065] Figure 9 It is a schematic structural diagram of Paper 1 involved in the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0066] The technical solutions in the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0067] As Figures 1 to 7 shown, an embodiment of the present invention proposes a broadband satellite on - board switching system based on multi - port dynamic allocation of shared multi - queues, including:

[0068] An input processing unit, configured to receive on - board data of multiple ports and perform cache scheduling on the on - board data;

[0069] An output processing unit, configured to receive the data output by the input processing unit and transmit it to the corresponding port for output;

[0070] Wherein, the input processing unit includes a plurality of input processing subunits, and the input processing subunits include: an on-board data multiplexing processing module, a multi-port dynamic allocation shared multi-queue module, a data block processing module, and a queue cache scheduling module;

[0071] An on-board data multiplexing processing module, configured to obtain the on-board data input by the corresponding port, detect the on-board data, and perform multiplexing processing on the on-board data of several ports through fair polling;

[0072] A multi-port dynamic allocation shared multi-queue module, configured to obtain the cache status and read the on-board data after the on-board data multiplexing processing module, and allocate the on-board data according to the cache status;

[0073] A data block processing module, configured to perform block processing and information extraction on the allocated on-board data to obtain on-board data blocks, destination ports, and priority information;

[0074] A queue cache scheduling module, configured to cache and schedule the on-board data according to the destination port and priority information;

[0075] The working principle of the above technical solution: The present invention takes the 16-port on-board data exchange as a model for embodiment elaboration. Through simple adjustment, the design of the present invention is also suitable for 24-port on-board data exchange, and has a certain range of applicability;

[0076] Multiple terminals (ground terminals or on-board terminals) send on-board data, which enter the input processing unit through multiple input ports (P0, P1,..., P14, P15) for cache processing, and then are scheduled for output from the destination ports (D0, D1,..., D14, D15) in the order of priority. The 16 input ports are divided into 4 groups, and the on-board data of each group of input ports enters an input processing subunit, that is, the input processing unit contains 4 input processing subunits; in the input processing subunit, the on-board data frame header detection, bit width conversion, data block allocation, data block caching, bus scheduling, etc. are completed through the provided on-board data multiplexing processing module, multi-port dynamic allocation shared multi-queue module, data block processing module, and queue cache scheduling module; at the same time, through the provided multi-port dynamic allocation shared multi-queue module, the subsequent cache status and the idle time of the on-board data multiplexing processing module are obtained, the on-board data after the on-board data multiplexing processing module is read, and the on-board data is allocated according to the cache status and idle time information;

[0077] Beneficial effects of the above technical solution: Through the multi-port dynamic allocation and shared multi-queue module, according to the idle time of the on-board data multiplexing processing module of the input processing sub-unit and the cache status of the data buffer, it is determined whether to allocate the on-board data to other input processing sub-units for processing, realizing the dynamic allocation of data cache space and improving the cache utilization rate of the entire on-board switching system.

[0078] In one embodiment, the on-board data multiplexing processing module includes several mac_r modules and a fair queueing scheduler;

[0079] The on-board data multiplexing processing module performs the following operations:

[0080] The mac_r module acquires the on-board data input from the corresponding port, and performs frame header detection on the on-board data to determine whether the frame header of the on-board data conforms to a preset format; if not, the on-board data is discarded;

[0081] If it conforms, perform CRC check and frame length detection on the on-board data to determine whether the CRC check result and the data length conform to the preset format; if not, discard the on-board data; if it conforms, cache the on-board data into the mac_r module;

[0082] The fair queueing scheduler sequentially reads the on-board data in the mac_r module in a fair queueing manner to obtain the multiplexed on-board data;

[0083] Working principle and beneficial effects of the above technical solution: The on-board data multiplexing processing module consists of 4 mac_r modules and a fair queueing scheduler, which respectively receive on-board data from input ports P0, P1, P2, and P3; the mac_r module performs frame header detection on the received data to determine whether the frame header of the on-board data conforms to the preset format; if not, discard the on-board data; if it conforms, perform CRC check and frame length detection on the on-board data to determine whether the CRC check result and the data length conform to the preset format; if not, discard the on-board data; if it conforms, cache the on-board data into the FIFO queue of the mac_r module waiting for output; the fair queueing scheduler sequentially reads the on-board data in the FIFO queues of the 4 mac_r modules in a fair queueing manner to complete the on-board data multiplexing processing.

[0084] In one embodiment, the multi-port dynamic allocation and shared multi-queue module performs the following operations:

[0085] Read the multiplexed on-board data output from the previous-stage on-board data multiplexing processing module;

[0086] Obtain the cache status of the data block buffer in the input processing subunit where the multi-port dynamic allocation shared multi-queue module is located, and the idle time of the on-board data multiplexing processing module in other input processing subunits; wherein, the cache status includes: unable to continue storing and can continue storing.

[0087] When there is an input processing subunit with an idle time greater than the preset idle time, send the on-board data to this input processing subunit for processing.

[0088] When there is no input processing subunit with an idle time greater than the preset idle time, determine whether to send the on-board data to other input processing subunits for processing according to the cache status; if the cache status is unable to continue storing, send the on-board data to other input processing subunits for processing; if the cache status is can continue storing, do not send the on-board data to other input processing subunits for processing.

[0089] The working principle and beneficial effects of the above technical solution: Read the on-board data output from the previous-stage on-board data multiplexing processing module in each input processing subunit; for example: the multiplexed data in input processing subunit 0 is unit0_data, the multiplexed data in input processing subunit 1 is unit1_data, and so on; in order to achieve multi-port queue dynamic allocation, a dynamic chip selector is designed and added. The dynamic chip selector in each input processing subunit will access the multiplexed data output by the on-board data multiplexing processing module of all input processing subunits, and then determine which input processing subunit the received multiplexed data enters for subsequent processing according to the cache status of the data block buffer in the subunit; for example, taking input processing subunit 0 as an example, assuming that the storage space of data block buffer 0 is not enough to cache an on-board data with the maximum frame length, the corresponding full indication signal (cache status) will be pulled high and inform the previous dynamic chip selector; when the dynamic chip selector receives the indication and there is unit0_data at this time, this data will not enter data block buffer 0, but will be sent to the other three input processing subunits for storage processing according to the chip selection result of the dynamic chip selector.

[0090] In addition, if the on-board data is only transmitted in a certain input processing subunit, and it is detected that the idle time of the on-board data multiplexing processing module in the other three input processing subunits is greater than the preset idle time, then the dynamic chip selector will sequentially send the multiplexed data into the data block buffers of other input processing subunits. Since the on-board data in each data block buffer will be transmitted to 4 cross nodes horizontally in the corresponding Crossbar output matrix, the function of multi-port multi-queue dynamic allocation and shared caching of on-board data is realized. At the same time, according to the result of the dynamic chip selector, the flow direction of the multiplexed data can be better controlled, and the space utilization rate of the subsequent cache unit can be improved.

[0091] In one embodiment, the data block processing module performs the following operations:

[0092] Perform bit-width conversion and information extraction processing on the on-board data to obtain the converted data stream, destination port, and priority information;

[0093] Perform block processing on the converted data stream to obtain on-board data blocks;

[0094] The working principle and beneficial effects of the above technical solution: The role of the data block processing module is to perform block processing on the on-board data output by the dynamic chip selector, which is convenient for subsequent block storage in the buffer area; the data block processing module performs bit-width conversion on the obtained on-board data, converts it into a 128-bit data stream and sends it to the subsequent bus, and at the same time extracts information from the on-board data to obtain the destination port and priority information; then perform block processing on the on-board data, and each data block is a fixed 64 Bytes; if there is a data block less than 64 Bytes, a certain amount of data needs to be filled.

[0095] In one embodiment, the queue cache scheduling module includes: a data block buffer, a multicast counter, a block number queue, a queue scheduling module, and a priority queue;

[0096] The block number queue is used to assign block numbers to the on-board data blocks input to the queue scheduling module;

[0097] The queue scheduling module is used to control the data block buffer to cache the received on-board data blocks, and when receiving a read request from the output processing unit, schedule and output the on-board data blocks;

[0098] The data block buffer is used to store the on-board data blocks, and when receiving an output instruction from the queue scheduling module, output the on-board data blocks corresponding to the block numbers;

[0099] The priority queue module is used to store the block numbers according to the destination port and priority information, and when receiving an output instruction from the queue scheduling module, select and output the block numbers in a certain priority queue corresponding to a certain destination port according to the scheduling strategy; among them, there are priority queue groups corresponding to the number of several destination ports in the priority queue module, and each priority queue group is composed of 8 different priority queues; each priority queue is set with an initial weight value;

[0100] Working principle and beneficial effects of the above technical solution: The queue cache scheduling module is the core of the cache scheduling method for the on-board switching system. It is specifically composed of a data block buffer, a multicast counter, a block number queue, a priority queue, and a queue scheduling module. The data block buffer is used to store on-board data blocks. When receiving the output indication from the queue scheduling module, it outputs the on-board data block corresponding to the block number. The block number queue writes the numbers (storage addresses) corresponding to all the space blocks in the data block buffer into the queue during initialization. Whenever a data block is received, a block number is assigned to the data block and stored in the corresponding buffer area through the block number. The queue scheduling module is responsible for caching the received on-board data blocks and outputting the corresponding on-board data blocks according to the priority queue scheduling rules when receiving the output request from the output processing unit.

[0101] To solve the head-of-line blocking problem of multicast on-board data at the Crossbar cross-node, a multicast counter is designed. When the queue scheduling module receives an on-board data block, it first determines the multicast count value based on the destination port information (this value is the number of destination ports to which the on-board data block needs to be transmitted), then assigns a block number to the data block, stores the multicast count value in the RAM of the multicast counter using this block number as the address, and at the same time the block number enters the priority queue of the corresponding destination port. Since it is multicast data, the block number may enter the priority queues of several destination ports at the same time, ensuring that subsequent multicast on-board data can be output from the corresponding destination ports. Whenever a block number is scheduled and output, the multicast count value corresponding to the block number is decremented by 1. Only when the multicast count value of the block number is decremented to 0, it means that the multicast on-board data has been output from several corresponding destination ports, ensuring the integrity of the multicast function. Since this method does not need to consider whether the subsequent Crossbar cross-nodes simultaneously meet the ready condition, there is no head-of-line blocking problem for multicast on-board data.

[0102] In one embodiment, the queue scheduling module performs the following operations:

[0103] When receiving an on-board data block, determine the multicast count value based on the destination port information;

[0104] Control the block number queue to assign a block number to each on-board data block, send the on-board data block to the data block buffer for storage according to the address corresponding to the block number, send the assigned block number to the priority queue module for storage, and send the multicast count value to the multicast counter for storage;

[0105] After receiving the output request from the output processing unit, it simultaneously performs fair polling to the corresponding destination port, obtains the scheduling parameter information of the external input, selects the preset priority queue scheduling algorithm according to the scheduling parameter information to schedule the stored block numbers, and issues an output instruction to the data block buffer to control the data block buffer to output the on-board data blocks corresponding to the block numbers.

[0106] Decrease by 1 the multicast count value corresponding to the block number stored in the multicast counter; among them, when the multicast count value corresponding to the block number stored in the multicast counter becomes 0, recycle the block number to the block number queue.

[0107] The scheduling parameter information includes: the first scheduling parameter and the second scheduling parameter; the preset priority queue scheduling algorithms include: strict priority and adaptive weighted scheduling algorithm.

[0108] Obtain the scheduling parameter information of the external input, and select the preset priority queue scheduling algorithm according to the scheduling parameter information to schedule the stored block numbers, including:

[0109] If the scheduling parameter information is the first scheduling parameter, schedule the on-board data according to the strict priority algorithm and the priority information.

[0110] If the scheduling parameter information is the second scheduling parameter, schedule the on-board data according to the adaptive weighted scheduling algorithm.

[0111] Schedule the on-board data according to the strict priority algorithm and the priority information, including:

[0112] The priority queue group of the destination port includes priority queue 7, priority queue 6, priority queue 5, priority queue 4, priority queue 3, priority queue 2, priority queue 1, and priority queue 0. The block number will enter one of the priority queues according to the destination port and the priority information.

[0113] When there is a block number in priority queue 7 of the destination port, regardless of whether there are data block numbers in other priority queues, preferentially output the data block numbers in priority queue 7; until there are no data block numbers in priority queue 7, then poll to the next priority queue with existing data block numbers and output the block number; in the strict priority algorithm, the output priority of the data block number decreases in turn in priority queue 7, priority queue 6, priority queue 5, priority queue 4, priority queue 3, priority queue 2, priority queue 1, and priority queue 0.

[0114] Schedule the on-board data according to the adaptive weighted scheduling algorithm, including:

[0115] When there is no priority queue with a weight value of 0 in the priority queue group of the destination port, poll the priority queues of the destination port until the block number is output by a priority queue, then decrement the weight value of that priority queue by 1 and stop polling; among them, during the polling process, when a priority queue with a non-zero weight value has no block number, continue polling to the next priority queue;

[0116] When there is a priority queue with a weight value of 0 in the priority queue group of the destination port and there is a block number for a priority queue with a non-zero weight value, poll the priority queues of the destination port until a priority queue outputs a block number, and decrement the weight value of that priority queue by 1; among them, during the polling process, when polling reaches a priority queue with a weight value of 0, do not output the block number and continue polling to the next priority queue;

[0117] When there is a priority queue with a weight value of 0 in the priority queue group of the destination port, there is a block number for the priority queue with a weight value of 0, and there is no block number for a priority queue with a non-zero weight value, poll the priority queues of the destination port until a priority queue outputs a block number, and the weight value of that priority queue remains unchanged; among them, during the polling process, when polling reaches a priority queue with a weight value of 0, output the block number;

[0118] Among them, after the destination port outputs a block number and receives an output request again, poll the priority queues of the destination port starting from the next priority queue after the priority queue that output the block number last time; continuously poll the priority queues of the destination port until the weight values of all priority queues become 0, then calculate and update the initial weight value of each priority queue for the next cycle, and the calculation formula is as follows:

[0119]

[0120] Among them, K 1 represents the initial weight value for the next cycle, K 0 represents the initial weight value for the current cycle, and n represents the number of times of responding to output requests after the weight value of the priority queue becomes 0 within one cycle;

[0121] Working principle and beneficial effects of the above technical solution: The on-board switching system has 16 switching ports. If each port's queue has 8 priority queues, then there are a total of 128 priority queues. If only the on-board data block numbers are stored in the priority queues, then all these 128 priority queues are virtual output queues (VOQs). Since the on-board data block numbers are stored in the virtual output queues, it can effectively reduce the queue storage resources. In addition, scheduling the numbers (virtual scheduling) is more convenient and efficient than directly scheduling the actual on-board data, greatly reducing the complexity of the scheduling algorithm and improving the efficiency of queue scheduling.

[0122] Determine the multicast count value based on the destination port information. The destination port information consists of 16-bit data. Assuming the destination port information is "0000_0000_0000_0001", the number of "1"s in it determines whether it is unicast or multicast. When there is only 1 "1", then the on-board data is unicast data. When the number of "1"s is greater than 1, then the on-board data is multicast data. At the same time, the position of the "1" in the destination port information also determines which destination ports the on-board data needs to be sent to. For example, "0000_0000_0010_0011" needs to be sent to three destination ports, DP5, DP1, and DP0. The 16 bits in the destination port information represent destination ports DP15, DP14, …, DP1, DP0 in sequence. Use the number of "1"s in the destination port information as the multicast count value to ensure the normal sending of subsequent multicast data.

[0123] In order to improve the quality of service (QoS) of priority queue scheduling, two preset priority queue scheduling algorithms are added to the priority queue module, and one of the preset priority queue scheduling algorithms can be selected for scheduling through the externally input scheduling parameter information. That is, if the scheduling parameter information is the first scheduling parameter, schedule the on-board data according to the strict priority algorithm and priority information. When using the strict priority (SP) scheduling method for scheduling, when receiving the output request of the output processing unit and polling to the corresponding destination port at the same time, the priority queue module selects the block number of the priority queue with the highest priority level for output. For example, when there are on-board data block numbers in multiple priority queues (priority queue 7, priority queue 5, priority queue 2) of a destination port at the same time, directly output the block number of priority queue 7. Since one output request corresponds to one on-board data, the priority queue output may output multiple block numbers.

[0124] If the scheduling parameter information is the second scheduling parameter, the on-board data is scheduled according to the Adaptive Weighted Round Robin (AWRR) algorithm. That is, when there is no priority queue with a weight value of 0 in the priority queue group of the destination port, the priority queues of the destination port are polled until a block number is output from a priority queue, and then the weight value of that priority queue is decreased by 1, and the polling stops. Among them, during the polling process, when a priority queue with a non-zero weight value has no block number, the polling continues to the next priority queue. When there is a priority queue with a weight value of 0 in the priority queue group of the destination port and there are block numbers in the priority queues with non-zero weight values, the priority queues of the destination port are polled until a block number is output from a priority queue, and then the weight value of that priority queue is decreased by 1. Among them, during the polling process, when polling reaches a priority queue with a weight value of 0, no block number is output, and the polling continues to the next priority queue. When there is a priority queue with a weight value of 0 in the priority queue group of the destination port, there are block numbers in the priority queues with a weight value of 0, and there are no block numbers in the priority queues with non-zero weight values, the priority queues of the destination port are polled until a block number is output from a priority queue, and then the weight value of that priority queue remains unchanged. Among them, during the polling process, when polling reaches a priority queue with a weight value of 0, a block number is output. After a scheduling cycle is completed, the number of response output requests after the weight value of the priority queue becomes 0 within a scheduling cycle is counted. The difference between this value and the initial weight value of the corresponding priority queue is obtained as the change amount, which is divided by 4 as the update amount of the corresponding priority queue, and then added to the original weight value as the initial weight value for the next scheduling cycle. The calculation result of the update amount has positive and negative values. A positive value represents that the weight value needs to be increased in the next scheduling cycle, and a negative value represents that the weight value needs to be decreased in the next scheduling cycle. Among them, a scheduling cycle is when the weight values of all priority queues are all decreased to 0.

[0125] The actual situation of scheduling by the Adaptive Weighted Round Robin algorithm is as follows. Suppose the 8 priority queues of a certain destination port are: Priority Queue 7, Priority Queue 6, Priority Queue 5, Priority Queue 4, Priority Queue 3, Priority Queue 2, Priority Queue 1, Priority Queue 0; their initial weight values are set to 3, 2, 1, 2, 1, 2, 2, 1 respectively.

[0126] Suppose there are a large number of block numbers of on-board data simultaneously in all priority queues of the destination port. When an output request for this destination port is received, starting from priority queue 7, if the weight is greater than 0, output the block number of a certain on-board data, and subtract 1 from the weight of priority queue 7; when an output request for this destination port is received again, start from priority queue 6, if the weight is greater than 0, output the corresponding block number, and subtract 1 from its own weight; when an output request for this destination port is received again, start from priority queue 5, if the weight is greater than 0, output the corresponding block number, and subtract 1 from its own weight; when an output request for this destination port is received again, start from priority queue 4, if the weight is greater than 0, output the corresponding block number, and subtract 1 from its own weight; when an output request for this destination port is received again, start from priority queue 3, if the weight is greater than 0, output the corresponding block number, and subtract 1 from its own weight; when an output request for this destination port is received again, start from priority queue 2, if the weight is greater than 0, output the corresponding block number, and subtract 1 from its own weight; when an output request for this destination port is received again, start from priority queue 1, if the weight is greater than 0, output the corresponding block number, and subtract 1 from its own weight; when an output request for this destination port is received again, start from priority queue 0, if the weight is greater than 0, output the corresponding block number, and subtract 1 from its own weight; when an output request for this destination port is received again, start from priority queue 7, if the weight is greater than 0, output the corresponding block number, and subtract 1 from its own weight; when an output request for this destination port is received again, start from priority queue 6, if the weight is greater than 0, output the corresponding block number, and subtract 1 from its own weight; when an output request for this destination port is received again, start from priority queue 5, if the weight is 0, then judge the weight of priority queue 4, if this weight is greater than 0, output the corresponding block number, and subtract 1 from its own weight; when an output request for this destination port is received again, start from priority queue 3, if the weight is 0, then judge the weight of priority queue 2, if this weight is greater than 0, output the corresponding block number, and subtract 1 from its own weight; when an output request for this destination port is received again, start from priority queue 1, if the weight is greater than 0, output the corresponding block number, and subtract 1 from its own weight; when an output request for this destination port is received again, start from priority queue 0, if the weight is found to be 0, then judge the weight of priority queue 7, if this weight is greater than 0, output the corresponding block number, and subtract 1 from its own weight; since the weights of all priority queues are 0, this scheduling cycle ends, and the weights are restored to the initial values; suppose there are no on-board data block numbers in priority queue 7, priority queue 6, priority queue 5, priority queue 4, priority queue 3, priority queue 2, and priority queue 0, and only priority queue 1 (with a weight of 0 and an initial weight value of 2) is responded to. After 8 responses are completed, when this scheduling cycle ends, the initial weight value of priority queue 1 will become 3.

[0127] In one embodiment, the output processing unit is an output processing unit based on the Crossbar architecture. Similar to the current mainstream Crossbar architecture, it adopts the Combined Input and Crosspoint Queued (CICQ) structure. The Crossbar cross-point uses ping-pong FIFOs to cache and read out on-board data. Each cross-point can cache at most the on-board data of two maximum frame lengths. When there is on-board data at the cross-point and the corresponding destination port is enabled, the vertical Crossbar bus will sequentially read the on-board data of the vertical cross-points through fair polling and transmit it to the next-level module. The output scheduling module sends the on-board data to the corresponding mac_t module according to the destination port information of the read on-board data. The mac_t module is responsible for restoring the on-board data and outputting it through the corresponding port.

[0128] In one embodiment, the specific working process of the on-board switching system is as follows:

[0129] The on-board data enters the on-board switching system through 16 write ports. Every four ports are aggregated into one combined data stream. It is determined by the dynamic demultiplexer which combined data streams are sent to the subsequent buffer for storage. The final on-board data is subjected to bit-width conversion to convert it into a 128-bit data stream. At the same time, the destination port and priority information of the on-board data are extracted, and then data block allocation is performed. Data blocks less than 64 Bytes are filled with data. Finally, the data blocks are sent to the queue scheduling buffer module;

[0130] When the queue scheduling buffer module receives the on-board data block, a block number (address information) is assigned to each on-board data block. At the same time, this block number is sent to the corresponding priority queue according to the destination port and priority information. The on-board data block enters the buffer for storage according to the address information. In addition, the multicast count value is calculated according to the destination port information, and the calculated multicast count value is stored in the RAM of the multicast counter with the block number as the storage address;

[0131] The input processing sub-units, with every four ports as a group, respectively represent a group of Crossbar buses (corresponding to four cross nodes horizontally in the Crossbar output matrix). For example, for the on-board data of the 16 destination ports in input processing sub-unit 0, the on-board data with destination ports DP0, DP1, DP2, and DP3 enters cross node M11, the on-board data with destination ports DP4, DP5, DP6, and DP7 enters cross node M12, the on-board data with destination ports DP8, DP9, DP10, and DP11 enters cross node M13, and the on-board data with destination ports DP12, DP13, DP14, and DP15 enters cross node M14;

[0132] When there is an idle cross node horizontally in the Crossbar output matrix, it sends an output request to the queue scheduling module at the previous level. For example, cross node M11 sends an output request to the previous-level queue scheduling module. If there is block number data exactly in the priority queues of destination ports DP0, DP1, DP2, and DP3 in the previous-level priority queue and it happens to be polled to this destination port at the same time, a response signal is given, and the block numbers are scheduled and output according to the preset priority scheduling algorithm. The corresponding on-board data blocks are extracted from the data block buffer area according to the block numbers (address information) and written into cross node M11 to complete an on-board data writing task;

[0133] When reading out the on-board data of the cross node, first, a fair poll is performed on the four cross nodes vertically in the Crossbar output matrix to determine whether there is a data read request for a certain vertical cross node. At the same time, the output scheduling module detects the output status of the corresponding port. If the destination port is idle and there is data in the vertical cross node, the on-board data is sent to the corresponding mac_t module to complete the on-board data restoration process and perform port output; among them, the process of restoring the on-board data block is to delete the padding data added by the data block processing module.

[0134] The present invention also provides a broadband satellite on-board switching method based on multi-port dynamic allocation and shared multi-queues, including the following steps:

[0135] Receive the on-board data of multiple ports and perform cache scheduling on the on-board data;

[0136] Receive the data after cache scheduling and transfer it to the corresponding port for output;

[0137] Receiving the on-board data of multiple ports and performing cache scheduling on the on-board data includes:

[0138] Obtain the on-board data input from the corresponding port and perform detection and multiplexing processing on the on-board data;

[0139] Obtain the cache status and read the on-board data after multiplexing processing, and allocate the on-board data according to the cache status;

[0140] Perform block processing and information extraction on the allocated on-board data to obtain on-board data blocks, destination ports, and priority information;

[0141] Cache and schedule the on-board data according to the destination port and priority information.

[0142] As Figure 8 shown, the present invention also provides a broadband satellite on-board switching device based on multi-port dynamic allocation and shared multi-queues.

[0143] This on-board switching device is implemented based on the XC7VX690T platform and adopts custom FIFO and RAM modules; peripheral conversion devices and on-board devices perform data interaction with the switching unit through GTX transceivers, and each port can support a transmission rate of up to 4.9 Gbps at most; on-board data enters the on-board switching system through 16 input ports, and the internal system clock of the on-board switching system adopts 156.25 MHz; the data of 4 input ports is taken as a group and enters the RAM of an input processing sub-unit for scheduling. Each processing sub-unit represents a bus, and the data bit-width of the bus is 128 bits, and the transmission rate can reach up to 19.5 Gbps at most. The Crossbar network consists of 16 ping-pong FIFOs with a cache resource of 4K to complete the writing and output of on-board data; in the FPGA design, due to the fixed capacity of the BRAM unit block, resource waste is easily caused when instantiating small-capacity RAM / FIFOs; in terms of FPGA deployment of the on-board switching system, custom storage modules are adopted and combined with the on-chip distributed RAM resources at the same time. The storage resource consumption is 30%, the logic resource consumption is 19%, and the timing requirements are met.

[0144] The invention device diagram of the on-board switching system mainly shows the use of some registers, RAM, FIFO and the processing of interfaces. First, the on-board data is input into the on-board switching system through 16 ports P0 - P15. Since high-speed and large-bandwidth data needs to be processed, the GTX resources of FPGA are selected for data processing. At the same time, the GTX input processing module also includes functions consistent with frame check and mac_r. Finally, it is cached in FIFO_0 - FIFO_15 (corresponding to the FIFO of the mac_r module). The subsequent information extraction data processing module is to combine the on-board data, extract information and divide data blocks, corresponding to the dynamic chip selector and data block allocation of the input processing sub-unit. The extracted on-board data blocks, destination ports and priority information will be stored in the corresponding registers. There are 4 groups of registers divided by 4 input processing sub-units. The register control module (queue scheduling module) extracts the on-board data blocks, destination ports and priority information, extracts the block number from the address parameter register (block number queue) and assigns it to the on-board data block. The on-board data block with the assigned block number is then cached in the RAM (data buffer area) waiting for output. When the subsequent Crossbar cross-network (ping-pong FIFO0 - FIFO15, M11 is ping-pong FIFO0, M12 is ping-pong FIFO1, M13 is ping-pong FIFO2, M14 is ping-pong FIFO3, M21 is ping-pong FIFO4, M22 is ping-pong FIFO5, M23 is ping-pong FIFO6, M24 is ping-pong FIFO7, M31 is ping-pong FIFO8, M32 is ping-pong FIFO9, M33 is ping-pong FIFO10, M34 is ping-pong FIFO11, M41 is ping-pong FIFO12, M42 is ping-pong FIFO13, M43 is ping-pong FIFO14, M44 is ping-pong FIFO15) sends an output request, the on-board data block is output. Finally, the output scheduling control module (output scheduling 0 - 3) is responsible for selecting the corresponding destination port, and after the on-board data is restored in the GTX interface output processing module, it is output.

[0145] Meanwhile, the present invention also provides a comparison between this technical solution and the existing system solutions, which is as follows:

[0146] First, as Figure 9As shown in the existing public paper 1 (Wang Fangyuan. Design and Implementation of a 24-Port Spaceborne Switch Based on Crossbar [D]. Xidian University, 2019), the spaceborne switch is realized by integrating Crossbar switching with the partial buffer sharing (PBS) structure, featuring multiple ports, high speed, and large capacity. Since the spaceborne switch serves as the backbone network of the space-ground integrated network, it not only needs to meet the requirements of speed and capacity but also has very high latency requirements. The crossbar matrix characteristic can solve the internal blocking problem, so each port on the bus can work at full speed, thus greatly improving the transmission rate and switching capacity and making high-speed and large-capacity switching possible. The entire switching unit uses a system clock of 156.25 MHz, the bus bit width is 64 bits, the maximum bus rate is 9.7 Gbps, there are 24 ports in total, the transmission rate of each port reaches 1.2 Gbps, and the switching capacity reaches 28.8 Gbit;

[0147] The existing public paper 2 (Zhang Xiaowen. Design and Implementation of the Switching Unit of a High-Speed Spaceborne Router [D]. Xidian University, 2021) designed a high-speed spaceborne router based on the shared buffer structure. Combining typical queue scheduling algorithms with project requirements, it proposed a fair arbitration round-robin algorithm (Round Robin, RR) based on output port status feedback and a deficit weighted round-robin algorithm (Deficit Weighted Round Robin, DWRR) based on priority, and completed the design and implementation of a multi-level queue scheduling scheme by introducing the token bucket algorithm. The bus bit width of the data switching unit is 80 bit, the clock of the switching unit is 156.25 MHz, and the maximum bus rate can reach 12.2 Gbps;

[0148] As shown in Table 1 (Comparison Table of Resources and Performance of Spaceborne Switching Systems), both the above-mentioned Paper 1 and Paper 2 are spaceborne switching systems designed using XC7VX690T chips; compared with Paper 1 and Paper 2, the technical solution of the present invention (taking 16 ports as an example for comparison) first reduces the occupancy rate of chip storage resources in terms of storage resources because the design of the present invention is to set up custom RAM and FIFO storage units and utilize the on-chip distributed RAM resources, while reducing the block number bit width and simplifying the scheduling strategy; since the system of the present invention uses a high-bit-width spaceborne data stream for transmission scheduling internally, the bus rate is relatively high; compared with the above two technical solutions, it is superior in terms of switching rate and switching capacity; at the same time, the system of the present invention adds a dynamic adjustment strategy, which can perform multi-queue dynamic allocation of spaceborne data according to the cache state and the idle time of the spaceborne data multiplexing processing module of the input processing sub-unit, improving the system switching efficiency; the present invention internally records the multicast count value of spaceborne data, ensuring the normal transmission of multicast spaceborne data without additional resources; compared with the first two solutions, the present invention adds an adaptive weighted scheduling algorithm to the queue scheduling algorithm, effectively improving the quality of service of queue scheduling by adaptively adjusting the weight values of the priority queues;

[0149] Table 1 Comparison Table of Resources and Performance of Spaceborne Switching Systems

[0150]

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A broadband satellite onboard switching system based on multi-port dynamic allocation and sharing of multiple queues, characterized in that: include: An input processing unit, used for receiving satellite data from multiple ports and performing cache scheduling on the satellite data; The output processing unit is used to receive the output data of the input processing unit and transmit it to the corresponding port for output; The input processing unit includes several input processing sub-units, and the input processing sub-units include: a satellite data combining processing module, a multi-port dynamic allocation shared multi-queue module, a data block processing module and a queue cache scheduling module; The satellite data combining processing module is used to obtain the satellite data input from the corresponding port, detect the satellite data, and combine the satellite data of several ports through fair polling; The multi-port dynamic allocation shared multi-queue module is used to obtain the cache status and read the onboard data after the onboard data combining processing module, and allocate the onboard data according to the cache status; A data block processing module is used to perform block processing and information extraction on the allocated satellite data to obtain satellite data blocks, destination ports and priority information; A queue cache scheduling module is used to cache and schedule onboard data according to the destination port and priority information; The multi-port dynamic allocation shared multi-queue module performs the following operations: Read the combined satellite data output from the previous satellite data combining processing module; Obtaining the cache status of the data block cache area of ​​the input processing subunit where the multi-port dynamic allocation shared multi-queue module is located, and the idle time of the onboard data combining processing module of other input processing subunits; wherein the cache status includes: unable to continue to store and able to continue to store; When there is an input processing subunit whose idle time is greater than a preset idle time, the satellite-borne data is sent to the input processing subunit for processing; When there is no input processing subunit whose idle time is greater than the preset idle time, it is determined whether to send the onboard data to other input processing subunits for processing according to the cache status; if the cache status is that it cannot continue to be stored, the onboard data is sent to other input processing subunits for processing; if the cache status is that it can continue to be stored, the onboard data is not sent to other input processing subunits for processing.

2. The broadband satellite onboard switching system based on multi-port dynamic allocation and sharing of multiple queues as claimed in claim 1, characterized in that: Onboard data combining and processing module, including several modules and fair pollers; The satellite data combining and processing module performs the following operations: The mac_r module obtains the satellite data input from the corresponding port, and performs frame header detection on the satellite data to determine whether the frame header of the satellite data conforms to the preset format; if not, the satellite data is discarded; If it is in compliance, perform CRC check and frame length detection on the satellite data to determine whether the CRC check result and data length conform to the preset format; if it is not in compliance, discard the satellite data; If it matches, cache the satellite data to In the module; The fair poller reads the satellite data in the mac_r module in turn in a fair polling manner to obtain the combined satellite data.

3. The broadband satellite onboard switching system based on multi-port dynamic allocation and sharing of multiple queues as claimed in claim 1, characterized in that: The data block processing module performs the following operations: Perform bit width conversion and information extraction on the satellite data to obtain the converted data stream, destination port and priority information; The converted data stream is processed into blocks to obtain onboard data blocks.

4. The broadband satellite onboard switching system based on multi-port dynamic allocation and sharing of multiple queues as claimed in claim 1, characterized in that: A queue cache scheduling module, including: a data block cache area, a multicast counter, a block number queue, a queue scheduling module and a priority queue; A block number queue, used to assign block numbers to onboard data blocks input to the queue scheduling module; The queue scheduling module is used to control the data block buffer area to cache the received satellite data blocks, and when receiving the read request of the output processing unit, schedule the output of the satellite data blocks; The data block buffer is used to store the satellite data blocks, and when receiving the output instruction of the queue scheduling module, it outputs the satellite data block with the corresponding block number; The priority queue module is used to store block numbers according to the destination port and priority information. When receiving the output instruction of the queue scheduling module, the block number in a priority queue corresponding to the destination port is selected for output according to the scheduling strategy. Among them, the priority queue module has priority queue groups corresponding to the number of destination ports, and each priority queue group is composed of 8 different priority queues; each priority queue is set with an initial weight value.

5. The broadband satellite onboard switching system based on multi-port dynamic allocation and sharing of multiple queues as claimed in claim 4, characterized in that: The queue scheduling module performs the following operations: When receiving the onboard data block, determining a multicast count value based on the destination port information; The control block number queue assigns a block number to each satellite data block, sends the satellite data block to the data block buffer area according to the address corresponding to the block number for storage, sends the assigned block number to the priority queue module for storage, and sends the multicast count value to the multicast counter for storage; When receiving the output request of the output processing unit, and at the same time fairly polling the corresponding destination port, obtaining the external input scheduling parameter information, selecting the preset priority queue scheduling algorithm to schedule the stored block number according to the scheduling parameter information, and issuing an output instruction to the data block buffer area, controlling the data block buffer area to output the onboard data block of the corresponding block number; The multicast count value corresponding to the block number stored in the multicast counter is controlled to be reduced by 1; wherein, when the multicast count value corresponding to the block number stored in the multicast counter becomes 0, the block number is recycled to the block number queue.

6. The broadband satellite onboard switching system based on multi-port dynamic allocation and sharing of multiple queues as claimed in claim 5, characterized in that: The scheduling parameter information includes: a first scheduling parameter and a second scheduling parameter; the preset priority queue scheduling algorithm includes: a strict priority and an adaptive weighted scheduling algorithm; Obtain external input scheduling parameter information, and select a preset priority queue scheduling algorithm to schedule the stored block number according to the scheduling parameter information, including: If the scheduling parameter information is the first scheduling parameter, scheduling the onboard data according to the strict priority algorithm and the priority information; If the scheduling parameter information is the second scheduling parameter, the satellite-borne data is scheduled according to an adaptive weighted scheduling algorithm.

7. The broadband satellite onboard switching system based on multi-port dynamic allocation and sharing of multiple queues as claimed in claim 6, characterized in that: The satellite data is scheduled according to the adaptive weighted scheduling algorithm, including: When there is no priority queue with a weight value of 0 in the priority queue group of the destination port, the priority queue of the destination port is polled until the priority queue outputs a block number, the weight value of the priority queue is reduced by 1, and the polling is stopped; wherein, during the polling process, when the priority queue with a weight value not 0 has no block number, the polling continues to the next priority queue; When the priority queue group of the destination port has a priority queue with a weight value of 0, and the priority queue with a weight value other than 0 has a block number, the priority queues of the destination port are polled until a priority queue outputs a block number, and the weight value of the priority queue is reduced by 1; wherein, during the polling process, when the priority queue with a weight value of 0 is polled, the block number is not output, and the next priority queue is polled; When the priority queue group of the destination port has a priority queue with a weight value of 0, and the priority queue with a weight value of 0 has a block number, and the priority queue with a weight value other than 0 does not have a block number, the priority queues of the destination port are polled until a priority queue outputs a block number, and the weight value of the priority queue remains unchanged; wherein, during the polling process, when the priority queue with a weight value of 0 is polled, the block number is output; Among them, after the destination port outputs the block number, when an output request is received again, the priority queue of the destination port is polled, starting from the next priority queue of the priority queue that output the block number last time; the priority queue of the destination port is continuously polled until the weight values ​​of all priority queues become 0, and the initial weight value of each priority queue in the next cycle is calculated and updated. The calculation formula is as follows: in, represents the initial weight value of the next cycle, Indicates the initial weight value of the current period, Indicates the number of response output requests after the priority queue's weight value becomes 0 within a cycle.

8. A broadband satellite onboard switching method based on multi-port dynamic allocation and sharing of multiple queues, characterized in that: The broadband satellite onboard switching system based on multi-port dynamic allocation and sharing of multiple queues as described in any one of claims 1 to 7 comprises the following steps: Receive satellite data from multiple ports and perform cache scheduling on the satellite data; Receive the data after cache scheduling and pass it to the corresponding port for output; Receive multi-port satellite data and perform cache scheduling on the satellite data, including: Obtain the satellite data input from the corresponding port, and perform detection and combination processing on the satellite data; Obtain the cache status and read the onboard data after the combined processing, and distribute the onboard data according to the cache status, including: Read the satellite data after combining processing; Acquire the cache status of the data block cache area of ​​the current input processing subunit and the idle time of other input processing subunits during the merging process, wherein the cache status includes being unable to continue to store and being able to continue to store; When there is an input processing subunit whose idle time is greater than a preset idle time, the satellite-borne data is sent to the input processing subunit for processing; When there is no input processing subunit whose idle time is greater than the preset idle time, it is determined whether to send the onboard data to other input processing subunits for processing according to the cache status: if the cache status indicates that the data cannot be stored any more, the onboard data is sent to other input processing subunits for processing; if the cache status indicates that the data can be stored any more, the onboard data is not sent to other input processing subunits for processing; Perform block processing and information extraction on the allocated satellite data to obtain satellite data blocks, destination ports and priority information; The onboard data is cached and scheduled according to the destination port and priority information.

9. A broadband satellite onboard switching device based on multi-port dynamic allocation and sharing of multiple queues, characterized in that: Used to implement the broadband satellite onboard switching system based on multi-port dynamic allocation and sharing of multiple queues as described in claim 1.

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