Cumulative probability density distribution statistical loop circuit

Abstract

The present invention discloses a cumulative probability density distribution statistical loop circuit, belonging to the field of wireless communications. The circuit extracts the envelope signal of a radio frequency signal through a peak detection module; compares the feedback output voltage and the envelope signal through a cumulative probability density comparison module to obtain a probability density signal; then, in a cumulative probability density quantization module, obtains a cumulative probability density quantized voltage signal; finally, in a cumulative probability density voltage generation module, the output voltage of the circuit is regulated based on the cumulative probability density quantized voltage signal; furthermore, a lock detection module outputs a lock signal to stabilize the output voltage; and a control signal generation module generates a control signal throughout the entire operation process. The present invention is implemented using an analog circuit and has the advantages of a simple structure, low power consumption, and a wide applicable frequency band, making it suitable for amplitude alignment of various signals.

Description

Technical Field

[0001] The invention belongs to the field of wireless communications, and in particular relates to a cumulative probability density distribution statistical loop circuit. Background Art

[0002] With the development of science and technology and the Internet, people have higher demands on the data volume and transmission rate of information transmitted by wireless communication systems. Increasing the data rate and spectrum utilization will lead to an increase in the bandwidth and peak-to-average ratio of the signal, causing serious nonlinear distortion in the power amplifier. In order to improve the quality of the output signal of the power amplifier and evaluate the distortion of the signal after amplification, it is generally necessary to compare the input and output signals at the same level, that is, to align the amplitudes of the input and output signals.

[0003] Currently, common signal amplitude alignment methods include maximum-minimum alignment and power alignment. Maximum-minimum alignment normalizes the signal using the maximum and minimum values ​​of the signal swing as a reference. Power alignment normalizes the signal by averaging all the signal energy to obtain a reference amplitude value. These two methods are widely used in error analysis of adaptive predistortion circuits and in controlling PAPR (peak-to-average ratio) in OFDM (orthogonal frequency division multiplexing) systems.

[0004] However, the above two methods are generally implemented using digital algorithms, and there are no public reports on their direct circuit implementation. Therefore, finding a method that is simple to implement and has good normalization effect is an important research topic in circuit signal preprocessing amplitude alignment. Summary of the Invention

[0005] Aiming at the problem of signal amplitude alignment in signal preprocessing, the present invention proposes a cumulative probability density distribution statistical loop circuit.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] A cumulative probability density distribution statistical loop circuit is characterized by comprising a peak detection module, a cumulative probability density comparison module, a cumulative probability density quantization module, a cumulative probability density voltage generation module, a control signal generation module, and a lock detection module.

[0008] The peak detection module is used to perform envelope peak detection on the input radio frequency signal, amplify the amplitude of the envelope signal obtained by detection, and then output the amplified envelope signal to the cumulative probability density comparison module.

[0009] The cumulative probability density comparison module is used to receive the envelope signal input by the peak detection module and the cumulative probability density voltage signal input by the cumulative probability density voltage generation module, and compare the two received signals to obtain a probability density signal, and output the probability density signal to the cumulative probability density quantization module; the probability density signal carries the probability information that the envelope signal is distributed below the cumulative probability density voltage value.

[0010] The cumulative probability density quantization module is used to generate the switching signal V PULSE1 and the switching signal V RESET Under the control of , the voltage information of the input probability density signal is extracted to obtain a cumulative probability density quantized voltage signal (the voltage value of the voltage signal is linearly related to the probability density value of the envelope signal obtained by the peak detection of the RF signal, that is, the probability density of the envelope signal is mapped to a specific voltage value), and the cumulative probability density quantized voltage signal is output to the cumulative probability density voltage generation module.

[0011] The cumulative probability density voltage generating module is used to receive the cumulative probability density quantized voltage value signal and the switch signal V PULSE2 , lock signal LOCK; generate a control voltage signal according to the cumulative probability density quantized voltage signal, and send it to the lock detection module; at the same time, according to the control voltage signal, the switch signal V PULSE2 and the lock signal LOCK, generating the output voltage V out The output voltage is also fed back to the cumulative probability density comparison module as a cumulative probability density voltage value signal.

[0012] The control signal generating module is used to generate a control signal for the circuit, and the control signal includes a switch signal V PULSE1 , switching signal V PULSE1 , switching signal V RESET ; Wherein, the switching signal V PULSE1 , used to control the start and stop integration of the cumulative probability density quantization module; the switch signal V PULSE2 , used to control the working state of the cumulative probability density voltage generating module; the control signal V RESET , used to control the reset of the cumulative probability density quantization module and return to the initial state.

[0013] The lock detection module is used to generate a lock signal LOCK according to the received control voltage signal and send the lock signal LOCK to the cumulative probability density voltage generation module.

[0014] Preferably, the peak detection module is composed of an RC peak detection circuit and a common source amplifier circuit connected in series.

[0015] Preferably, the control signal generating module is composed of a voltage controlled oscillator (VCO), a time delay device and a phase frequency detector (PFD); the voltage controlled oscillator is used to generate a switching signal V PULSE1 And sent to the cumulative probability density quantization module, the time delay device and the frequency phase detector; the time delay device converts the switching signal V PULSE1 Perform time delay to obtain the switching signal V RESET And sent to the cumulative probability density quantization module and the frequency detector; the frequency detector, the switching signal V PULSE1 and the switching signal V RESET Perform frequency and phase discrimination to generate a switching signal V PULSE2 And sent to the cumulative probability density voltage generation module.

[0016] Preferably, the cumulative probability density comparison module is composed of a first comparator and an inverter connected in series; the input of the first comparator is an envelope signal and a cumulative probability density voltage signal, and the output is a square wave signal; this square wave signal reflects the probability density of the envelope signal input by the peak detection module during this observation time relative to the cumulative probability density voltage value signal output by the overall circuit, that is, the probability that the envelope signal is distributed above the circuit output voltage during this period; the inverter is used to invert the square wave signal to obtain a probability density signal; the high level time of this probability density signal reflects the probability that the envelope signal is distributed below the circuit output voltage during this period.

[0017] Preferably, the cumulative probability density quantization module includes a capacitor C STA , constant current source, first switch, second switch, third switch;

[0018] The capacitor C STA One end of the circuit is grounded, and the other end is connected to three branches; wherein the first branch is grounded through the second switch, the second branch is connected to the constant current source through the third switch, and the third branch serves as the output end of the cumulative probability density quantization module;

[0019] The on / off state of the first switch is determined by the switch signal V PULSE1 Control; the opening and closing state of the second switch is controlled by the switch signal V RESET Control; the on-off state of the third switch is controlled by the probability density signal, and the probability density signal is input to the third switch through the first switch.

[0020] When the first switch and the third switch are closed, the capacitor C STA Start charging, so that the cumulative probability density quantized voltage value begins to integrate; when the second switch is closed, the capacitor C STA Discharge to clear the cumulative probability density quantization voltage value to zero.

[0021] Preferably, the cumulative probability density voltage generating module includes a second comparator, a charge pump, a capacitor C OUT , fourth switch, fifth switch; the input of the second comparator is the cumulative probability density quantized voltage signal and the preset reference probability density quantized voltage signal, and the output is a control voltage signal; the control voltage signal is input to the charge pump; the output end of the charge pump is connected to the circuit output end through the fourth switch and the fifth switch in series, and the capacitor C OUT Charge and discharge; the capacitor C OUT One end is connected to the node between the fifth switch and the circuit output terminal, and the other end is grounded; the on / off state of the fourth switch is determined by the switch signal V PULSE2 Control; the off state of the fifth switch is controlled by the lock signal LOCK; by controlling the on and off states of the fourth and fifth switches, thereby controlling the output voltage V of the circuit out .

[0022] Preferably, the lock detection module includes four D flip-flops cascaded in sequence; wherein, the R ports of the four D flip-flops are all input with the same reset signal; the C port of the first D flip-flop is input with the control voltage signal, and the C ports of the other three D flip-flops are connected to the Q ports of the preceding D flip-flops; the D port of the fourth flip-flop is connected to a high level, and at the same time, the Q port of the fourth flip-flop outputs a lock signal LOCK. When the lock detection module detects that the input control voltage signal has eight rising edges (i.e., the probability that the envelope signal is distributed below the final output voltage eight times is higher than the expected probability density), the lock signal is switched from a low level to a high level, the fifth switch is controlled to be disconnected, and the output voltage V of the cumulative probability density voltage generation module is locked. out When the lock detection module detects that the input reset signal is low, the lock signal is switched from high to low, the fifth switch is controlled to close, and the output voltage V of the cumulative probability density voltage generating module is adjusted. out .

[0023] Beneficial effects of the present invention:

[0024] The present invention extracts the envelope signal of the input radio frequency signal through a peak detection module; compares the output voltage fed back by the current circuit with the envelope signal through a cumulative probability density comparison module to obtain a signal reflecting the probability density of the envelope signal relative to the output voltage of the final circuit (cumulative probability density voltage signal) during this observation time; inputs this probability density signal into a cumulative probability density quantization module to obtain a cumulative probability density quantized voltage signal; the cumulative probability density voltage generation module regulates the output voltage of the circuit according to the cumulative probability density quantized voltage signal; in addition, the lock detection module outputs a lock signal to the cumulative probability density voltage generation module after the output voltage of the circuit reaches the requirement, indicating that the entire circuit has reached stability; and the control signal generation module generates the control signal required for the entire working process of the circuit.

[0025] The present invention is implemented by an analog circuit. Compared with digital amplitude alignment, this circuit has the advantages of simple structure, low power consumption, and applicable bandwidth. It can be applied to the amplitude alignment of various signals, including but not limited to the circuit amplitude alignment of radio frequency power amplifiers, antenna arrays, and radar signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Overall structural block diagram of the cumulative probability density statistics loop system.

[0027] Figure 2 Schematic diagram of the control signal generation module structure.

[0028] Figure 3 Time domain waveform of the control signal generated by the control signal generating module.

[0029] Figure 4 Schematic diagram of the cumulative probability density quantization module structure.

[0030] Figure 5 The signal time domain waveform when the cumulative probability density quantization module is working.

[0031] Figure 6 Schematic diagram of the signal time domain waveform when the cumulative probability density voltage generation module is working.

[0032] Figure 7 Schematic diagram of the lock detection module structure.

[0033] Figure 8 The signal time domain waveform when the lock detection module is working.

[0034] Figure 9 Virtuoso outputs simulation results after providing parameters. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below in conjunction with the implementation methods and drawings.

[0036] A cumulative probability density distribution statistics loop circuit of this embodiment, Figure 1 As shown, it includes a peak detection module, a cumulative probability density comparison module, a cumulative probability density quantization module, a cumulative probability density voltage generation module, a control signal generation module, and a lock detection module.

[0037] The peak detection module is composed of an RC peak detection circuit and a common source amplifier circuit in series, which is used to perform envelope peak detection on the input RF signal and amplify the amplitude of the envelope signal obtained by detection, and then convert the amplified envelope signal V SIGN Output to the Cumulative Probability Density Comparison module.

[0038] The cumulative probability density comparison module is composed of a first comparator and an inverter connected in series; the input of the first comparator is the envelope signal and the cumulative probability density voltage signal, and the output is a square wave signal; this square wave signal reflects the probability density of the envelope signal input by the peak detection module during this observation period relative to the cumulative probability density voltage value signal output by the entire circuit, that is, the probability that the envelope signal is distributed above the circuit output voltage during this period; the inverter is used to invert the square wave signal to obtain the probability density signal V COM ; This probability density signal is input to the cumulative probability density quantization module, and the high level time reflects the probability that the envelope signal is distributed below the circuit output voltage during this period of time.

[0039] The cumulative probability density quantization module is used to extract the input probability density signal V under the control of the control signal. COM The voltage information is obtained to obtain the cumulative probability density quantized voltage signal V STA And output to the cumulative probability density voltage generation module.

[0040] like Figure 4 As shown, the cumulative probability density quantization module includes a capacitor C STA , constant current source, first switch, second switch, third switch; wherein, the capacitor C STA One end of the circuit is grounded, and the other end is connected to three branches; the first branch is grounded through the second switch, the second branch is connected to the constant current source through the third switch, and the third branch serves as the output end of the cumulative probability density quantization module.

[0041] The on / off state of the first switch is determined by the switch signal V PULSE1 Control; the opening and closing state of the second switch is controlled by the switch signal V RESET Control; the on-off state of the third switch is determined by the probability density signal V COMControl, and the probability density signal is input to the third switch through the first switch.

[0042] like Figure 5 As shown, when the switching signal V PULSE1 is low, the first switch is closed, making the probability density signal V COM Input to the third switch; probability density signal V COM The high level triggers the third switch to close, so that the capacitor C STA Charging begins, the cumulative probability density quantized voltage value begins to integrate, and the low level triggers the third switch to open, making the capacitor C STA Stop charging, and the cumulative probability density quantized voltage value stops integrating. PULSE1 is high, the first switch is disconnected, and the probability density signal V COM The third switch cannot be triggered to close, i.e. the capacitor C STA Stop charging. During the integration process, when the switch signal V RESET Switched to high level, the second switch is closed, so that the capacitor C STA Discharge, the cumulative probability density quantization voltage value is cleared.

[0043] The voltage value of the cumulative probability density quantized voltage signal is linearly related to the probability density value of the envelope signal obtained by peak detection of the RF signal. The high-level time in the envelope signal is mapped to a specific voltage value through the cumulative probability density quantization module.

[0044] The cumulative probability density voltage generating module is used to receive the cumulative probability density quantized voltage value signal V STA , switching signal V PULSE2 , lock signal LOCK; generate a control voltage signal according to the cumulative probability density quantized voltage signal, and send it to the lock detection module; at the same time, according to the control voltage signal, the switch signal V PULSE2 and the lock signal LOCK, generating the output voltage V out The output voltage is also fed back to the cumulative probability density comparison module as a cumulative probability density voltage value signal.

[0045] The cumulative probability density voltage generating module is as follows: Figure 1 As shown, it includes a second comparator, a charge pump, a capacitor C OUT , a fourth switch, and a fifth switch. Wherein, the input of the second comparator is the cumulative probability density quantized voltage signal V STA and the preset reference probability density quantized voltage signal V REF , the output is the control voltage signal V COM2 ; The control voltage signal V COM2Input to the lock detection module and the charge pump. The output end of the charge pump is connected to the circuit output end through the fourth switch and the fifth switch connected in series; the capacitor C OUT One end is connected to the node between the fifth switch and the circuit output terminal, and the other end is grounded; the on / off state of the fourth switch is determined by the switch signal V PULSE2 Control; the off state of the fifth switch is controlled by the lock signal LOCK; by controlling the on and off states of the fourth and fifth switches, thereby controlling the output voltage V of the circuit out , the output voltage V out At the same time, it is fed back to the cumulative probability density comparison module as a cumulative probability density voltage value signal.

[0046] like Figure 6 As shown, when the switching signal V PULSE2 is high, the lock signal LOCK is low, then the fourth switch and the fifth switch are closed; at this time, when the cumulative probability density quantized voltage signal V STA Less than the preset reference probability density quantized voltage signal V REF , control voltage signal V COM2 is low, the charge pump is OUT Charging is performed when the cumulative probability density quantizes the voltage signal V STA Greater than the preset reference probability density quantized voltage signal V REF , control voltage signal V COM2 If high, the charge pump will OUT Discharge; when the switch signal V PULSE2 When the lock signal LOCK is at a low level, or the lock signal LOCK is at a high level, the fourth switch or the fifth switch is disconnected, and the capacitor C OUT Keep stable, that is, the output voltage V out Stay stable.

[0047] The control signal generating module is as follows: Figure 2 As shown, it consists of a voltage controlled oscillator (VCO), a time delay device and a phase frequency detector (PFD); the voltage controlled oscillator is used to generate a switching signal V PULSE1 And sent to the cumulative probability density quantization module, the time delay device and the frequency phase detector; the time delay device converts the switching signal V PULSE1 Perform time delay to obtain the switching signal V RESET And sent to the cumulative probability density quantization module and the frequency detector; the frequency detector, the switching signal V PULSE1 and the switching signal V RESET Perform frequency and phase discrimination to generate a switching signal V PULSE2 And sent to the cumulative probability density voltage generation module.

[0048] Switching signal V PULSE1 , switching signal VRESET , switching signal V PULSE2 The time domain waveform is as follows Figure 3 As shown, the voltage controlled oscillator generates a switching signal V PULSE1 , switching signal V RESET is the switching signal V PULSE1 The signal after the delay of the delay device, the switch signal V PULSE2 is the switching signal V PULSE1 and the switching signal V RESET After the frequency and phase detection signal. When the switch signal V PULSE1 is low level, the switch signal V PULSE2 is low level, that is, the cumulative probability density quantized voltage value integral (V PULSE1 is low), the fourth switch is disconnected, making the output voltage V out Keep stable; when the switching signal V PULSE1 is high level, the switching signal V PULSE2 At the same time, the fourth switch will be closed, that is, when the cumulative probability density quantized voltage signal V STA When the integration stops and reaches stability, the cumulative probability density voltage generation module will quantize the cumulative probability density voltage value V STA The reference probability density quantized voltage value V REF Compare and get the control voltage signal V COM2 ; When the preset time (delay time) has passed, the switch signal V RESET becomes high level, initializes the cumulative probability density quantization module, and at the same time the frequency detector and phase detector make the switching signal V PULSE2 turns to low level, disconnecting the fourth switch and making the output voltage V out Keep steady for the next observation.

[0049] The lock detection module is used to generate a lock signal LOCK according to the received control voltage signal and send it to the cumulative probability density voltage generation module. Figure 7 As shown, it includes 4 D flip-flops cascaded in sequence; wherein, the R ports of the 4 D flip-flops all input the same reset signal RET_LOCK; the C port of the first D flip-flop inputs the control voltage signal V COM2 , the C ports of the other three D flip-flops are connected to the Q ports of the previous D flip-flops; the D port of the fourth flip-flop is connected to a high level, and at the same time, the Q port of the fourth flip-flop outputs a lock signal LOCK. Figure 8 As shown in FIG, when the lock detection module detects that the input control voltage signal has 8 rising edges (i.e., the probability that the envelope signal is distributed below the final output voltage 8 times is higher than the expected probability density), the lock signal is switched from low level to high level, the fifth switch is controlled to be disconnected, and the output voltage V of the cumulative probability density voltage generating module is locked.out When the lock detection module detects that the input reset signal RET_LOCK is low, the lock signal is switched from high to low, the fifth switch is controlled to close, and the output voltage V of the cumulative probability density voltage generating module is adjusted. out .

[0050] The principle of cumulative probability density quantization module is: fixed observation time t, charging current I, capacitance value C, according to The voltage on the capacitor can be obtained where t h is the signal V entering the quantization circuit COM The total time of high level in one observation cycle, and the 100% probability density quantized voltage value is the value when the constant current source continuously supplies the capacitor C under the condition that the signal is always high level in one observation cycle. STA Voltage value after charging Then the voltage value V quantified by the expected probability density of the circuit is REF You can use V full Calculate (for example, if 80% probability density is required, set the voltage to 0.8V full ), V REF Input the actual voltage V quantized by the AND circuit in the second comparator STA By comparing, we can determine whether the probability density of the circuit's current signal distribution below the output voltage is the expected probability density.

[0051] When the cumulative probability density voltage generation module is working, the cumulative probability density quantized voltage value V STA When it is not stable (i.e., the probability of the RF envelope signal being distributed below the final output voltage of the device does not reach the expected probability density), the fifth switch controlled by the control signal LOCK output by the lock detection module always remains closed; the control voltage signal V output by the comparator in the cumulative probability density voltage generation module is used to generate the control voltage signal V. COM2 Control the charge pump to the capacitor C OUT During this process, if the control voltage signal V COM2 If the voltage is low, it means that the probability of the RF envelope signal being distributed below the final output voltage of the device does not reach the expected probability density, and a charge pump is needed to charge the capacitor C. OUT Charging, increasing the output voltage V out ; If the control voltage signal V COM2 If the voltage is high, it means that the probability of the RF envelope signal being distributed below the final output voltage of the device is higher than the expected probability density, and a charge pump is needed to charge the capacitor C. OUT Discharge, reduce V out voltage, and finally stabilize the output voltage at the required probability density value; the output voltage V outAfter stabilization, the lock signal LOCK becomes high level to control the fifth switch to be disconnected, locking the output voltage V out , the output voltage of the circuit is V out The voltage waveform results are as follows Figure 9 The error relative to the theoretical probability density error is shown in Table 1.

[0052] Table 1

[0053] Theoretical probability density (%) Loop stability probability density output (%) error 90 90.75-93.83 3.83％ 75 75.29-77.29 2.29％ 60 62.27-63.93 3.93％ 50 51.90-53.56 3.56％

Claims

1. A cumulative probability density distribution statistical loop circuit, characterized in that: It includes a peak detection module, a cumulative probability density comparison module, a cumulative probability density quantization module, a cumulative probability density voltage generation module, a control signal generation module, and a lock detection module; The peak detection module is used to perform envelope peak detection on the input radio frequency signal, amplify the amplitude of the envelope signal obtained by detection, and then output the amplified envelope signal to the cumulative probability density comparison module; The cumulative probability density comparison module is used to receive the envelope signal input by the peak detection module and the cumulative probability density voltage signal input by the cumulative probability density voltage generation module, compare the two received signals to obtain a probability density signal, and output the probability density signal to the cumulative probability density quantization module; the probability density signal carries probability information that the envelope signal is distributed below the cumulative probability density voltage value; The cumulative probability density quantization module is used to generate the switching signal V PULSE1 and the switching signal V RESET Under the control of , extracting the voltage information of the input probability density signal to obtain a cumulative probability density quantized voltage signal, and outputting the cumulative probability density quantized voltage signal to the cumulative probability density voltage generating module; The cumulative probability density voltage generating module is used to receive the cumulative probability density quantized voltage value signal and the switch signal V PULSE2 , lock signal LOCK; generate a control voltage signal according to the cumulative probability density quantized voltage signal, and send it to the lock detection module; at the same time, according to the control voltage signal, the switch signal V PULSE2 and the lock signal LOCK, generating the output voltage V out , the output voltage is also fed back to the cumulative probability density comparison module as a cumulative probability density voltage value signal; The control signal generating module is used to generate a control signal for the circuit, and the control signal includes a switch signal V PULSE1 , switching signal V PULSE2 , switching signal V RESET ; Wherein, the switching signal V PULSE1 , used to control the start and stop integration of the cumulative probability density quantization module; the switch signal V PULSE2 , used to control the working state of the cumulative probability density voltage generating module; the control signal V RESET , used to control the reset of the cumulative probability density quantization module and return to the initial state; The lock detection module is used to generate a lock signal LOCK according to the received control voltage signal and send it to the cumulative probability density voltage generation module to lock the output voltage V out .

2. A cumulative probability density distribution statistics loop circuit as claimed in claim 1, characterized in that: The control signal generating module is composed of a voltage controlled oscillator, a time delay device and a frequency and phase detector; the voltage controlled oscillator is used to generate a switching signal V PULSE1 And sent to the cumulative probability density quantization module, the time delay device and the frequency phase detector; the time delay device converts the switching signal V PULSE1 Perform time delay to obtain the switching signal V RESET And sent to the cumulative probability density quantization module and the frequency detector; the frequency detector, the switching signal V PULSE1 and the switching signal V RESET Perform frequency and phase discrimination to generate a switching signal V PULSE2 And sent to the cumulative probability density voltage generation module.

3. A cumulative probability density distribution statistics loop circuit as claimed in claim 2, characterized in that: The cumulative probability density quantization module includes a capacitor C STA , constant current source, first switch, second switch, third switch; The capacitor C STA One end of the circuit is grounded, and the other end is connected to three branches; wherein the first branch is grounded through the second switch, the second branch is connected to the constant current source through the third switch, and the third branch serves as the output end of the cumulative probability density quantization module; The on / off state of the first switch is determined by the switch signal V PULSE1 Control; the opening and closing state of the second switch is controlled by the switch signal V RESET control; the on / off state of the third switch is controlled by the probability density signal, and the probability density signal is input to the third switch through the first switch; When the first switch and the third switch are closed, the capacitor C STA Start charging, so that the cumulative probability density quantized voltage value begins to integrate; when the second switch is closed, the capacitor C STA Discharge to clear the cumulative probability density quantization voltage value to zero.

4. A cumulative probability density distribution statistics loop circuit as claimed in claim 3, characterized in that: The cumulative probability density voltage generation module includes a second comparator, a charge pump, a capacitor C OUT , fourth switch, fifth switch; the input of the second comparator is the cumulative probability density quantized voltage signal and the preset reference probability density quantized voltage signal, and the output is a control voltage signal; the control voltage signal is input to the charge pump; the output end of the charge pump is connected to the circuit output end through the fourth switch and the fifth switch in series, and the capacitor C OUT Charge and discharge; the capacitor C OUT One end is connected to the node between the fifth switch and the circuit output terminal, and the other end is grounded; the on / off state of the fourth switch is determined by the switch signal V PULSE2 Control; the off state of the fifth switch is controlled by the lock signal LOCK; by controlling the on and off states of the fourth and fifth switches, thereby controlling the output voltage V of the circuit out .

5. A cumulative probability density distribution statistics loop circuit as claimed in claim 4, characterized in that: The cumulative probability density comparison module is composed of a first comparator and an inverter connected in series; the input of the first comparator is an envelope signal and a cumulative probability density voltage signal, and the output is a square wave signal; this square wave signal reflects the probability density of the envelope signal input by the peak detection module during this observation time relative to the cumulative probability density voltage value signal output by the overall circuit; the inverter is used to invert the square wave signal to obtain a probability density signal; the high-level time of this probability density signal reflects the probability that the envelope signal is distributed below the circuit output voltage during this period of time.

6. A cumulative probability density distribution statistics loop circuit as claimed in claim 5, characterized in that: The lock detection module includes four D flip-flops cascaded in sequence; wherein the R ports of the four D flip-flops are all input with the same reset signal; the C port of the first D flip-flop is input with the control voltage signal, and the C ports of the other three D flip-flops are connected to the Q ports of the preceding D flip-flops; the D port of the fourth flip-flop is connected to a high level, and at the same time, the Q port of the fourth flip-flop outputs a lock signal LOCK; when the lock detection module detects that the input control voltage signal has eight rising edges, the lock signal is switched from a low level to a high level, the fifth switch is controlled to be disconnected, and the output voltage V of the cumulative probability density voltage generating module is locked. out When the lock detection module detects that the input reset signal is low, the lock signal is switched from high to low, the fifth switch is controlled to close, and the output voltage V of the cumulative probability density voltage generating module is adjusted. out .

7. A cumulative probability density distribution statistics loop circuit as claimed in claim 6, characterized in that: The peak detection module is composed of an RC peak detection circuit and a common source amplifier circuit connected in series.

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