A method and device for measuring the delay determinacy of a superheterodyne digital receiver

Abstract

The present invention discloses a method and device for measuring the delay determinism of a superheterodyne digital receiver, comprising: performing analog down-conversion, analog-to-digital conversion, and digital down-conversion on an acquired radio frequency single-tone test signal a to obtain a baseband I / Q test signal m; generating a pulse reset signal i synchronized with a reference clock d at every preset interval to periodically reset modules such as the ADC and a data interface; delaying the signal i to serve as a data acquisition enable mark k; triggering synchronous acquisition of a segment of the baseband I / Q test signal m as a test data sample n each time the mark k is received; calculating the phase value o corresponding to the sample n, and performing an error comparison on the phase value o according to a preset strategy to obtain the main signal link delay state of the superheterodyne digital receiver. The method and device for measuring the delay determinism of a superheterodyne digital receiver of the present application realize fast and automated measurement and can quickly identify jumps in link delay.

Description

Technical Field

[0001] The present invention relates to the technical field of superheterodyne digital receivers, and in particular to a method and device for measuring the delay determinism of a superheterodyne digital receiver. Background Art

[0002] In modern communications and radar systems, the determinism of the main signal link delay in a superheterodyne digital receiver directly impacts the system's synchronization accuracy, ranging precision, and overall signal processing architecture. However, due to factors such as inconsistent setup and hold times for ADC synchronization signals, clock domain conversion, serial-to-parallel conversion, and asynchronous decimation, signal link delay can exhibit jitter as small as a sampling clock cycle. Determining the determinism of a superheterodyne digital receiver's main signal link delay through measurement is a critical issue that needs to be addressed.

[0003] Measuring the deterministic link delay of a superheterodyne digital receiver is challenging. The fact that the input signal is an RF signal and the output signal is a baseband digital signal makes traditional delay measurement tools such as oscilloscopes or network analyzers impractical. One possible approach is to evaluate delay consistency by forming a closed loop with the superheterodyne digital transmitter and continuously comparing the phase relationship between the transmitter and receiver. However, this method requires an additional dedicated transmitter and a complex test signal generation process, making it cumbersome, equipment-intensive, and costly.

[0004] Given this situation, and from the perspectives of engineering efficiency and cost-effectiveness, there is an urgent need to develop a simplified, fast, and economical measurement method to evaluate the determinism of link delay in superheterodyne digital receivers at each power-up. The ideal solution should be able to quickly identify link delay jumps, eliminate the need for specialized equipment, and support automated and rapid measurement. Summary of the Invention

[0005] In order to solve the technical problems existing in the background technology, the present invention proposes a method and device for measuring the delay determinism of a superheterodyne digital receiver.

[0006] The present invention proposes a method for measuring the delay determinism of a superheterodyne digital receiver, comprising the following steps:

[0007] S1, performing analog down-conversion, filtering, and amplification processing on the acquired RF single-tone test signal a to obtain an intermediate frequency single-tone test signal f, and performing analog-to-digital conversion and clock domain conversion on the intermediate frequency single-tone test signal f to obtain an intermediate frequency digital test signal h;

[0008] S2. Digitally down-convert the intermediate frequency digital test signal h to obtain a baseband I / Q test signal m;

[0009] S3, generating a pulse reset signal i synchronized with the reference clock d of the superheterodyne digital receiver at every preset interval, and delaying the periodic pulse reset signal i by M reference clock d periods as a data acquisition enable mark k;

[0010] S4. When a data acquisition enable flag k is received each time, trigger synchronous acquisition of a continuous baseband I / Q test signal m, and use the synchronously acquired baseband I / Q test signal as a test data sample n;

[0011] S5. Calculate the phase value o corresponding to the test data sample n, and perform an error comparison on the phase value o according to a preset strategy to obtain a main signal link delay state of the superheterodyne digital receiver, where the delay state includes a fixed delay and a variable delay;

[0012] The preset strategy specifically includes:

[0013] Calculate the difference between the maximum and minimum values corresponding to the phase value o, and compare the difference with a preset reference error value;

[0014] When the difference is less than a preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a fixed delay;

[0015] When the difference is not less than a preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a delay change;

[0016] The calculation process of the preset reference error value λ is as follows:

[0017]

[0018] Among them, f a is the frequency of the RF single-tone test signal a; f LO is the frequency of the simulated local oscillator b; f nco is the frequency of the digital local oscillator j; f adc is the sampling frequency of the ADC, that is, the phase value of the baseband I / Q test signal h converted from the phase difference fluctuation of half the ADC conversion period.

[0019] Preferably, calculating the phase value o corresponding to the test data sample n specifically includes:

[0020] Perform fast Fourier transform on the test data sample n to obtain complex spectrum data;

[0021] Determine the peak I / Q data corresponding to the maximum modulus value in the complex spectrum data;

[0022] The phase value corresponding to the peak I / Q data is calculated and used as the phase value o of the test data sample n.

[0023] Preferably, determining the peak I / Q data corresponding to the maximum modulus value in the complex spectrum data specifically includes:

[0024] The complex spectrum data is modulo-calculated to find the position index corresponding to the maximum modulus value, and the corresponding peak I / Q data in the complex spectrum data is retrieved according to the position index.

[0025] Preferably, calculating the phase value corresponding to the peak I / Q data specifically includes:

[0026] Use a coordinate rotation digital calculation algorithm to find the inverse tangent of the peak I / Q data.

[0027] Preferably, the frequency f of the RF single-tone test signal a a The frequency f of the analog local oscillator b LO The absolute value of the difference between the two is the frequency f of the reference clock d base An integer multiple of |f a -f LO |=K×f base , where K is any positive integer.

[0028] The present invention proposes a device for measuring the delay determinism of a superheterodyne digital receiver, comprising:

[0029] The analog frequency conversion channel module is used to perform analog down-conversion, filtering, and amplification processing on the acquired RF single-tone test signal a to obtain an intermediate frequency single-tone test signal f;

[0030] A signal conversion module is used to perform analog-to-digital conversion and clock domain conversion on the intermediate frequency single-tone test signal f to obtain an intermediate frequency digital test signal h;

[0031] A digital down-conversion module is used to digitally down-convert the intermediate frequency digital test signal h to obtain a baseband I / Q test signal m;

[0032] A timing synchronization reset generation module is used to generate a pulse reset signal i synchronized with the reference clock d of the superheterodyne digital receiver at every preset interval to reset the ADC and its related circuits, the data interface module and the digital oscillator used by the digital down-conversion module;

[0033] A delay unit is used to delay the pulse reset signal i by M reference clock d cycles as a data acquisition enable mark k, where M is a fixed integer;

[0034] A synchronous data acquisition module is configured to trigger synchronous acquisition of a continuous baseband I / Q test signal m upon receiving a data acquisition enable flag k, and use the baseband I / Q test signal that triggers synchronous acquisition as a test data sample n;

[0035] Phase calculation module, used to calculate the phase value o corresponding to the test data sample n;

[0036] The delay determination module is used to perform error comparison on the phase value o according to a preset strategy to obtain the main signal link delay state of the superheterodyne digital receiver. The delay state includes fixed delay and variable delay.

[0037] In the delay determination module, the preset strategy specifically includes:

[0038] Calculate the difference between the maximum and minimum values corresponding to the phase value o, and compare the difference with a preset reference error value;

[0039] When the difference is less than a preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a fixed delay;

[0040] When the difference is not less than a preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a delay change;

[0041] The calculation process of the preset reference error value λ is as follows:

[0042]

[0043] Among them, f a is the frequency of the RF single-tone test signal a; f LO is the frequency of the simulated local oscillator b; f nco is the frequency of the digital local oscillator j; f adc is the sampling frequency of the ADC, that is, the phase value of the baseband I / Q test signal h converted from the phase difference fluctuation of half the ADC conversion period.

[0044] Preferably, the timing synchronization reset generation module includes:

[0045] A timer is used to generate a cycle counter with a period of N using a reference clock d, the counter is incremented by 1 at each clock cycle, and the cycle counter value is output to a synchronous reset generating unit;

[0046] The synchronous reset generating unit is used to output a pulse reset signal i synchronized with the reference clock d every time the cycle counter value cycles through one cycle.

[0047] Preferably, the phase calculation module includes:

[0048] An FFT calculation unit is used to perform a fast Fourier transform on the test data sample n and output complex spectrum data to the peak search calculation unit;

[0049] The peak-finding calculation unit is used to find the modulus of the complex spectrum data, find the position index corresponding to the maximum modulus value, extract the corresponding peak I / Q data in the complex spectrum data according to the position index, and send it to the CORDIC inverse tangent calculation unit;

[0050] The CORDIC inverse tangent calculation unit uses a coordinate rotation digital calculation algorithm to calculate the inverse tangent of the peak I / Q data, obtains the phase value o of the test data sample n and outputs it.

[0051] The present invention proposes a method and device for measuring the delay determinism of a superheterodyne digital receiver. Upon receiving a data acquisition enable flag k, the device triggers the synchronous acquisition of a continuous baseband I / Q test signal m, using the triggered synchronous acquisition as test data sample n. The device then calculates the phase value o corresponding to test data sample n and, according to a preset strategy, performs an error comparison on the phase value o obtained during each reset cycle to determine the main signal link delay state of the superheterodyne digital receiver. Delay states include fixed and variable delays. If the calculated phase value o is consistent within the error range, the main signal link delay of the superheterodyne digital receiver is fixed; otherwise, the delay is variable. During the measurement process, the present invention utilizes periodic automatic reset, digital acquisition, and calculation, replacing repeated power-on measurements. This enables rapid, automated measurement and can quickly identify jumps in link delay. Therefore, the embodiments of the present invention provide a simple, efficient, and cost-effective measurement solution for link delay determinism in superheterodyne digital receivers, greatly benefiting those skilled in the relevant field. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A schematic diagram of the working process structure of a method for measuring the delay determinism of a superheterodyne digital receiver proposed by the present invention;

[0053] Figure 2 This is a schematic diagram of the module architecture of a device for measuring the delay determinism of a superheterodyne digital receiver proposed by the present invention;

[0054] Figure 3 This is a structural diagram of a timing synchronization reset generation module of a device for measuring the delay determinism of a superheterodyne digital receiver proposed by the present invention;

[0055] Figure 4 This is a structural diagram of a phase calculation module of a device for measuring delay determinism of a superheterodyne digital receiver proposed by the present invention. DETAILED DESCRIPTION

[0056] Reference Figure 1-4 The present invention proposes a method for measuring the delay determinism of a superheterodyne digital receiver, comprising the following steps:

[0057] S1. Perform analog down-conversion, filtering, and amplification on the acquired RF single-tone test signal a to obtain an intermediate frequency single-tone test signal f, and perform analog-to-digital conversion and clock domain conversion on the intermediate frequency single-tone test signal f to obtain an intermediate frequency digital test signal h.

[0058] In this embodiment, the signal source generates a coherent radio frequency single-tone test signal a, an analog local oscillator b, and a reference clock c; the phase-locked loop generates a reference clock d and a processing clock e according to the reference clock c.

[0059] In this embodiment, the frequency f of the RF single-tone test signal a is a The frequency f of the analog local oscillator b LO The absolute value of the difference between the two is the frequency f of the reference clock d base An integer multiple of |f a -f LO |=K×f base , where K is an arbitrary positive integer. The frequency of the reference clock d is an integer multiple of the reference clock c; the frequency of the processing clock e is an integer multiple of the reference clock d; the signal source must not be powered off or restarted during the measurement process to ensure that the initial phase difference between the RF single-tone test signal a and the analog local oscillator b remains constant during the measurement.

[0060] In this embodiment, the frequency f of the RF single-tone test signal a is a =5.2GHz, analog local oscillator frequency f LO =5GHz, the frequency of the reference clock c is f c =20MHz, the frequency of the reference clock d is f base =20MHz, the frequency f of the processing clock e e =240MHz.

[0061] In this embodiment, the sampling frequency of the analog-to-digital converter may be equal to the frequency of the processing clock e, and the clock domain conversion refers to switching the collected data from the sampling clock domain to the clock domain of the processing clock e.

[0062] In the embodiment of the present invention, the sampling frequency is 240 MSPS.

[0063] S2. Digitally down-convert the intermediate frequency digital test signal h to obtain a baseband I / Q test signal m.

[0064] In this embodiment, the frequency f of the digital local oscillator j used in digital down-conversion is j Not equal to the frequency f of the RF single-tone test signal a a The frequency f of the analog local oscillator b LO The absolute value of the difference between |f a -f LO |, to ensure that the frequency of the baseband I / Q test signal m is not equal to 0.

[0065] In the embodiment of the present invention, the frequency of the digital local oscillator j is 180 MHz.

[0066] S3. Generate a pulse reset signal i synchronized with the reference clock d of the superheterodyne digital receiver at every preset interval, and delay the periodic pulse reset signal i by M reference clock d periods as a data acquisition enable mark k.

[0067] In this embodiment, the pulse reset signal i is used to periodically reset the ADC and its related circuits, the ADC data interface, and the digital oscillator that provides the digital local oscillator j for digital down-conversion.

[0068] In this embodiment, the reset mode of the digital oscillator is synchronous reset; the time interval between generating two pulse reset signals i is greater than the sum of the ADC delay, data interface delay, digital down-conversion delay, and the time required for synchronous acquisition of the baseband I / Q test signal h, so as to ensure that the baseband I / Q test signal h is stable each time it is acquired.

[0069] In the embodiment of the present invention, the time interval between generating two pulse reset signals i is set to 10 ms, which is large enough and is an integer multiple of the reference clock d period.

[0070] In this embodiment, the number M of delay periods of the pulse reset signal i is a fixed integer.

[0071] S4. When the data acquisition enable flag k is received, synchronous acquisition of a continuous baseband I / Q test signal m is triggered, and the baseband I / Q test signal that triggers synchronous acquisition is used as the test data sample n.

[0072] In the embodiment of the present invention, M takes a value of 50000, that is, the pulse reset signal i is delayed by 5ms as the data acquisition enable mark k, triggering the synchronous acquisition of 1000 consecutive baseband I / Q test signal m data as the test data sample n.

[0073] S5. Calculate the phase value o corresponding to the test data sample n, and perform error comparison on the phase value o according to a preset strategy to obtain the main signal link delay state of the superheterodyne digital receiver, where the delay state includes fixed delay and variable delay.

[0074] In this embodiment, if the phase value o calculated each time is consistent within the error range, it means that the main signal link delay of the superheterodyne digital receiver is fixed; otherwise, it means that the delay will vary.

[0075] In this embodiment, calculating the phase value o corresponding to the test data sample n specifically includes:

[0076] Perform fast Fourier transform on the test data sample n to obtain complex spectrum data;

[0077] Determine the peak I / Q data corresponding to the maximum modulus value in the complex spectrum data;

[0078] The phase value corresponding to the peak I / Q data is calculated and used as the phase value o of the test data sample n.

[0079] In this embodiment, determining the peak I / Q data corresponding to the maximum modulus value in the complex spectrum data specifically includes:

[0080] The complex spectrum data is modulo-calculated to find the position index corresponding to the maximum modulus value, and the corresponding peak I / Q data in the complex spectrum data is retrieved according to the position index.

[0081] In this embodiment, calculating the phase value corresponding to the peak I / Q data specifically includes:

[0082] Use a coordinate rotation digital calculation algorithm to find the inverse tangent of the peak I / Q data.

[0083] In this embodiment, the preset strategy specifically includes:

[0084] Calculate the difference between the maximum and minimum values corresponding to the phase value o, and compare the difference with a preset reference error value;

[0085] When the difference is less than a preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a fixed delay;

[0086] When the difference is not less than a preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a delay change.

[0087] In this embodiment, the calculation process of the preset reference error value λ is as follows:

[0088]

[0089] Among them, f a is the frequency of the RF single-tone test signal a; f LO is the frequency of the simulated local oscillator b; f nco is the frequency of the digital local oscillator j; f adc is the sampling frequency of the ADC, that is, the phase value of the baseband I / Q test signal h converted from the phase difference fluctuation of half the ADC conversion period.

[0090] In the embodiment of the present invention, the number of fast Fourier transform points is 1000. The more points there are, the higher the signal-to-noise ratio of the peak I / Q data and the more accurate the calculated phase.

[0091] The criterion for the consistency of the phase values calculated each time within the error range is that the difference between the maximum and minimum phase values is less than λ;

[0092]

[0093] That is, the range of the phase value calculated each time is less than It can be considered that the main signal link of the superheterodyne digital receiver achieves deterministic delay.

[0094] Reference Figure 1-4 The present invention proposes a device for measuring the delay determinism of a superheterodyne digital receiver, comprising:

[0095] The analog frequency conversion channel module is used to perform analog down-conversion, filtering, and amplification processing on the acquired RF single-tone test signal a to obtain an intermediate frequency single-tone test signal f.

[0096] The signal conversion module is used to perform analog-to-digital conversion and clock domain conversion on the intermediate frequency single-tone test signal f to obtain an intermediate frequency digital test signal h.

[0097] The digital down-conversion module is used to digitally down-convert the intermediate frequency digital test signal h to obtain the baseband I / Q test signal m.

[0098] A timing synchronization reset generation module is used to generate a pulse reset signal i synchronized with the reference clock d of the superheterodyne digital receiver at every preset interval to reset the ADC and its related circuits, the data interface module and the digital oscillator used by the digital down-conversion module;

[0099] The delay unit is used to delay the pulse reset signal i by M reference clock d cycles as a data acquisition enable mark k, where M is a fixed integer.

[0100] The synchronous data acquisition module is used to trigger the synchronous acquisition of a continuous baseband I / Q test signal m when receiving the data acquisition enable mark k, and use the baseband I / Q test signal that triggers the synchronous acquisition as the test data sample n.

[0101] The phase calculation module is used to calculate the phase value o corresponding to the test data sample n.

[0102] The delay determination module is used to perform error comparison on the phase value o according to a preset strategy to obtain the main signal link delay state of the superheterodyne digital receiver. The delay state includes fixed delay and variable delay.

[0103] In this embodiment, in the delay determination module, the preset strategy specifically includes:

[0104] Calculate the difference between the maximum and minimum values corresponding to the phase value o, and compare the difference with a preset reference error value;

[0105] When the difference is less than a preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a fixed delay;

[0106] When the difference is not less than a preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a delay change;

[0107] The calculation process of the preset reference error value λ is as follows:

[0108]

[0109] Among them, f a is the frequency of the RF single-tone test signal a; f LO is the frequency of the simulated local oscillator b; f nco is the frequency of the digital local oscillator j; f adc is the sampling frequency of the ADC, that is, the phase value of the baseband I / Q test signal h converted from the phase difference fluctuation of half the ADC conversion period.

[0110] In this embodiment, a coherent RF single-tone test signal a and an analog local oscillator b are output to the analog frequency conversion channel module through a signal source, and a coherent reference clock c is output to the phase-locked loop; the analog frequency conversion channel module uses the analog local oscillator b to perform analog down-conversion, filtering, and amplification processing on the RF single-tone test signal a, and outputs the intermediate frequency single-tone test signal f to the ADC module; the ADC module performs analog-to-digital conversion on the intermediate frequency single-tone test signal f, and outputs data g to the data interface module; the data interface module performs clock domain conversion on the data g, and outputs the intermediate frequency digital test signal h to the digital down-conversion module; the digital down-conversion module uses the digital local oscillator j to perform digital down-conversion on the intermediate frequency digital test signal h, and outputs the baseband I / Q test signal m to the synchronous data acquisition module; the synchronous data acquisition module uses the data acquisition enable mark k as a trigger, and synchronously acquires a continuous baseband I / Q test signal m each time, and sends it to the phase Calculation module; Phase calculation module, calculates the phase of each test data sample n sent, and outputs the phase value o to the phase data upload module; The phase data upload module uploads the phase value o sent each time to the computer display terminal; The phase-locked loop generates a reference clock d based on the reference clock c to the timing synchronization reset generation module, and generates a processing clock e to the digital oscillator and data interface module; The timing synchronization reset generation module uses the reference clock d to generate a pulse reset signal i synchronized with the reference clock d every several reference clock d cycles to the ADC module and its related circuits, data interface module, digital oscillator and delay unit; The digital oscillator outputs a digital local oscillator j to the digital down-conversion module, and the pulse reset signal i is used to synchronize the digital oscillator; The delay unit delays the pulse reset signal i by M reference clock d cycles as a data acquisition enable mark k and sends it to the synchronous data acquisition module, where M is a fixed integer.

[0111] In a specific implementation of the embodiment of the present invention, Figure 3 This is a structural diagram of a timing synchronization reset generation module in a device for measuring the delay determinism of a superheterodyne digital receiver provided by an embodiment of the present invention. The timing synchronization reset generation module includes:

[0112] A timer is used to generate a cycle counter with a period of N using a reference clock d, the counter is incremented by 1 at each clock cycle, and the cycle counter value is output to a synchronous reset generating unit;

[0113] The synchronous reset generating unit is used to output a pulse reset signal i synchronized with the reference clock d every time the cycle counter value cycles through one cycle.

[0114] In a specific implementation of the embodiment of the present invention, Figure 4 A schematic structural diagram of a phase calculation module in a device for measuring delay determinism of a superheterodyne digital receiver provided by an embodiment of the present invention, wherein the phase calculation module includes:

[0115] An FFT calculation unit is used to perform a fast Fourier transform on the test data sample n and output complex spectrum data to the peak search calculation unit;

[0116] The peak-finding calculation unit is used to find the modulus of the complex spectrum data, find the position index corresponding to the maximum modulus value, extract the corresponding peak I / Q data in the complex spectrum data according to the position index, and send it to the CORDIC inverse tangent calculation unit;

[0117] The CORDIC inverse tangent calculation unit uses a coordinate rotation digital calculation algorithm to calculate the inverse tangent of the peak I / Q data, obtains the phase value o of the test data sample n and outputs it.

[0118] In this embodiment, CORDIC means coordinate rotation digital calculation algorithm.

[0119] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A method for measuring the delay determinism of a superheterodyne digital receiver, characterized in that: The following steps are involved: S1, performing analog down-conversion, filtering, and amplification processing on the acquired RF single-tone test signal a to obtain an intermediate frequency single-tone test signal f, and performing analog-to-digital conversion and clock domain conversion on the intermediate frequency single-tone test signal f to obtain an intermediate frequency digital test signal h; S2. Digitally down-convert the intermediate frequency digital test signal h to obtain a baseband I / Q test signal m; S3, generating a pulse reset signal i synchronized with the reference clock d of the superheterodyne digital receiver at every preset interval, and delaying the periodic pulse reset signal i by M reference clock d periods as a data acquisition enable mark k; S4. When a data acquisition enable flag k is received each time, trigger synchronous acquisition of a continuous baseband I / Q test signal m, and use the synchronously acquired baseband I / Q test signal as a test data sample n; S5. Calculate the phase value o corresponding to the test data sample n, and perform an error comparison on the phase value o according to a preset strategy to obtain a main signal link delay state of the superheterodyne digital receiver, where the delay state includes a fixed delay and a variable delay; The preset strategy specifically includes: Calculate the difference between the maximum and minimum values corresponding to the phase value o, and compare the difference with a preset reference error value; When the difference is less than a preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a fixed delay; When the difference is not less than a preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a delay change; The calculation process of the preset reference error value λ is as follows: Among them, f a is the frequency of the RF single-tone test signal a; f LO is the frequency of the simulated local oscillator b; f nco is the frequency of the digital local oscillator j; f adc is the sampling frequency of the ADC, that is, the phase value of the baseband I / Q test signal h converted from the phase difference fluctuation of half the ADC conversion period.

2. The method for measuring the delay determinism of a superheterodyne digital receiver according to claim 1, wherein: The calculating of the phase value o corresponding to the test data sample n specifically includes: Perform fast Fourier transform on the test data sample n to obtain complex spectrum data; Determine the peak I / Q data corresponding to the maximum modulus value in the complex spectrum data; The phase value corresponding to the peak I / Q data is calculated and used as the phase value o of the test data sample n.

3. The method for measuring the delay determinism of a superheterodyne digital receiver according to claim 2, wherein: Determining the peak I / Q data corresponding to the maximum modulus value in the complex spectrum data specifically includes: The complex spectrum data is modulo-calculated to find the position index corresponding to the maximum modulus value, and the corresponding peak I / Q data in the complex spectrum data is retrieved according to the position index.

4. The method for measuring the delay determinism of a superheterodyne digital receiver according to claim 2, wherein: Calculating the phase value corresponding to the peak I / Q data specifically includes: Use a coordinate rotation digital calculation algorithm to find the inverse tangent of the peak I / Q data.

5. The method for measuring the delay determinism of a superheterodyne digital receiver according to claim 1, wherein: Frequency f of the RF single-tone test signal a a The frequency f of the analog local oscillator b LO The absolute value of the difference between the two is the frequency f of the reference clock d base An integer multiple of |f a -f LO |=K×f base , where K is any positive integer.

6. A device for measuring the delay determinism of a superheterodyne digital receiver, characterized in that: include: The analog frequency conversion channel module is used to perform analog down-conversion, filtering, and amplification processing on the acquired RF single-tone test signal a to obtain an intermediate frequency single-tone test signal f; A signal conversion module is used to perform analog-to-digital conversion and clock domain conversion on the intermediate frequency single-tone test signal f to obtain an intermediate frequency digital test signal h; A digital down-conversion module is used to digitally down-convert the intermediate frequency digital test signal h to obtain a baseband I / Q test signal m; A timing synchronization reset generation module is used to generate a pulse reset signal i synchronized with the reference clock d of the superheterodyne digital receiver at every preset interval to reset the ADC and its related circuits, the data interface module and the digital oscillator used by the digital down-conversion module; A delay unit is used to delay the pulse reset signal i by M reference clock d cycles as a data acquisition enable mark k, where M is a fixed integer; A synchronous data acquisition module is configured to trigger synchronous acquisition of a continuous baseband I / Q test signal m upon receiving a data acquisition enable flag k, and use the baseband I / Q test signal that triggers synchronous acquisition as a test data sample n; Phase calculation module, used to calculate the phase value o corresponding to the test data sample n; The delay determination module is used to perform error comparison on the phase value o according to a preset strategy to obtain the main signal link delay state of the superheterodyne digital receiver, where the delay state includes fixed delay and variable delay; In the delay determination module, the preset strategy specifically includes: Calculate the difference between the maximum and minimum values corresponding to the phase value o, and compare the difference with a preset reference error value; When the difference is less than a preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a fixed delay; When the difference is not less than a preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a delay change; The calculation process of the preset reference error value λ is as follows: Among them, f a is the frequency of the RF single-tone test signal a; f LO is the frequency of the simulated local oscillator b; f nco is the frequency of the digital local oscillator j; f adc is the sampling frequency of the ADC, that is, the phase value of the baseband I / Q test signal h converted from the phase difference fluctuation of half the ADC conversion period.

7. The device for measuring the delay determinism of a superheterodyne digital receiver according to claim 6, wherein: The timing synchronous reset generation module includes: A timer, configured to generate a cycle counter with a period of N using a reference clock d, increment the counter by 1 at each clock cycle, and output the cycle counter value to a synchronous reset generating unit; The synchronous reset generating unit is used to output a pulse reset signal i synchronized with the reference clock d every time the cycle counter value cycles through one cycle.

8. The device for measuring the delay determinism of a superheterodyne digital receiver according to claim 6, wherein: The phase calculation module includes: An FFT calculation unit is used to perform a fast Fourier transform on the test data sample n and output complex spectrum data to the peak search calculation unit; The peak-finding calculation unit is used to find the modulus of the complex spectrum data, find the position index corresponding to the maximum modulus value, extract the corresponding peak I / Q data in the complex spectrum data according to the position index, and send it to the CORDIC inverse tangent calculation unit; The CORDIC inverse tangent calculation unit uses a coordinate rotation digital calculation algorithm to calculate the inverse tangent of the peak I / Q data, obtains the phase value o of the test data sample n and outputs it.

Images