Side channel attack vulnerability verification method and device, electronic equipment and storage medium

Abstract

The invention provides a side channel attack vulnerability verification method and device, electronic equipment and a storage medium, and the method comprises the steps: repeatedly executing a branch jump instruction in a first time interval, and enabling a branch jump target address of a branch target buffer to point to a first path; the first path corresponds to a first function, and the first function is used for loading secret data corresponding to the branch jump instruction to a cache; in response to the end of the first time interval, setting the branch jump target address to point to the second path, and executing the branch jump instruction; the second path corresponds to a second function; in response to completion of execution of the branch jump instruction, determining duration required for reading secret data corresponding to the branch jump instruction; and determining whether the side channel attack vulnerability exists or not based on the duration required for reading the secret data corresponding to the branch jump instruction, so that the vulnerability detection capability can be enhanced, corresponding security protection can be performed on the newly discovered vulnerability in time, the hardware security of a product is ensured, and the data security of a user is protected.

Description

Technical Field

[0001] The present disclosure relates to the field of information security technology, and in particular to a side-channel attack vulnerability verification method, device, electronic device and storage medium. Background Art

[0002] In the digital age, information security is of vital importance. As a potential threat, the core idea of ​​side-channel attacks is to cleverly use various types of information generated during the operation of hardware, and try to obtain ciphertext information through guesswork, thereby causing user data leakage, bringing huge risks and losses to individuals and enterprises.

[0003] Timely and effective detection of side channel attack vulnerabilities has become a key link in ensuring information security. However, current technologies have obvious limitations. At present, only side channel attack vulnerabilities based on explicit jumps of "if else" statements can be detected. However, side channel attacks based on branch target caches are beyond the capabilities of current side channel detection systems. This means that existing detection systems cannot accurately determine whether the central processing unit (CPU) has such hidden and dangerous vulnerabilities, making information systems vulnerable and vulnerable to this new type of attack. Summary of the invention

[0004] The present disclosure provides a side-channel attack vulnerability verification method, device, electronic device and storage medium to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, a side channel attack vulnerability verification method is provided, comprising:

[0006] In a first time interval, a branch jump instruction is repeatedly executed, and a branch target cache is made to point to a first path for a branch jump target address of the branch jump instruction; the first path corresponds to a first function, and the first function is used to load secret data corresponding to the branch jump instruction into a cache;

[0007] In response to the end of the first time interval, the branch target buffer is set to point to a second path for the branch jump target address of the branch jump instruction, and the branch jump instruction is executed; the second path corresponds to a second function;

[0008] In response to the completion of executing the branch jump instruction, determine the time required to read the secret data corresponding to the branch jump instruction; based on the time required to read the secret data corresponding to the branch jump instruction, determine whether there is a side channel attack vulnerability.

[0009] In the above scheme, the repeatedly executing the branch jump instruction and making the branch target buffer point to the first path for the branch jump target address of the branch jump instruction includes:

[0010] Executing the branch jump instruction, based on the branch jump target address, processing the branch jump instruction by a first function corresponding to the first path;

[0011] The first function determines a channel loaded into the cache based on the value of each element of the secret data corresponding to the branch jump instruction, including:

[0012] In response to the value of the element being 0, the first function loads the first channel into the cache;

[0013] In response to the value of the element being 1, the first function loads the second channel into the cache.

[0014] In the above solution, the step of determining the time required to read the data corresponding to the branch jump instruction includes:

[0015] Determine the duration required to access the first channel, the second channel, and the third channel respectively;

[0016] Determine the time required to access the first channel and the time required to access the second channel, and the time with a smaller value is the time required to read the data corresponding to the branch jump instruction;

[0017] The third channel is located in the memory, and the time required to access the third channel is determined to be a preset threshold.

[0018] In the above scheme, the duration required to access the first channel, the second channel, and the third channel is determined respectively, including performing the following operations on each channel:

[0019] When you start accessing any channel, pull the register level high to instruct the timer to start working;

[0020] When the data of any of the channels is read, the register level is pulled low to indicate that the timer ends its work;

[0021] The timer writes the time difference between the corresponding time of starting the work and the corresponding time of ending the work into the register, and the time difference is the time required to access any channel.

[0022] In the above scheme, determining whether there is a side channel attack vulnerability based on the time required to read the data corresponding to the branch jump instruction includes:

[0023] In response to the time required to read the data corresponding to the branch jump instruction being greater than a preset threshold, it is determined that a side channel attack vulnerability exists; in response to the time required to read the data corresponding to the branch jump instruction being less than or equal to the preset threshold, it is determined that no side channel attack vulnerability exists.

[0024] In the above scheme, determining whether there is a side channel attack vulnerability based on the time required to read the data corresponding to the branch jump instruction includes:

[0025] Determining predicted secret information of the branch jump instruction by reading the time required for the data corresponding to the branch jump instruction;

[0026] The predicted secret information is matched with the secret information corresponding to the branch jump instruction. If the predicted secret information is the same as the secret information, it is determined that a side channel attack vulnerability exists; if the predicted secret information is different from the secret information, it is determined that no side channel attack vulnerability exists.

[0027] In the above scheme, the method of determining the predicted secret information of the branch jump instruction by reading the time required for the data corresponding to the branch jump instruction includes:

[0028] Determine a preset cache duration; the preset cache duration includes the duration required to read data in the cache;

[0029] Determine a difference between a first duration required to access the first channel and the preset cache duration, and a difference between a second duration required to access the second channel and the preset cache duration;

[0030] The channel with the smaller difference is confirmed to be loaded into the cache, and the predicted secret information of the branch jump instruction is determined based on the correspondence between the channel and the value of the element.

[0031] According to a second aspect of the present disclosure, a side channel attack vulnerability verification device is provided, the device comprising:

[0032] A pre-training module is used to repeatedly execute a branch jump instruction within a first time interval, and to make a branch target cache point to a first path for a branch jump target address of the branch jump instruction; the first path corresponds to a first function, and the first function is used to load secret data corresponding to the branch jump instruction into a cache;

[0033] A test module, configured to, in response to the end of the first time interval, set a branch target buffer to point a branch jump target address of a branch jump instruction to a second path, and execute the branch jump instruction; the second path corresponds to a second function;

[0034] The result comparison module is used to determine the time required to read the secret data corresponding to the branch jump instruction in response to the completion of the execution of the branch jump instruction; based on the time required to read the secret data corresponding to the branch jump instruction, determine whether there is a side channel attack vulnerability.

[0035] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0036] at least one processor; and

[0037] a memory communicatively connected to the at least one processor; wherein,

[0038] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present disclosure.

[0039] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method described in the present disclosure.

[0040] The side-channel attack vulnerability verification method disclosed in the present invention is to repeatedly execute a branch jump instruction within a first time interval, and make a branch target cache point to a first path for a branch jump target address of the branch jump instruction; the first path corresponds to a first function, and the first function is used to load secret data corresponding to the branch jump instruction into a cache; in response to the end of the first time interval, the branch target cache is set to point to a second path for the branch jump target address of the branch jump instruction, and the branch jump instruction is executed; the second path corresponds to a second function; in response to the completion of executing the branch jump instruction, determine the time required to read the secret data corresponding to the branch jump instruction; based on the time required to read the secret data corresponding to the branch jump instruction, determine whether there is a side-channel attack vulnerability. In this way, the branch jump target address is pointed to the first path through pre-training, and an implicit jump is artificially constructed; then the branch jump target address is pointed to the second path. Since the function of the first path is to load the secret data into the cache, that is, if there is an implicit jump (i.e., jump to the first path) in the process of executing the branch jump instruction, the first function will be executed, and then when reading the secret data, it will be read from the cache; the time required to read data from the cache is different from the time required to read data from the memory. It is possible to determine whether there is an implicit jump by determining the time required to read the secret data, and then determine whether there is a side channel attack vulnerability.

[0041] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which:

[0043] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0044] Figure 1 A first optional flow chart of the side channel attack vulnerability verification method provided by an embodiment of the present disclosure is shown;

[0045] Figure 2 A second optional flow chart of the side channel attack vulnerability verification method provided by an embodiment of the present disclosure is shown;

[0046] Figure 3 A third optional flow chart of the side channel attack vulnerability verification method provided by an embodiment of the present disclosure is shown;

[0047] Figure 4 A first optional structural diagram of a side channel attack vulnerability detection device provided by an embodiment of the present disclosure is shown;

[0048] Figure 5 is a schematic diagram of the workflow of the pre-training module provided in an embodiment of the present disclosure;

[0049] Figure 6 is a schematic diagram of the workflow of the test module provided in an embodiment of the present disclosure;

[0050] Figure 7 is a schematic diagram of the workflow of the result comparison module provided in an embodiment of the present disclosure;

[0051] Figure 8 A second optional structural diagram of the side channel attack vulnerability verification device provided by an embodiment of the present disclosure is shown;

[0052] Fig. 9 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0053] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0054] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0055] In the following description, the terms "first\second" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0056] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as those commonly understood by those skilled in the art to which this disclosure belongs. The terms used in this disclosure are only for the purpose of describing the embodiments of this disclosure and are not intended to limit this disclosure.

[0057] It should be understood that in the various embodiments of the present disclosure, the size of the serial number of each implementation process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

[0058] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations.

[0059] 1) Branch Target Buffer (BTB). In order to reduce the impact of branch instructions interrupting pipeline work and on computer performance, modern processors introduce BTB to store four types of information (branch tags, branch tag addresses, prediction information and branch jumps). When encountering a branch instruction, BTB will predict the execution path of the future branch instruction to reduce the impact on pipeline work.

[0060] 2) Vulnerability verification (Proof of Concept, POC) is a method of proof of concept or experimental vulnerability exploitation. In a security research project, POC usually verifies whether the vulnerability really exists by establishing a laboratory environment and a simulation environment. Specifically, it uses known vulnerabilities, writes corresponding codes and tests them on the attacked target system to prove that the vulnerability can be exploited by attackers. If the POC obtains a successful result, it means that the vulnerability really exists and corresponding protective measures need to be taken. If the POC fails, it means that the vulnerability does not exist. In the related art, for the side channel vulnerability verification method of conditional branches, for the common "if else" instruction branch code, the CPU will predict which branch is more likely to be executed. If the prediction is successful, it will bring a high performance improvement. If the prediction is wrong, the incorrect result will be discarded, but the cached operation will still be saved. Taking advantage of this, predecessors invented a side channel vulnerability verification method based on conditional branches, that is, predicting and training branch predictions through "if else" instructions, so that the program can control their execution path when predicting execution to leak secret information.

[0061] However, side channel attacks are a field that is constantly evolving and improving. Current technology can only detect side channel attack vulnerabilities based on explicit jumps of the "ifelse" instruction. Side channel attacks based on branch target caches exceed the capabilities of the current side channel detection system, and the system cannot detect whether the CPU has such vulnerabilities. If such vulnerabilities in products are not detected in a timely manner and corresponding security repair measures are not implemented, then attackers can optimize attacks by adjusting attack methods, attack paths, etc., complete attacks, and cause user data leakage and other problems.

[0062] In view of the defect that the related technology can only detect the side channel attack vulnerability of the explicit jump of if else, the embodiment of the present disclosure provides a side channel attack vulnerability verification method, artificially constructs the side channel attack of BTB implicit jump, and determines whether there is an implicit jump based on the cache access time, so as to solve some or all of the above technical problems.

[0063] The main concept of the disclosed embodiment includes: the branch target cache vulnerability is a vulnerability induced by training using the BTB. In order to improve performance, the CPU has added two schemes, out-of-order execution and predictive execution, so that the processor may use the waiting time to predict the execution of subsequent instructions, and add the predicted data that may be used to the cache in advance. The BTB is a branch target cache that is used to store the address and target address of the most recently accessed branch instruction in order to predict the execution path of future branch instructions. When multiple programs (or functions) share a BTB at the same time, the attacker can pre-train the BTB through a malicious program, control the forward path of the victim program, and make the victim program execute the pre-trained path in the forward state to load secret information into the cache in advance. After the prediction is wrong, the processor will only cancel the execution result and will not process the data in the cache, that is, although the error information loaded in advance is revoked, its modification of the cache still exists. However, there is a difference in access time between cache and main memory (or internal memory). An attacker can traverse a piece of address and determine whether each data has been loaded in advance, that is, whether it is located in cache or main memory, by the speed (or length of time) of accessing each data. In this way, the attacker can determine whether the data has been used in inducing the attack, thereby stealing the user's secret information.

[0064] The side channel attack vulnerability verification method provided by the embodiment of the present disclosure can be applied to the ARM platform and perform branch jumps based on the blr instruction; the assembly instructions can also be redesigned and written and migrated to other platforms.

[0065] Figure 1 A first optional flow chart of the side channel attack vulnerability verification method provided by an embodiment of the present disclosure is shown, and will be explained according to each step.

[0066] Step S101, within a first time interval, repeatedly executing a branch jump instruction, and making a branch jump target buffer point to a first path for a branch jump target address of the branch jump instruction.

[0067] In some embodiments, in order to verify whether there is a side channel attack vulnerability of implicit jump, it is first necessary to create a side channel attack of implicit jump; that is, within a first time interval, the carrier (hereinafter referred to as the carrier) that implements the side channel attack vulnerability verification method makes the branch jump target address of the branch jump instruction point to the first path; the first path corresponds to the first function, and the first function is an attack function (attack function), which will load the secret information in the branch jump instruction into the cache. The cache can speed up data access, that is, the response time of cache hit and failure is different. The attacker can use this time difference to infer the information in the cache and obtain secret data. Subsequently, it can be judged by the time required to read the secret information whether there is an implicit jump side channel tool when the branch jump instruction is actually executed. Among them, the branch jump target address includes the target address of the branch jump instruction, that is, the predicted execution path of the branch jump instruction.

[0068] In some embodiments, the first time interval is a pre-training time interval and can be set according to actual needs.

[0069] In some embodiments, the carrier can be a computer program, electronic circuit, database, mobile application, electronic device, cloud computing platform, distributed system, artificial intelligence framework, mathematical model, automation tool and microcontroller, etc., which can implement software or hardware of algorithm and method flow.

[0070] Step S102, in response to the end of the first time interval, setting the branch target buffer to point the branch jump target address of the branch jump instruction to the second path, and executing the branch jump instruction.

[0071] In some embodiments, when the first time interval ends, that is, the pre-training ends, the branch target cache is pointed to the second path for the branch jump target address of the branch jump instruction. The second path corresponds to a second function, which is a function for processing the secret data. The processing method does not include loading the secret data into the cache, that is, the functions of the first function and the second function are different. Optionally, the second function may include a function that does not perform any processing on the secret data.

[0072] In some embodiments, after the branch target cache is pointed to the second path for the branch target address of the branch instruction, the execution of the branch instruction begins.

[0073] Step S103, in response to the completion of executing the branch jump instruction, determining the time required to read the secret data corresponding to the branch jump instruction; based on the time required to read the secret data corresponding to the branch jump instruction, determining whether there is a side channel attack vulnerability.

[0074] In some embodiments, after the branch jump instruction is executed, it can be determined whether there is an implicit jump in the jump process; specifically, if there is an implicit jump, it will jump to the first path, and the first function will load the secret data into the cache; if there is no implicit jump, it will jump to the second path, and the secret data is still in the memory, and the time required to read the data from the cache is different from the time required to read the data from the memory. Therefore, the time required to read the secret data can be used to determine whether there is a side channel attack vulnerability.

[0075] Further, if the time required to read the secret data is less than a preset threshold, it is determined that there is a side channel attack vulnerability; if the time required to read the secret data is greater than or equal to the preset threshold, it is determined that there is no side channel attack vulnerability. Alternatively, if the difference between the time required to read the secret data and the preset threshold is greater than a first threshold, it is determined that there is a side channel attack vulnerability; if the difference between the time required to read the secret data and the preset threshold is less than the first threshold, it is determined that there is no side channel attack vulnerability.

[0076] In this way, through the side channel attack vulnerability verification method provided by the embodiment of the present disclosure, the branch jump target address is pointed to the first path through pre-training, and an implicit jump is artificially constructed; then the branch jump target address is pointed to the second path. Since the function of the first path is to load the secret data into the cache, that is, if there is an implicit jump (i.e., jump to the first path) during the execution of the branch jump instruction, the first function will be executed, and then when the secret data is read, it will be read from the cache; the time required to read data from the cache is different from the time required to read data from the memory, it can be determined by determining the time required to read the secret data to determine whether there is an implicit jump, and then determine whether there is a side channel attack.

[0077] Figure 2 A second optional flow chart of the side channel attack vulnerability verification method provided by the embodiment of the present disclosure is shown, and will be explained according to each step.

[0078] Step S201, pre-training the branch target buffer.

[0079] In some embodiments, the carrier pre-trains the branch target buffer based on the first function. In a first time interval, the branch target buffer points to a first path for a branch jump target address of a branch jump instruction, and the first path corresponds to a first function.

[0080] In a specific implementation, the carrier executes the branch jump instruction, and based on the branch jump target address, the first function corresponding to the first path processes the branch jump instruction. The first function determines the channel loaded into the cache based on the value of each element of the secret data corresponding to the branch jump instruction, specifically including: in response to the value of the element being 0, the first function modifies the first channel and loads the modified first channel into the cache; in response to the value of the element being 1, the first function modifies the second channel and loads the modified second channel into the cache.

[0081] In some embodiments, in response to the branch target buffer pre-training being completed, first indication information is sent, wherein the indication information is used to indicate that the branch target buffer pre-training is completed and the side channel attack vulnerability test is started.

[0082] Step S202: Perform a side channel attack test on the branch target cache.

[0083] In some embodiments, in response to receiving the first indication information, the carrier points the branch target cache for the score jump information of the branch jump instruction from the first path to the second path, and then executes the branch jump instruction; under normal circumstances, during the execution of the branch jump instruction, the branch target cache will point the branch jump instruction to the second path; the second path corresponds to a second function, and the second function includes a function that does not perform any processing operations on secret data.

[0084] Step S203, determining whether there is a side channel attack vulnerability.

[0085] In some embodiments, the carrier predetermines the duration of reading data from the cache and the duration of reading data from the memory, ie, a preset threshold.

[0086] During specific implementation, the carrier can use register counting to determine the duration of reading data from the cache and the duration of reading data from the memory. Specifically, when the timing starts, 1 is written to the register address to pull up the register level, indicating that the timer has started working; when the timing ends, 0 is written to the register address to lower the register level, indicating that the timer has ended working; the timer will write the time difference into the register to obtain the reading duration.

[0087] In some optional embodiments, the carrier may pre-load test data into the cache, access the test data and time it to obtain the cache duration; it may also load test data into the memory, access the test data and obtain the memory duration. Whether accessing the cache or the memory, the duration obtained may fluctuate, so the access process will be repeated many times. When the frequency of a certain duration (cache duration or memory duration) exceeds a certain threshold, it will be confirmed as the cache duration or memory duration. The certain threshold can be set according to actual needs, such as 50%, 60%, or any percentage greater than 50%.

[0088] In some embodiments, the branch jump instruction can be executed multiple times, that is, step S202 can be repeatedly executed multiple times. After each execution, the first channel and the second channel are accessed respectively, and the duration of accessing the first channel and the second channel is obtained respectively. The duration is compared with the preset threshold. If the duration required to access the first channel or the second channel is less than the preset threshold, it is determined that there is a side channel attack vulnerability; if the duration required to access the first channel or the second channel is greater than or equal to the preset threshold, it is determined that there is no side channel attack vulnerability. Alternatively, if the difference between the duration required to access the first channel or the second channel and the preset threshold is greater than the first threshold, it is determined that there is a side channel attack vulnerability; if the difference between the duration required to access the first channel or the second channel and the preset threshold is less than the first threshold, it is determined that there is no side channel attack vulnerability. The first threshold can be set according to actual needs. Considering that there may be differences in the access duration, the first threshold is introduced. If the difference between the duration required to access the first channel or the second channel and the preset threshold is small, it means that the duration required to access the first channel or the second channel is not much different from the preset threshold (that is, there is a certain reasonable error).

[0089] In other embodiments, the carrier does not predetermine the duration of reading data from the cache and the duration of reading data from the memory, that is, the preset threshold, but accesses the first channel, the second channel, and the third channel respectively after executing a branch jump instruction each time; the first channel and the second channel are channels related to reading secret data, and the third channel is a reference channel, which is stored in the memory. Compare the duration required to access the first channel with the duration required to access the third channel, or compare the duration required to access the second channel with the duration required to access the third channel; if the duration required to access the first channel or the second channel is less than the duration required to access the third channel, it is determined that there is a side channel attack vulnerability; if the duration required to access the first channel or the second channel is greater than or equal to the duration required to access the third channel, it is determined that there is no side channel attack vulnerability. Alternatively, if the difference between the duration required to access the first channel or the second channel and the duration required to access the third channel is greater than the first threshold, it is determined that there is a side channel attack vulnerability; if the difference between the duration required to access the first channel or the second channel and the duration required to access the third channel is less than the first threshold, it is determined that there is no side channel attack vulnerability.

[0090] In some optional embodiments, when the carrier determines that the time required to access the first channel or the second channel is less than a preset threshold, the difference between the time required to access the first channel or the second channel and the preset threshold is greater than the first threshold, the time required to access the first channel or the second channel is less than the time required to access the third channel, or the difference between the time required to access the first channel or the second channel and the time required to access the third channel is greater than the first threshold, the carrier can further determine the predicted secret information corresponding to the branch jump instruction based on the time to access the first channel and the second channel; match the predicted secret information with the secret information corresponding to the branch jump instruction, and if the predicted secret information is the same as the secret information, determine that a side channel attack vulnerability exists; if the predicted secret information is different from the secret information, determine that there is no side channel attack vulnerability.

[0091] In specific implementation, the carrier can determine the preset cache duration; the preset cache duration includes the duration required to read the data in the cache; determine the difference between the first duration required to access the first channel and the preset cache duration, and the difference between the second duration required to access the second channel and the preset cache duration; confirm that the channel with the smaller difference is loaded into the cache, and determine the predicted secret information of the branch jump instruction based on the correspondence between the channel and the value of the element. The preset cache duration can load test data into the cache in advance, access the test data and obtain the preset cache duration through register timing. In this way, the bit value read at a certain moment when the first function reads the secret data bit by bit can be accurately determined.

[0092] In this way, through the side channel attack vulnerability verification method provided by the embodiment of the present disclosure, the branch jump target address is pointed to the first path through pre-training, and an implicit jump is artificially constructed; then the branch jump target address is pointed to the second path. Since the function of the first path is to load the secret data into the cache, that is, if there is an implicit jump (i.e., jump to the first path) during the execution of the branch jump instruction, the first function will be executed, and then when the secret data is read, it will be read from the cache; the time required to read data from the cache is different from the time required to read data from the memory, it can be determined by determining the time required to read the secret data to determine whether there is an implicit jump, and then determine whether there is a side channel attack.

[0093] Figure 3 A third optional flow chart of the side channel attack vulnerability verification method provided by an embodiment of the present disclosure is shown and will be explained according to each step.

[0094] Step S301, pre-training the BTB.

[0095] In some embodiments, after the processor obtains the branch jump instruction from the memory, it will first store the address of the branch jump instruction as an index in the BTB. If the corresponding branch jump instruction address is found in the BTB at the same time, the BTB considers that the branch jump instruction is a branch instruction and has been processed before. Next, the BTB will combine the branch jump target address before the branch jump instruction to predict the path of this jump. The core idea of ​​the prediction is that for the same instruction, the path that has been executed many times before is also likely to be executed in the future. Therefore, during pre-training, the BTB should be trained as much as possible so that it can predict the jump to the set attack function attack (i.e., the first function) in subsequent attacks based on the branch jump target address.

[0096] In some embodiments, the attack function is a function for loading data. For an array consisting of multiple channels, the attack function will randomly access an element of the channel and load the data into the cache. The attack function implementation specifically includes: each element of the secret data is composed of 8 bits. In order to improve the accuracy of the test, each array element is split into 8 operations, that is, data is loaded for each bit, so that each bit of data can only be 0 or 1. If the current bit is 0, channel

[4096] (first channel) is loaded into the cache; if the current bit is 1, channel

[8192] (second channel) is loaded into the cache to prevent the cache line from affecting the test results.

[0097] Specifically, in the disclosed embodiment, the secret data is read bit by bit, and the value of the bit is either 0 or 1. If the value read is 0, channel[0] is set to 1, and if the value read is 1, channel[1] is set to 1. Affected by spatial proximity, it is very likely that when a value (such as channel[0]) is read, the platform will also add the value near channel[0] to the cache. Then, when judging later, it is impossible to distinguish whether channel[0] or channel[1] is modified (because both are taken to the cache). Therefore, in the disclosed embodiment, two channels are set to channel

[4096] and channel

[8192] . If the value of the bit read is 0, channel

[4096] is modified and added to the cache, and channel

[8192] is not affected; if the value of the bit read is 1, channel

[8192] is modified and added to the cache, and channel

[4096] is not affected, thereby avoiding the influence of cacheline. The channel setting is determined according to channel[bit_value+x]. bit_value is the value of the current bit. If the value of the bit is 0, bit_value is 0. If the value of the bit is 1, bit_value is 4096. The value of x can be set according to actual needs. In the embodiment of the present disclosure, it is set to 4096.

[0098] In some embodiments, due to the limited number of entries in the BTB, the BTB will replace the branch jump information based on two strategies: LRU (least recently used) and MPP (minimum performance potential). In the test, in order to ensure the accuracy of the results, it is necessary to ensure that the pre-trained branch jump target address is in the BTB to ensure that the predicted path of the branch jump instruction is correct.

[0099] First, two processes are set up, one is the pre-training process A, and the other is the test process B. In process A, the alarm signal is first used to set the timer to the first time interval (such as 120 seconds). In the first time interval, the branch jump instruction will be executed cyclically to the attack function, that is, the branch jump target address will be added to the BTB table. To prevent the above information from being replaced, a signal capture function is set in process B. When the alarm signal (first indication information) is triggered, the test starts.

[0100] Step S302, testing the BTB.

[0101] In some embodiments, at the beginning of the test, that is, in process B, the target address of the branch jump target address actually points to the safe_attack function (the second function), in which no operation is performed on the secret data, and the flush instruction is used to clear the cached information to prevent the pre-training results from affecting the test results. That is, in the test phase, each time a branch jump instruction is executed, the operation of clearing the data in the cache is performed.

[0102] In some embodiments, after initialization, the branch jump instruction is executed again. Under normal circumstances, in the B process, there is no permission to execute the attack function, and only the safe_attack function can be executed. If there is an implicit jump vulnerability, at this time, BTB will predict that the branch jump instruction points to the attack function (i.e., jump to the first path) based on the previously pre-trained information, and in the forward-looking state, pre-fetch a series of data used in the attack function, that is, take out a part of the data from the memory to the cache. If there is no implicit jump vulnerability, or certain protective measures are taken, the safe_attack function will be executed at this time (i.e., jump to the second path), and no operation will be performed on the secret data in the memory.

[0103] Step S303, determine whether there is a side channel attack vulnerability.

[0104] In some embodiments, after each branch jump instruction is executed, it is necessary to access the elements in the three channels of channel [0], channel

[4096] and channel

[8192] , and determine whether data (i.e., secret data) is loaded into the cache by the difference in the duration of the access, so as to infer whether the branch jump instruction predicts the execution of the attack function during the test, and determine whether the platform is vulnerable to attacks against the BTB. In order to significantly reflect the time difference between accessing the memory and accessing the cache, it is necessary to select a time unit with small precision for counting. In the disclosed embodiment, register counting is used. When the timing starts, 1 is written to the register address to pull the level high, indicating that the timer starts working. When the timing ends, 0 is written to the register address to pull the level low, indicating that the timer ends working. At this time, the timer will write the time difference into the register.

[0105] When implementing it, you should first set the threshold, that is, calculate the duration of accessing the memory (set as memory_time) and the duration of accessing the cache (set as cache_time). You can declare a temp variable (i.e. test data), and after clearing all caches, make sure that temp is in the memory, then access temp to get memory_time. cache_time can be calculated after temp is loaded, and then access temp to get cache_time. Since the results of memory_time and cache_time may fluctuate, this process will be repeated many times. When the frequency of a certain data exceeds 50%, it is considered a threshold.

[0106] After each branch jump instruction in step S302 is executed, channel[0], channel

[4096] and channel

[8192] are accessed respectively. If during the test, the BTB makes a violation prediction, i.e., predicts a jump to the attack function, then one of channel

[4096] or channel

[8192] will be illegally loaded, and the data access time will be significantly shorter. On the contrary, if the BTB does not make a violation prediction, the safe_attack function is executed, the channel data is not illegally accessed, and the access time of the array is approximately the same and approximately equal to the preset threshold.

[0107] Based on the above time results, we can infer whether the bit of the current data is 0 or 1, and thus infer the predicted secret data. Finally, we compare the predicted secret data with the preset secret data to determine whether a vulnerability exists.

[0108] In this way, the side-channel attack vulnerability verification method provided by the embodiment of the present invention can detect previously undetectable vulnerabilities such as side-channel attacks based on branch target cache. On the original basis, a side-channel attack vulnerability verification method based on BTB implicit branch jump is added. Branch jump instructions are used to control program implicit jumps, train BTB, and control the forward execution path of programs sharing the BTB, inducing the victim program to leak secrets to enter the cache, and infer cache information by accessing the time difference between the cache and the main memory. The side-channel vulnerability verification method of the arm platform is expanded, the vulnerability detection capability of the arm architecture chip is strengthened, the ability to detect unknown attacks is enhanced, and corresponding security protection can be made for newly discovered vulnerabilities in a timely manner to ensure the hardware security of the product and protect the data security of users.

[0109] Figure 4A first optional structural diagram of the side channel attack vulnerability detection device provided by an embodiment of the present disclosure is shown, and will be explained according to each step.

[0110] In some embodiments, the side channel attack vulnerability detection device 400 may include a timing module 401 , a pre-training module 402 , a testing module 403 and a result comparison module 404 .

[0111] In some embodiments, the timing module 401 uses register counting. When the timing starts, 1 is written to the register address to pull the level high, indicating that the timer starts working. When the timing ends, 0 is written to the register address to pull the level low, indicating that the timer ends working. At this time, the timer will write the time difference into the register, so that the time accuracy obtained is smaller, which can significantly reflect the time difference between accessing the cache and accessing the memory, and the result is more stable than the function using software encapsulation.

[0112] Before the test begins, you need to determine the current time to read the data in the cache and the time to read the data in the memory. You can first clear the data in the cache, and then load a. This period of time is considered to be the time to read the data in the memory. After reading, the variable a has been loaded into the cache, so a is loaded again. This period of time can be considered to be the time to read the cache. In order to ensure the stability of the data, the method of multiple readings and taking the majority is adopted. After a certain number of loops (which can be set according to actual needs, such as 1000 times), a set of cache data cache_time_array and a set of memory data memory_time_array will be obtained. These two arrays are traversed in turn. In the same array, different data values ​​are allowed to cancel each other out. The remaining values ​​are considered to be the cache duration cache_time and memory duration memory_time of this experiment.

[0113] In some embodiments, the timing module 401 is used to time the pre-training process, that is, to time the first time interval, and is also used to obtain a preset threshold, memory duration, cache duration, and during verification, to obtain the duration of reading the first channel, the duration of reading the second channel, and the duration of reading the third channel.

[0114] In some embodiments, the pre-training module 402 is used to implement step S101, step S201 and step S301.

[0115] Figure 5 It is a schematic diagram of the workflow of the pre-training module provided in the embodiment of the present disclosure.

[0116] In some embodiments, in the pre-training module 402, the BTB is mainly trained to induce the BTB to make "wrong" predictions during testing, so that the jump path of the branch jump instruction is biased towards the attack function. Since the BTB has limited entries, the BTB will replace the branch jump target address based on the LRU (least recently used) and MPP (minimum performance potential) strategies. In order to prevent the pre-trained branch jump target address from being replaced, during pre-training, such as Figure 5 As shown, the program will call (fork) a process specifically for pre-training, and set a 120s timer through the timing module 401 ( Figure 5 In the first specified time interval, set the branch jump target address (i.e. Figure 5 The branch jump address in the command is the path corresponding to the attack function. The pre-training will execute the branch jump instruction in a loop so that the branch jump instruction jumps to the attack function.

[0117] The attack function is a function that loads secret information. In a computer, all characters are stored in bits, and each bit is either 0 or 1. Figure 5 As shown in the figure, in the attack function, in order to improve the accuracy of the test, a bit-by-bit test is performed, and each character of the secret data is declared to be a uint8_t type, that is, each character consists of 8 bits. Each attack test will loop 8 times, and each character will be tested bit by bit. If the i-th bit is currently tested, and the value of the current bit is bit_value, but affected by the cacheline, each time the platform fetches data from the memory to the cache, it will also fetch nearby adjacent data. In order to eliminate this effect, in the attack function, channel[bit_value+4096] will be loaded, that is, channel

[4096] or channel

[8192] .

[0118] like Figure 5 As shown, the attack function traverses the secret data bit by bit, sets the value of the current bit to bit_value, and loads channel[bit_value+4096] accordingly, i.e., if the current bit is 0, the value is 0, and channel

[4096] is loaded; if the current bit is 1, the value is 4096, and channel

[8192] is loaded. After the channel corresponding to the current bit is loaded, it is determined whether all the secret data has been traversed. If not, the secret data continues to be traversed bit by bit; if all the secret data has been traversed, it is determined whether the pre-training is completed (i.e., whether the first time interval has arrived) and an alarm signal is generated to instruct the test module 403 to start executing the test process.

[0119] In some embodiments, the pre-training process will continuously loop the attack and execute this process within the time preset by the timer to train the branch jump behavior of the BTB. When the time is up, the system will release an alarm signal, at which time the pre-training stops and the test module 403 is executed.

[0120] Figure 6 It is a schematic diagram of the workflow of the test module provided in the embodiment of the present disclosure.

[0121] In some embodiments, Figure 6 As shown, the test module 403 captures the alarm signal and starts the test process. During the test, the branch jump target address of the preset BTB points to the safe_target function, that is, the process does not have the permission to execute the attack function. In the design of some platforms, due to the excessive pursuit of computer performance improvement, all processes will share the BTB, resulting in the prediction of the BTB only based on the previous branch jump record, while ignoring the permission issues between processes.

[0122] When the test starts, the process will also execute the branch jump instruction. After the execution is completed, the program will access channel[0], channel

[4096] , and channel

[8192] , and calculate the access time. Channel[0] is the third channel and has never been accessed. The access time of channel[0] can be set to the preset threshold.

[0123] like Figure 6 As shown, if the platform does not have a side channel attack vulnerability of implicit jump, then the attack function is not predicted to be executed, and the access time of the three channels, channel[0], channel

[4096] , and channel

[8192] , should be similar and approximately equal to memory_time (preset threshold). If the platform has a side channel attack vulnerability of implicit jump, then the attack function may be predicted to be executed in a forward-looking situation and the corresponding secret data will be retrieved. In this case, the access time of one of the channels, channel[0], channel

[4096] , and channel

[8192] , will be significantly shorter than the access time of the other two channels. If this happens, the bits loaded into the cache are inferred based on the access time, the predicted secret data is obtained, and the record is saved in the result.

[0124] Figure 7 It is a schematic diagram of the workflow of the result comparison module provided in the embodiment of the present disclosure.

[0125] In some embodiments, Figure 7As shown, the result comparison module 404 compares the predicted secret data and the secret data; if the predicted secret data is consistent with the secret data, there is a side channel attack vulnerability of implicit jump; if the predicted secret data is inconsistent with the secret data, there is no side channel attack vulnerability of implicit jump.

[0126] Figure 8 A second optional structural diagram of the side-channel attack vulnerability verification device provided by an embodiment of the present disclosure is shown, and will be explained according to each part.

[0127] In some embodiments, the side channel attack vulnerability detection device 400 may include a timing module 401 , a pre-training module 402 , a testing module 403 and a result comparison module 404 .

[0128] The pre-training module 402 is used to repeatedly execute a branch jump instruction within a first time interval, and make a branch target cache point to a first path for a branch jump target address of the branch jump instruction; the first path corresponds to a first function, and the first function is used to load secret data corresponding to the branch jump instruction into a cache;

[0129] The test module 403 is used for setting the branch target buffer to point to a second path for the branch jump target address of the branch jump instruction in response to the end of the first time interval, and executing the branch jump instruction; the second path corresponds to a second function;

[0130] The result comparison module 404 is used to determine the time required to read the secret data corresponding to the branch jump instruction in response to the completion of executing the branch jump instruction; based on the time required to read the secret data corresponding to the branch jump instruction, determine whether there is a side channel attack vulnerability.

[0131] The pre-training module 402 is specifically used to execute the branch jump instruction, and based on the branch jump target address, the branch jump instruction is processed by the first function corresponding to the first path;

[0132] The first function determines a channel loaded into the cache based on the value of each element of the secret data corresponding to the branch jump instruction, including:

[0133] In response to the value of the element being 0, the first function loads the first channel into the cache;

[0134] In response to the value of the element being 1, the first function loads the second channel into the cache.

[0135] The result comparison module 404 is specifically used to determine the time required to access the first channel, the second channel and the third channel respectively;

[0136] Determine the time required to access the first channel and the time required to access the second channel, and the time with a smaller value is the time required to read the data corresponding to the branch jump instruction;

[0137] The third channel is located in the memory, and the time required to access the third channel is determined to be a preset threshold.

[0138] In some embodiments, the side channel attack vulnerability verification device also includes 401.

[0139] The 401 is specifically used to perform the following operations on each channel:

[0140] When you start accessing any channel, pull the register level high to instruct the timer to start working;

[0141] When the data of any of the channels is read, the register level is pulled low to indicate that the timer ends its work;

[0142] The timer writes the time difference between the corresponding time of starting the work and the corresponding time of ending the work into the register, and the time difference is the time required to access any channel.

[0143] The result comparison module 404 is specifically used to determine that a side channel attack vulnerability exists in response to the time required for reading the data corresponding to the branch jump instruction being greater than a preset threshold; and to determine that no side channel attack vulnerability exists in response to the time required for reading the data corresponding to the branch jump instruction being less than or equal to the preset threshold.

[0144] The result comparison module 404 is specifically used to determine the predicted secret information of the branch jump instruction by reading the time required for the secret data corresponding to the branch jump instruction;

[0145] The predicted secret information is matched with the secret information corresponding to the branch jump instruction. If the predicted secret information is the same as the secret information, it is determined that a side channel attack vulnerability exists; if the predicted secret information is different from the secret information, it is determined that no side channel attack vulnerability exists.

[0146] The result comparison module 404 is specifically used to determine a preset cache duration; the preset cache duration includes the duration required to read the data in the cache;

[0147] Determine a difference between a first duration required to access the first channel and the preset cache duration, and a difference between a second duration required to access the second channel and the preset cache duration;

[0148] The channel with the smaller difference is confirmed to be loaded into the cache, and the predicted secret information of the branch jump instruction is determined based on the correspondence between the channel and the value of the element.

[0149] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0150] Fig. 9 A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0151] like Fig. 9 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0152] Multiple components in the electronic device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the electronic device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0153] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as the side channel attack vulnerability verification method. For example, in some embodiments, the side channel attack vulnerability verification method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the side channel attack vulnerability verification method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the side channel attack vulnerability verification method in any other appropriate manner (e.g., by means of firmware).

[0154] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0155] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0156] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0157] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0158] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communications network). Examples of communications networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0159] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0160] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0161] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0162] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A side channel attack vulnerability verification method, characterized in that: The method comprises: In a first time interval, a branch jump instruction is repeatedly executed, and a branch target cache is made to point to a first path for a branch jump target address of the branch jump instruction; the first path corresponds to a first function, and the first function is used to load secret data corresponding to the branch jump instruction into a cache; In response to the end of the first time interval, the branch target buffer is set to point to a second path for the branch jump target address of the branch jump instruction, and the branch jump instruction is executed; the second path corresponds to a second function; In response to the completion of executing the branch jump instruction, determine the time required to read the secret data corresponding to the branch jump instruction; based on the time required to read the secret data corresponding to the branch jump instruction, determine whether there is a side channel attack vulnerability.

2. The method according to claim 1, characterized in that The repeatedly executing the branch jump instruction and making the branch target buffer point to the first path for the branch jump target address of the branch jump instruction, comprises: Executing the branch jump instruction, based on the branch jump target address, processing the branch jump instruction by a first function corresponding to the first path; The first function determines a channel loaded into the cache based on the value of each element of the secret data corresponding to the branch jump instruction, including: In response to the value of the element being 0, the first function loads the first channel into the cache; In response to the value of the element being 1, the first function loads the second channel into the cache.

3. The method according to claim 2, characterized in that The determining of the time required for reading the data corresponding to the branch jump instruction includes: Determine the duration required to access the first channel, the second channel, and the third channel respectively; Determine the time required to access the first channel and the time required to access the second channel, and the time with a smaller value is the time required to read the data corresponding to the branch jump instruction; The third channel is located in the memory, and the time required to access the third channel is determined to be a preset threshold.

4. The method according to claim 3, characterized in that: Determine the duration required to access the first channel, the second channel, and the third channel, respectively, including performing the following operations on each channel: When you start accessing any channel, pull the register level high to instruct the timer to start working; When the data of any of the channels is read, the register level is pulled low to indicate that the timer ends its work; The timer writes the time difference between the corresponding time of starting the work and the corresponding time of ending the work into the register, and the time difference is the time required to access any channel.

5. The method according to claim 1 or 3, characterized in that: The determining whether there is a side channel attack vulnerability based on the time required to read the data corresponding to the branch jump instruction includes: In response to the time required to read the data corresponding to the branch jump instruction being greater than a preset threshold, it is determined that a side channel attack vulnerability exists; in response to the time required to read the data corresponding to the branch jump instruction being less than or equal to the preset threshold, it is determined that no side channel attack vulnerability exists.

6. The method according to claim 1 or 3, characterized in that: The determining whether there is a side channel attack vulnerability based on the time required to read the data corresponding to the branch jump instruction includes: Determine the predicted secret information of the branch jump instruction by reading the time required for the secret data corresponding to the branch jump instruction; The predicted secret information is matched with the secret information corresponding to the branch jump instruction. If the predicted secret information is the same as the secret information, it is determined that a side channel attack vulnerability exists; if the predicted secret information is different from the secret information, it is determined that no side channel attack vulnerability exists.

7. The method according to claim 6, characterized in that The step of determining the predicted secret information of the branch jump instruction by reading the time required for the data corresponding to the branch jump instruction includes: Determine a preset cache duration; the preset cache duration includes the duration required to read data in the cache; Determine a difference between a first duration required to access the first channel and the preset cache duration, and a difference between a second duration required to access the second channel and the preset cache duration; The channel with the smaller difference is confirmed to be loaded into the cache, and the predicted secret information of the branch jump instruction is determined based on the correspondence between the channel and the value of the element.

8. A side channel attack vulnerability verification device, characterized in that: The device comprises: A pre-training module is used to repeatedly execute a branch jump instruction within a first time interval, and to make a branch target cache point to a first path for a branch jump target address of the branch jump instruction; the first path corresponds to a first function, and the first function is used to load secret data corresponding to the branch jump instruction into a cache; A test module, configured to, in response to the end of the first time interval, set a branch target buffer to point a branch jump target address of a branch jump instruction to a second path, and execute the branch jump instruction; the second path corresponds to a second function; The result comparison module is used to determine the time required to read the secret data corresponding to the branch jump instruction in response to the completion of the execution of the branch jump instruction; based on the time required to read the secret data corresponding to the branch jump instruction, determine whether there is a side channel attack vulnerability.

9. An electronic device, characterized in that: include: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to make a computer execute the method according to any one of claims 1-7.

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