Pixel array, arrangement structure, image sensor and control method

Abstract

The invention provides a pixel array, an arrangement structure, an image sensor and a control method.The pixel array comprises a plurality of pixel blocks arranged in rows and columns, and each pixel block comprises a first photosensitive unit, a second photosensitive unit, a first reset unit, a second reset unit, a first signal output unit, a second signal output unit, a first gain control unit and a second gain control unit; the first photosensitive unit is coupled to the first floating diffusion node, the first reset unit is coupled between the first pixel power supply and the first floating diffusion node, and the first signal output unit is coupled to the first floating diffusion node and outputs a first pixel signal; the second photosensitive unit is coupled to the second floating diffusion node, the second reset unit is coupled between the second pixel power supply and the second floating diffusion node, and the second signal output unit is coupled to the second floating diffusion node and outputs a second pixel signal; the first gain control unit and the second gain control unit are coupled between the first floating diffusion node and the second floating diffusion node after being connected in series.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and in particular to a pixel array, an arrangement structure, an image sensor and a control method. Background Art

[0002] With the increasing development of image sensors, their applications in various fields (e.g., mobile phones, security, and automotive) are becoming more and more extensive. At present, the pixel circuit structure of image sensors is simple. In addition, in terms of imaging performance, in addition to conventional parameter requirements, it is often necessary to flexibly read out different types of data, and the focus performance requirements of image sensors are also getting higher and higher. The traditional contrast focus method is gradually being eliminated due to its slow focusing speed; phase focus (PDAF) is increasingly replacing contrast focus as an alternative due to its high-speed focusing performance.

[0003] In addition, dynamic range is a key factor in the imaging quality of image sensors. A large dynamic range can output scene image information within a wider range of light intensity, presenting richer image details. Normally, the dynamic range of image sensor output is about 60db-70db; in general natural environment applications, the dynamic range required to capture image information of highlights and shadows at the same time is about 100db. Therefore, how to maintain a high dynamic range under full-pixel PDAF has become a technical problem that urgently needs to be solved. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a pixel array, an arrangement structure, an image sensor and a control method, which are used to solve the problems in the prior art such as the single pixel circuit structure and the inability to achieve high dynamic range under full-pixel PDAF.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a pixel array, comprising a plurality of pixel blocks arranged in rows and columns, wherein the pixel blocks include: a first photosensitive unit, a second photosensitive unit, a first reset unit, a second reset unit, a first signal output unit, a second signal output unit, a first gain control unit, and a second gain control unit; wherein:

[0006] The first photosensitive unit is coupled to a first floating diffusion node, the first reset unit is coupled between a first pixel power source and the first floating diffusion node, and the first signal output unit is coupled to the first floating diffusion node and outputs a first pixel signal;

[0007] The second photosensitive unit is coupled to the second floating diffusion node, the second reset unit is coupled between the second pixel power supply and the second floating diffusion node, and the second signal output unit is coupled to the second floating diffusion node and outputs a second pixel signal;

[0008] The first gain control unit and the second gain control unit are connected in series and coupled between the first floating diffusion node and the second floating diffusion node.

[0009] Optionally, the first reset unit includes a first reset transistor, the second reset unit includes a second reset transistor, the first signal output unit includes a first source follower transistor, the second signal output unit includes a second source follower transistor, the first gain control unit includes a first gain transistor, and the second gain control unit includes a second gain transistor; wherein:

[0010] The control end of the first reset transistor receives a first reset control signal, the first end is coupled to the first pixel power supply, and the second end is coupled to the first floating diffusion node and coupled to the first end of the first gain transistor; the control end of the first source follower transistor is coupled to the first floating diffusion node, the first end is coupled to the third pixel power supply, and the second end outputs the first pixel signal;

[0011] The control terminal of the second reset transistor receives the second reset control signal, the first terminal is coupled to the second pixel power supply, and the second terminal is coupled to the second floating diffusion node and coupled to the first terminal of the second gain transistor; the control terminal of the second source follower transistor is coupled to the second floating diffusion node, the first terminal is coupled to the fourth pixel power supply, and the second terminal outputs the second pixel signal;

[0012] The control end of the first gain transistor receives a first gain control signal, and the second end is coupled to the second end of the second gain transistor; the control end of the second gain transistor receives a second gain control signal.

[0013] Optionally, the pixel block further includes a selection control unit coupled to output ends of the first signal output unit and the second signal output unit and outputting a pixel signal.

[0014] Optionally, the selection control unit includes a selection transistor. When the first signal output unit includes a first source follower transistor and the second signal output unit includes a second source follower transistor, the control end of the selection transistor receives a selection control signal, the first end is coupled to the second ends of the first source follower transistor and the second source follower transistor, and the second end outputs the pixel signal.

[0015] Optionally, in the same column, the second ends of the selection transistors are coupled to the same column line; or, in the same column, the second ends of two adjacent selection transistors are coupled to different column lines.

[0016] Optionally, the selection control unit includes a first selection transistor and a second selection transistor, and when the first signal output unit includes a first source follower transistor and the second signal output unit includes a second source follower transistor,

[0017] The control terminal of the first selection transistor receives a first selection control signal, the first terminal is coupled to the second terminal of the first source follower transistor, and the second terminal outputs the first pixel signal;

[0018] The control terminal of the second selection transistor receives a second selection control signal, the first terminal is coupled to the second terminal of the second source follower transistor, and the second terminal outputs the second pixel signal.

[0019] Optionally, the second terminals of the first selection transistor and the second selection transistor are coupled to the same or different column lines.

[0020] Optionally, when the second terminals of the first selection transistor and the second selection transistor are coupled to different column lines:

[0021] In the same column, the second terminals of the first selection transistors are coupled to the same column line, and the second terminals of the second selection transistors are coupled to the same column line;

[0022] Alternatively, in the same column, the second ends of two adjacent first selection transistors are coupled to different column lines, and the second ends of two adjacent second selection transistors are coupled to different column lines.

[0023] Optionally, the first photosensitive unit and the second photosensitive unit have the same circuit, including at least one photosensitive element and a corresponding transmission transistor;

[0024] The control end of the transmission transistor receives a transmission control signal, the first end is coupled to the corresponding floating diffusion node, and the second end is coupled to the first end of the photosensitive element; the second end of the photosensitive element is coupled to the first reference potential;

[0025] And / or, the pixel array further includes a plurality of filter areas, the filter areas correspond to the pixel blocks one by one, or the pixel array includes a plurality of color acquisition units, the color acquisition units correspond to the pixel blocks one by one, and each of the color acquisition units corresponds to a plurality of filter areas, so as to acquire color information based on the color acquisition units;

[0026] And / or, the pixel array further includes a plurality of micro lenses, and the micro lenses correspond to the pixel blocks one by one, or one pixel block corresponds to a plurality of micro lenses arranged in an array.

[0027] Optionally, the first photosensitive unit and the second photosensitive unit each include four photosensitive elements and four transmission transistors corresponding to the photosensitive elements.

[0028] Optionally, the pixel block also includes a gain capacitor coupled between a coupling node between the first gain control unit and the second gain control unit and a second reference potential; and / or, the pixel block also includes at least one gain adjustment switch, which is connected in series between the first gain control unit and the second gain control unit.

[0029] The present invention further provides an arrangement structure of a pixel array as described in any one of the above items, comprising:

[0030] The transmission transistors corresponding to the photosensitive elements in the first photosensitive unit are enclosed to form a first enclosed area, and the transmission transistors corresponding to the photosensitive elements in the second photosensitive unit are enclosed to form a second enclosed area, and the first enclosed area and the second enclosed area are arranged in parallel in the row direction;

[0031] The first resetting unit is disposed outside the first enclosed area and above the first enclosed area, and the second resetting unit is disposed outside the second enclosed area and above the second enclosed area;

[0032] The first gain control unit is disposed at one side of the first reset unit, the second gain control unit is disposed at one side of the second reset unit, and the first gain control unit and the second gain control unit are disposed adjacent to each other.

[0033] Optionally, when the first reset unit includes a first reset transistor, the second reset unit includes a second reset transistor, the first signal output unit includes a first source follower transistor, the second signal output unit includes a second source follower transistor, the first gain control unit includes a first gain transistor, and the second gain control unit includes a second gain transistor:

[0034] The first source follower transistor is disposed in the first enclosed area, and the second source follower transistor is disposed in the second enclosed area;

[0035] The first floating diffusion node is disposed in the first enclosed area and disposed on both sides of the first source follower transistor, and the second floating diffusion node is disposed in the second enclosed area and disposed on both sides of the second source follower transistor;

[0036] The first reset transistor is disposed outside the first enclosed area and above the first source follower transistor, and the second reset transistor is disposed outside the second enclosed area and above the second source follower transistor;

[0037] The first gain transistor is disposed at one side of the first reset transistor, the second gain transistor is disposed at one side of the second reset transistor, and the first gain transistor and the second gain transistor are disposed adjacent to each other.

[0038] Optionally, the pixel block further includes a selection control unit, which is arranged below the first enclosed area and the second enclosed area; wherein:

[0039] When the selection control unit includes a selection transistor, the selection transistor is arranged below the second source follower transistor in the second signal output unit and arranged on the other side of the second reset transistor in the second reset unit;

[0040] When the selection control unit includes a first selection transistor and a second selection transistor, the first selection transistor is arranged below the first source follower transistor in the first signal output unit and on the other side of the first reset transistor in the first reset unit, and the second selection transistor is arranged below the second source follower transistor in the second signal output unit and on the other side of the second reset transistor in the second reset unit.

[0041] Optionally, the first photosensitive unit and the second photosensitive unit each include four photosensitive elements and corresponding four transmission transistors, the four photosensitive elements are arranged in an array, the four transmission transistors are in a strip shape, and are correspondingly arranged at the opposite corners of the four photosensitive elements at an inclined angle to respectively form the first enclosed area and the second enclosed area; and / or, each of the photosensitive elements is arranged in a rectangular shape, and two adjacent photosensitive elements in the row direction are arranged in a square shape.

[0042] The present invention also provides an image sensor, comprising the pixel array as described in any one of the above items.

[0043] The present invention also provides a control method for the image sensor as described above, comprising:

[0044] The first gain control unit and the second gain control unit in the pixel block are controlled to be turned on and off to control the pixel block to enter a merging mode or a gain mode.

[0045] Optionally, when the first gain control unit includes a first gain transistor and the second gain control unit includes a second gain transistor, the control method includes:

[0046] Controlling the first gain transistor and the second gain transistor in the pixel block to turn on, so that the pixel block enters a merging mode;

[0047] Controlling at least one of the first gain transistor and the second gain transistor in the pixel block to turn on, so that two pixel circuits in the pixel block enter respective gain modes;

[0048] The first pixel circuit includes a first photosensitive unit, a first reset transistor, a first source follower transistor and the first gain transistor, and the second pixel circuit includes a second photosensitive unit, a second reset transistor, a second source follower transistor and the second gain transistor; wherein:

[0049] Controlling the first gain transistor in the pixel block to be turned on and the second gain transistor to be turned off, so that the first pixel circuit enters a low conversion gain mode and the second pixel circuit enters a high conversion gain mode;

[0050] Controlling the first gain transistor in the pixel block to be turned off and the second gain transistor to be turned on, so that the first pixel circuit enters a high conversion gain mode and the second pixel circuit enters a low conversion gain mode;

[0051] The first gain transistor and the second gain transistor in the pixel block are controlled to be turned off, so that the first pixel circuit and the second pixel circuit enter a high conversion gain mode.

[0052] Optionally, when the pixel block further includes at least one gain adjustment switch, the control method includes:

[0053] Controlling the opening and closing of the first gain control unit and the second gain control unit in the pixel block and coordinating with adjusting the opening and closing of the gain adjustment switch to control the pixel block to enter a merging mode or a gain mode;

[0054] Wherein, in the gain mode, at least one of the gain adjustment switches is controlled to be closed, so that the two pixel circuits in the pixel block enter their respective gain modes.

[0055] Optionally, the first gain control unit also corresponds to a first selection transistor, and the second gain control unit also corresponds to a second selection transistor. The first selection transistor and the second selection transistor are read out through different column lines, so that the first pixel circuit and the second pixel circuit are read out simultaneously in their respective gain modes.

[0056] Optionally, the control method includes implementing phase focusing based on the pixel block; wherein:

[0057] When the pixel block corresponds to one microlens: dividing the pixel group corresponding to the pixel block into two sensing areas via an axis passing through the center of the microlens, and acquiring focusing information based on the two sensing areas to perform phase focusing;

[0058] When the pixel block corresponds to at least two microlenses arranged in an array, phase focusing is performed based on the pixels at the corresponding positions of each of the microlenses, wherein when the pixel block corresponds to four microlenses arranged in an array, the first photosensitive unit of the pixel block includes a first photosensitive group and a second photosensitive group corresponding to each other, and the second photosensitive unit of the pixel block includes a third photosensitive group and a fourth photosensitive group corresponding to each other, and each photosensitive group corresponds to each microlens, wherein: if the four microlenses correspond to different colors, for any color, focusing information is obtained based on the corresponding photosensitive group to perform phase focusing; if the four microlenses correspond to the same color, focusing information is obtained based on the corresponding pixels of the four photosensitive groups to perform phase focusing.

[0059] As described above, the pixel array, arrangement structure, image sensor and control method of the present invention propose a new pixel circuit structure through the design of the first photosensitive unit, the second photosensitive unit, the first reset unit, the second reset unit, the first signal output unit, the second signal output unit, the first gain control unit and the second gain control unit in the pixel block, which can not only achieve high dynamic range under full-pixel PDAF, but also realize the merging of pixels of the same color in the charge domain; moreover, by selecting the design of the control unit, it is also possible to realize the simultaneous readout of two pixel circuits in the pixel block in their respective gain modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1-Figure 3 It is a schematic diagram showing the structure of the pixel array selection control unit of the present invention when it includes a selection transistor, wherein: Figure 1 Corresponding to a column line, Figure 2 Corresponding to 2 column lines, Figure 3 Corresponding to 4 column lines.

[0061] Figure 4 Display as Figure 2 A schematic diagram of a first pixel circuit and a second pixel circuit in a pixel block in a merging mode is shown.

[0062] Figure 5 Display as Figure 4 Timing diagram for the pixel block shown.

[0063] Figure 6 Display as Figure 2 A schematic diagram showing a first pixel circuit in a high conversion gain mode and a second pixel circuit in a low conversion gain mode in a pixel block.

[0064] Figure 7 Display as Figure 6 Timing diagram for the pixel block shown.

[0065] Figure 8 Display as Figure 1-Figure 3 Schematic diagram of the arrangement structure of the pixel array shown.

[0066] Figure 9-11 It is a schematic diagram showing the structure of the pixel array selection control unit of the present invention when it includes a first selection transistor and a second selection transistor, wherein: Fig. 9 Corresponding to a column line, Fig.10 Corresponding to 2 column lines, Fig.11 Corresponding to 4 column lines.

[0067] Fig.12 Display as Fig.10 A schematic diagram of a first pixel circuit and a second pixel circuit in a pixel block in a merging mode is shown.

[0068] Fig.13 Display as Fig.12 Timing diagram for the pixel block shown.

[0069] Fig.14 Display as Fig.10 A schematic diagram showing a first pixel circuit in a high conversion gain mode and a second pixel circuit in a low conversion gain mode in a pixel block.

[0070] Fig.15 Display as Fig.14 Timing diagram for the pixel block shown.

[0071] Fig.16 Display as Figure 9-11 Schematic diagram of the arrangement structure of the pixel array shown.

[0072] Fig.17 It shows an embodiment of the arrangement of the filter areas corresponding to the pixel array of the present invention.

[0073] Fig.18 Display as Fig.10 The schematic diagram shown is a schematic diagram of diagonal pixels in the same pixel block outputting the same gain mode.

[0074] Component number description

[0075] 100 pixel array

[0076] 110 pixel block

[0077] 111 First photosensitive unit

[0078] 112 Second photosensitive unit

[0079] 113 First reset unit

[0080] 114 Second reset unit

[0081] 115 First signal output unit

[0082] 116 Second signal output unit

[0083] 117 First gain control unit

[0084] 118 Second gain control unit

[0085] 119 Select control unit DETAILED DESCRIPTION

[0086] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0087] See also Figures 1 to 18 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0088] Embodiment 1

[0089] like Figure 1-Figure 3 and Figure 9-11 As shown, this embodiment provides a pixel array 100, including a plurality of pixel blocks 110 arranged in rows and columns; the pixel block 110 includes a first photosensitive unit 111, a second photosensitive unit 112, a first reset unit 113, a second reset unit 114, a first signal output unit 115, a second signal output unit 116, a first gain control unit 117 and a second gain control unit 118. Wherein:

[0090] The first photosensitive unit 111 is coupled to the first floating diffusion node FD1 , and the second photosensitive unit 112 is coupled to the second floating diffusion node FD2 , for receiving a light signal and generating a charge signal based on the light signal.

[0091] Specifically, the circuits of the first photosensitive unit 111 and the second photosensitive unit 112 are the same, including at least one photosensitive element and a corresponding transfer transistor; wherein the control end of the transfer transistor receives a transmission control signal, the first end is coupled to the corresponding floating diffusion node, the second end is coupled to the first end of the photosensitive element, and the second end of the photosensitive element is coupled to the first reference potential.

[0092] As an optional solution, the first photosensitive unit 111 and the second photosensitive unit 112 each include four photosensitive elements and four transmission transistors corresponding to the photosensitive elements.

[0093] As an example, the photosensitive element can be any one of a photodiode, a grating or a photoconductor, and the transfer transistor can be any one of an NMOS tube or a PMOS tube; in this embodiment, the photosensitive element is a photodiode, such as a pin-type photodiode, and the transfer transistor is an NMOS tube.

[0094] For example, the first photosensitive unit 111 includes four photodiodes PD1-PD4 and four NMOS tubes M11-M14, and the second photosensitive unit 112 includes four photodiodes PD5-PD8 and four NMOS tubes M15-M18; for the first photosensitive unit 111: the anode end of the photodiodes PD1-PD4 is connected to the first reference potential, the cathode end is correspondingly connected to the source end of the NMOS tubes M11-M14, the gate end of the NMOS tubes M11-M14 is correspondingly connected to the transmission control signal TX1-TX4, and the drain end is connected to the first floating diffusion node FD1; for the second photosensitive unit 112: the anode end of the photodiodes PD5-PD8 is connected to the first reference potential, the cathode end is correspondingly connected to the source end of the NMOS tubes M15-M18, the gate end of the NMOS tubes M15-M18 is correspondingly connected to the transmission control signal TX5-TX8, and the drain end is connected to the second floating diffusion node FD2. In practical applications, the first reference potential is usually a reference ground potential. In other embodiments, the first reference potential can also be a negative potential.

[0095] The first reset unit 113 is coupled between the first pixel power source RSTD1 and the first floating diffusion node FD1 , and the second reset unit 114 is coupled between the second pixel power source RSTD2 and the second floating diffusion node FD2 , for performing a reset operation on the corresponding floating diffusion node.

[0096] Specifically, the first reset unit 113 includes a first reset transistor, a control end receiving a first reset control signal RST1, a first end coupled to a first pixel power supply RSTD1, and a second end coupled to a first floating diffusion node FD1; the second reset unit 114 includes a second reset transistor, a control end receiving a second reset control signal RST2, a first end coupled to a second pixel power supply RSTD2, and a second end coupled to a second floating diffusion node FD2.

[0097] As an example, the first reset transistor and the second reset transistor may be any one of an NMOS transistor and a PMOS transistor; in this embodiment, the first reset transistor and the second reset transistor are NMOS transistors.

[0098] Take the example that the first reset transistor includes an NMOS tube M21 and the second reset transistor includes an NMOS tube M22; for the first reset transistor: the gate end of the NMOS tube M21 is connected to the first reset control signal RST1, the drain end is connected to the first pixel power supply RSTD1, and the source end is connected to the first floating diffusion node FD1; for the second reset transistor: the gate end of the NMOS tube M22 is connected to the second reset control signal RST2, the drain end is connected to the second pixel power supply RSTD2, and the source end is connected to the second floating diffusion node FD2. Among them, the first reset transistor is turned on when the first reset control signal RST1 is valid and the first pixel power supply RSTD1 is at a high potential, and the second reset transistor is turned on when the second reset control signal RST2 is valid and the second pixel power supply RSTD2 is at a high potential. In addition, the opening and closing of the corresponding source follower transistor can be controlled based on the first pixel power supply RSTD1 and the second pixel power supply RSTD2, for example, in the case where Figure 1 In the example shown, it may be advantageous to control the output of a signal based on a pixel selection transistor.

[0099] In practical applications, the corresponding pixel power supply can be designed to always be at a high potential, and the corresponding reset control signal can be controlled to realize the opening and closing of the corresponding reset transistor; the corresponding reset control signal can be designed to always be valid, and the corresponding reset transistor can be realized by controlling the corresponding pixel power supply; of course, the corresponding pixel power supply and the corresponding reset control signal can also be controlled at the same time to realize the opening and closing of the corresponding reset transistor.

[0100] The first signal output unit 115 is coupled to the first floating diffusion node FD1 and outputs a first pixel signal, and the second signal output unit 116 is coupled to the second floating diffusion node FD2 and outputs a second pixel signal.

[0101] Specifically, the first signal output unit 115 includes a first source follower transistor, a control end coupled to the first floating diffusion node FD1, a first end coupled to the third pixel power supply VDD1, and a second end outputting a first pixel signal; the second signal output unit 116 includes a second source follower transistor, a control end coupled to the second floating diffusion node FD2, a first end coupled to the fourth pixel power supply VDD2, and a second end outputting a second pixel signal.

[0102] As an example, the first source follower transistor and the second source follower transistor may be any one of an NMOS transistor and a PMOS transistor; in this embodiment, the first source follower transistor and the second source follower transistor are NMOS transistors.

[0103] Take the first source follower transistor including NMOS transistor M31 and the second source follower transistor including NMOS transistor M32 as an example; for the first source follower transistor: the gate end of NMOS transistor M31 is connected to the first floating diffusion node FD1, the drain end is connected to the third pixel power supply VDD1, and the source end outputs the first pixel signal; for the second source follower transistor: the gate end of NMOS transistor M32 is connected to the second floating diffusion node FD2, the drain end is connected to the fourth pixel power supply VDD2, and the source end outputs the second pixel signal. Among them, when the third pixel power supply VDD1 is at a high potential, the first source follower transistor has an output, and when the fourth pixel power supply VDD2 is at a high potential, the second source follower transistor has an output; in practical applications, the design of the third pixel power supply VDD1 and the fourth pixel power supply VDD2 can be used to control whether the corresponding source follower transistor outputs.

[0104] The first gain control unit 117 and the second gain control unit 118 are connected in series and coupled between the first floating diffusion node FD1 and the second floating diffusion node FD2, and are used to form a modulation storage area with the corresponding floating diffusion node, and form a voltage signal (i.e., a pixel signal, including a reset signal and an image signal) corresponding to the charge signal based on the modulation storage area.

[0105] Specifically, the first gain control unit 117 includes a first gain transistor, and the second gain control unit 118 includes a second gain transistor; wherein, the control end of the first gain transistor receives a first gain control signal DCG1, the first end is coupled to the first floating diffusion node FD1, and the second end is coupled to the second end of the second gain transistor; the control end of the second gain transistor receives a second gain control signal DCG2, the first end is coupled to the second floating diffusion node FD2, and the second end is coupled to the second end of the first gain transistor.

[0106] As an example, the first gain transistor and the second gain transistor may be any one of an NMOS transistor and a PMOS transistor; in this embodiment, the first gain transistor and the second gain transistor are NMOS transistors.

[0107] Taking the first gain transistor including the NMOS tube M41 and the second gain transistor including the NMOS tube M42 as an example; for the first gain transistor: the gate terminal of the NMOS tube M41 is connected to the first gain control signal DCG1, the drain terminal is connected to the first floating diffusion node FD1, and the source terminal is connected to the source terminal of the NMOS tube M42; for the second gain transistor: the gate terminal of the NMOS tube M42 is connected to the second gain control signal DCG2, the drain terminal is connected to the second floating diffusion node FD2, and the source terminal is connected to the source terminal of the NMOS tube M41.

[0108] In this embodiment, the first gain transistor and the first floating diffusion node FD1 form a first modulation storage area, and the second gain transistor and the second floating diffusion node FD2 form a second modulation storage area; when the first gain transistor is turned off, the capacity of the first modulation storage area is the capacity of the first floating diffusion node FD1, and when the first gain transistor is turned on, the capacity of the first modulation storage area is the sum of the capacity of the first floating diffusion node FD1 and the capacity corresponding to the first gain transistor; when the second gain transistor is turned off, the capacity of the second modulation storage area is the capacity of the second floating diffusion node FD2, and when the second gain transistor is turned on, the capacity of the second modulation storage area is the sum of the capacity of the second floating diffusion node FD2 and the capacity corresponding to the second gain transistor.

[0109] In this embodiment, the second ends of the first gain transistor and the second gain transistor are directly connected, and the first gain transistor and the second gain transistor cannot be turned on at the same time to adjust the capacity of their respective modulation storage areas, and only one of them can be turned on and the other closed; in order to enable the first gain transistor and the second gain transistor to be turned on at the same time, the pixel block 110 of this embodiment also includes at least one gain adjustment switch (not shown in the figure), which is connected in series between the first gain transistor in the first gain control unit 117 and the second end of the second gain transistor in the second gain control unit 118, for example, at least one gain adjustment switch is connected in series between the NMOS tube M41 and the NMOS tube M42. Among them, the gain adjustment switch can be any one of an NMOS tube or a PMOS tube, and in this embodiment, NMOS tubes are selected.

[0110] Among them, when the number of gain adjustment switches is multiple (i.e., greater than one), through the opening and closing design of multiple gain adjustment switches, not only can the first gain transistor and the second gain transistor be turned on at the same time to adjust the capacity of their respective modulation storage areas, but the capacity values ​​of the corresponding modulation storage areas can also be diversified, thereby adding more gain modes.

[0111] In practical applications, the capacity corresponding to the corresponding gain transistor can be provided by parasitic capacitance, or the capacity corresponding to the corresponding gain transistor can be provided by device capacitance, which has no substantial impact on this embodiment. When the capacity corresponding to the corresponding gain transistor is provided by device capacitance, the pixel block 110 of this embodiment also includes a gain capacitor (not shown in the figure), which is coupled between the coupling node of the first gain control unit 117 and the second gain control unit 118 and the second reference potential; when the pixel block 110 of this embodiment also includes a gain adjustment switch, a gain capacitor can be provided between each coupling node formed by the first gain control unit 117, the gain adjustment switch and the second gain control unit 118 connected in series and the second reference potential; wherein the second reference potential is usually a reference ground potential, and of course, it can also be set to a variable voltage according to actual needs.

[0112] Furthermore, the pixel block 110 of the present embodiment further includes a selection control unit 119 coupled to output ends of the first signal output unit 115 and the second signal output unit 116 and outputting a pixel signal.

[0113] Specifically, in a possible implementation manner, as Figure 1-Figure 3 As shown, the selection control unit 119 includes a selection transistor, a control end receives a selection control signal RS, a first end is coupled to the first source follower transistor in the first signal output unit 115 and the second end of the second source follower transistor in the second signal output unit 116, and the second end outputs a pixel signal. In this embodiment, the first source follower transistor and the second source follower transistor share the same selection transistor, and the first pixel signal and the second pixel signal are read out in sequence through the selection transistor.

[0114] In the same column, the second end of each selection transistor is coupled to the same column line to read out each row of pixel blocks row by row. Figure 1 As shown; or, in the same column, the second ends of two adjacent selection transistors are coupled to different column lines to simultaneously read out at least two rows of pixel blocks, thereby increasing the readout speed and the image frame rate, such as Figure 2 and Figure 3 shown.

[0115] It should be noted that the second ends of two adjacent selection transistors in the same column are coupled to different column lines. The second ends of all selection transistors in the same column may be coupled to different column lines, or the second ends of some selection transistors in the same column may be coupled to different column lines. For example, a column of selection transistors may be divided into multiple groups, and the corresponding selection transistors in each group are connected to the same column line. For example, Figure 2 As shown, the same column of pixel blocks is divided into two groups, each of which shares two column lines BL1 and BL2. Figure 3 As shown, the pixel blocks in the same column are divided into four groups which respectively share four column lines BL1, BL2, BL3, and BL4.

[0116] As an example, the selection transistor may be any one of an NMOS transistor or a PMOS transistor; in this embodiment, the selection transistor is an NMOS transistor. Taking the selection transistor including an NMOS transistor M5 as an example, the gate end of the NMOS transistor M5 is connected to the selection control signal RS, the drain end is connected to the second end of the first source follower transistor and the second source follower transistor, and the source end outputs a pixel signal.

[0117] In another possible implementation, Figure 9-11As shown, the selection control unit 119 includes a first selection transistor and a second selection transistor; wherein, the control end of the first selection transistor receives the first selection control signal RS1, the first end is coupled to the second end of the first source follower transistor in the first signal output unit 115, and the second end outputs the first pixel signal; the control end of the second selection transistor receives the second selection control signal RS2, the first end is coupled to the second end of the second source follower transistor in the second signal output unit 116, and the second end outputs the second pixel signal.

[0118] The second ends of the first selection transistor and the second selection transistor are coupled to the same column line to sequentially read out two pixel signals in the same pixel block. Fig. 9 Alternatively, the second ends of the first selection transistor and the second selection transistor are coupled to different column lines to simultaneously read out two pixel signals in the same pixel block, such as Fig.10 and Fig.11 shown.

[0119] When the second ends of the first selection transistor and the second selection transistor are coupled to different column lines: in the same column, the second ends of the first selection transistors are coupled to the same column line, and the second ends of the second selection transistors are coupled to the same column line, so as to read out each row of pixel blocks row by row. Fig.10 As shown; or, in the same column, the second ends of two adjacent first selection transistors are coupled to different column lines, and the second ends of two adjacent second selection transistors are coupled to different column lines, so as to simultaneously read out at least two rows of pixel blocks, thereby improving the readout speed and the image frame rate, such as Fig.11 shown.

[0120] It should be noted that the second ends of two adjacent first selection transistors in the same column are coupled to different column lines. The second ends of all the first selection transistors in the same column may be coupled to different column lines, or the second ends of some of the first selection transistors in the same column may be coupled to different column lines. For example, a column of first selection transistors is divided into multiple groups, and the corresponding first selection transistors in each group are connected to the same column line. The same is true for the second selection transistors and will not be repeated.

[0121] As an example, the first selection transistor and the second selection transistor may be any one of an NMOS transistor and a PMOS transistor; in this embodiment, the first selection transistor and the second selection transistor are NMOS transistors.

[0122] Taking the first selection transistor including the NMOS tube M51 and the second selection transistor including the NMOS tube M52 as an example; for the first selection transistor: the gate end of the NMOS tube M51 is connected to the first selection control signal RS1, the drain end is connected to the second end of the first source follower transistor, and the source end outputs the first pixel signal; for the second selection transistor: the gate end of the NMOS tube M52 is connected to the second selection control signal RS2, the drain end is connected to the second end of the second source follower transistor, and the source end outputs the second pixel signal.

[0123] In this embodiment, the pixel array 100 further includes a plurality of filter regions, which correspond to the pixel blocks 110 one by one and are arranged above the pixel blocks 110 so that the corresponding pixel blocks 110 receive light of a specific color, such as Fig.17 As shown, each pixel block 110 corresponds to a color filter of one color. In the 8 pixel blocks shown, the color filters of different colors form two groups of Bayer array arrangements, that is, the pixel block 110 receives red (R), green (G) and blue (B) light to form an RGGB Bayer array. In other embodiments, the pixel array may include a plurality of color acquisition units, the color acquisition units correspond to the pixel blocks one by one, and each color acquisition unit corresponds to a plurality of filter areas to acquire color information based on the color acquisition unit, such as a pixel block 110 corresponds to four filter areas arranged in an array, so that the corresponding pixel block receives light of different colors. For example, a pixel block 110 corresponds to a color acquisition unit, and each color acquisition unit corresponds to a color filter of a different color, such as each color acquisition unit corresponds to receiving red (R), green (G) and blue (B) light to form an RGGB Bayer array. In an example in which a pixel block includes 8 pixels, the 8 pixels may be combined in pairs to form an RGGB Bayer array arrangement. It should be noted that the color filter area for obtaining color can be a color filter of various colors, such as red, green, blue, yellow, cyan, magenta, etc., and can also be a transparent filter that transmits white light and visible light, or an IR filter that transmits infrared light.

[0124] In addition, in one embodiment, the pixel array 100 further includes a plurality of micro lenses (not shown in the figure), and the micro lenses correspond to the pixel blocks 110 one by one and are arranged above the pixel blocks 110; in other embodiments, one pixel block 110 may correspond to a plurality of micro lenses arranged in an array, for example, one pixel block 110 may correspond to four micro lenses arranged in an array, for example, Fig.17 As shown, eight micro lenses in each pixel block may be arranged in pairs corresponding to four arrays.

[0125] Correspondingly, such as Figure 8 and Fig.16As shown, the present embodiment also provides an arrangement structure of the pixel array 100 as described above, including: the transfer transistors corresponding to the photosensitive elements in the first photosensitive unit 111 are enclosed to form a first enclosed area, and the transfer transistors corresponding to the photosensitive elements in the second photosensitive unit 112 are enclosed to form a second enclosed area, and the first enclosed area and the second enclosed area are arranged in parallel in the row direction; the first reset unit 113 is arranged outside the first enclosed area and above the first enclosed area, and the second reset unit 114 is arranged outside the second enclosed area and above the second enclosed area; the first gain control unit 117 is arranged on one side of the first reset unit 113, the second gain control unit 118 is arranged on one side of the second reset unit 114, and the first gain control unit 117 and the second gain control unit 118 are arranged adjacent to each other.

[0126] In addition, the first signal output unit 115 is set in the first enclosed area, the first floating diffusion node FD1 is set in the first enclosed area and on both sides of the first signal output unit 115; the second signal output unit 116 is set in the second enclosed area, and the second floating diffusion node FD2 is set in the second enclosed area and on both sides of the second signal output unit 116.

[0127] As an example, the first photosensitive unit 111 and the second photosensitive unit 112 each include four photosensitive elements and corresponding four transmission transistors, the four photosensitive elements are arranged in an array, the four transmission transistors are in a strip shape, and are correspondingly arranged at the corners of the four photosensitive elements facing each other at an inclined angle to form a first enclosed area and a second enclosed area respectively. In a possible implementation, the photosensitive elements are arranged in a rectangular shape, and two adjacent photosensitive elements in the row direction are arranged in a square shape.

[0128] In practical applications, the tilt angles of the transmission transistors can be set to be completely identical, completely different, or even partially identical, which has no substantial impact on this embodiment. However, for the sake of symmetry of the layout structure, the tilt angles of the transmission transistors are usually set to be completely identical, such as 45°, that is, the four transmission transistors are all set at a 45° tilt angle at the corners corresponding to the four photosensitive elements; of course, other non-45° tilt angles are also applicable to this embodiment.

[0129] It should be noted that the enclosed area can be considered as the outline shape formed by the transfer transistor, not an enclosure in the strict sense, which can be understood by those skilled in the art; in fact, the enclosed area mentioned in this embodiment can be an area away from the photosensitive element formed when a strip-shaped transfer transistor is arranged at an inclined angle at the corner of the corresponding photosensitive element, or it can be an area enclosed when two or more strip-shaped transfer transistors are arranged at an inclined angle at the opposite corners of the corresponding photosensitive elements.

[0130] As an example, when the first reset unit 113 includes a first reset transistor, the second reset unit 114 includes a second reset transistor, the first signal output unit 115 includes a first source follower transistor, the second signal output unit 116 includes a second source follower transistor, the first gain control unit 117 includes a first gain transistor and the second gain control unit 118 includes a second gain transistor: the first source follower transistor is arranged in the first enclosed area, and the second source follower transistor is arranged in the second enclosed area; the first floating diffusion node is arranged in the first enclosed area and on both sides of the first source follower transistor, and the second floating diffusion node is arranged in the second enclosed area and on both sides of the second source follower transistor; the first reset transistor is arranged outside the first enclosed area and above the first source follower transistor, and the second reset transistor is arranged outside the second enclosed area and above the second source follower transistor; the first gain transistor is arranged on one side of the first reset transistor, the second gain transistor is arranged on one side of the second reset transistor, and the first gain transistor and the second gain transistor are arranged adjacent to each other.

[0131] Among them, the first source follower transistor is arranged in the central area of ​​the first enclosed area, and is arranged on the central connection line of the first floating diffusion node on both sides thereof, so that the distance between the gate terminal of the first source follower transistor and the first floating diffusion node is shorter; the second source follower transistor is arranged in the central area of ​​the second enclosed area, and is arranged on the central connection line of the second floating diffusion node on both sides thereof, so that the distance between the gate terminal of the second source follower transistor and the second floating diffusion node is shorter.

[0132] Furthermore, the pixel block 110 of this embodiment further includes a selection control unit 119, which is disposed below the first enclosed area and the second enclosed area; in this embodiment, the transistors corresponding to the selection control unit 119 and other units are respectively disposed on the opposite side of the photosensitive unit. Wherein: when the selection control unit 119 includes a selection transistor, the selection transistor is disposed below the second source follower transistor in the second signal output unit 116 and on the other side of the second reset transistor in the second reset unit 114, such as Figure 8 As shown; when the selection control unit includes a first selection transistor and a second selection transistor, the first selection transistor is arranged below the first source follower transistor in the first signal output unit 115 and arranged on the other side of the first reset transistor in the first reset unit 113, and the second selection transistor is arranged below the second source follower transistor in the second signal output unit 116 and arranged on the other side of the second reset transistor in the second reset unit 114, as shown Fig.16 shown.

[0133] In this embodiment, all wiring such as connection lines, power lines, signal lines, etc. between devices are made of metal wires to achieve corresponding line connections; among them, these metal wires can be set in the same layer or different layers based on actual needs, which has no substantial impact on this embodiment.

[0134] Embodiment 2

[0135] This embodiment provides an image sensor, including the pixel array 100 as described in Embodiment 1. Furthermore, the image sensor of this embodiment also includes a readout circuit for converting the analog signal output by the pixel array 100 into a digital signal and reading it out; of course, the image sensor of this embodiment may also include other functional circuits, which are not limited thereto.

[0136] Accordingly, this embodiment also provides a control method of the image sensor as described above, including: controlling the opening and closing of the first gain control unit 117 and the second gain control unit 118 in the pixel block 110 to control the pixel block 110 to enter the merging mode or the gain mode.

[0137] The pixel block 110 of this embodiment includes two pixel circuits, the first pixel circuit includes a first photosensitive unit 111, a first reset unit 113, a first signal output unit 115 and a first gain control unit 117, and the second pixel circuit includes a second photosensitive unit 112, a second reset unit 114, a second signal output unit 116 and a second gain control unit 118; wherein the first reset unit 113 includes a first reset transistor, the first signal output unit 115 includes a first source follower transistor, the first gain control unit 117 includes a first gain transistor, the second reset unit 114 includes a second reset transistor, the second signal output unit 116 includes a second source follower transistor, and the second gain control unit 118 includes a second gain transistor.

[0138] For the merging mode, the first gain transistor and the second gain transistor in the pixel block 110 are controlled to be turned on, so that the two pixel circuits in the pixel block 110 enter the merging mode.

[0139] For the gain mode, at most one of the first gain transistor and the second gain transistor in the pixel block 110 is controlled to be turned on, so that the two pixel circuits in the pixel block 110 enter their respective gain modes; specifically:

[0140] Controlling the first gain transistor in the pixel block 110 to be turned on and the second gain transistor to be turned off, so that the first pixel circuit enters a low conversion gain mode and the second pixel circuit enters a high conversion gain mode;

[0141] Controlling the first gain transistor in the pixel block 110 to be turned off and the second gain transistor to be turned on, so that the first pixel circuit enters a high conversion gain mode and the second pixel circuit enters a low conversion gain mode;

[0142] The first gain transistor and the second gain transistor in the pixel block 110 are controlled to be turned off, so that the first pixel circuit and the second pixel circuit enter a high conversion gain mode.

[0143] The pixel block 110 of the present embodiment further includes a selection control unit 119 coupled to output ends of the first signal output unit 115 and the second signal output unit 116 and outputting a pixel signal.

[0144] In the case where the selection control unit 119 includes a selection transistor, Figure 2 Taking the circuit shown as an example, different modes and readout conditions of two pixel circuits in the pixel block 110 are described.

[0145] In merge mode:

[0146] like Figure 4 and Figure 5 As shown, the first gain transistor and the second gain transistor are turned on, so that the first pixel circuit and the second pixel circuit in the pixel block 110 enter the merge mode, at which time the first modulation storage area and the second modulation storage area are merged, and the capacity of the merged modulation storage area is the sum of the capacity of the first floating diffusion node FD1, the capacity of the second floating diffusion node FD2, the capacity corresponding to the first gain transistor, and the capacity corresponding to the second gain transistor;

[0147] Turn on the first reset transistor and the second reset transistor to reset the merged modulation storage area; turn off the first reset transistor and the second reset transistor, and read out the reset signal through the first source follower transistor and the selection transistor or the second source follower transistor and the selection transistor; turn on the four transfer transistors in the first photosensitive unit 111 and the four transfer transistors in the second photosensitive unit 112 to transfer the charge and then turn them off; read out the image signal through the first source follower transistor and the selection transistor or the second source follower transistor and the selection transistor.

[0148] It should be noted that Figure 5 TX in the figure represents TX1-TX8. When TX is valid, the four transmission transistors in the first photosensitive unit 111 and the four transmission transistors in the second photosensitive unit 112 are all turned on. Of course, the number of transistors turned on can also be selected according to actual needs. For example, TX can also represent TX1, TX2, TX7, and TX8.

[0149] In gain mode:

[0150] like Figure 6 and Figure 7 As shown, it is taken as an example that the first pixel circuit in the pixel block 110 enters the high conversion gain mode and the second pixel circuit enters the low conversion gain mode;

[0151] The first gain transistor is turned off and the second gain transistor is turned on, so that the first pixel circuit in the pixel block 110 enters a high conversion gain mode and the second pixel circuit enters a low conversion gain mode. At this time, the capacity of the first modulation storage area is the capacity of the first floating diffusion node FD1, and the capacity of the second modulation storage area is the sum of the capacity of the second floating diffusion node FD2 and the capacity corresponding to the second gain transistor;

[0152] Turn on the first reset transistor to reset the first modulation storage area; turn off the first reset transistor, and read out the first reset signal through the first source follower transistor and the selection transistor; turn on the four transfer transistors in the first photosensitive unit 111 to transfer the charge and then turn them off; read out the first image signal through the first source follower transistor and the selection transistor;

[0153] Turn on the second reset transistor to reset the second modulation storage area; turn off the second reset transistor, and read out the second reset signal through the second source follower transistor and the selection transistor; turn on the four transfer transistors in the second photosensitive unit 112 to transfer the charge and then turn them off; read out the second image signal through the second source follower transistor and the selection transistor.

[0154] Since the first source follower transistor and the second source follower transistor share the same selection transistor, the pixel signals output by the first pixel circuit and the second pixel circuit need to be read out in sequence and cannot be read out at the same time.

[0155] It should be noted that Figure 7 The first TX in the example represents TX1-TX4, and the second TX represents TX5-TX8; when the first TX is valid, the four transmission transistors in the first photosensitive unit 111 are turned on; when the second TX is valid, the four transmission transistors in the second photosensitive unit 112 are turned on. Of course, the specific number of transistors turned on can also be selected according to actual needs, for example, the first TX represents TX1 and TX2, and the second TX represents TX7 and TX8.

[0156] Of course, the gain mode of this embodiment also includes other combinations of two pixel circuits, such as, the first pixel circuit enters a low conversion gain mode, the second pixel circuit enters a high conversion gain mode, or both the first pixel circuit and the second pixel circuit enter a high conversion gain mode, but the control is similar to the above combination and will not be repeated.

[0157] In the case where the selection control unit 119 includes a first selection transistor and a second selection transistor, Fig.10Taking the circuit shown as an example, different modes and readout conditions of two pixel circuits in the pixel block 110 are described.

[0158] In merge mode:

[0159] like Fig.12 and Fig.13 As shown, the first gain transistor and the second gain transistor are turned on, so that the first pixel circuit and the second pixel circuit in the pixel block 110 enter the merge mode, at which time the first modulation storage area and the second modulation storage area are merged, and the capacity of the merged modulation storage area is the sum of the capacity of the first floating diffusion node FD1, the capacity of the second floating diffusion node FD2, the capacity corresponding to the first gain transistor, and the capacity corresponding to the second gain transistor;

[0160] The first reset transistor and the second reset transistor are turned on to reset the merged modulation storage area; the first reset transistor and the second reset transistor are turned off, and the reset signal is read out through the second source follower transistor and the second selection transistor; the four transmission transistors in the first photosensitive unit 111 and the four transmission transistors in the second photosensitive unit 112 are turned on to transfer the charge and then turned off; the image signal is read out through the second source follower transistor and the second selection transistor. Of course, the reset signal and the image signal can also be read out through the first source follower transistor and the first selection transistor.

[0161] It should be noted that Fig.13 TX in the figure represents TX1-TX8. When TX is valid, the four transmission transistors in the first photosensitive unit 111 and the four transmission transistors in the second photosensitive unit 112 are all turned on. Of course, the number of transistors turned on can also be selected according to actual needs. For example, TX can also represent TX1, TX2, TX7, and TX8.

[0162] In gain mode:

[0163] like Figure 14-15 As shown, it is taken as an example that the first pixel circuit in the pixel block 110 enters the high conversion gain mode and the second pixel circuit enters the low conversion gain mode;

[0164] The first gain transistor is turned off and the second gain transistor is turned on, so that the first pixel circuit in the pixel block 110 enters a high conversion gain mode and the second pixel circuit enters a low conversion gain mode. At this time, the capacity of the first modulation storage area is the capacity of the first floating diffusion node FD1, and the capacity of the second modulation storage area is the sum of the capacity of the second floating diffusion node FD2 and the capacity corresponding to the second gain transistor;

[0165] Turning on the first reset transistor and the second reset transistor to respectively perform a reset operation on the first modulation storage area and the second modulation storage area;

[0166] Turn off the first reset transistor, and read out the first reset signal through the first source follower transistor and the first selection transistor; turn on the four transfer transistors in the first photosensitive unit 111 to transfer the charge and then turn them off; read out the second image signal through the first source follower transistor and the first selection transistor;

[0167] The second reset transistor is turned off, and the second reset signal is read out through the second source follower transistor and the second selection transistor; the four transfer transistors in the second photosensitive unit 112 are turned on for charge transfer and then turned off; the second image signal is read out through the second source follower transistor and the second selection transistor.

[0168] Since the first source follower transistor and the second source follower transistor are connected to different selection transistors (i.e., the first source follower transistor is connected to the first selection transistor, and the second source follower transistor is connected to the second selection transistor), and the first selection transistor and the second selection transistor are read out through different column lines, the first pixel circuit and the second pixel circuit can be read out simultaneously in their respective gain modes, such as, the first reset signal and the second reset signal are read out simultaneously, and the first image signal and the second image signal are read out simultaneously.

[0169] It should be noted that Fig.15 The first TX in the example represents TX1-TX4, and the second TX represents TX5-TX8; when the first TX is valid, the four transmission transistors in the first photosensitive unit 111 are turned on; when the second TX is valid, the four transmission transistors in the second photosensitive unit 112 are turned on. Of course, the specific number of transistors turned on can also be selected according to actual needs, for example, the first TX represents TX1 and TX2, and the second TX represents TX7 and TX8. In addition, the corresponding pixels under different gains can be selected according to actual needs, for example, see Fig.18 As shown, the pixels corresponding to TX5 and TX6 can be read out in a low conversion gain (LCG) mode, the pixels corresponding to TX3 and TX4 can be read out in a low gain LCG mode, the pixels corresponding to TX1 and TX2 can be read out in a high conversion gain (HCG) mode, and the pixels corresponding to TX7 and TX8 can be read out in a high conversion gain (HCG) mode, and the corresponding pixel circuits can be controlled to achieve corresponding outputs.

[0170] Of course, the gain mode of this embodiment also includes other combinations of two pixel circuits, such as, the first pixel circuit enters a low conversion gain mode, the second pixel circuit enters a high conversion gain mode, or both the first pixel circuit and the second pixel circuit enter a high conversion gain mode, but the control is similar to the above combination and will not be repeated.

[0171] In this embodiment, since the second ends of the first gain transistor and the second gain transistor are directly connected, in the gain mode, the two pixel circuits in the pixel block 110 cannot enter the low gain mode at the same time (because the pixel block 110 will enter the merge mode when the two gain transistors are turned on at the same time). In order to allow the two pixel circuits to enter the low gain mode at the same time, the pixel block 110 of this embodiment also includes at least one gain adjustment switch (not shown in the figure), which is connected in series between the second ends of the first gain transistor and the second gain transistor. At this time, the control method includes:

[0172] The pixel block 110 is controlled to enter the merge mode or the gain mode by controlling the opening and closing of the first gain control unit 117 and the second gain control unit 118 in the pixel block 110 and coordinating the opening and closing of the gain adjustment switch; wherein, in the gain mode, at least one gain adjustment switch is controlled to be closed, so that the two pixel circuits in the pixel block 110 enter their respective gain modes. In practical applications, the gain adjustment switch is generally implemented by a switching transistor, and the opening in this embodiment refers to controlling the transistor to be turned on, and the closing refers to controlling the transistor to be turned off.

[0173] In the combined mode: regardless of whether the number of gain adjustment switches is one or more (i.e. greater than or equal to 2), all of them need to be turned on, and the control of other transistors remains unchanged.

[0174] In gain mode: when the number of switches is one, the gain adjustment switch is closed, so that the two pixel circuits can enter the low gain mode at the same time, and the control of other transistors remains unchanged; when the number of switches is multiple, at least one gain adjustment switch is closed, so that the two pixel circuits can enter the low gain mode at the same time, and through the on / off design of the gain adjustment switch, the pixel circuit can also have more gain modes in addition to the high conversion gain and low conversion gain modes, and the control of other transistors remains unchanged. The high conversion gain and low conversion gain described in this application are not limited to a specific single value, which can be understood by those skilled in the art.

[0175] The control method of this embodiment may further include a step of implementing phase focusing based on pixel blocks, wherein:

[0176] When a pixel block corresponds to one microlens: the pixel group corresponding to the pixel block is divided into two sensing areas via an axis passing through the center of the microlens, and focusing information is obtained based on the two sensing areas to perform phase focusing.

[0177] For example, see Fig.10 and Fig.18As shown, it can be a horizontal axis, dividing the pixel block into pixels corresponding to PD1, PD2, PD5, and PD6 to obtain the first phase information, and dividing the pixel block into pixels corresponding to PD3, PD4, PD7, and PD8 to obtain the second phase information, so as to perform phase focusing based on the first phase information and the second phase information. Of course, a part of the pixels of the phase information on one side can also be selected to obtain the focusing information. Similarly, the axis can also be a vertical line or a diagonal line. When it is a diagonal line, the pixels corresponding to the axis can be ignored, and the pixels for focusing can be selected from other pixels on both sides of the axis.

[0178] When the pixel block corresponds to at least two micro-lenses arranged in an array, phase focusing is performed based on the pixels at the corresponding position of each micro-lens, such as two lenses, such as two lenses arranged left and right or up and down. Of course, other numbers of lenses can also be used, which can be designed according to actual needs. When the pixel block corresponds to four micro-lenses arranged in an array:

[0179] See also Fig.10 and Fig.18 As shown, the first photosensitive unit of the pixel block includes a first photosensitive group PD1, PD2 and a second photosensitive group PD3, PD4 corresponding to each other, and the second photosensitive unit of the pixel block includes a third photosensitive group PD5, PD6 and a fourth photosensitive group PD7, PD8 corresponding to each other, and each photosensitive group corresponds to each microlens, wherein:

[0180] If the four microlenses correspond to different colors, for any color, phase focusing is performed based on the focus information obtained based on the corresponding photosensitive group. For example, phase information of different phases is respectively obtained based on the first photosensitive groups PD1 and PD2 for focusing; if the four microlenses correspond to the same color, phase focusing is performed based on the corresponding pixels of the four photosensitive groups. For example, the first phase information is obtained based on PD1, PD3, PD5, and PD7, and the second phase information is obtained based on PD2, PD4, PD6, and PD8, so that phase focusing is performed based on the first phase information and the second phase information.

[0181] In summary, the pixel array, arrangement structure, image sensor and control method of the present invention propose a new pixel circuit structure through the design of the first photosensitive unit, the second photosensitive unit, the first reset unit, the second reset unit, the first signal output unit, the second signal output unit, the first gain control unit and the second gain control unit in the pixel block, which can not only achieve high dynamic range under full pixel PDAF, but also realize the merging of the same color pixels in the charge domain; and, by selecting the design of the control unit, it can also realize the simultaneous reading of two pixel circuits in the pixel block in their respective gain modes. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0182] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A pixel array, characterized in that: The invention comprises a plurality of pixel blocks arranged in rows and columns, wherein the pixel blocks comprise: a first photosensitive unit, a second photosensitive unit, a first reset unit, a second reset unit, a first signal output unit, a second signal output unit, a first gain control unit and a second gain control unit; wherein: The first photosensitive unit is coupled to a first floating diffusion node, the first reset unit is coupled between a first pixel power source and the first floating diffusion node, and the first signal output unit is coupled to the first floating diffusion node and outputs a first pixel signal; The second photosensitive unit is coupled to the second floating diffusion node, the second reset unit is coupled between the second pixel power supply and the second floating diffusion node, and the second signal output unit is coupled to the second floating diffusion node and outputs a second pixel signal; The first gain control unit and the second gain control unit are connected in series and coupled between the first floating diffusion node and the second floating diffusion node.

2. The pixel array according to claim 1, characterized in that: The first reset unit includes a first reset transistor, the second reset unit includes a second reset transistor, the first signal output unit includes a first source follower transistor, the second signal output unit includes a second source follower transistor, the first gain control unit includes a first gain transistor, and the second gain control unit includes a second gain transistor; wherein: The control end of the first reset transistor receives a first reset control signal, the first end is coupled to the first pixel power supply, and the second end is coupled to the first floating diffusion node and coupled to the first end of the first gain transistor; the control end of the first source follower transistor is coupled to the first floating diffusion node, the first end is coupled to the third pixel power supply, and the second end outputs the first pixel signal; The control terminal of the second reset transistor receives the second reset control signal, the first terminal is coupled to the second pixel power supply, and the second terminal is coupled to the second floating diffusion node and coupled to the first terminal of the second gain transistor; the control terminal of the second source follower transistor is coupled to the second floating diffusion node, the first terminal is coupled to the fourth pixel power supply, and the second terminal outputs the second pixel signal; The control end of the first gain transistor receives a first gain control signal, and the second end is coupled to the second end of the second gain transistor; the control end of the second gain transistor receives a second gain control signal.

3. The pixel array according to claim 1, characterized in that: The pixel block further includes a selection control unit coupled to output ends of the first signal output unit and the second signal output unit and outputting a pixel signal.

4. The pixel array according to claim 3, characterized in that: The selection control unit includes a selection transistor. When the first signal output unit includes a first source follower transistor and the second signal output unit includes a second source follower transistor, the control end of the selection transistor receives a selection control signal, the first end is coupled to the second ends of the first source follower transistor and the second source follower transistor, and the second end outputs the pixel signal.

5. The pixel array according to claim 4, characterized in that: In the same column, the second ends of the selection transistors are coupled to the same column line; or, in the same column, the second ends of two adjacent selection transistors are coupled to different column lines.

6. The pixel array according to claim 3, characterized in that: The selection control unit includes a first selection transistor and a second selection transistor. When the first signal output unit includes a first source follower transistor and the second signal output unit includes a second source follower transistor, The control terminal of the first selection transistor receives a first selection control signal, the first terminal is coupled to the second terminal of the first source follower transistor, and the second terminal outputs the first pixel signal; The control terminal of the second selection transistor receives a second selection control signal, the first terminal is coupled to the second terminal of the second source follower transistor, and the second terminal outputs the second pixel signal.

7. The pixel array according to claim 6, characterized in that: Second terminals of the first selection transistor and the second selection transistor are coupled to the same or different column lines.

8. The pixel array according to claim 7, characterized in that: When the second terminals of the first selection transistor and the second selection transistor are coupled to different column lines: In the same column, the second terminals of the first selection transistors are coupled to the same column line, and the second terminals of the second selection transistors are coupled to the same column line; Alternatively, in the same column, the second ends of two adjacent first selection transistors are coupled to different column lines, and the second ends of two adjacent second selection transistors are coupled to different column lines.

9. The pixel array according to claim 1, characterized in that: The circuits of the first photosensitive unit and the second photosensitive unit are the same, including at least one photosensitive element and a corresponding transmission transistor; The control end of the transmission transistor receives a transmission control signal, the first end is coupled to the corresponding floating diffusion node, and the second end is coupled to the first end of the photosensitive element; the second end of the photosensitive element is coupled to the first reference potential; And / or, the pixel array further includes a plurality of filter areas, the filter areas correspond to the pixel blocks one by one, or the pixel array includes a plurality of color acquisition units, the color acquisition units correspond to the pixel blocks one by one, and each of the color acquisition units corresponds to a plurality of filter areas, so as to acquire color information based on the color acquisition units; And / or, the pixel array further includes a plurality of micro lenses, and the micro lenses correspond to the pixel blocks one by one, or one pixel block corresponds to a plurality of micro lenses arranged in an array.

10. The pixel array according to claim 9, characterized in that: The first photosensitive unit and the second photosensitive unit each include four photosensitive elements and four transmission transistors corresponding to the photosensitive elements.

11. The pixel array according to any one of claims 1 to 10, characterized in that: The pixel block also includes a gain capacitor coupled between a coupling node between the first gain control unit and the second gain control unit and a second reference potential; and / or the pixel block also includes at least one gain adjustment switch, which is connected in series between the first gain control unit and the second gain control unit.

12. An arrangement structure of a pixel array as claimed in any one of claims 1 to 11, characterized in that: include: The transmission transistors corresponding to the photosensitive elements in the first photosensitive unit are enclosed to form a first enclosed area, and the transmission transistors corresponding to the photosensitive elements in the second photosensitive unit are enclosed to form a second enclosed area, and the first enclosed area and the second enclosed area are arranged in parallel in the row direction; The first resetting unit is disposed outside the first enclosed area and above the first enclosed area, and the second resetting unit is disposed outside the second enclosed area and above the second enclosed area; The first gain control unit is disposed at one side of the first reset unit, the second gain control unit is disposed at one side of the second reset unit, and the first gain control unit and the second gain control unit are disposed adjacent to each other.

13. The arrangement structure of the pixel array according to claim 12, characterized in that: When the first reset unit includes a first reset transistor, the second reset unit includes a second reset transistor, the first signal output unit includes a first source follower transistor, the second signal output unit includes a second source follower transistor, the first gain control unit includes a first gain transistor, and the second gain control unit includes a second gain transistor: The first source follower transistor is disposed in the first enclosed area, and the second source follower transistor is disposed in the second enclosed area; The first floating diffusion node is disposed in the first enclosed area and disposed on both sides of the first source follower transistor, and the second floating diffusion node is disposed in the second enclosed area and disposed on both sides of the second source follower transistor; The first reset transistor is disposed outside the first enclosed area and above the first source follower transistor, and the second reset transistor is disposed outside the second enclosed area and above the second source follower transistor; The first gain transistor is disposed at one side of the first reset transistor, the second gain transistor is disposed at one side of the second reset transistor, and the first gain transistor and the second gain transistor are disposed adjacent to each other.

14. The arrangement structure according to claim 12, characterized in that: The pixel block further includes a selection control unit, which is arranged below the first enclosed area and the second enclosed area; wherein: When the selection control unit includes a selection transistor, the selection transistor is arranged below the second source follower transistor in the second signal output unit and arranged on the other side of the second reset transistor in the second reset unit; When the selection control unit includes a first selection transistor and a second selection transistor, the first selection transistor is arranged below the first source follower transistor in the first signal output unit and on the other side of the first reset transistor in the first reset unit, and the second selection transistor is arranged below the second source follower transistor in the second signal output unit and on the other side of the second reset transistor in the second reset unit.

15. The arrangement structure according to claim 12, characterized in that: The first photosensitive unit and the second photosensitive unit each include four photosensitive elements and corresponding four transmission transistors, the four photosensitive elements are arranged in an array, the four transmission transistors are in a strip shape, and are correspondingly arranged at the opposite corners of the four photosensitive elements at an inclined angle to form the first enclosed area and the second enclosed area respectively; and / or, each of the photosensitive elements is arranged in a rectangular shape, and two adjacent photosensitive elements in the row direction are arranged in a square shape.

16. An image sensor, characterized in that: Comprising a pixel array as described in any one of claims 1-11.

17. A method for controlling an image sensor as claimed in claim 16, characterized in that: include: The first gain control unit and the second gain control unit in the pixel block are controlled to be turned on and off to control the pixel block to enter a merging mode or a gain mode.

18. The control method according to claim 17, characterized in that: When the first gain control unit includes a first gain transistor and the second gain control unit includes a second gain transistor, the control method includes: Controlling the first gain transistor and the second gain transistor in the pixel block to turn on, so that the pixel block enters a merging mode; Controlling at most one of the first gain transistor and the second gain transistor in the pixel block to turn on, so that two pixel circuits in the pixel block enter respective gain modes; The first pixel circuit includes a first photosensitive unit, a first reset transistor, a first source follower transistor and the first gain transistor, and the second pixel circuit includes a second photosensitive unit, a second reset transistor, a second source follower transistor and the second gain transistor; wherein: Controlling the first gain transistor in the pixel block to be turned on and the second gain transistor to be turned off, so that the first pixel circuit enters a low conversion gain mode and the second pixel circuit enters a high conversion gain mode; Controlling the first gain transistor in the pixel block to be turned off and the second gain transistor to be turned on, so that the first pixel circuit enters a high conversion gain mode and the second pixel circuit enters a low conversion gain mode; The first gain transistor and the second gain transistor in the pixel block are controlled to be turned off, so that the first pixel circuit and the second pixel circuit enter a high conversion gain mode.

19. The control method according to claim 17, characterized in that: When the pixel block further includes at least one gain adjustment switch, the control method includes: Controlling the opening and closing of the first gain control unit and the second gain control unit in the pixel block and coordinating with adjusting the opening and closing of the gain adjustment switch to control the pixel block to enter a merging mode or a gain mode; Wherein, in the gain mode, at least one of the gain adjustment switches is controlled to be closed, so that the two pixel circuits in the pixel block enter their respective gain modes.

20. The control method according to claim 17, characterized in that: The first gain control unit also corresponds to a first selection transistor, and the second gain control unit also corresponds to a second selection transistor. The first selection transistor and the second selection transistor are read out through different column lines, so that the first pixel circuit and the second pixel circuit are read out simultaneously in their respective gain modes.

21. The control method according to any one of claims 17 to 20, characterized in that: The control method includes realizing phase focusing based on the pixel block; wherein: When the pixel block corresponds to one microlens: dividing the pixel group corresponding to the pixel block into two sensing areas via an axis passing through the center of the microlens, and acquiring focusing information based on the two sensing areas to perform phase focusing; When the pixel block corresponds to at least two microlenses arranged in an array, phase focusing is performed based on the pixels at the corresponding positions of each of the microlenses, wherein when the pixel block corresponds to four microlenses arranged in an array, the first photosensitive unit of the pixel block includes a first photosensitive group and a second photosensitive group corresponding to each other, and the second photosensitive unit of the pixel block includes a third photosensitive group and a fourth photosensitive group corresponding to each other, and each photosensitive group corresponds to each microlens, wherein: if the four microlenses correspond to different colors, for any color, focusing information is obtained based on the corresponding photosensitive group to perform phase focusing; if the four microlenses correspond to the same color, focusing information is obtained based on the corresponding pixels of the four photosensitive groups to perform phase focusing.

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