Preparation method of semiconductor structure

Abstract

The invention provides a preparation method of a semiconductor structure, and the method comprises the steps: providing a substrate which is provided with an array active region and a peripheral active region, forming a peripheral channel, wherein the peripheral channel is located in the peripheral active region; an embedded word line is formed, and the embedded word line is located in the array active region and corresponds to an array channel in the array active region; a bit line contact structure and a peripheral gate structure are formed, the peripheral gate structure and the bit line contact structure are both located on the substrate, the peripheral gate structure corresponds to the peripheral channel, and the bit line contact structure corresponds to and is connected with the array active region; and doping a part of the substrate and the bit line contact structure, and forming an isolation well in the substrate of the array active region and the peripheral active region. The manufacturing process of the semiconductor structure can be simplified.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that can write and read data randomly at high speed and is widely used in data storage devices or apparatuses.

[0003] DRAM includes an array area and a peripheral area surrounding the array area. The array area is provided with an array circuit and a plurality of memory cells arranged in an array. The array circuit is used to provide a driving current for the plurality of memory cells to realize the storage process of the memory cells. A peripheral circuit is provided in the peripheral area. The peripheral circuit is used to provide a driving current for the array circuit and control the working timing of the array circuit. In the related art, the circuit structures of the array area and the peripheral area are prepared separately.

[0004] However, the manufacturing process of the above DRAM is relatively complicated. Summary of the invention

[0005] The present disclosure provides a method for preparing a semiconductor structure, which can effectively simplify the manufacturing process of the semiconductor structure.

[0006] The present disclosure provides a method for preparing a semiconductor structure, comprising:

[0007] Providing a substrate, the substrate having an array active region and a peripheral active region that are spaced apart;

[0008] forming a peripheral channel, the peripheral channel being located in the peripheral active region;

[0009] forming a buried word line, the buried word line being located in the array active area and corresponding to the array channel in the array active area;

[0010] Forming a bit line contact structure and a peripheral gate structure, both of which are located on the substrate, the peripheral gate structure corresponds to the peripheral channel, and the bit line contact structure corresponds to and is connected to the array active area;

[0011] Part of the substrate and the bit line contact structure are doped to form isolation wells in the array active area and the peripheral active area.

[0012] In the above-mentioned method for preparing the semiconductor structure, optionally, it further includes: forming an array channel, and the formation of the array channel and the formation of the peripheral channel are completed simultaneously.

[0013] In the above-mentioned method for preparing the semiconductor structure, optionally, it further includes: forming an array channel, and the formation of the array channel is completed after forming the peripheral channel and before forming the buried word line.

[0014] In the above-mentioned method for preparing the semiconductor structure, optionally, doping a portion of the substrate and the bit line contact structure includes: forming a first mask layer, the first mask layer covers the substrate and the bit line contact structure, a first mask opening of the first mask layer exposes a portion between the array active region and a portion of the peripheral active region, and exposes the bit line contact structure;

[0015] The exposed substrate and the bit line contact structure are doped along the first mask opening to form isolation wells in the array active area and the peripheral active area.

[0016] In the above-mentioned method for preparing a semiconductor structure, optionally, the peripheral gate structure includes a peripheral gate dielectric layer, a peripheral gate semiconductor layer, a peripheral gate metal layer and a peripheral gate protection layer; the bit line contact structure includes a contact semiconductor layer and a contact metal layer; forming the peripheral gate structure and the bit line contact structure includes:

[0017] forming a peripheral gate dielectric layer, the peripheral gate dielectric layer being located on the substrate and corresponding to the peripheral channel;

[0018] Forming a peripheral gate semiconductor layer and a contact semiconductor layer, wherein the peripheral gate semiconductor layer is located on the peripheral gate dielectric layer, and the contact semiconductor layer is located on the substrate and corresponds to and is connected to the array active area;

[0019] forming a peripheral gate metal layer and a contact metal layer, wherein the peripheral gate metal layer is located on the peripheral gate semiconductor layer, and the contact metal layer is located on the contact semiconductor layer;

[0020] A peripheral gate protection layer is formed, and the peripheral gate protection layer is located on the peripheral gate metal layer.

[0021] In the above-mentioned method for preparing the semiconductor structure, optionally, forming the peripheral channel includes: forming a second mask layer, the second mask layer covers the substrate, and a second mask opening of the second mask layer exposes a portion of the peripheral active area;

[0022] The peripheral active region is doped along the second mask opening to form a peripheral channel.

[0023] In the above-mentioned method for preparing a semiconductor structure, optionally, forming the array channel includes: the second mask opening also exposes a portion of the array active area;

[0024] The array active region is doped along the second mask opening to form an array channel.

[0025] In the above-mentioned method for preparing the semiconductor structure, optionally, forming the peripheral gate dielectric layer includes: forming an initial gate dielectric layer, the initial gate dielectric layer covering the substrate located in the peripheral active area;

[0026] Forming a peripheral gate semiconductor layer and a contact semiconductor layer includes: forming an initial semiconductor layer, the initial semiconductor layer covering the substrate and the initial gate dielectric layer located in the array active area;

[0027] Forming a peripheral gate metal layer and a contact metal layer includes: forming an initial metal layer, wherein the initial metal layer covers the initial semiconductor layer;

[0028] The peripheral gate protection layer is formed, including: forming an initial protection layer, wherein the initial protection layer covers an initial metal layer corresponding to the peripheral active area.

[0029] In the above-mentioned method for preparing a semiconductor structure, optionally, after forming the initial protective layer, the method further comprises: removing part of the initial gate dielectric layer, part of the initial semiconductor layer, part of the initial metal layer and part of the initial protective layer;

[0030] The initial semiconductor layer and the initial metal layer corresponding to the array active area are retained to form the contact semiconductor layer and the contact metal layer of the bit line contact structure respectively; the initial gate dielectric layer, the initial semiconductor layer, the initial metal layer and the initial protective layer corresponding to the peripheral channel are retained to form the peripheral gate dielectric layer, the peripheral gate semiconductor layer, the peripheral gate metal layer and the peripheral gate protective layer of the peripheral gate structure respectively.

[0031] In the above-mentioned method for preparing a semiconductor structure, optionally, the buried word line includes an array gate dielectric layer, an array gate semiconductor layer, an array gate metal layer and an array gate protection layer;

[0032] Forming a buried word line includes: forming a first trench in an array channel;

[0033] An array gate dielectric layer is formed in the first trench, the array gate dielectric layer covers a portion of the inner wall of the trench, the top surface of the array gate dielectric layer is lower than the top surface of the substrate, and a second trench is formed in the array gate dielectric layer;

[0034] An array gate semiconductor layer and an array gate metal layer are sequentially formed in the second trench, wherein the top surface of the array gate metal layer is flush with the top surface of the array gate dielectric layer;

[0035] An array gate protection layer is formed in the first trench, the array gate protection layer covers the top surfaces of the array gate dielectric layer and the array gate metal layer, and the top surface of the array gate protection layer is flush with the top surface of the substrate.

[0036] In the above-mentioned method for preparing a semiconductor structure, optionally, providing a substrate includes: providing an initial substrate, the initial substrate including an array region and a peripheral region;

[0037] The initial substrate is doped to form an array active region in the substrate in the array region and a peripheral active region in the substrate in the peripheral region.

[0038] In the above-mentioned method for preparing the semiconductor structure, optionally, after doping a portion of the substrate and the bit line contact structure, the method further includes: forming a bit line, wherein the bit line is connected to the bit line contact structure.

[0039] In the above-mentioned method for preparing a semiconductor structure, optionally, after forming the bit line, the method further includes: forming an array contact structure and a peripheral contact structure, the array contact structure is connected to the array active area, and the peripheral contact structure is connected to the peripheral active area and the peripheral gate structure;

[0040] A capacitor structure and a peripheral circuit are formed, wherein the capacitor structure is connected to the array contact structure, and the peripheral circuit is connected to the peripheral contact structure.

[0041] In the above-mentioned method for preparing the semiconductor structure, optionally, forming the array contact structure and the peripheral contact structure includes: forming a dielectric layer, the dielectric layer covering the substrate, the bit line contact structure, the bit line and the peripheral gate structure;

[0042] forming a channel in the dielectric layer, wherein the channel exposes the array active area and the peripheral active area;

[0043] An initial conductive layer is formed in the channel, the initial conductive layer connected to the array active area forms an array contact structure, and the initial conductive layer connected to the peripheral active area and the peripheral gate structure forms a peripheral contact structure.

[0044] In the above-mentioned method for preparing a semiconductor structure, optionally, the capacitor structure includes a first capacitor conductive layer, a capacitor dielectric layer and a second capacitor conductive layer;

[0045] Forming a capacitor structure and a peripheral circuit, including: forming a first capacitor conductive layer and a peripheral circuit, wherein the first capacitor conductive layer is located on the dielectric layer and corresponds to and is connected to the array contact structure, and the peripheral circuit is located on the dielectric layer and corresponds to and is connected to the peripheral contact structure;

[0046] forming a capacitor dielectric layer, wherein the capacitor dielectric layer is located on the first capacitor conductive layer;

[0047] A second capacitor conductive layer is formed, and the second capacitor conductive layer is located on the capacitor dielectric layer.

[0048] The method for preparing the semiconductor structure provided by the present disclosure provides a support foundation for the subsequent formation of the structure by setting a substrate. By forming a peripheral channel and a buried word line, a foundation is provided for the subsequent formation of an array transistor and a peripheral transistor. By forming a bit line contact structure and a part of the structure of the peripheral gate structure simultaneously, the process of the semiconductor structure can be effectively simplified. By forming an isolation well and a doped bit line contact structure by doping a substrate simultaneously, not only can the process of the semiconductor structure be effectively simplified, but also the electrical performance of the bit line contact structure can be improved. Therefore, the present disclosure can effectively simplify the process of the semiconductor structure and improve the electrical performance of the semiconductor structure.

[0049] The construction of the present disclosure as well as other inventive objects and advantageous effects thereof will be more clearly understood through the description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0051] Figure 1 A schematic diagram of a process for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0052] Figure 2 A schematic diagram of a process of providing a substrate in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0053] Figure 3 A schematic diagram of a process for forming a peripheral channel in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0054] Figure 4 A schematic diagram of a process for forming a buried word line in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0055] Figure 5 A schematic diagram of a process for forming a bit line contact structure and a peripheral gate structure in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0056] Figure 6 A schematic flow chart of a doped substrate and a bit line contact structure of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0057] Figure 7 A schematic diagram of a process for forming an array contact structure and a peripheral contact structure in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0058] Figure 8 A schematic diagram of a process for forming a capacitor structure and peripheral circuits in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0059] Fig. 9 A schematic diagram of the area division of a substrate of a semiconductor structure provided by an embodiment of the present disclosure;

[0060] Fig.10 A schematic structural diagram of an initial substrate of a semiconductor structure provided by an embodiment of the present disclosure;

[0061] Fig.11 A schematic structural diagram of a substrate and a second mask layer for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0062] Fig.12 A schematic diagram of a structure for forming an array channel and a peripheral channel of a semiconductor structure provided in an embodiment of the present disclosure;

[0063] Fig.13 A schematic structural diagram of removing the second mask layer of the semiconductor structure provided by an embodiment of the present disclosure;

[0064] Fig.14 A schematic structural diagram of forming a first trench in a semiconductor structure provided by an embodiment of the present disclosure;

[0065] Fig.15 A schematic diagram of a structure of a semiconductor structure providing an embodiment of the present disclosure that forms an array gate dielectric layer;

[0066] Fig.16 A schematic diagram of a structure of forming an array gate semiconductor layer and an array gate metal layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0067] Fig.17 A schematic diagram of a structure for forming an array gate protection layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0068] Fig.18 A schematic diagram of a structure for forming an initial gate dielectric layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0069] Fig.19 A schematic diagram of a structure for forming a peripheral gate dielectric layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0070] Fig. 20 A schematic diagram of a structure for forming an array source region, an array drain region, a peripheral source region and a peripheral drain region of a semiconductor structure provided in an embodiment of the present disclosure;

[0071] Fig.21 A schematic diagram of the structure of forming an initial semiconductor layer and an initial metal layer of a semiconductor structure provided in an embodiment of the present disclosure;

[0072] Fig. 22 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure that forms a bit line contact structure and a portion of a peripheral gate structure;

[0073] Fig.23 A schematic diagram of a structure for forming a peripheral gate protection layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0074] Fig.24 A schematic diagram of a structure for forming a sidewall of a semiconductor structure provided by an embodiment of the present disclosure;

[0075] Fig.25 A schematic structural diagram of forming a first mask layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0076] Fig.26 A schematic diagram of a structure for forming an isolation well and a doped bit line contact structure of a semiconductor structure provided in an embodiment of the present disclosure;

[0077] Fig. 27 A schematic diagram of a structure for forming a bit line of a semiconductor structure provided by an embodiment of the present disclosure;

[0078] Fig.28 A schematic structural diagram of a dielectric layer formed in a semiconductor structure provided by an embodiment of the present disclosure;

[0079] Fig.29 A schematic diagram of a structure for forming a channel of a semiconductor structure provided by an embodiment of the present disclosure;

[0080] Fig.30 A schematic diagram of a structure for forming an initial conductive layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0081] Fig.31 A schematic diagram of a structure forming an array contact structure and a peripheral contact structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0082] Fig.32 A schematic diagram of the structure of the semiconductor structure provided in the embodiment of the present disclosure that forms a capacitor structure and peripheral circuits.

[0083] Description of reference numerals:

[0084] 100, substrate; 100a, array active region; 100b, peripheral active region; 101, initial substrate; 101a, array region; 101b, peripheral region; 200, array transistor; 201, array channel; 201a, first trench; 201b, second trench; 202, array source region; 203, array drain region; 204, buried word line; 204a, array gate dielectric layer; 204b, array gate semiconductor layer; 204c, array gate metal layer; 204d, array gate protection layer; 205, bit line contact structure; 205a, contact semiconductor layer; 205b, contact metal layer; 300, peripheral transistor; 301, peripheral channel; 302, peripheral source region; 303, peripheral drain region; 304, peripheral gate Structure; 304a, peripheral gate dielectric layer; 304b, peripheral gate semiconductor layer; 304c, peripheral gate metal layer; 304d, peripheral gate protection layer; 305, side wall; 400, isolation well; 500, bit line; 600, array contact structure; 700, peripheral contact structure; 800, capacitor structure; 801, first capacitor conductive layer; 802, capacitor dielectric layer; 803, second capacitor conductive layer; 900, peripheral line; M1, first mask layer; M1a, first mask opening; M2, second mask layer; M2a, second mask opening; DL, dielectric layer; DLa, channel; L1, initial gate dielectric layer; L2, initial semiconductor layer; L3, initial metal layer; L4, initial protection layer; L5, initial conductive layer. DETAILED DESCRIPTION

[0085] DRAM includes an array area and a peripheral area surrounding the array area. The array area is provided with an array circuit and a plurality of memory cells arranged in an array. The array circuit is used to provide a driving current for the plurality of memory cells to realize the storage process of the memory cells. A peripheral circuit is provided in the peripheral area. The peripheral circuit is used to provide a driving current for the array circuit and control the working timing of the array circuit. Among them, the peripheral circuit includes sub-circuits with different driving functions, and the plurality of sub-circuits can provide driving signals with different functions for the array circuit. The array circuit in the array area includes a plurality of array transistors, and the memory cells may include any one of a capacitor and a magnetic tunnel junction. The sources (or drains) of the plurality of array transistors are connected to the plurality of memory cells in a one-to-one correspondence, and the drains (or sources) and gates of the plurality of array transistors are all connected to different sub-circuits of the peripheral circuit.

[0086] When the peripheral circuit is working, a subcircuit inputs a storage signal (or a read signal) to the source of the array transistor, and another subcircuit inputs a drive signal to the gate of the array transistor. When the drive signal acts on the array transistor to make it in a conductive state, the storage signal (or the read signal) is written into the storage unit through the drain of the array transistor to achieve signal storage (or reading). The multiple subcircuits in the peripheral circuit may include peripheral transistors with different conductivity types in the channel region, such as N-type transistors and P-type transistors. The array transistor in the array region may be an N-type transistor.

[0087] In the related art, the circuit structures in the array area and the peripheral area are prepared separately using different processes. Specifically, the array transistor is an N-type transistor as an example. For example, when preparing an N-type array transistor, a mask layer is needed to shield the peripheral area, and the substrate of the array area is etched and doped to form the structure of the array transistor. At the same time, it is also necessary to prepare the bit line, contact structure and capacitor structure of the array area by means of a mask. When preparing the peripheral transistor, it is also necessary to use a mask layer to shield the array area, and to etch and dope the substrate of the peripheral area. In addition, the N-type peripheral transistor and the P-type peripheral transistor with different conductivity types in the channel area also need to be doped separately. At the same time, it is also necessary to prepare the contact structure and peripheral circuit of the peripheral area by means of a mask. Therefore, in the above process, the mask layer needs to be used multiple times, and the preparation process is relatively cumbersome.

[0088] The method for preparing the semiconductor structure provided by the present disclosure provides a support foundation for the subsequent formation of the structure by setting a substrate. By forming a peripheral channel and a buried word line, a foundation is provided for the subsequent formation of an array transistor and a peripheral transistor. By forming a bit line contact structure and a part of the structure of the peripheral gate structure simultaneously, the process of the semiconductor structure can be effectively simplified. By forming an isolation well and a doped bit line contact structure by doping a substrate simultaneously, not only can the process of the semiconductor structure be effectively simplified, but also the electrical performance of the bit line contact structure can be improved. Therefore, the present disclosure can effectively simplify the process of the semiconductor structure and improve the electrical performance of the semiconductor structure.

[0089] In order to make the purpose, technical solution and advantages of the present disclosure clearer, the technical solution in the embodiment of the present disclosure will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present disclosure. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limitations on the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure. The embodiments of the present disclosure are described in detail below in conjunction with the drawings.

[0090] The present disclosure embodiment provides a method for preparing a semiconductor structure. The semiconductor structure may be a memory, and the memory may include a DRAM, a static random access memory (Static Random Access Memory, SRAM for short), a flash memory, an electrically erasable programmable read-only memory (EEPROM for short), a phase change random access memory (PRAM for short), or a magnetoresistive random access memory (MRAM for short). The present disclosure embodiment does not limit the specific type of memory. Below, the semiconductor structure is DRAM as an example for explanation.

[0091] Reference Figure 1 As shown, the method for preparing a semiconductor structure provided by an embodiment of the present disclosure includes:

[0092] S100: providing a substrate, wherein the substrate has an array active region and a peripheral active region that are spaced apart.

[0093] Reference Figure 2 As shown, a substrate 100 is provided, including: S101: providing an initial substrate, the initial substrate including an array region and a peripheral region; S102: performing doping treatment on the initial substrate to form an array active region in the substrate in the array region and a peripheral active region in the substrate in the peripheral region.

[0094] Combination Fig.10 , Fig. 22 , Fig.23 and Fig.32As shown, the initial substrate provided by the embodiment of the present disclosure may be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound or silicon on insulator (SOI), etc., or other materials known to those skilled in the art. The initial substrate may provide a structural basis for supporting the array transistor 200, peripheral transistor 300, capacitor structure 800, bit line 500 and peripheral line 900, etc., which are subsequently arranged. The initial substrate may be formed by deposition. For example, it may be a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), or an atomic layer deposition process (ALD).

[0095] Reference Fig. 9 and Fig.11 As shown, the array active area 100a and the peripheral active area 100b of the substrate 100 can be formed by doping the initial substrate, and the ion doping type of the array active area 100a and the peripheral active area 100b can be adjusted by controlling the doped ions. In this embodiment, the ions doped in the array active area 100a and the peripheral active area 100b can be group III elements (B or Ga), and the formation of the P-type array active area 100a and the peripheral active area 100b is used as an example for explanation. In other embodiments, the ions doped in the array active area 100a and the peripheral active area 100b can be group V elements (As or P), thereby forming the N-type array active area 100a and the peripheral active area 100b.

[0096] The initial substrate may include an array area 101a (array area) and a peripheral area 101b (periphery area), and the peripheral area 101b is arranged at the periphery of the array area 101a. The peripheral active area 100b formed by doping the initial substrate may be provided with a sense amplifier circuit (sense amplifier, SA for short) and a sub word line driver circuit (sub word line driver, SWD for short) (such as Fig. 9 As shown in FIG. 1 ). Based on the fact that a variety of circuits are arranged in the peripheral active region 100b, the circuits may include a peripheral transistor 300. The array active region 100a formed by doping the initial substrate is provided with an array transistor 200 and a memory cell.

[0097] In this embodiment, combined with Fig. 22 , Fig.23 and Fig.32As shown, the array active area 100a includes a storage structure and an array transistor 200. The embodiment of the present disclosure is described by taking the storage structure as a capacitor structure 800 as an example. Among them, the gate of the array transistor 200 is connected to the word line (Word Line, referred to as WL), the source is connected to the bit line 500 (Bit Line, referred to as BL), and the drain is connected to the capacitor structure 800. The word line is connected to the sub-word line driving circuit, and the sub-word line driving circuit controls the signal writing on the word line. The bit line 500 is connected to the sensing amplifier circuit, and the sensing amplifier circuit controls the signal writing or signal reading on the bit line 500. The voltage signal on the word line can control the opening or closing of the array transistor 200, read the data information stored in the capacitor structure 800 through the bit line 500, or write the data information into the capacitor structure 800 through the bit line 500 for storage. In the embodiment of the present disclosure, the gate of the array transistor 200 is the buried word line 204.

[0098] After the substrate 100 is formed, the following steps are included: S200 : forming a peripheral channel, where the peripheral channel is located in the peripheral active region.

[0099] Reference Figure 3 As shown, forming the peripheral channel 301 includes:

[0100] S201: forming a second mask layer, the second mask layer covers the substrate, and a second mask opening of the second mask layer exposes a portion of the peripheral active area. Fig.11 As shown, the second mask layer M2 can be formed by deposition, and the material of the second mask layer M2 can be silicon nitride or silicon oxynitride. The second mask opening M2a exposes a portion of the top surface of the substrate 100 of the peripheral active region 100b.

[0101] S202: doping the peripheral active region along the second mask opening to form a peripheral channel. The ion doping type of the peripheral channel 301 can be N-type or P-type. The ion doping type of the peripheral channel 301 can be the same as the ion doping type of the array channel 201, or different.

[0102] In an optional embodiment, the preparation method further includes: forming the array channel 201, and the formation of the array channel 201 is completed simultaneously with the formation of the peripheral channel 301. At this time, the ion doping type of the array channel 201 and the peripheral channel 301 is the same.

[0103] In this embodiment, forming the array channel 201 includes: S203: the second mask opening further exposes a portion of the array active region, and doping the array active region along the second mask opening to form the array channel.

[0104] Reference Fig.12As shown, in this embodiment, the second mask opening M2a exposes the top surface of the substrate 100 of a portion of the array active area 100a. Taking the ion doping type of the array channel 201 and the peripheral channel 301 as an example, both the array transistor 200 and the peripheral transistor 300 formed subsequently are N-type transistors. In this way, the array channel 201 and the peripheral channel 301 are doped simultaneously, which can effectively reduce the number of masks used in the formation process of the two, thereby simplifying the process of the semiconductor structure.

[0105] After forming the array channel 201 and the peripheral channel 301, the second mask layer M2 is removed. Fig.13 As shown, the array channels 201 and the peripheral channels 301 are formed and arranged in the substrate 100 at intervals.

[0106] In another optional embodiment, the preparation method further includes: forming an array channel 201, and the formation of the array channel 201 is completed after forming the peripheral channel 301 and before forming the buried word line 204. At this time, the ion doping type of the array channel 201 is different from that of the peripheral channel 301. The ion doping type of the array channel 201 is P-type, and the ion doping type of the peripheral channel 301 can be N-type, and the array transistor 200 formed accordingly is an N-type transistor, and the peripheral transistor 300 is a P-type transistor.

[0107] After forming the array channel 201 and the peripheral channel 301 , the method further includes: S300 : forming a buried word line, wherein the buried word line is located in the array active area and corresponds to the array channel in the array active area.

[0108] In an optional embodiment, the buried word line 204 includes an array gate dielectric layer 204a, an array gate semiconductor layer 204b, an array gate metal layer 204c and an array gate protection layer 204d. In the present disclosure, the buried word line 204 can be used as the gate of the array transistor 200.

[0109] Reference Figure 4 As shown, forming a buried word line 204 includes: S301: forming a first trench in the array channel. Fig.14 As shown, the first trench 201 a may be formed by mask etching, and the depth of the first trench 201 a may be smaller than the depth of the array trench 201 .

[0110] S302: forming an array gate dielectric layer in the first trench, wherein the array gate dielectric layer covers a portion of the inner wall of the trench, the top surface of the array gate dielectric layer is lower than the top surface of the substrate, and the array gate dielectric layer has a second trench. Fig.15As shown, the material of the array gate dielectric layer 204a can be selected from silicon oxide, hafnium oxide, doped hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, etc. The array gate dielectric layer 204a can be formed by deposition, covering the bottom and sidewalls of the first trench 201a, and there is a distance between the top surface of the array gate dielectric layer 204a located on the sidewalls of the trench and the top surface of the substrate 100. A second trench 201b is formed in the array gate dielectric layer 204a.

[0111] S303: forming an array gate semiconductor layer and an array gate metal layer in sequence in the second trench, wherein the top surface of the array gate metal layer is flush with the top surface of the array gate dielectric layer. Fig.16 As shown, the array gate semiconductor layer 204b and the array gate metal layer 204c can be formed in the second trench 201b by deposition. The material of the array gate semiconductor layer 204b can be polysilicon, and the material of the array gate metal layer 204c can be tungsten.

[0112] S304: forming an array gate protection layer in the first trench, the array gate protection layer covering the top surfaces of the array gate dielectric layer and the array gate metal layer, and the top surface of the array gate protection layer is flush with the top surface of the substrate. Fig.17 As shown, the array gate protection layer 204d can be formed in the first trench 201a by deposition. The material of the array gate protection layer 204d can be silicon nitride, which can protect the working stability of the array gate semiconductor layer 204b and the array gate metal layer 204c in the buried word line 204.

[0113] In the present disclosure, by disposing the buried word line 204 of the array transistor 200 in the substrate 100 , it is possible to avoid occupying the top space of the substrate 100 , thereby helping to improve the integration of the semiconductor structure.

[0114] Reference Fig.18 As shown, after the buried word line 204 is formed, it also includes: forming an array source region 202 and an array drain region 203 by mask doping. The array source region 202 and the array drain region 203 are respectively located on both sides of the array channel 201. When the array transistor 200 is an N-type transistor, the ion doping type of the array source region 202 and the array drain region 203 are both N-type. The array channel 201, the array source region 202, the array drain region 203 and the buried word line 204 together constitute the array transistor 200. In some embodiments, in addition to the above-mentioned structure, the array transistor 200 may also include other structures such as an array well region, and the specific structure of the array transistor 200 disclosed in the present invention is not limited to the above-mentioned example.

[0115] In this disclosure, reference is made to Figure 1As shown, after the buried word line 204 is formed, the process further includes: S400: forming a bit line contact structure and a peripheral gate structure, both of which are located on the substrate, the peripheral gate structure corresponds to the peripheral channel, and the bit line contact structure corresponds to and is connected to the array active area.

[0116] Combination Fig. 22 As shown, the peripheral gate structure includes a peripheral gate dielectric layer 304a, a peripheral gate semiconductor layer 304b, a peripheral gate metal layer 304c and a peripheral gate protection layer 304d; the bit line contact structure 205 includes a contact semiconductor layer 205a and a contact metal layer 205b.

[0117] Based on the specific structure of the above peripheral gate structure 304, refer to Figure 5 As shown, forming a peripheral gate structure 304 and a bit line contact structure 205 includes: S401: forming a peripheral gate dielectric layer, the peripheral gate dielectric layer is located on the substrate and corresponds to the peripheral channel.

[0118] Optional, combined Fig.19 As shown, forming a peripheral gate dielectric layer 304a includes: forming an initial gate dielectric layer L1, the initial gate dielectric layer L1 covers the substrate 100 located in the peripheral active area 100b. The initial gate dielectric layer L1 can be formed by deposition, and its material can be selected from silicon oxide, hafnium oxide, doped hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, etc.

[0119] Optional, continue to refer to Figure 5 As shown, after forming the initial gate dielectric layer L1, it also includes: S402: forming a peripheral gate semiconductor layer and a contact semiconductor layer, wherein the peripheral gate semiconductor layer is located on the peripheral gate dielectric layer, and the contact semiconductor layer is located on the substrate and corresponds to and is connected to the array active area.

[0120] S403: forming a peripheral gate metal layer and a contact metal layer, wherein the peripheral gate metal layer is located on the peripheral gate semiconductor layer, and the contact metal layer is located on the contact semiconductor layer.

[0121] S404: forming a peripheral gate protection layer, wherein the peripheral gate protection layer is located on the peripheral gate metal layer.

[0122] Among them, combined Fig. 20 As shown, forming the peripheral gate semiconductor layer 304b and the contact semiconductor layer 205a includes: forming an initial semiconductor layer L2, the initial semiconductor layer L2 covers the substrate 100 located in the array active area 100a and the initial gate dielectric layer L1.

[0123] Among them, combined Fig. 20As shown, forming the peripheral gate metal layer 304c and the contact metal layer 205b includes: forming an initial metal layer L3, the initial metal layer L3 covers the initial semiconductor layer L2. The initial semiconductor layer L2 and the initial metal layer L3 can be formed by deposition, the material of the initial semiconductor layer L2 can be polysilicon, and the material of the initial metal layer L3 can be tungsten.

[0124] Among them, combined Fig.21 As shown, forming a peripheral gate protection layer 304d includes: forming an initial protection layer L4, the initial protection layer L4 covers the initial metal layer L3 corresponding to the peripheral active area 100b. The initial protection layer L4 can be formed by deposition, and its material can be silicon nitride. The initial protection layer L4 can protect the initial metal layer L3, the initial semiconductor layer L2 and the initial gate dielectric layer L1 at the bottom corresponding to it. Fig. 22 As shown, the initial gate dielectric layer L1, the initial semiconductor layer L2, the initial metal layer L3 and the initial protection layer L4 can form a peripheral gate structure 304 after being processed. Therefore, the initial protection layer L4 is conducive to ensuring the structural stability of the peripheral gate structure 304 formed subsequently.

[0125] Optional, see Fig. 22 As shown, after the initial protection layer L4 is formed, the process further includes: removing a portion of the initial gate dielectric layer L1, a portion of the initial semiconductor layer L2, a portion of the initial metal layer L3 and a portion of the initial protection layer L4.

[0126] The removal method may be mask etching, and the initial semiconductor layer L2 and the initial metal layer L3 corresponding to the array active area 100a are retained to form the contact semiconductor layer 205a and the contact metal layer 205b of the bit line contact structure 205. The initial gate dielectric layer L1, the initial semiconductor layer L2, the initial metal layer L3 and the initial protection layer L4 corresponding to the peripheral channel 301 are retained to form the peripheral gate dielectric layer 304a, the peripheral gate semiconductor layer 304b, the peripheral gate metal layer 304c and the peripheral gate protection layer 304d of the peripheral gate structure 304. The material of the peripheral gate dielectric layer 304a and the array gate dielectric layer 204a may be the same.

[0127] The contact semiconductor layer 205a of the bit line contact structure 205 abuts and conducts with the array source region 202 to achieve signal transmission. In other embodiments, the contact semiconductor layer 205a may also abut and conduct with the array drain region 203, which is not limited in the present disclosure.

[0128] In the present disclosure, by preparing the bit line contact structure 205 and part of the peripheral gate structure 304 at the same time, compared with preparing the two separately, the process of the semiconductor structure can be effectively reduced and the process complexity can be reduced.

[0129] It should be pointed out that, referring to Fig.23 As shown, after forming the peripheral gate structure 304, the peripheral source region 302 and the peripheral drain region 303 can be formed by mask doping. The peripheral source region 302 and the peripheral drain region 303 are located on both sides of the peripheral channel 301. The peripheral transistor 300 can be an N-type transistor, and the ion doping type of the peripheral source region 302 and the peripheral drain region 303 are both N-type. Alternatively, when the peripheral transistor 300 can be a P-type transistor, the ion doping type of the peripheral source region 302 and the peripheral drain region 303 are both P-type.

[0130] Reference Fig.24 As shown, after the peripheral gate structure 304 is formed, it also includes: forming a side wall 305, and the side wall 305 covers the side of the peripheral gate structure 304. The side wall 305 can be made of an insulating material, and the material of the side wall 305 can include silicon oxide, silicon nitride or silicon oxynitride. In some embodiments, along the direction away from the side of the peripheral gate structure 304, the side wall 305 may include an oxide layer, a nitride layer and an oxide layer stacked in sequence (that is, an ONO structure), or a nitride layer, an oxide layer and a nitride layer stacked in sequence (that is, a NON structure). In other embodiments, the side wall 305 may have an air gap structure (gap) inside. The above-mentioned side walls 305 all have a good isolation effect, can protect the peripheral gate structure 304, and improve the structural and electrical stability of the peripheral gate structure 304. In the present application Fig.23 and Fig.24 In the structure shown, the sidewall spacer 305 is formed after the peripheral source region 302 and the peripheral drain region 303. In other embodiments, the sidewall spacer 305 may also be formed before the peripheral source region 302 and the peripheral drain region 303. The present application does not limit the order of forming the sidewall spacer 305, the peripheral source region 302 and the peripheral drain region 303.

[0131] Combination Figure 1 As shown, after the peripheral gate structure 304 and the bit line contact structure 205 are formed, the process further includes: S500: doping a portion of the substrate and the bit line contact structure to form isolation wells in the array active region and the peripheral active region.

[0132] Optional, see Figure 6 As shown, the doping process of the substrate 100 and the bit line contact structure 205 includes:

[0133] S501: forming a first mask layer, the first mask layer covers the substrate and the bit line contact structure, and the first mask opening of the first mask layer exposes a portion of the array active area and a portion of the peripheral active area, as well as the bit line contact structure. Fig.25As shown, the first mask layer M1 can be formed by deposition, and the material of the first mask layer M1 can be silicon nitride or silicon oxynitride. The first mask layer M1 can cover the substrate 100 and the bit line contact structure 205, and the top surface of the first mask layer M1 is higher than the top surface of the bit line contact structure 205 and the peripheral gate structure 304.

[0134] S502: doping the exposed substrate and bit line contact structure along the first mask opening to form isolation wells in the array active area and the peripheral active area. Fig.26 As shown, the first mask opening M1a can expose the array transistor 200, the peripheral transistor 300, the bit line contact structure 205, and a portion of the top surface of the substrate 100 near the array transistor 200 and the peripheral transistor 300. Along the first mask opening M1a, by adjusting the angle of ion doping, a portion of the substrate 100 near the array transistor 200 and the peripheral transistor 300, and a contact semiconductor layer 205a of the bit line contact structure 205 are doped, so that an isolation well 400 can be formed in the substrate 100.

[0135] The isolation well 400 and the contact semiconductor layer 205a have the same ion doping type, and both can be N-type. After the contact semiconductor layer 205a of the bit line contact structure 205 is doped with N-type ions, the contact resistance between the bit line contact structure 205 and the N-type array source region 202 can be effectively reduced, thereby improving the electron transmission efficiency of the bit line contact structure 205 between the array source region 202 and the subsequently formed bit line 500, which helps to improve the electrical performance of the semiconductor structure.

[0136] It should be noted that the drawings of this embodiment show that the isolation well 400 surrounds the array source region 202, the array channel 201 and the array drain region 203, and surrounds the peripheral source region 302, the peripheral channel 301 and the peripheral drain region 303. In this way, the array transistor 200 and the peripheral transistor 300 can be prevented from being electrically interfered. The depth of the isolation well 400 can be greater than the depth of the array channel 201 and the peripheral channel 301, and can also be greater than the depth of the array source region 202, the array drain region 203, the peripheral drain region 303 and the peripheral source region 302, so as to improve the isolation effect.

[0137] After the doping of the substrate 100 and the bit line contact structure 205 is completed, the first mask layer M1 can be removed to form Fig. 27 structure.

[0138] Continue to refer to Figure 1 As shown, in the present disclosure, after the doping treatment of the substrate 100 and the bit line contact structure 205, the following further includes: S600: forming a bit line, the bit line is connected to the bit line contact structure. Fig. 27As shown, the bit line 500 can be formed on the bit line contact structure 205 by deposition, and the material of the bit line 500 can be titanium nitride, tungsten, rubidium or copper.

[0139] In some embodiments, a concave structure and / or a convex structure (not shown in the figure) may be provided on the top of the bit line contact structure 205. After the bit line 500 is deposited, a convex structure and / or a concave structure corresponding in position and matching in shape to the concave structure and / or convex structure of the bit line contact structure 205 may be formed, so that the contact surface of the bit line 500 and the bit line contact structure 205 is connected by the concave and convex shapes. In this way, the contact area between the two can be increased, the contact resistance can be reduced, and the electrical signal transmission capability between the two can be improved, which is helpful to improve the electrical performance of the semiconductor structure.

[0140] Optional, continue to refer to Figure 1 As shown, after the bit line 500 is formed, the process further includes: S700: forming an array contact structure and a peripheral contact structure, wherein the array contact structure is connected to the array active region, and the peripheral contact structure is connected to the peripheral active region and the peripheral gate structure.

[0141] Reference Figure 7 As shown, an array contact structure 600 and a peripheral contact structure 700 are formed, including:

[0142] S701: forming a dielectric layer, the dielectric layer covers the substrate, the bit line contact structure, the bit line and the peripheral gate structure. Fig.28 As shown, the dielectric layer DL may be formed by deposition, and the material of the dielectric layer DL may be silicon oxide or silicon oxynitride.

[0143] S702: forming a channel in the dielectric layer, wherein the channel exposes the array active area and the peripheral active area. Fig.29 As shown, the channel DLa can be formed by mask etching, and the depth of the channel DLa needs to ensure that the substrate 100 is exposed. The channel DLa corresponds to the array drain region 203 of the array active region 100a, and corresponds to the peripheral source region 302 and the peripheral drain region 303 of the peripheral active region 100b.

[0144] S703: forming an initial conductive layer in the channel, the initial conductive layer connected to the array active area forms an array contact structure, and the initial conductive layer connected to the peripheral active area and the peripheral gate structure forms a peripheral contact structure. Fig.30 As shown, the initial conductive layer L5 is formed by deposition, and the initial conductive layer L5 corresponding to the position of the trench DLa is filled in the trench DLa. The material of the initial conductive layer L5 can be titanium nitride, tungsten or copper. Fig.31As shown, by chemical mechanical polishing (CMP), part of the initial conductive layer L5 is removed along the surface of the dielectric layer DL, and the initial conductive layer L5 in the channel DLa is retained. The initial conductive layer L5 in the channel DLa correspondingly connected to the array drain region 203 forms an array contact structure 600, and the initial conductive layer L5 in the channel DLa correspondingly connected to the peripheral source region 302 and the peripheral drain region 303 forms a peripheral contact structure 700. It should be noted that Fig.31 The peripheral contact structure 700 connected to the peripheral gate structure 304 is not shown in the cross-sectional view of FIG.

[0145] Continue to refer to Figure 1 As shown, after the array contact structure 600 and the peripheral contact structure 700 are formed, the following further includes: S800: forming a capacitor structure and a peripheral circuit, wherein the capacitor structure is connected to the array contact structure, and the peripheral circuit is connected to the peripheral contact structure.

[0146] Combination Fig.32 As shown, the capacitor structure 800 includes a first capacitor conductive layer 801, a capacitor dielectric layer DL and a second capacitor conductive layer 803. Figure 8 As shown, a capacitor structure 800 and a peripheral circuit 900 are formed, including:

[0147] S801: forming a first capacitor conductive layer, where the first capacitor conductive layer is located on the dielectric layer and corresponds to and is connected to the array contact structure.

[0148] S802: forming a capacitor dielectric layer, wherein the capacitor dielectric layer is located on the first capacitor conductive layer.

[0149] S803: forming a second capacitor conductive layer and a peripheral circuit, wherein the second capacitor conductive layer is located on the capacitor dielectric layer, and the peripheral circuit is located on the dielectric layer and corresponds to and is connected to the peripheral contact structure.

[0150] It should be noted that the materials of the first capacitor conductive layer 801, the second capacitor conductive layer 803 and the peripheral circuit 900 can be the same, and the first capacitor conductive layer 801 and the peripheral circuit 900 are formed synchronously, so that the process of the semiconductor structure can be effectively simplified. In other embodiments, the peripheral circuit 900 can also be formed synchronously with the second capacitor conductive layer 803, and the present disclosure does not limit this.

[0151] The first capacitor conductive layer 801 corresponds to and is connected to the array contact structure 600, so as to realize the transmission of the electrical signal of the array drain region 203 of the array transistor 200 to the capacitor structure 800, or read the electrical signal stored in the capacitor structure 800. The peripheral circuit 900 corresponds to and is connected to the peripheral contact structure 700, so as to realize the transmission of the electrical signal between the peripheral source region 302 and the peripheral drain region 303 of the peripheral transistor 300 and the peripheral circuit 900. Among them, the peripheral circuit 900 connected to the peripheral source region 302 and the peripheral circuit 900 connected to the peripheral drain region 303 are different circuits, so as to realize the transmission of the electrical signal of the peripheral transistor 300.

[0152] In the description of the embodiments of the present disclosure, it should be understood that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances. The orientation or position relationship indicated by the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise precisely and specifically specified.

[0153] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present disclosure described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0154] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has an array active region and a peripheral active region that are spaced apart; forming a peripheral channel, the peripheral channel being located in the peripheral active region; forming a buried word line, wherein the buried word line is located in the array active area and corresponds to an array channel in the array active area; forming a bit line contact structure and a peripheral gate structure, wherein both the peripheral gate structure and the bit line contact structure are located on the substrate, the peripheral gate structure corresponds to the peripheral channel, and the bit line contact structure corresponds to and is connected to the array active area; Part of the substrate and the bit line contact structure are doped to form isolation wells in the array active area and the peripheral active area.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: Also includes: The array channel is formed, and the formation of the array channel and the formation of the peripheral channel are completed simultaneously.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: Also includes: The array channel is formed, and the formation of the array channel is completed after the formation of the peripheral channel and before the formation of the buried word line.

4. The method for preparing a semiconductor structure according to claim 2 or 3, characterized in that: The doping treatment part of the substrate and the bit line contact structure includes: Forming a first mask layer, wherein the first mask layer covers the substrate and the bit line contact structure, and a first mask opening of the first mask layer exposes a portion of the array active area and a portion of the peripheral active area, as well as the bit line contact structure; The substrate and the bit line contact structure exposed by doping are performed along the first mask opening to form the isolation well in the array active area and the peripheral active area.

5. The method for preparing a semiconductor structure according to claim 2 or 3, characterized in that: The peripheral gate structure includes a peripheral gate dielectric layer, a peripheral gate semiconductor layer, a peripheral gate metal layer and a peripheral gate protection layer; The bit line contact structure includes a contact semiconductor layer and a contact metal layer; Forming the peripheral gate structure and the bit line contact structure includes: forming the peripheral gate dielectric layer, wherein the peripheral gate dielectric layer is located on the substrate and corresponds to the peripheral channel; Forming the peripheral gate semiconductor layer and the contact semiconductor layer, wherein the peripheral gate semiconductor layer is located on the peripheral gate dielectric layer, and the contact semiconductor layer is located on the substrate and corresponds to and is connected to the array active area; forming the peripheral gate metal layer and the contact metal layer, wherein the peripheral gate metal layer is located on the peripheral gate semiconductor layer, and the contact metal layer is located on the contact semiconductor layer; The peripheral gate protection layer is formed, and the peripheral gate protection layer is located on the peripheral gate metal layer.

6. The method for preparing a semiconductor structure according to claim 2, characterized in that: Forming the peripheral channel includes: forming a second mask layer, wherein the second mask layer covers the substrate, and a second mask opening of the second mask layer exposes a portion of the peripheral active area; The peripheral active region is doped along the second mask opening to form the peripheral channel.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: Forming the array channel comprises: The second mask opening also exposes a portion of the array active region, and the array active region is doped along the second mask opening to form the array channel.

8. The method for preparing a semiconductor structure according to claim 5, characterized in that: Forming the peripheral gate dielectric layer includes: forming an initial gate dielectric layer, wherein the initial gate dielectric layer covers the substrate located in the peripheral active area; Forming the peripheral gate semiconductor layer and the contact semiconductor layer includes: forming an initial semiconductor layer, the initial semiconductor layer covering the substrate and the initial gate dielectric layer located in the array active area; Forming the peripheral gate metal layer and the contact metal layer includes: forming an initial metal layer, wherein the initial metal layer covers the initial semiconductor layer; The peripheral gate protection layer is formed, including: forming an initial protection layer, wherein the initial protection layer covers the initial metal layer corresponding to the peripheral active area.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: After forming the initial protective layer, the method further comprises: removing part of the initial gate dielectric layer, part of the initial semiconductor layer, part of the initial metal layer and part of the initial protective layer; The initial semiconductor layer and the initial metal layer corresponding to the array active area are retained to form the contact semiconductor layer and the contact metal layer of the bit line contact structure respectively; the initial gate dielectric layer, the initial semiconductor layer, the initial metal layer and the initial protective layer corresponding to the peripheral channel are retained to form the peripheral gate dielectric layer, the peripheral gate semiconductor layer, the peripheral gate metal layer and the peripheral gate protective layer of the peripheral gate structure respectively.

10. The method for preparing a semiconductor structure according to claim 2 or 3, characterized in that: The buried word line comprises an array gate dielectric layer, an array gate semiconductor layer, an array gate metal layer and an array gate protection layer; Forming the buried word line comprises: forming a first trench in the array channel; forming an array gate dielectric layer in the first trench, wherein the array gate dielectric layer covers a portion of the inner wall of the trench, the top surface of the array gate dielectric layer is lower than the top surface of the substrate, and the array gate dielectric layer has a second trench; forming the array gate semiconductor layer and the array gate metal layer in sequence in the second trench, wherein the top surface of the array gate metal layer is flush with the top surface of the array gate dielectric layer; The array gate protection layer is formed in the first trench, the array gate protection layer covers the top surfaces of the array gate dielectric layer and the array gate metal layer, and the top surface of the array gate protection layer is flush with the top surface of the substrate.

11. The method for preparing a semiconductor structure according to claim 2 or 3, characterized in that: Providing the substrate, including: Providing an initial substrate, wherein the initial substrate comprises an array region and a peripheral region; The initial substrate is doped to form the array active region in the substrate in the array region and the peripheral active region in the substrate in the peripheral region.

12. The method for preparing a semiconductor structure according to claim 2 or 3, characterized in that: After the substrate and the bit line contact structure are partially doped, the method further includes: forming a bit line, wherein the bit line is connected to the bit line contact structure.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that: After forming the bit line, the method further includes: forming an array contact structure and a peripheral contact structure, wherein the array contact structure is connected to the array active area, and the peripheral contact structure is connected to the peripheral active area and the peripheral gate structure; A capacitor structure and a peripheral circuit are formed, wherein the capacitor structure is connected to the array contact structure, and the peripheral circuit is connected to the peripheral contact structure.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that: Forming the array contact structure and the peripheral contact structure includes: forming a dielectric layer, wherein the dielectric layer covers the substrate, the bit line contact structure, the bit line and the peripheral gate structure; forming a channel in the dielectric layer, wherein the channel exposes the array active area and the peripheral active area; An initial conductive layer is formed in the channel, the initial conductive layer connected to the array active area forms the array contact structure, and the initial conductive layer connected to the peripheral active area and the peripheral gate structure forms the peripheral contact structure.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that: The capacitor structure comprises a first capacitor conductive layer, a capacitor dielectric layer and a second capacitor conductive layer; Forming the capacitor structure and the peripheral circuit includes: Forming a first capacitor conductive layer and the peripheral circuit, wherein the first capacitor conductive layer is located on the dielectric layer and corresponds to and is connected to the array contact structure, and the peripheral circuit is located on the dielectric layer and corresponds to and is connected to the peripheral contact structure; forming a capacitor dielectric layer, wherein the capacitor dielectric layer is located on the first capacitor conductive layer; A second capacitor conductive layer is formed, wherein the second capacitor conductive layer is located on the capacitor dielectric layer.

Images