Method for preparing semiconductor structure

Abstract

The present disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate having an array active region and a peripheral active region spaced apart; forming a peripheral channel located in the peripheral active region; forming a buried word line located in the array active region and corresponding to the array channel in the array active region; forming a bit line contact structure and a peripheral gate structure, both located on the substrate, the peripheral gate structure corresponding to the peripheral channel, and the bit line contact structure corresponding to and connected to the array active region; and doping a portion of the substrate and the bit line contact structure to form isolation wells in the substrate in the array active region and the peripheral active region. The present disclosure can simplify the fabrication process of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that can write and read data randomly at high speed and is widely used in data storage devices or apparatuses.

[0003] DRAM consists of an array area and a peripheral area surrounding the array area. The array area is equipped with array circuits and multiple memory cells arranged in an array. The array circuit is used to provide drive current to the multiple memory cells to implement the storage process of the memory cells. The peripheral area is equipped with peripheral circuits, which are used to provide drive current to the array circuit and control the operating timing of the array circuit. In related art, the circuit structures of the array area and the peripheral area are prepared separately.

[0004] However, the manufacturing process of the above-mentioned DRAM is relatively complicated. Summary of the Invention

[0005] The present disclosure provides a method for preparing a semiconductor structure, which can effectively simplify the manufacturing process of the semiconductor structure.

[0006] The present disclosure provides a method for preparing a semiconductor structure, comprising:

[0007] Providing a substrate having an array active region and a peripheral active region that are spaced apart;

[0008] forming a peripheral channel, wherein the peripheral channel is located in the peripheral active region;

[0009] forming a buried word line, wherein the buried word line is located in the array active area and corresponds to the array channel in the array active area;

[0010] forming a bit line contact structure and a peripheral gate structure, both of which are located on the substrate, the peripheral gate structure corresponding to the peripheral channel, and the bit line contact structure corresponding to and connected to the array active area;

[0011] Part of the substrate and the bit line contact structure are doped to form isolation wells in the array active area and the peripheral active area.

[0012] In the above-mentioned method for preparing the semiconductor structure, optionally, it further includes: forming an array channel, and the formation of the array channel and the formation of the peripheral channel are completed simultaneously.

[0013] In the above-mentioned method for preparing a semiconductor structure, optionally, it further includes: forming an array channel, and the formation of the array channel is completed after forming the peripheral channel and before forming the buried word line.

[0014] In the above-mentioned method for preparing a semiconductor structure, optionally, doping a portion of the substrate and the bit line contact structure includes: forming a first mask layer, the first mask layer covering the substrate and the bit line contact structure, a first mask opening of the first mask layer exposing a portion between the array active region and a portion of the peripheral active region, and exposing the bit line contact structure;

[0015] The exposed substrate and bit line contact structure are doped along the first mask opening to form isolation wells in the array active area and the peripheral active area.

[0016] In the above-mentioned method for preparing a semiconductor structure, optionally, the peripheral gate structure includes a peripheral gate dielectric layer, a peripheral gate semiconductor layer, a peripheral gate metal layer, and a peripheral gate protection layer; the bit line contact structure includes a contact semiconductor layer and a contact metal layer; and forming the peripheral gate structure and the bit line contact structure includes:

[0017] forming a peripheral gate dielectric layer, the peripheral gate dielectric layer being located on the substrate and corresponding to the peripheral channel;

[0018] forming a peripheral gate semiconductor layer and a contact semiconductor layer, wherein the peripheral gate semiconductor layer is located on the peripheral gate dielectric layer, and the contact semiconductor layer is located on the substrate and corresponds to and is connected to the array active area;

[0019] forming a peripheral gate metal layer and a contact metal layer, wherein the peripheral gate metal layer is located on the peripheral gate semiconductor layer, and the contact metal layer is located on the contact semiconductor layer;

[0020] A peripheral gate protection layer is formed, and the peripheral gate protection layer is located on the peripheral gate metal layer.

[0021] In the above-mentioned method for preparing a semiconductor structure, optionally, forming the peripheral channel includes: forming a second mask layer, the second mask layer covering the substrate, and a second mask opening of the second mask layer exposing a portion of the peripheral active area;

[0022] Doping the peripheral active region along the second mask opening to form a peripheral channel.

[0023] In the above-mentioned method for preparing a semiconductor structure, optionally, forming the array channel includes: the second mask opening further exposing a portion of the array active area;

[0024] The array active region is doped along the second mask opening to form an array channel.

[0025] In the above-mentioned method for preparing the semiconductor structure, optionally, forming the peripheral gate dielectric layer includes: forming an initial gate dielectric layer, the initial gate dielectric layer covering the substrate located in the peripheral active area;

[0026] Forming a peripheral gate semiconductor layer and a contact semiconductor layer includes: forming an initial semiconductor layer, the initial semiconductor layer covering the substrate located in the array active area and the initial gate dielectric layer;

[0027] Forming a peripheral gate metal layer and a contact metal layer includes: forming an initial metal layer, wherein the initial metal layer covers the initial semiconductor layer;

[0028] The peripheral gate protection layer is formed, including: forming an initial protection layer, wherein the initial protection layer covers the initial metal layer corresponding to the peripheral active area.

[0029] In the above-mentioned method for preparing a semiconductor structure, optionally, after forming the initial protective layer, the method further comprises: removing a portion of the initial gate dielectric layer, a portion of the initial semiconductor layer, a portion of the initial metal layer, and a portion of the initial protective layer;

[0030] The initial semiconductor layer and the initial metal layer corresponding to the array active area are retained to form the contact semiconductor layer and the contact metal layer of the bit line contact structure respectively; the initial gate dielectric layer, the initial semiconductor layer, the initial metal layer and the initial protective layer corresponding to the peripheral channel are retained to form the peripheral gate dielectric layer, the peripheral gate semiconductor layer, the peripheral gate metal layer and the peripheral gate protective layer of the peripheral gate structure respectively.

[0031] In the above-mentioned method for preparing a semiconductor structure, optionally, the buried word line includes an array gate dielectric layer, an array gate semiconductor layer, an array gate metal layer and an array gate protection layer;

[0032] Forming a buried word line includes: forming a first trench in an array channel;

[0033] forming an array gate dielectric layer in the first trench, the array gate dielectric layer covering a portion of the inner wall of the trench, the top surface of the array gate dielectric layer being lower than the top surface of the substrate, and the array gate dielectric layer having a second trench;

[0034] forming an array gate semiconductor layer and an array gate metal layer in sequence in the second trench, wherein the top surface of the array gate metal layer is flush with the top surface of the array gate dielectric layer;

[0035] An array gate protection layer is formed in the first trench, the array gate protection layer covers the top surfaces of the array gate dielectric layer and the array gate metal layer, and the top surface of the array gate protection layer is flush with the top surface of the substrate.

[0036] In the above-mentioned method for preparing a semiconductor structure, optionally, providing a substrate includes: providing an initial substrate, the initial substrate including an array region and a peripheral region;

[0037] The initial substrate is doped to form an array active region in the substrate in the array region and a peripheral active region in the substrate in the peripheral region.

[0038] In the above-mentioned method for preparing a semiconductor structure, optionally, after doping a portion of the substrate and the bit line contact structure, the method further includes: forming a bit line, and connecting the bit line to the bit line contact structure.

[0039] In the above-mentioned method for preparing a semiconductor structure, optionally, after forming the bit line, the method further includes: forming an array contact structure and a peripheral contact structure, wherein the array contact structure is connected to the array active region, and the peripheral contact structure is connected to the peripheral active region and the peripheral gate structure;

[0040] A capacitor structure and a peripheral circuit are formed, wherein the capacitor structure is connected to the array contact structure, and the peripheral circuit is connected to the peripheral contact structure.

[0041] In the above-mentioned method for preparing the semiconductor structure, optionally, forming the array contact structure and the peripheral contact structure includes: forming a dielectric layer, the dielectric layer covering the substrate, the bit line contact structure, the bit line and the peripheral gate structure;

[0042] forming a channel in the dielectric layer, wherein the channel exposes the array active area and the peripheral active area;

[0043] An initial conductive layer is formed in the channel, the initial conductive layer connected to the array active area forms an array contact structure, and the initial conductive layer connected to the peripheral active area and the peripheral gate structure forms a peripheral contact structure.

[0044] In the above-mentioned method for preparing a semiconductor structure, optionally, the capacitor structure includes a first capacitor conductive layer, a capacitor dielectric layer, and a second capacitor conductive layer;

[0045] Forming a capacitor structure and a peripheral circuit includes: forming a first capacitor conductive layer and a peripheral circuit, wherein the first capacitor conductive layer is located on the dielectric layer and corresponds to and is connected to the array contact structure; and the peripheral circuit is located on the dielectric layer and corresponds to and is connected to the peripheral contact structure;

[0046] forming a capacitor dielectric layer, the capacitor dielectric layer being located on the first capacitor conductive layer;

[0047] A second capacitor conductive layer is formed, and the second capacitor conductive layer is located on the capacitor dielectric layer.

[0048] The method for preparing a semiconductor structure provided by the present disclosure provides a support foundation for the subsequent formation of the structure by setting a substrate. By forming a peripheral channel and a buried word line, a foundation is provided for the subsequent formation of an array transistor and a peripheral transistor. By synchronously forming a bit line contact structure and a portion of a peripheral gate structure, the manufacturing process of the semiconductor structure can be effectively simplified. By synchronously completing the formation of an isolation well and a doped bit line contact structure on a doped substrate, not only can the manufacturing process of the semiconductor structure be effectively simplified, but the electrical performance of the bit line contact structure can also be improved. Therefore, the present disclosure can effectively simplify the manufacturing process of the semiconductor structure and improve the electrical performance of the semiconductor structure.

[0049] The configuration of the present disclosure and other inventive objects and advantageous effects thereof will become more apparent through the description of preferred embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0051] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0052] Figure 2 A schematic diagram of a process for providing a substrate in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0053] Figure 3 A schematic diagram of a process for forming a peripheral channel in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0054] Figure 4 A schematic diagram of a process for forming a buried word line in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0055] Figure 5 A schematic diagram of a process for forming a bit line contact structure and a peripheral gate structure in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0056] Figure 6 A schematic flow chart of a doped substrate and a bit line contact structure in a method for fabricating a semiconductor structure provided by an embodiment of the present disclosure;

[0057] Figure 7 A schematic diagram of a process for forming an array contact structure and a peripheral contact structure in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0058] Figure 8 A schematic diagram of a process for forming a capacitor structure and peripheral circuits in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0059] Figure 9 A schematic diagram of the region division of a substrate of a semiconductor structure provided by an embodiment of the present disclosure;

[0060] Figure 10 A schematic structural diagram of an initial substrate for a semiconductor structure provided by an embodiment of the present disclosure;

[0061] Figure 11 A schematic structural diagram of a substrate and a second mask layer for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0062] Figure 12 A schematic structural diagram of forming array channels and peripheral channels of a semiconductor structure provided by an embodiment of the present disclosure;

[0063] Figure 13 A schematic structural diagram of removing the second mask layer of the semiconductor structure provided by an embodiment of the present disclosure;

[0064] Figure 14 A schematic structural diagram of forming a first trench in a semiconductor structure provided by an embodiment of the present disclosure;

[0065] Figure 15 A schematic structural diagram of a semiconductor structure forming an array gate dielectric layer according to an embodiment of the present disclosure;

[0066] Figure 16 A schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure that forms an array gate semiconductor layer and an array gate metal layer;

[0067] Figure 17 A schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure that forms an array gate protection layer;

[0068] Figure 18 A schematic structural diagram of forming an initial gate dielectric layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0069] Figure 19 A schematic structural diagram of forming a peripheral gate dielectric layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0070] Figure 20 A schematic structural diagram of forming an array source region, an array drain region, a peripheral source region, and a peripheral drain region of a semiconductor structure provided by an embodiment of the present disclosure;

[0071] Figure 21 A schematic structural diagram of forming an initial semiconductor layer and an initial metal layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0072] Figure 22 A schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure that forms a bit line contact structure and a portion of a peripheral gate structure;

[0073] Figure 23 A schematic structural diagram of forming a peripheral gate protection layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0074] Figure 24 A schematic diagram of a structure for forming a sidewall spacer in a semiconductor structure provided by an embodiment of the present disclosure;

[0075] Figure 25 A schematic structural diagram of forming a first mask layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0076] Figure 26 A schematic structural diagram of forming an isolation well and a doped bit line contact structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0077] Figure 27 A schematic structural diagram of forming a bit line of a semiconductor structure provided by an embodiment of the present disclosure;

[0078] Figure 28 A schematic structural diagram of a dielectric layer formed in a semiconductor structure provided by an embodiment of the present disclosure;

[0079] Figure 29 A schematic structural diagram of a channel forming semiconductor structure provided by an embodiment of the present disclosure;

[0080] Figure 30 A schematic structural diagram of forming an initial conductive layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0081] Figure 31 A schematic structural diagram of forming an array contact structure and a peripheral contact structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0082] Figure 32 A schematic structural diagram of a capacitor structure and peripheral circuits formed in a semiconductor structure provided in an embodiment of the present disclosure.

[0083] Description of reference numerals:

[0084] 100, substrate; 100a, array active region; 100b, peripheral active region; 101, initial substrate; 101a, array region; 101b, peripheral region; 200, array transistor; 201, array channel; 201a, first trench; 201b, second trench; 202, array source region; 203, array drain region; 204, buried word line; 204a, array gate dielectric layer; 204b, array gate semiconductor layer; 204c, array gate metal layer; 204d, array gate protection layer; 205, bit line contact structure; 205a, contact semiconductor layer; 205b, contact metal layer; 300, peripheral transistor; 301, peripheral channel; 302, peripheral source region; 303, peripheral drain region; 304, peripheral gate Structure; 304a, peripheral gate dielectric layer; 304b, peripheral gate semiconductor layer; 304c, peripheral gate metal layer; 304d, peripheral gate protective layer; 305, sidewall; 400, isolation well; 500, bit line; 600, array contact structure; 700, peripheral contact structure; 800, capacitor structure; 801, first capacitor conductive layer; 802, capacitor dielectric layer; 803, second capacitor conductive layer; 900, peripheral line; M1, first mask layer; M1a, first mask opening; M2, second mask layer; M2a, second mask opening; DL, dielectric layer; DLa, channel; L1, initial gate dielectric layer; L2, initial semiconductor layer; L3, initial metal layer; L4, initial protective layer; L5, initial conductive layer. DETAILED DESCRIPTION

[0085] DRAM includes an array area and a peripheral area surrounding the array area. The array area is provided with an array circuit and a plurality of memory cells arranged in an array. The array circuit is used to provide a driving current for the plurality of memory cells to realize the storage process of the memory cells. A peripheral circuit is provided in the peripheral area. The peripheral circuit is used to provide a driving current for the array circuit and control the working timing of the array circuit. Among them, the peripheral circuit includes sub-circuits with different driving functions, and the plurality of sub-circuits can provide driving signals with different functions for the array circuit. The array circuit in the array area includes a plurality of array transistors, and the memory cells may include any one of a capacitor and a magnetic tunnel junction. The source (or drain) of the plurality of array transistors is connected to the plurality of memory cells in a one-to-one correspondence, and the drain (or source) and gate of the plurality of array transistors are all connected to different sub-circuits of the peripheral circuit.

[0086] When the peripheral circuit is operating, a subcircuit inputs a storage signal (or a read signal) to the source of the array transistor, and another subcircuit inputs a drive signal to the gate of the array transistor. When the drive signal acts on the array transistor, causing it to be in the on state, the storage signal (or the read signal) is written into the memory cell through the drain of the array transistor, realizing the storage (or reading) of the signal. The multiple subcircuits in the peripheral circuit can include peripheral transistors with different conductivity types in the channel region, such as N-type transistors and P-type transistors. The array transistors in the array region can be N-type transistors.

[0087] In the related art, the circuit structures in the array area and the peripheral area are prepared separately using different processes. Specifically, the array transistor is an N-type transistor as an example. For example, when preparing an N-type array transistor, it is necessary to use a mask layer to block the peripheral area, and perform operations such as etching and doping on the substrate of the array area to form the structure of the array transistor. At the same time, it is also necessary to use a mask to prepare the bit lines, contact structures, and capacitor structures of the array area. When preparing peripheral transistors, it is also necessary to use a mask layer to block the array area, and perform etching and doping on the substrate of the peripheral area. In addition, the N-type peripheral transistors and P-type peripheral transistors with different conductivity types in the channel area also need to be doped separately. At the same time, it is also necessary to use a mask to prepare the contact structure and peripheral lines of the peripheral area. Therefore, in the above process, the mask layer needs to be used multiple times, and the preparation process is relatively cumbersome.

[0088] The method for preparing a semiconductor structure provided by the present disclosure provides a support foundation for the subsequent formation of the structure by setting a substrate. By forming a peripheral channel and a buried word line, a foundation is provided for the subsequent formation of an array transistor and a peripheral transistor. By synchronously forming a bit line contact structure and a portion of a peripheral gate structure, the manufacturing process of the semiconductor structure can be effectively simplified. By synchronously completing the formation of an isolation well and a doped bit line contact structure on a doped substrate, not only can the manufacturing process of the semiconductor structure be effectively simplified, but the electrical performance of the bit line contact structure can also be improved. Therefore, the present disclosure can effectively simplify the manufacturing process of the semiconductor structure and improve the electrical performance of the semiconductor structure.

[0089] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present disclosure. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present disclosure, and should not be understood as limitations on the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure. The embodiments of the present disclosure are described in detail below in conjunction with the drawings.

[0090] The present disclosure provides a method for preparing a semiconductor structure. The semiconductor structure may be a memory, which may include DRAM, static random access memory (SRAM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change random access memory (PRAM), or magnetoresistive random access memory (MRAM). The present disclosure does not limit the specific type of memory. The following description takes the semiconductor structure being DRAM as an example.

[0091] Reference Figure 1 As shown, the method for preparing a semiconductor structure provided by an embodiment of the present disclosure includes:

[0092] S100: providing a substrate, wherein the substrate has an array active region and a peripheral active region that are spaced apart.

[0093] Reference Figure 2 As shown, providing a substrate 100 includes: S101: providing an initial substrate, the initial substrate including an array region and a peripheral region; S102: performing doping treatment on the initial substrate to form an array active region in the substrate in the array region and a peripheral active region in the substrate in the peripheral region.

[0094] Combine Figure 10 、 Figure 22 、 Figure 23 and Figure 32As shown, the initial substrate provided by the embodiment of the present disclosure can be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound or silicon on insulator (SOI), etc., or other materials known to those skilled in the art. The initial substrate can provide a structural basis for supporting the array transistor 200, peripheral transistor 300, capacitor structure 800, bit line 500 and peripheral line 900 that are subsequently arranged. The initial substrate can be formed by deposition. For example, it can be a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD) or an atomic layer deposition process (ALD).

[0095] Reference Figure 9 and Figure 11 As shown, the array active area 100a and the peripheral active area 100b of the substrate 100 can be formed by doping the initial substrate. By controlling the doped ions, the ion doping type of the array active area 100a and the peripheral active area 100b can be adjusted. In this embodiment, the ions doped in the array active area 100a and the peripheral active area 100b can be group III elements (B or Ga), and the formation of P-type array active area 100a and peripheral active area 100b is described as an example. In other embodiments, the ions doped in the array active area 100a and the peripheral active area 100b can be group V elements (As or P), thereby forming N-type array active area 100a and peripheral active area 100b.

[0096] The initial substrate may include an array area 101a and a peripheral area 101b. The peripheral area 101b is disposed outside the array area 101a. The peripheral active area 100b formed by doping the initial substrate may be provided with a sense amplifier circuit (SA) and a sub-word line driver circuit (SWD). Figure 9 As shown in FIG. 1 , a plurality of circuits are provided in the peripheral active region 100 b, which may include a peripheral transistor 300. An array transistor 200 and a memory cell are provided in the array active region 100 a formed by doping an initial substrate.

[0097] In this embodiment, combined with Figure 22 、 Figure 23 and Figure 32As shown, the array active area 100a includes a storage structure and an array transistor 200. The embodiment of the present disclosure is described using the storage structure being a capacitor structure 800 as an example. The gate of the array transistor 200 is connected to a word line (WL), the source is connected to a bit line 500 (BL), and the drain is connected to the capacitor structure 800. The word line is connected to a sub-word line driver circuit, which controls the writing of signals on the word line. The bit line 500 is connected to a sense amplifier circuit, which controls the writing or reading of signals on the bit line 500. The voltage signal on the word line can control the turning on or off of the array transistor 200, reading data information stored in the capacitor structure 800 through the bit line 500, or writing data information into the capacitor structure 800 through the bit line 500 for storage. In the embodiment of the present disclosure, the gate of the array transistor 200 is a buried word line 204.

[0098] After the substrate 100 is formed, the following steps are included: S200 : forming a peripheral channel, where the peripheral channel is located in the peripheral active region.

[0099] Reference Figure 3 As shown, forming the peripheral channel 301 includes:

[0100] S201: forming a second mask layer, the second mask layer covers the substrate, and the second mask opening of the second mask layer exposes a portion of the peripheral active area. Figure 11 As shown, the second mask layer M2 can be formed by deposition, and the material of the second mask layer M2 can be silicon nitride or silicon oxynitride. The second mask opening M2a exposes a portion of the top surface of the substrate 100 of the peripheral active area 100b.

[0101] S202: doping the peripheral active region along the second mask opening to form a peripheral channel. The ion doping type of the peripheral channel 301 can be N-type or P-type. The ion doping type of the peripheral channel 301 can be the same as or different from the ion doping type of the array channel 201.

[0102] In an optional embodiment, the manufacturing method further includes: forming the array channel 201, and the formation of the array channel 201 is completed simultaneously with the formation of the peripheral channel 301. At this time, the ion doping type of the array channel 201 and the peripheral channel 301 is the same.

[0103] In this embodiment, forming the array channel 201 includes: S203: the second mask opening further exposes a portion of the array active region, and doping the array active region along the second mask opening to form the array channel.

[0104] Reference Figure 12As shown, in this embodiment, the second mask opening M2a exposes a portion of the top surface of the substrate 100 in the array active area 100a. For example, the ion doping type of both the array channel 201 and the peripheral channel 301 is P-type. The subsequently formed array transistor 200 and peripheral transistor 300 are both N-type transistors. Thus, by simultaneously doping the array channel 201 and the peripheral channel 301, the number of masks used in their formation can be effectively reduced, thereby simplifying the manufacturing process of the semiconductor structure.

[0105] After forming the array channel 201 and the peripheral channel 301, the second mask layer M2 is removed. The structure can be referred to Figure 13 As shown, the array channels 201 and the peripheral channels 301 are formed and spaced apart in the substrate 100 .

[0106] In another optional embodiment, the fabrication method further includes forming an array channel 201, wherein the formation of the array channel 201 is completed after forming the peripheral channel 301 and before forming the buried word line 204. In this case, the array channel 201 and the peripheral channel 301 have different ion doping types. The ion doping type of the array channel 201 is P-type, and the ion doping type of the peripheral channel 301 can be N-type. The array transistor 200 formed subsequently is an N-type transistor, and the peripheral transistor 300 is a P-type transistor.

[0107] After forming the array channel 201 and the peripheral channel 301 , the method further includes: S300 : forming a buried word line, where the buried word line is located in the array active area and corresponds to the array channel in the array active area.

[0108] In an alternative embodiment, the buried word line 204 includes an array gate dielectric layer 204 a , an array gate semiconductor layer 204 b , an array gate metal layer 204 c , and an array gate protection layer 204 d . In the present disclosure, the buried word line 204 may serve as a gate of the array transistor 200 .

[0109] Reference Figure 4 As shown, forming the buried word line 204 includes: S301: forming a first trench in the array channel. Figure 14 As shown, the first trench 201 a can be formed by mask etching, and the depth of the first trench 201 a can be smaller than the depth of the array channel 201 .

[0110] S302: forming an array gate dielectric layer in the first trench, wherein the array gate dielectric layer covers a portion of the inner wall of the trench, the top surface of the array gate dielectric layer is lower than the top surface of the substrate, and the array gate dielectric layer has a second trench. Figure 15As shown, the material of the array gate dielectric layer 204a can be selected from silicon oxide, hafnium oxide, doped hafnium oxide, zirconium oxide, aluminum oxide, and lanthanum oxide. The array gate dielectric layer 204a can be formed by deposition and covers the bottom and sidewalls of the first trench 201a. A distance is provided between the top surface of the array gate dielectric layer 204a located on the sidewalls and the top surface of the substrate 100. A second trench 201b is formed in the array gate dielectric layer 204a.

[0111] S303: forming an array gate semiconductor layer and an array gate metal layer in sequence in the second trench, wherein the top surface of the array gate metal layer is flush with the top surface of the array gate dielectric layer. Figure 16 As shown, the array gate semiconductor layer 204b and the array gate metal layer 204c can be formed in the second trench 201b by deposition. The material of the array gate semiconductor layer 204b can be polysilicon, and the material of the array gate metal layer 204c can be tungsten.

[0112] S304: forming an array gate protection layer in the first trench, the array gate protection layer covering the top surfaces of the array gate dielectric layer and the array gate metal layer, and the top surface of the array gate protection layer is flush with the top surface of the substrate. Figure 17 As shown, the array gate protection layer 204d can be formed in the first trench 201a by deposition. The material of the array gate protection layer 204d can be silicon nitride, which can protect the working stability of the array gate semiconductor layer 204b and the array gate metal layer 204c in the buried word line 204.

[0113] In the present disclosure, by disposing the buried word line 204 of the array transistor 200 in the substrate 100 , it is possible to avoid occupying the top space of the substrate 100 , thereby helping to improve the integration of the semiconductor structure.

[0114] Reference Figure 18 As shown, after the buried word line 204 is formed, the following further steps are performed: forming an array source region 202 and an array drain region 203 by mask doping. The array source region 202 and the array drain region 203 are respectively located on both sides of the array channel 201. When the array transistor 200 is an N-type transistor, the ion doping type of the array source region 202 and the array drain region 203 are both N-type. The array channel 201, the array source region 202, the array drain region 203, and the buried word line 204 together constitute the array transistor 200. In some embodiments, in addition to the above-mentioned structure, the array transistor 200 may also include other structures such as an array well region. The specific structure of the array transistor 200 disclosed in the present disclosure is not limited to the above-mentioned example.

[0115] In this disclosure, reference is made to Figure 1As shown, after the buried word line 204 is formed, the process further includes: S400: forming a bit line contact structure and a peripheral gate structure, both of which are located on the substrate, the peripheral gate structure corresponds to the peripheral channel, and the bit line contact structure corresponds to and is connected to the array active area.

[0116] Combine Figure 22 As shown, the peripheral gate structure includes a peripheral gate dielectric layer 304a, a peripheral gate semiconductor layer 304b, a peripheral gate metal layer 304c and a peripheral gate protection layer 304d; the bit line contact structure 205 includes a contact semiconductor layer 205a and a contact metal layer 205b.

[0117] Based on the specific structure of the above peripheral gate structure 304, refer to Figure 5 As shown, forming the peripheral gate structure 304 and the bit line contact structure 205 includes: S401: forming a peripheral gate dielectric layer, the peripheral gate dielectric layer is located on the substrate and corresponds to the peripheral channel.

[0118] Optional, combined Figure 19 As shown, forming the peripheral gate dielectric layer 304a includes forming an initial gate dielectric layer L1, which covers the substrate 100 located in the peripheral active area 100b. The initial gate dielectric layer L1 can be formed by deposition, and its material can be selected from silicon oxide, hafnium oxide, doped hafnium oxide, zirconium oxide, aluminum oxide, and lanthanum oxide.

[0119] Optional, continue to refer to Figure 5 As shown, after forming the initial gate dielectric layer L1, it also includes: S402: forming a peripheral gate semiconductor layer and a contact semiconductor layer, the peripheral gate semiconductor layer is located on the peripheral gate dielectric layer, the contact semiconductor layer is located on the substrate, and corresponds to and is connected to the array active area.

[0120] S403: forming a peripheral gate metal layer and a contact metal layer, wherein the peripheral gate metal layer is located on the peripheral gate semiconductor layer, and the contact metal layer is located on the contact semiconductor layer.

[0121] S404: forming a peripheral gate protection layer, where the peripheral gate protection layer is located on the peripheral gate metal layer.

[0122] Among them, combined Figure 20 As shown, forming the peripheral gate semiconductor layer 304b and the contact semiconductor layer 205a includes forming an initial semiconductor layer L2, where the initial semiconductor layer L2 covers the substrate 100 located in the array active area 100a and the initial gate dielectric layer L1.

[0123] Among them, combined Figure 20As shown, forming the peripheral gate metal layer 304c and the contact metal layer 205b includes forming an initial metal layer L3, where the initial metal layer L3 covers the initial semiconductor layer L2. The initial semiconductor layer L2 and the initial metal layer L3 can be formed by deposition. The material of the initial semiconductor layer L2 can be polysilicon, and the material of the initial metal layer L3 can be tungsten.

[0124] Among them, combined Figure 21 As shown, forming the peripheral gate protection layer 304d includes: forming an initial protection layer L4, the initial protection layer L4 covering the initial metal layer L3 corresponding to the peripheral active area 100b. The initial protection layer L4 can be formed by deposition, and its material can be silicon nitride. The initial protection layer L4 can protect the initial metal layer L3, the initial semiconductor layer L2 and the initial gate dielectric layer L1 at the bottom thereof. Figure 22 As shown, the initial gate dielectric layer L1 , the initial semiconductor layer L2 , the initial metal layer L3 and the initial protection layer L4 can form a peripheral gate structure 304 after processing. Therefore, the initial protection layer L4 is conducive to ensuring the structural stability of the peripheral gate structure 304 formed subsequently.

[0125] Optional, see Figure 22 As shown, after the initial protection layer L4 is formed, the process further includes: removing a portion of the initial gate dielectric layer L1 , a portion of the initial semiconductor layer L2 , a portion of the initial metal layer L3 and a portion of the initial protection layer L4 .

[0126] The removal method may be masked etching, retaining the initial semiconductor layer L2 and initial metal layer L3 corresponding to the array active area 100a to form the contact semiconductor layer 205a and contact metal layer 205b of the bitline contact structure 205. The initial gate dielectric layer L1, initial semiconductor layer L2, initial metal layer L3, and initial protective layer L4 corresponding to the peripheral channel 301 are retained to form the peripheral gate dielectric layer 304a, peripheral gate semiconductor layer 304b, peripheral gate metal layer 304c, and peripheral gate protective layer 304d of the peripheral gate structure 304. The peripheral gate dielectric layer 304a may be made of the same material as the array gate dielectric layer 204a.

[0127] The contact semiconductor layer 205a of the bit line contact structure 205 abuts and conducts with the array source region 202 to achieve signal transmission. In other embodiments, the contact semiconductor layer 205a may also abut and conduct with the array drain region 203, which is not limited in this disclosure.

[0128] In the present disclosure, by preparing the bit line contact structure 205 and part of the peripheral gate structure 304 at the same time, compared with preparing the two separately, the manufacturing process of the semiconductor structure can be effectively reduced and the process complexity can be reduced.

[0129] It should be pointed out that, referring to Figure 23 As shown, after forming the peripheral gate structure 304, a peripheral source region 302 and a peripheral drain region 303 can be formed by mask doping. The peripheral source region 302 and the peripheral drain region 303 are located on both sides of the peripheral channel 301. The peripheral transistor 300 can be an N-type transistor, and the ion doping type of the peripheral source region 302 and the peripheral drain region 303 are both N-type. Alternatively, when the peripheral transistor 300 can be a P-type transistor, the ion doping type of the peripheral source region 302 and the peripheral drain region 303 are both P-type.

[0130] Reference Figure 24 As shown, after the peripheral gate structure 304 is formed, it also includes: forming a side wall 305, and the side wall 305 covers the side of the peripheral gate structure 304. The side wall 305 can be made of an insulating material, and the material of the side wall 305 can include silicon oxide, silicon nitride or silicon oxynitride. In some embodiments, along the direction away from the side of the peripheral gate structure 304, the side wall 305 can include an oxide layer, a nitride layer and an oxide layer stacked in sequence (i.e., an ONO structure), or a nitride layer, an oxide layer and a nitride layer stacked in sequence (i.e., a NON structure). In other embodiments, the side wall 305 can have an air gap structure (gap) inside. The above-mentioned side walls 305 all have good isolation effects, can protect the peripheral gate structure 304, and improve the structural and electrical stability of the peripheral gate structure 304. In the present application Figure 23 and Figure 24 In the illustrated structure, the spacers 305 are formed after the peripheral source region 302 and the peripheral drain region 303. In other embodiments, the spacers 305 may also be formed before the peripheral source region 302 and the peripheral drain region 303. This application does not limit the order in which the spacers 305, the peripheral source region 302, and the peripheral drain region 303 are formed.

[0131] Combine Figure 1 As shown, after the peripheral gate structure 304 and the bit line contact structure 205 are formed, the process further includes: S500: doping a portion of the substrate and the bit line contact structure to form isolation wells in the array active region and the peripheral active region.

[0132] Optional, see Figure 6 As shown, the doping process of the substrate 100 and the bit line contact structure 205 includes:

[0133] S501: forming a first mask layer, the first mask layer covering the substrate and the bit line contact structure, the first mask opening of the first mask layer exposing a portion of the array active area and a portion of the peripheral active area, as well as exposing the bit line contact structure. Figure 25As shown, the first mask layer M1 can be formed by deposition. The material of the first mask layer M1 can be silicon nitride or silicon oxynitride. The first mask layer M1 can cover the substrate 100 and the bit line contact structure 205. The top surface of the first mask layer M1 is higher than the top surfaces of the bit line contact structure 205 and the peripheral gate structure 304.

[0134] S502: doping the exposed substrate and bit line contact structure along the first mask opening to form isolation wells in the array active area and the peripheral active area. Figure 26 As shown, the first mask opening M1a can expose the array transistor 200, the peripheral transistor 300, the bit line contact structure 205, and a portion of the top surface of the substrate 100 near the array transistor 200 and the peripheral transistor 300. By adjusting the angle of ion doping along the first mask opening M1a, a portion of the substrate 100 near the array transistor 200 and the peripheral transistor 300, as well as the contact semiconductor layer 205a of the bit line contact structure 205, can be doped, thereby forming an isolation well 400 in the substrate 100.

[0135] The isolation well 400 and the contact semiconductor layer 205a have the same ion doping type, and both can be N-type. After the contact semiconductor layer 205a of the bit line contact structure 205 is doped with N-type ions, the contact resistance between the bit line contact structure 205 and the N-type array source region 202 can be effectively reduced, thereby improving the electron transmission efficiency between the bit line contact structure 205 and the subsequently formed bit line 500, thereby helping to improve the electrical performance of the semiconductor structure.

[0136] It should be noted that the drawings of this embodiment show that the isolation well 400 surrounds the array source region 202, the array channel 201, and the array drain region 203, as well as the peripheral source region 302, the peripheral channel 301, and the peripheral drain region 303. This prevents electrical interference between the array transistor 200 and the peripheral transistor 300. The depth of the isolation well 400 can be greater than the depth of the array channel 201 and the peripheral channel 301, and can also be greater than the depth of the array source region 202, the array drain region 203, the peripheral drain region 303, and the peripheral source region 302, to improve isolation.

[0137] After the doping of the substrate 100 and the bit line contact structure 205 is completed, the first mask layer M1 can be removed to form Figure 27 structure.

[0138] Continue to refer to Figure 1 As shown, in the present disclosure, after the doping treatment of the substrate 100 and the bit line contact structure 205, the method further includes: S600: forming a bit line, the bit line being connected to the bit line contact structure. Figure 27As shown, the bit line 500 can be formed on the bit line contact structure 205 by deposition. The material of the bit line 500 can be titanium nitride, tungsten, rubidium or copper.

[0139] In some embodiments, a concave and / or convex structure (not shown) may be provided on the top of the bitline contact structure 205. After the bitline 500 is deposited, a convex and / or concave structure may be formed that corresponds in position and shape to the concave and / or convex structure of the bitline contact structure 205, so that the contact surfaces of the bitline 500 and the bitline contact structure 205 are interlocked and connected through the concave and convex shapes. This can increase the contact area between the two, reduce contact resistance, and improve the electrical signal transmission capability between the two, thereby helping to enhance the electrical performance of the semiconductor structure.

[0140] Optional, continue to refer to Figure 1 As shown, after the bit line 500 is formed, the process further includes: S700: forming an array contact structure and a peripheral contact structure, wherein the array contact structure is connected to the array active region, and the peripheral contact structure is connected to the peripheral active region and the peripheral gate structure.

[0141] Reference Figure 7 As shown, an array contact structure 600 and a peripheral contact structure 700 are formed, including:

[0142] S701: forming a dielectric layer, the dielectric layer covers the substrate, the bit line contact structure, the bit line and the peripheral gate structure. Figure 28 As shown, the dielectric layer DL may be formed by deposition, and the material of the dielectric layer DL may be silicon oxide or silicon oxynitride.

[0143] S702: forming a channel in the dielectric layer, wherein the channel exposes the array active area and the peripheral active area. Figure 29 As shown, the channel DLa can be formed by mask etching, and the depth of the channel DLa needs to ensure that the substrate 100 is exposed. The channel DLa corresponds to the array drain region 203 of the array active region 100a, and corresponds to the peripheral source region 302 and the peripheral drain region 303 of the peripheral active region 100b.

[0144] S703: forming an initial conductive layer in the channel, forming an array contact structure with the initial conductive layer connected to the array active area, and forming a peripheral contact structure with the initial conductive layer connected to the peripheral active area and the peripheral gate structure. Figure 30 As shown, the initial conductive layer L5 is formed by deposition, and the initial conductive layer L5 corresponding to the position of the trench DLa is filled in the trench DLa. The material of the initial conductive layer L5 can be titanium nitride, tungsten or copper. Figure 31As shown, a portion of the initial conductive layer L5 is removed along the surface of the dielectric layer DL by a chemical mechanical polishing process (CMP), and the initial conductive layer L5 remains in the channel DLa. The initial conductive layer L5 in the channel DLa correspondingly connected to the array drain region 203 forms an array contact structure 600, and the initial conductive layer L5 in the channel DLa correspondingly connected to the peripheral source region 302 and the peripheral drain region 303 forms a peripheral contact structure 700. It should be noted that Figure 31 The peripheral contact structure 700 connected to the peripheral gate structure 304 is not shown in the cross-sectional view of FIG.

[0145] Continue to refer to Figure 1 As shown, after the array contact structure 600 and the peripheral contact structure 700 are formed, the following further includes: S800: forming a capacitor structure and a peripheral circuit, wherein the capacitor structure is connected to the array contact structure, and the peripheral circuit is connected to the peripheral contact structure.

[0146] Combine Figure 32 As shown, the capacitor structure 800 includes a first capacitor conductive layer 801, a capacitor dielectric layer DL and a second capacitor conductive layer 803. Figure 8 As shown, a capacitor structure 800 and a peripheral circuit 900 are formed, including:

[0147] S801: forming a first capacitor conductive layer, where the first capacitor conductive layer is located on the dielectric layer and corresponds to and is connected to the array contact structure.

[0148] S802: forming a capacitor dielectric layer, where the capacitor dielectric layer is located on the first capacitor conductive layer.

[0149] S803: forming a second capacitor conductive layer and a peripheral circuit, wherein the second capacitor conductive layer is located on the capacitor dielectric layer, and the peripheral circuit is located on the dielectric layer and corresponds to and is connected to the peripheral contact structure.

[0150] It should be noted that the first capacitor conductive layer 801, the second capacitor conductive layer 803, and the peripheral circuit 900 can be made of the same material. By forming the first capacitor conductive layer 801 and the peripheral circuit 900 simultaneously, the semiconductor structure manufacturing process can be effectively simplified. In other embodiments, the peripheral circuit 900 can also be formed simultaneously with the second capacitor conductive layer 803, and this disclosure is not limited to this.

[0151] The first capacitor conductive layer 801 corresponds to and is connected to the array contact structure 600, enabling the transmission of electrical signals from the array drain region 203 of the array transistor 200 to the capacitor structure 800, or reading electrical signals stored in the capacitor structure 800. The peripheral circuit 900 corresponds to and is connected to the peripheral contact structure 700, enabling the transmission of electrical signals between the peripheral source region 302 and the peripheral drain region 303 of the peripheral transistor 300 and the peripheral circuit 900. Specifically, the peripheral circuit 900 connected to the peripheral source region 302 and the peripheral circuit 900 connected to the peripheral drain region 303 are different circuits, thereby enabling the transmission of electrical signals from the peripheral transistor 300.

[0152] In the description of the embodiments of the present disclosure, it should be understood that, unless otherwise expressly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or it can be an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances. The orientations or positional relationships indicated by the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present disclosure. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise precisely and specifically specified.

[0153] The terms "first," "second," "third," "fourth," and the like (if any) in the specification and claims of the present disclosure and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present disclosure described herein, for example, can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0154] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate having an array active region and a peripheral active region that are spaced apart; forming a peripheral channel, wherein the peripheral channel is located in the peripheral active region; forming a buried word line, wherein the buried word line is located in the array active area and corresponds to the array channel in the array active area; forming a bit line contact structure and a peripheral gate structure, wherein both the peripheral gate structure and the bit line contact structure are located on the substrate, the peripheral gate structure corresponds to the peripheral channel, and the bit line contact structure corresponds to and is connected to the array active area; Doping a portion of the substrate and the bit line contact structure to form isolation wells in the array active area and the peripheral active area; Wherein, the doping treatment of the substrate and the bit line contact structure includes: forming a first mask layer, wherein the first mask layer covers the substrate and the bit line contact structure, and a first mask opening of the first mask layer exposes a portion of the array active area and a portion of the peripheral active area, as well as the bit line contact structure; The substrate and the bit line contact structure exposed by doping are performed along the first mask opening to form the isolation well in the array active area and the peripheral active area.

2. The method for preparing a semiconductor structure according to claim 1, wherein: Also includes: The array channel is formed, and the formation of the array channel and the formation of the peripheral channel are completed simultaneously.

3. The method for preparing a semiconductor structure according to claim 1, wherein: Also includes: The array channel is formed, and the formation of the array channel is completed after the formation of the peripheral channel and before the formation of the buried word line.

4. The method for preparing a semiconductor structure according to claim 2 or 3, wherein: The peripheral gate structure includes a peripheral gate dielectric layer, a peripheral gate semiconductor layer, a peripheral gate metal layer and a peripheral gate protection layer; The bit line contact structure includes a contact semiconductor layer and a contact metal layer; Forming the peripheral gate structure and the bit line contact structure includes: forming the peripheral gate dielectric layer, wherein the peripheral gate dielectric layer is located on the substrate and corresponds to the peripheral channel; forming the peripheral gate semiconductor layer and the contact semiconductor layer, wherein the peripheral gate semiconductor layer is located on the peripheral gate dielectric layer, and the contact semiconductor layer is located on the substrate and corresponds to and is connected to the array active area; forming the peripheral gate metal layer and the contact metal layer, wherein the peripheral gate metal layer is located on the peripheral gate semiconductor layer, and the contact metal layer is located on the contact semiconductor layer; The peripheral gate protection layer is formed, and the peripheral gate protection layer is located on the peripheral gate metal layer.

5. The method for preparing a semiconductor structure according to claim 2, wherein: Forming the peripheral trench includes: forming a second mask layer, wherein the second mask layer covers the substrate, and a second mask opening of the second mask layer exposes a portion of the peripheral active area; The peripheral active region is doped along the second mask opening to form the peripheral channel.

6. The method for preparing a semiconductor structure according to claim 5, wherein: Forming the array channel includes: The second mask opening also exposes a portion of the array active area, and the array active area is doped along the second mask opening to form the array channel.

7. The method for preparing a semiconductor structure according to claim 4, wherein: Forming the peripheral gate dielectric layer includes: forming an initial gate dielectric layer, wherein the initial gate dielectric layer covers the substrate located in the peripheral active area; Forming the peripheral gate semiconductor layer and the contact semiconductor layer includes: forming an initial semiconductor layer, wherein the initial semiconductor layer covers the substrate and the initial gate dielectric layer located in the array active area; Forming the peripheral gate metal layer and the contact metal layer includes: forming an initial metal layer, wherein the initial metal layer covers the initial semiconductor layer; The peripheral gate protection layer is formed, comprising: forming an initial protection layer, wherein the initial protection layer covers the initial metal layer corresponding to the peripheral active area.

8. The method for preparing a semiconductor structure according to claim 7, wherein: After forming the initial protective layer, the method further includes: removing a portion of the initial gate dielectric layer, a portion of the initial semiconductor layer, a portion of the initial metal layer, and a portion of the initial protective layer; The initial semiconductor layer and the initial metal layer corresponding to the array active area are retained to form the contact semiconductor layer and the contact metal layer of the bit line contact structure respectively; the initial gate dielectric layer, the initial semiconductor layer, the initial metal layer and the initial protective layer corresponding to the peripheral channel are retained to form the peripheral gate dielectric layer, the peripheral gate semiconductor layer, the peripheral gate metal layer and the peripheral gate protective layer of the peripheral gate structure respectively.

9. The method for preparing a semiconductor structure according to claim 2 or 3, characterized in that: The buried word line includes an array gate dielectric layer, an array gate semiconductor layer, an array gate metal layer and an array gate protection layer; Forming the buried word line includes: forming a first trench in the array channel; forming an array gate dielectric layer in the first trench, wherein the array gate dielectric layer covers a portion of an inner wall of the trench, a top surface of the array gate dielectric layer is lower than a top surface of the substrate, and a second trench is formed in the array gate dielectric layer; forming the array gate semiconductor layer and the array gate metal layer in sequence in the second trench, wherein the top surface of the array gate metal layer is flush with the top surface of the array gate dielectric layer; The array gate protection layer is formed in the first trench, the array gate protection layer covers the top surfaces of the array gate dielectric layer and the array gate metal layer, and the top surface of the array gate protection layer is flush with the top surface of the substrate.

10. The method for preparing a semiconductor structure according to claim 2 or 3, characterized in that: Providing the substrate, including: Providing an initial substrate, wherein the initial substrate includes an array region and a peripheral region; The initial substrate is doped to form the array active region in the substrate in the array region and the peripheral active region in the substrate in the peripheral region.

11. The method for preparing a semiconductor structure according to claim 2 or 3, characterized in that: After the substrate and the bit line contact structure are partially doped, the method further includes: forming a bit line, wherein the bit line is connected to the bit line contact structure.

12. The method for preparing a semiconductor structure according to claim 11, wherein: After forming the bit line, the method further includes: forming an array contact structure and a peripheral contact structure, wherein the array contact structure is connected to the array active area, and the peripheral contact structure is connected to the peripheral active area and the peripheral gate structure; A capacitor structure and a peripheral circuit are formed, wherein the capacitor structure is connected to the array contact structure, and the peripheral circuit is connected to the peripheral contact structure.

13. The method for preparing a semiconductor structure according to claim 12, wherein: Forming the array contact structure and the peripheral contact structure includes: forming a dielectric layer, wherein the dielectric layer covers the substrate, the bit line contact structure, the bit line, and the peripheral gate structure; forming a channel in the dielectric layer, wherein the channel exposes the array active area and the peripheral active area; An initial conductive layer is formed in the channel. The initial conductive layer connected to the array active area forms the array contact structure. The initial conductive layer connected to the peripheral active area and the peripheral gate structure forms the peripheral contact structure.

14. The method for preparing a semiconductor structure according to claim 13, wherein: The capacitor structure includes a first capacitor conductive layer, a capacitor dielectric layer and a second capacitor conductive layer; Forming the capacitor structure and the peripheral circuit includes: forming a first capacitor conductive layer and the peripheral circuit, wherein the first capacitor conductive layer is located on the dielectric layer and corresponds to and is connected to the array contact structure, and the peripheral circuit is located on the dielectric layer and corresponds to and is connected to the peripheral contact structure; forming a capacitor dielectric layer, wherein the capacitor dielectric layer is located on the first capacitor conductive layer; A second capacitor conductive layer is formed, where the second capacitor conductive layer is located on the capacitor dielectric layer.

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