Three-dimensional floating body storage device

Abstract

A three-dimensional floating body memory is provided. Integrated circuit (IC) devices implementing three-dimensional (3D) floating body memories are disclosed. An example IC device includes: a floating body memory cell including a transistor having a first source or drain (S / D) region, a second S / D region, and a gate over a channel portion between the first and second S / D regions; a BL coupled to the first S / D region and parallel to a first axis of the Cartesian coordinate system; an SL coupled to the second S / D region and parallel to a second axis of the coordinate system; and a WL coupled to or part of the gate and parallel to the third axis of the coordinate system. IC devices implementing 3D floating body memories as described herein can be used to address extension challenges of conventional memory technologies and enable implementation of high density embedded memories compatible with advanced CMOS processes.

Description

Background Art

[0001] Embedded memory is very important to the performance of modern system-on-chip (SoC) technology. Low-power and high-density embedded memory is used in many different computer products, and further improvements are always expected. Floating body memory, such as floating body dynamic random access memory (FBDRAM), is a popular choice for various types of computer systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments will be easily understood through the following detailed description in conjunction with the accompanying drawings.

[0003] Figure 1 A perspective view of an example integrated circuit (IC) device implementing a nanoribbon-based field effect transistor (FET) according to some embodiments of the present disclosure is provided.

[0004] Figure 2-3 are circuit diagrams of two example arrays of floating body memory cells according to some embodiments of the present disclosure.

[0005] Figure 4 According to some embodiments of the present disclosure Figure 2 A circuit diagram of a cross-sectional side view of an example IC device implementing a three-dimensional (3D) floating body memory.

[0006] Figure 5-8 According to some embodiments of the present disclosure Figure 3 A circuit diagram of a cross-sectional side view of an example IC device implementing a 3D floating body memory.

[0007] Fig. 9 A top view of a wafer and die is provided that may include one or more IC devices implementing a 3D floating body memory according to any of the embodiments disclosed herein.

[0008] Fig.10 is a cross-sectional side view of an IC package that may include one or more IC devices implementing a 3D floating body memory according to any of the embodiments disclosed herein.

[0009] Fig.11 is a cross-sectional side view of an IC device assembly that may include one or more IC devices implementing a 3D floating body memory according to any of the embodiments disclosed herein.

[0010] Fig.12 is a block diagram of an example computing device that may include 3D floating body memory according to any of the embodiments disclosed herein.

[0011] Fig.13is a block diagram of an example processing device that may include a 3D floating body memory according to any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0012] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the following description and drawings.

[0013] For the purpose of illustrating an IC device implementing a 3D floating body memory as described herein, it may be useful to first understand the phenomena that may be at work in certain IC arrangements. The following basic information may be considered as a basis on which the present disclosure may be properly explained. This information is provided for the purpose of explanation only and, therefore, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.

[0014] Some memory devices may be considered "stand-alone" devices because they are included in a chip that also does not include computing logic (wherein, as used herein, the term "computing logic device," or simply "computing logic" or "logic device," refers to an IC component, such as a transistor, that is used to perform computing / processing operations). Other memory devices may be included in a chip along with computing logic, and may be referred to as "embedded" memory devices. Using embedded memory to support computing logic may improve performance by bringing the memory and computing logic closer together and eliminating interfaces that increase latency. Various embodiments of the present disclosure relate to embedded memory arrays, and corresponding methods and devices.

[0015] In the past, access transistors have been used to implement memories, where each memory cell includes a capacitor for storing the memory state of the cell (e.g., a logical "1" or "0") and an access transistor that controls access to the cell (e.g., access to write information to the cell or access to read information from the cell). Such a memory cell may be referred to as a "1T-1C memory cell," highlighting the fact that it uses one access transistor (i.e., the "1T" in the term "1T-1C memory cell") and one capacitor (i.e., the "1C" in the term "1T-1C memory cell"). One capacitor electrode of the capacitor of the 1T-1C memory cell may be coupled to a source or drain (S / D) terminal / region of the access transistor (e.g., coupled to the source terminal / region of the access transistor), while the other S / D terminal / region of the access transistor (e.g., the drain terminal / region) may be coupled to a bit line, the gate terminal of the access transistor may be coupled to a word line, and the other capacitor electrode of the capacitor may be coupled to a plate line. Because this memory cell can be fabricated with as few as a single access transistor, it can offer higher density and lower standby power than some other types of memory in the same process technology.

[0016] Floating body memory is even simpler than 1T-1C memory because it uses only a single transistor as a memory cell. In floating body memory, a memory cell (also referred to as a "floating body memory cell") can store data using the floating body of a single transistor, which eliminates the need to use a capacitor to store charge representing the memory state compared to 1T-1C memory. In a floating body memory cell, a first S / D terminal is coupled to a bit line (BL), a second S / D terminal is coupled to a select line (SL), and a gate terminal of the transistor is coupled to a word line (WL). In this context, as used herein, the term "coupled" may mean a direct electrical connection (as opposed to, for example, capacitive coupling), possibly via an intermediate conductive structure (e.g., a conductive via) having a portion that is electrically and physically in contact with a terminal of the transistor and another portion that is electrically and physically in contact with WL, BL, or SL. As used herein, A and B may be described as being in physical contact if one or more interface layers that may be formed when A and B are in physical contact are considered to be part of A and / or part of B. One of the first and second S / D terminals / regions of the transistor of the floating body memory cell may be a source terminal / region, and the other may be a drain terminal / region. Because the names of "source" and "drain" in transistors may be interchangeable, which control line is BL and which control line is SL may also be interchangeable. Thus, in general, BL, SL, and WL may be referred to as the first, second, and third control lines, respectively, for controlling the floating body memory cell.

[0017] In some deployment scenarios, floating body memory cells may have advantages over conventional memory cells given their simple structure and high scalability. One challenge is that, given the available surface area of ​​a supporting structure such as a substrate, die, wafer, or chip, only so many floating body memory cells can be formed in that area, which limits the density of floating body memory arrays. In conventional solutions, attempts to increase memory density include reducing the critical dimensions of various components of the memory cell (e.g., reducing transistor size), which requires ever-increasing process complexity and cost, resulting in diminishing returns and an expected slow rate of memory expansion at future nodes.

[0018] Embodiments of the present disclosure can improve at least some of the above challenges and problems by increasing the number of active memory layers to generate vertically stacked floating memory designs using fewer masks and at a lower cost. Specifically, embodiments of the present disclosure are based on the use of semiconductor material structures or vertical transistors stacked on top of each other above a support structure to achieve high-density 3D floating memory. In the context of the present disclosure, the term "above" may refer to a support structure away from an IC device, while the term "below" refers to a support structure closer to the IC device. Two 3D floating memory designs are presented herein. The first design is based on the use of vertical transistors (i.e., based on the use of transistors in which the channel region extends in a direction substantially perpendicular to the support structure) to achieve a 3D floating memory, wherein, for a given floating memory cell, different ones of WL, BL, and SL are parallel to different axes of a Cartesian coordinate system. An example IC device according to a first design includes a floating body memory cell, the floating body memory cell including a transistor having a first S / D region, a second S / D region, and a gate on a channel portion between the first and second S / D regions; a BL coupled (e.g., directly connected) to the first S / D region and parallel to a first axis of a Cartesian coordinate system; an SL coupled (e.g., directly connected) to the second S / D region and parallel to a second axis of the coordinate system; and a WL coupled (e.g., directly connected) to the gate or a portion of the gate and parallel to a third axis of the coordinate system. A second design is based on implementing a 3D floating body memory using horizontal transistors (i.e., based on using transistors in which the channel region extends in a plane substantially parallel to a support structure), wherein, for a given floating body memory cell, all of the WLs, BLs, and SLs are substantially parallel to the support structure, and the BLs and SLs are parallel to each other and perpendicular to the WLs (i.e., different ones of the WLs, BLs, and SLs are parallel to only two of the three different axes of the Cartesian coordinate system). An example IC device according to the second design includes a support structure; a semiconductor material in a layer substantially parallel to the support structure; first, second, third, and fourth transistors having channel regions in different portions of the semiconductor material; first, second, third, and fourth WLs, respectively coupled (e.g., directly connected) to gates of the first, second, third, and fourth transistors; a shared BL coupled (e.g., directly connected) to a first S / D region of each of the first, second, third, and fourth transistors; and a shared SL coupled (e.g., directly connected) to a second S / D region of each of the first, second, third, and fourth transistors, wherein the first, second, third, and fourth WLs are substantially parallel to each other and to the support structure, and wherein the shared BL and SL are substantially parallel to each other and to the support structure, and are substantially perpendicular to the first, second, third, and fourth WLs.

[0019] Incorporating different floating body memory cells in different layers relative to the support structure can allow the density of memory cells in a memory array having a given footprint area (the footprint area is defined as the area in the plane of the support structure or in a plane parallel to the plane of the support structure (i.e., the xy plane of the example coordinate system shown in the present figure)) to be significantly increased, or conversely, allow the footprint area of ​​a memory array having a given memory cell density to be significantly reduced. IC devices implementing 3D floating body memories as described herein can be used to address the scaling challenges of conventional memory technologies and enable the implementation of high-density embedded memories compatible with advanced complementary metal oxide semiconductor (CMOS) processes. Other technical effects will be apparent from the various embodiments described herein.

[0020] In the following detailed description, various aspects of the illustrative implementations may be described using terms that are commonly used by those skilled in the art to convey the essence of their work to other technicians in the field. For example, some descriptions may involve whether a particular S / D region of a transistor is a source region or a drain region. However, unless otherwise specified, it does not matter which region of the transistor is considered to be the source region and which region is considered to be the drain region, because it is common in the field of FETs that the names of the source and drain are generally interchangeable. Therefore, the description of some illustrative embodiments of the source region and the drain region provided herein is applicable to embodiments in which the names of the source region and the drain region can be reversed. In addition, in the context of the S / D region, the term "region" can be used interchangeably with the terms "contact" and "terminal" of the transistor.

[0021] As used herein, the term "connection" means a direct electrical or magnetic connection between connected things without any intermediate devices, and the term "coupling" means a direct electrical or magnetic connection between connected things, or an indirect connection through one or more passive or active intermediate devices. The term "circuit" means one or more passive and / or active components that are arranged to cooperate with each other to provide the desired function. If used, the terms "oxide", "carbide", "nitride", etc. refer to compounds containing oxygen, carbon, nitrogen, etc., respectively, the term "high-k dielectric" refers to a material with a dielectric constant (k) higher than silicon oxide, and the term "low-k dielectric" refers to a material with a k lower than silicon oxide. The terms "substantially", "close", "approximately", "nearby", and "approximately" generally refer to within + / -20% of a target value, such as within + / -5% or within + / -2%, based on the context of a specific value described herein or known in the art. Similarly, terms indicating the orientation of various elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements, generally refer to within + / - 5-20% of the target value based on the context of the specific value described herein or known in the art.

[0022] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with both layers, or may have one or more intervening layers. Conversely, a first layer "above" a second layer is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature, or may have one or more intervening layers.

[0023] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). When used with reference to a measurement range, the term "between" includes the endpoints of the measurement range. As used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0024] The description may use the phrases "in one embodiment" or "in an embodiment," each of which may refer to one or more of the same or different embodiments. In addition, the terms "including," "comprising," "having," and the like used with respect to the embodiments of the present disclosure are synonymous. The present disclosure may use perspective-based descriptions, such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments. The drawings are not necessarily drawn to scale. Unless otherwise specified, the use of ordinal adjectives "first," "second," and "third," etc. to describe common objects merely indicates that different instances of the same object are being referenced, and is not intended to imply that the objects so described must be in a given order in time, space, rank, or in any other manner.

[0025] In the following detailed description, reference is made to the accompanying drawings forming a part thereof, and embodiments that can be practiced are illustrated by way of illustration in the accompanying drawings. It should be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be understood as restrictive. For convenience, similar elements represented by different reference numerals after dashes in the accompanying drawings, such as the first and second S / D regions 114-1, 114-2, may be collectively referred to as "S / D regions 114" without reference numerals after dashes. In order not to confuse the accompanying drawings, if multiple instances of certain elements are shown, only some elements may be marked with reference numerals.

[0026] In the accompanying drawings, some schematic illustrations of example structures of various devices and components described herein may be shown with exact right angles and straight lines, but it should be understood that when any structure described herein is examined using, for example, scanning electron microscope (SEM) images or transmission electron microscope (TEM) images, these schematic illustrations may not reflect real-life process limitations that may cause features to appear less than "ideal". In such images of real structures, possible processing defects may also be visible, such as imperfectly straight edges of materials, tapered vias or other openings, accidental rounding of corners or thickness variations of different material layers, accidental spiral, edge or combined dislocations within a crystal region, and / or accidental dislocation defects of single atoms or clusters of atoms. There may be other defects that are not listed here but are common in the field of device manufacturing. Using, for example, an optical microscope, TEM or SEM to examine layout and mask data and reverse engineering portions of the device to reconstruct the circuit, and / or using, for example, physical failure analysis (PFA) to examine cross-sections of the device to detect the shape and position of various device elements described herein will allow the presence of an IC device that implements the 3D floating body memory described herein to be determined.

[0027] Various IC devices implementing 3D floating body memory as described herein may be implemented in or associated with one or more components associated with the IC, and / or may be implemented between various such components. In various embodiments, components associated with the IC include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with the IC may include components mounted on the IC or components connected to the IC. The IC may be analog or digital and may be used in many applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be used as part of a chipset for performing one or more related functions in a computer.

[0028] In general, a floating body memory cell can include transistors of any architecture, such as any planar or non-planar architecture. Non-planar transistors such as dual-gate transistors, tri-gate transistors, FinFETs, and nanowire / nanobelt / nanosheet transistors refer to transistors having a non-planar architecture. A non-planar architecture is any type of architecture in which a transistor channel has more than one confining surface, as compared to a planar architecture in which a transistor channel has only one confining surface. A confining surface refers to a specific orientation of a channel surface that is confined by a gate field. Non-planar transistors potentially improve performance relative to transistors having a planar architecture, such as a single-gate transistor.

[0029] Nanoribbon-based transistors may be particularly advantageous for the continued expansion of CMOS technology nodes due to the potential to form gates on all four sides of the channel material (thus, such transistors are sometimes referred to as "gate all around" transistors). As used herein, the term "nanoribbon" refers to an elongated structure of semiconductor material having a longitudinal axis parallel to a support structure (e.g., a substrate, die, chip, or wafer; also referred to herein simply as a "support") on which such structure is constructed. Typically, the length of such a structure (i.e., the dimension measured along the longitudinal axis, shown in this figure as the y-axis of an example xyz coordinate system) is greater than each of the width (i.e., the dimension measured along the x-axis of the example coordinate system shown in this figure) and the thickness / height (i.e., the dimension measured along the z-axis of the example coordinate system shown in this figure). In some arrangements, the term "nanoribbon" or "nanosheet" is used to describe an elongated semiconductor structure having a rectangular cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term "nanowire" is used to describe a similar elongated structure, but with a circular cross-section. In the present disclosure, the term "nanoribbon" is used to refer to all such nanowires, nanoribbons and nanosheets, as well as elongated semiconductor structures having a cross-section parallel to the longitudinal axis of the support structure and having any geometric shape (e.g., an elliptical cross-section or a polygonal cross-section with rounded corners). If the channel of the transistor is a portion of the nanoribbon, i.e., the portion around which the gate stack of the transistor can wrap, the transistor can be described as a "nanoribbon-based transistor". The semiconductor material in the nanoribbon portion that forms the transistor channel can be referred to as the "channel material", and the source and drain (S / D) regions of the transistor are provided on either side of the channel material.

[0030] Figure 1 A perspective view of an example IC device 100 having a nanoribbon-based transistor 110 is provided according to some embodiments of the present disclosure. Figure 1 As shown, IC device 100 includes semiconductor material formed into nanoribbons 104 extending substantially parallel to support member 102. Transistor 110 may be based on nanoribbon 104 by wrapping gate stack 106 around at least a portion of the nanoribbon referred to as the "channel portion" and by making source and drain regions (at Figure 1 1 and 10. The first S / D region 114-1 and the second S / D region 114-2 (collectively referred to as "S / D regions 114") are formed on either side of the gate stack 106. One of the S / D regions 114 is a source region, and the other is a drain region. However, because the names of source and drain are generally interchangeable, as is common in the field of FETs, they are simply referred to herein as the first S / D region 114-1 and the second S / D region 114-2.

[0031] Implementations of the present disclosure may be formed or performed on any suitable support 102, such as a substrate, a die, a wafer, or a chip. The support 102 may be, for example, a substrate, a die, a wafer, or a chip discussed below. Fig. 9 The wafer 2000 may be a die or may be included in a die, such as discussed below. Fig. 9 The single-cut tube core 2002. The support member 102 can be a semiconductor substrate composed of a semiconductor material system, including, for example, an N-type or P-type material system. In one implementation, the semiconductor substrate can be a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In other implementations, the semiconductor substrate can be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, aluminum indium arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, gallium indium nitride, aluminum indium nitride or gallium antimonide, or other combinations of III-V group materials (i.e., materials of Groups III and V of the periodic table), II-VI group (i.e., materials of Groups II and IV of the periodic table) or Group IV materials (i.e., materials of Group IV of the periodic table). In some embodiments, the substrate can be amorphous. In some embodiments, the support member 102 can be a printed circuit board (PCB) substrate, a packaging substrate, an interposer, a wafer or a tube core. Although several examples of materials from which support member 102 may be formed are described herein, any material that may be used as a basis upon which an IC structure having 3D floating body memory as described herein may be constructed falls within the spirit and scope of the present disclosure. Figure 1 Only one nanoribbon 104 is shown in FIG. 1 , but the IC device 100 may include a stack of such nanoribbons, wherein a plurality of nanoribbons 104 are stacked on top of each other, for example, as shown in FIG. Figure 5-6 , an IC device with 3D floating body memory implemented using nanoribbon-based transistors, such as transistor 110, is shown. In some embodiments, a portion of support 102 directly below the lowest nanoribbon 104 of the stack may be shaped as a sub-fin extending away from the substrate, as is known in the art of nanoribbon-based transistors.

[0032] For example, the nanoribbon 104 can take the form of a nanowire or a nanoribbon. In some embodiments, the cross-sectional area of ​​the nanoribbon 104 (i.e., Figure 1The area of ​​the nanoribbon 104 in the xz plane of the example coordinate system xyz shown, which is perpendicular to the longitudinal axis 120 of the nanoribbon 104, can be between about 25 and 10,000 square nanometers, including all values ​​and ranges therein (e.g., between about 25 and 1,000 square nanometers, or between about 25 and 500 square nanometers). In some embodiments, the width of the nanoribbon 104 (i.e., the dimension measured in a plane parallel to the support 102 and in a direction perpendicular to the longitudinal axis 120 of the nanoribbon 104, e.g., along Figure 1 The y-axis measurement of the example coordinate system shown) may be the height of the nanoribbon 104 (i.e., the dimension measured in a plane perpendicular to the support 102, e.g., along Figure 1 The z-axis measurement of the example coordinate system shown) - including all values ​​and ranges therein - is at least about 3 times, such as at least about 4 times or at least about 5 times. Although Figure 1 The nanoribbon 104 shown in is shown as having a rectangular cross-section, but the nanoribbon 104 may alternatively have a cross-section that is rounded at the corners or otherwise irregularly shaped, and the gate stack 106 may conform to the shape of the nanoribbon 104. The term "face" of the nanoribbon may refer to a side of the nanoribbon 104 that is larger than a side perpendicular thereto (when measured in a plane substantially perpendicular to the longitudinal axis 120 of the nanoribbon 104), the latter side being referred to as a "sidewall" of the nanoribbon.

[0033] In various embodiments, the semiconductor material of the nanoribbon 104 may be composed of a semiconductor material system, including, for example, an N-type or P-type material system. In some embodiments, the nanoribbon 104 may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the nanoribbon 104 may include a combination of semiconductor materials. In some embodiments, the nanoribbon 104 may include a single crystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the nanoribbon 104 may include a compound semiconductor having a first sublattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from Group V of the periodic table (e.g., P, As, Sb).

[0034] For some example N-type transistor embodiments (i.e., for embodiments where transistor 110 is an N-type metal oxide semiconductor (NMOS) transistor), the channel material of nanoribbon 104 may include a III-V material having a relatively high electron mobility, such as, but not limited to, InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material of nanoribbon 104 may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some In x Ga 1-x As fin embodiments, the In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In 0.7 Ga 0.3 As). For some example P-type transistor embodiments (i.e., for embodiments where transistor 110 is a P-type metal oxide semiconductor (PMOS) transistor), the channel material of nanoribbon 104 may advantageously be a Group IV material with high hole mobility, such as, but not limited to, Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material of nanoribbon 104 may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7.

[0035] In some embodiments, the channel material of the nanoribbon 104 can be a thin film material, such as a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, if the transistor formed in the nanoribbon is a thin film transistor (TFT), the channel material of the nanoribbon 104 may include one or more of the following: tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous silicon or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In some embodiments, the channel material of the nanoribbon 104 may have a thickness between about 5 and 75 nanometers, including all values ​​and ranges therein. In some embodiments, thin film channel materials may be deposited at relatively low temperatures, which allows the channel materials to be deposited within the thermal budget imposed by back end manufacturing to avoid damaging other components, eg, front end components such as logic devices.

[0036] like Figure 1As shown, the gate stack 106 including the gate electrode material 108 and the optional gate insulator material 112 can completely or almost completely wrap around a portion of the nanoribbon 104, and the active area (channel area) of the channel material of the transistor 110 corresponds to the portion of the nanoribbon 104 wrapped by the gate stack 106. Figure 1 As shown, the gate insulator material 112 may be wrapped around lateral portions of the nanoribbon 104 , and the gate electrode material 108 may be wrapped around the gate insulator material 112 .

[0037] The gate electrode material 108 may include at least one P-type work function metal or N-type work function metal, depending on whether the transistor of which it is a part is a PMOS or NMOS transistor. For example, when the transistor 110 is a PMOS transistor, a P-type work function metal may be used as the gate electrode material 108, and when the transistor 110 is an NMOS transistor, an N-type work function metal may be used as the gate electrode material 108. For a PMOS transistor, metals that may be used for the gate electrode material 108 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode material 108 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode material 108 may include a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a fill metal layer. For other purposes, additional metal layers may be included, such as barrier layers (e.g., tantalum, tantalum nitride, aluminum-containing alloys, etc.). In some embodiments, the gate electrode material 108 may include a resistance-reducing cap layer (e.g., copper, gold, cobalt, or tungsten). For other purposes, additional layers may be included alongside the gate electrode material 108, such as acting as diffusion barriers or / and adhesion layers.

[0038] In some embodiments, the gate insulator material 112 may include one or more high-k dielectrics, including any of the materials discussed herein with reference to the insulator material that may surround portions of the transistor 110. In some embodiments, during fabrication of the transistor 110, an annealing process may be performed on the gate insulator material 112 to improve the quality of the gate insulator material 112. In some embodiments, the gate insulator material 112 may have a thickness that may be between about 0.5 nanometers and 3 nanometers, including all values ​​and ranges therein (e.g., between about 1 and 3 nanometers, or between about 1 and 2 nanometers). In some embodiments, the gate stack 106 may be surrounded by a gate spacer, which may be Figure 1106 and the source / drain contacts of transistor 110, and may be made of a low-k dielectric material. Some examples of low-k dielectric materials include, but are not limited to, silicon dioxide, carbon-doped oxides, silicon nitride, organic polymers (such as perfluorocyclobutane or polytetrafluoroethylene), fused silica glass (FSG), and organosilicates (such as silsesquioxane, siloxane, or organosilicate glass). The gate spacer may include holes or air gaps to further reduce its dielectric constant.

[0039] In some embodiments, for example, when transistor 110 is a memory transistor of a hysteresis memory cell (i.e., a memory that functions based on the hysteresis phenomenon), gate insulator 112 may be replaced or supplemented by a hysteresis material. In some embodiments, the hysteresis material may be provided as a ferroelectric (FE) or antiferroelectric (AFE) material layer. For example, such FE / AFE materials may include one or more materials that exhibit sufficient FE / AFE behavior even in thin dimensions, such as an insulator material of which at least about 10% is in an orthorhombic or tetragonal phase (e.g., as a material in which up to about 90% of the material may be amorphous or in a monoclinic phase). Some examples of such materials include materials containing hafnium, oxygen, and zirconium (e.g., hafnium zirconium oxide (HfZrO, also referred to as HZO)), materials containing hafnium, oxygen, and silicon (e.g., silicon-doped (Si-doped) hafnium oxide), materials containing hafnium, oxygen, and germanium (e.g., germanium-doped (Ge-doped) hafnium oxide), materials containing hafnium, oxygen, and aluminum (e.g., aluminum-doped (Al-doped) hafnium oxide), and materials containing hafnium, oxygen, and yttrium (e.g., yttrium-doped (Y-doped) hafnium oxide). However, in other embodiments, any other material that exhibits FE / AFE behavior at thin dimensions may be used in place of or in addition to the gate insulator 112 and is within the scope of the present disclosure. In some embodiments, the FE / AFE material included in the gate stack 106 may have a thickness that may be between approximately 0.5 nanometers and 10 nanometers, including all values ​​and ranges therein (e.g., between approximately 1 and 8 nanometers, or between approximately 0.5 and 5 nanometers). In other embodiments, the hysteresis material may be provided as a stack of materials that together exhibit hysteresis behavior. Such a stack may include, for example, a stack of silicon oxide and silicon nitride. Unless otherwise specified, the description provided herein regarding the gate insulator 112 is equally applicable to embodiments in which the gate insulator 112 is replaced or supplemented by a hysteresis material.

[0040] Turning to the S / D region 114 of the transistor 110, in some embodiments, the S / D region may be highly doped, for example, with a dopant concentration of about 10 21 cm -3 , so as to advantageously connect with the corresponding S / D electrodes ( Figure 1114-1 and the second S / D region 114-2), and thus, may be referred to as a "highly doped" (HD) region. Even when doped as described herein to achieve threshold voltage tuning, the channel portion of the transistor typically includes semiconductor material having a doping concentration that is significantly less than the doping concentration of the S / D region 114.

[0041] The S / D region 114 of the transistor 110 can be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into the nanoribbon 104 to form source and drain regions. An annealing process to activate the dopants and diffuse them further into the nanoribbon 104 can follow the ion implantation process. In the latter process, a portion of the nanoribbon 104 can first be etched to form a recess at the location of the future S / D region 114. An epitaxial deposition process can then be performed to fill the recess with the material used to make the S / D region 114. In some implementations, the S / D region 114 can be made using a silicon alloy such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy can be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In further embodiments, the S / D region 114 can be formed using one or more alternative semiconductor materials, such as germanium or a III-V material or alloy. And in further embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D zones 114. In some embodiments, the distance between the first and second S / D zones 114 (i.e., the dimension measured along the longitudinal axis 120 of the nanoribbon 104) may be between about 5 and 40 nanometers, including all values ​​and ranges therein (e.g., between about 22 and 35 nanometers, or between about 20 and 30 nanometers).

[0042] Figure 1 The IC device 100 shown in FIG. 1 and the IC devices / structures shown in other figures of the present disclosure are intended to illustrate the relative arrangement of some of the components, and the IC device 100 or portions thereof may include other components not shown (e.g., electrical contacts to the S / D regions 114 of the transistor 110, additional layers such as spacers around the gate electrode of the transistor 110, etc.). For example, although not shown in FIG. Figure 1, but a dielectric spacer may be provided between a first S / D electrode (which may also be referred to as a “first S / D contact”) coupled to the first S / D region 114-1 of the transistor 110 and the gate stack 106, and between a second S / D electrode (which may also be referred to as a “second S / D contact”) coupled to the second S / D region 114-2 of the transistor 110 and the gate stack 106 to provide electrical insulation between the source electrode, the gate electrode, and the drain electrode. In another example, although there is no Figure 1 10 is specifically shown in the figure, but at least a portion of transistor 110 may be surrounded by an insulator material, such as any suitable interlayer dielectric (ILD) material. In some embodiments, such an insulator material may be a high-k dielectric, including elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used for this purpose may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium oxide silicon, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In other embodiments, the insulator material surrounding a portion of transistor 110 may be a low-k dielectric material.

[0043] Figure 2-3 is a circuit diagram of two example arrays of floating body memory cells according to some embodiments of the present disclosure. Figure 2-3 In each of the floating memory cells, the individual transistors of the different floating memory cells are labeled as transistors T BL,SL,WL , where the indices BL, SL, and WL indicate the respective BL, SL, and WL to which the transistor T is coupled. 1,1,1 Coupled to BL1, SL1 and WL1, etc. Each transistor T may be a FET (e.g., transistor 110 as described above) having a gate terminal, a source terminal and a drain terminal. Figure 2-3 , respectively, as terminals G, S, and D. For each transistor T, BL is coupled to a first S / D terminal / region of the transistor (e.g., coupled to the first S / D region 114-1 as described above), SL is coupled to a second S / D terminal / region of the transistor (e.g., coupled to the second S / D region 114-2 as described above), and WL is coupled to the gate of the transistor (e.g., coupled to the gate electrode material 108 as described above). Although Figure 2-3 A specific number of transistors BL, SL and WL are shown in FIG. Figure 2-3 The circuit diagram of the example implementation Figure 4-8 A specific number of transistors BL, SL, and WL are shown in the IC device of FIG. 1 , but in other embodiments, any suitable number of transistors BL, SL, and WL may be used in a 3D floating body memory according to the principles described herein.

[0044] Figure 2 An array 200 is shown in which, for a given floating body memory cell (denoted by Figure 2 Some different transistors T are shown), some different WL, BL and SL are parallel to different axes of the Cartesian coordinate system. For example, Figure 2 All BLs are shown parallel to the x-axis of the example xyz coordinate system shown, all SLs are parallel to the y-axis, and all WLs are parallel to the z-axis. In array 200, some transistors T may be coupled to a single (i.e., shared) WL while being coupled to different BLs and SLs. For example, Figure 2 As shown, transistor T 1,1,1 , T 2,2,1 and T 3,3,1 Coupled to shared WL1 (where transistor T 1,1,1 Further coupled to BL1 and SL1, transistor T 2,2,1 is further coupled to BL2 and SL2, and transistor T 3,3,1 is further coupled to BL3 and SL3), and transistor T 1,4,2 , T 2,5,2 and T 3,6,2 Coupled to shared WL2 (where transistor T 1,4,2 Further coupled to BL1 and SL4, transistor T 2,5,2 is further coupled to BL2 and SL5, and transistor T 3,6,2 BL3 and SL6). In addition, in array 200, some transistors T may be coupled to a single (ie, shared) BL and simultaneously coupled to different SLs and WLs. Figure 2 As shown, transistor T 1,1,1 and T 1,4,2 Coupled to shared BL1 (where transistor T 1,1,1 is further coupled to SL1 and WL1, and transistor T 1,4,2 Further coupled to SL4 and WL2), transistor T 2,2,1 and T 2,5,2 Coupled to shared BL2 (where transistor T 2,2,1 is further coupled to SL2 and WL1, and transistor T 2,5,2 is further coupled to SL5 and WL2), and transistor T 3,3,1 and T 3,6,2 Coupled to shared BL3 (where transistor T 3,3,1 is further coupled to SL3 and WL1, and transistor T 3,6,2 Further coupled to SL6 and WL2). In some embodiments, array 200 may include a Figure 2The 2D plane shown in FIG. 1 is further extended along the y-axis by an additional 2D plane of the 2D plane shown, the additional 2D plane containing an additional 2D sub-array of floating body memory cells. In such an embodiment, some transistors T may be coupled to a single (i.e., shared) SL while being coupled to different BLs and WLs. For example, although Figure 2 Not shown, transistor T 1,1,1 And one or more additional transistors in other xz planes may be coupled to the shared SL1 while being coupled to different BLs and WLs.

[0045] Figure 3 An array 300 is shown in which, for a given floating body memory cell (denoted by Figure 3 300 ), all of the WLs, BLs, and SLs are in layers parallel to the xy plane of the example Cartesian coordinate system shown in this figure (i.e., parallel to the support structure on which the array 300 is provided), wherein the BLs and SLs are substantially parallel to each other, and the SLs are substantially perpendicular to the BLs and SLs. For example, Figure 3 All WLs are shown parallel to the x-axis of the illustrated example xyz coordinate system, while all BLs and all SLs are parallel to the y-axis. In array 300, some transistors T may be coupled to a single (i.e., shared) BL and also to a single (i.e., shared) SL while being coupled to different WLs. For example, Figure 3 As shown, transistor T 1,1,1 , T 1,1,2 , T 1,1,3 and T 1,1,4 Each of them is coupled to the shared BL1 and the shared SL1, and is coupled to WL1, WL2, WL3 and WL4 respectively. Figure 3 As shown, transistor T 2,2,5 , T 2,2,6 , T 2,2,7 and T 2,2,8 Each of them is coupled to the shared BL2 and the shared SL2, and is also coupled to WL5, WL6, WL7, and WL8, respectively. In another example, Figure 3 As shown, transistor T 3,3,9 , T 3,3,10 , T 3,3,11 and T 3,3,12 Each of the transistors is coupled to a shared BL3 and a shared SL3, and is coupled to WL9, WL10, WL11, and WL12, respectively. In some embodiments, all transistors coupled to a BL and SL pair may be arranged in a corresponding layer 334 above the support structure, where different layers 334 may be stacked vertically above each other (i.e., stacked in the z-axis direction of the example coordinate system shown). This Figure 3, showing transistor T coupled to shared BL1 and shared SL1 1,1,1 , T 1,1,2 , T 1,1,3 and T 1,1,4 A transistor T is provided in layer 334-1, coupled to shared BL2 and shared SL2. 2,2,5 , T 2,2,6 , T 2,2,7 and T 2,2,8 The transistor T is provided in the layer 334-2 and coupled to the shared BL3 and the shared SL3. 3,3,9 , T 3,3,10 , T 3,3,11 and T 3,3,12 Provided in 334-3. The layers 334 may be parallel to each other and to the support structure on which the memory array 300 is provided. Each layer 334 may be viewed as a two-dimensional (2D) sub-array of floating body memory cells.

[0046] Furthermore, in some embodiments of the array 300, adjacent transistor pairs in a given layer 334 may share S / D regions coupled to either BL or SL. For example, in the first layer 334-1, transistors T 1,1,1 and T 1,1,2 The first S / D region (SD1) coupled to the shared BL1 can be shared, and the transistor T 1,1,3 and T 1,1,4 In another example, in the second layer 334-2, the transistor T 2,2,5 and T 2,2,6 The first S / D region coupled to the shared BL2 can be shared, and the transistor T 2,2,7 and T 2,2,8 Similarly, in the third layer 334-3, the transistor T 3,3,9 and T 3,3,10 The first S / D region coupled to the shared BL3 can be shared, and the transistor T 3,3,11 and T 3,3,12 Although not specifically shown, in other embodiments of the array 300, adjacent transistors may share their second S / D regions (SD2), which are coupled to a shared SL.

[0047] Figure 4-8 Shown according to Figure 2-3 Specifically, according to various embodiments of the present disclosure, Figure 4 is based on Figure 2 A circuit diagram of an example IC device implementing a 3D floating body memory is shown in cross-sectional side view. Figure 5-8 is based on Figure 3 A cross-sectional side view of an example IC device implementing a 3D floating body memory is shown in FIG. Figure 4-8 The various elements with reference numerals mentioned in the description of FIG. 1 are shown in different patterns in the figures, including Figure 4-8 A legend showing the correspondence between reference numerals and patterns is provided at the bottom of each drawing page of FIG. Figure 4-8 Different patterns are used to illustrate the support structure 402, the channel material 404, the gate electrode material 408, the gate insulator material 412, and so on.

[0048] Steering Figure 4 , shows an IC device 400, wherein the IC device 400 includes a support structure 402 and an insulator material 422 on the support structure 402. The support structure 402 can be an example of the support structure 102 described above. The insulator material 422 can include any suitable insulator material described above, such as any suitable ILD material described above. Figure 4 Also shown are two openings 424-1 and 424-2 extending from the top of the insulator material 422 toward the support structure 402. In some embodiments, the openings 424 may be through holes. Figure 4 The opening 424 is shown extending through all of the insulator material 422, stopping at the support structure 402, but in other embodiments of the IC device 400, this may not be the case, and the opening 424 may end somewhere within the insulator material 422 without reaching the support structure 402. Figure 4 As shown, a channel material 404 may be deposited to line the sidewalls of the opening 424. The material composition and thickness of the channel material 404 may be as described above with reference to the thin film channel materials that may be included in the transistor 110.

[0049] Once the channel material 404 has been deposited on the sidewalls of the openings 424, the sidewalls may be further lined with a gate insulator material 412, and then the remaining portion of the opening 424 may be filled with a gate electrode material 408. The gate material 412 and the gate electrode material 408 may be similar to the gate material 112 and the gate electrode material 108 described above with reference to the transistor 110. Although the same gate electrode material 408 is shown in both openings 424, in various embodiments, the material composition of the gate electrode material 408 in different openings 424 may be the same, but not necessarily. Similarly, although the same channel material 404 and the gate insulator material 412 are shown as lining the sidewalls of both openings 424, in various embodiments, the material composition of the channel material 404 in different openings 424 may be the same, but not necessarily, and the material composition of the gate insulator material 412 in different openings 424 may be the same, but not necessarily. Because the channel material 404 and the gate insulator material 412 are deposited to line the sidewalls of the opening 424, and the opening 424 is then filled with the gate electrode material 408, in the IC device 400, for each opening 424, the gate insulator material 412 can be a liner surrounding the gate electrode material 408, and the channel material 404 can be a liner surrounding the gate insulator material 412.

[0050] Figure 4 Also shown is an S / D interface material 426 that may be provided at the interface between the S / D regions of transistors formed based on the channel material 404 and the corresponding BLs and SLs coupled to these S / D regions. The S / D interface material 426 may be any suitable conductive material, as the material composition of the BLs and SLs of the IC device 400 may not be ideal for providing suitable contact to the S / D regions of the transistors of the various floating body memory cells, and the S / D interface material 426 may be used to ensure better contact. In other embodiments of the IC device 400, the S / D interface material 426 may be absent at one or more points where the BLs and SLs of the IC device 400 need to make electrical contact with the S / D regions of the various transistors. When present, the S / D interface material 426 may be a liner of the S / D regions in the channel material 404 surrounding the opening 424.

[0051] Figure 4 The IC device 400 is Figure 2 An example of an array 200, and therefore, in Figure 4 Use with Figure 2 The same symbols as those used in FIG. 1 are used to label the various transistors T and the control lines (ie, BL, SL, and WL), and with respect to Figure 2 The description provided is applicable to Figure 4 , and for the sake of brevity, it will not be repeated. Figure 4Different rectangles are shown to highlight the approximate boundaries of different transistors. In IC device 400, the conductive material used as gate electrode material 408 in opening 424 provides corresponding WLs, i.e., WL1 is formed by gate electrode material 408 in opening 424-1, and WL2 is formed by gate electrode material 408 in opening 424-2. Therefore, in IC device 400, WL extends in a direction substantially perpendicular to support structure 402. On the other hand, BL and SL extend in a direction substantially parallel to support structure 402, wherein BL is perpendicular to SL. Each transistor of the various floating body memory cells of IC device 400 is a vertical transistor because the gate length (i.e., the distance between the first and second S / D regions of the transistor) is measured in the vertical direction (i.e., in a direction substantially perpendicular to support structure 402).

[0052] Figure 4 As shown, in some embodiments, transistors of array 200 coupled to a single WL may be provided based on a channel material 404 deposited on the sidewalls of a single opening 424, wherein different ones of the transistors have channel regions in different portions of the channel material 404. Thus, Figure 4 As shown, in some embodiments, transistors of array 200 coupled to a single WL can be stacked vertically on top of each other. For example, Figure 4 Transistor T coupled to shared WL1 is shown 1,1,1 , T 2,2,1 and T 3,3,1 may be stacked vertically on top of each other and may have their channel regions in different portions of the channel material 404 on the sidewalls of the opening 424-1. Figure 4 shows transistor T coupled to shared WL2 1,4,2 , T 2,5,2 and T 3,6,2 may be stacked vertically on top of each other and may have their channel regions in different portions of the channel material 404 on the sidewalls of the opening 424 - 2 .

[0053] Figure 4 It is also shown that in some embodiments, transistors of array 200 coupled to a single BL may be provided based on channel material 404 deposited on sidewalls of different openings 424, but wherein the channel regions of different ones of these transistors may be substantially in the same layer relative to support structure 402. Thus, Figure 4 As shown, in some embodiments, the transistors of array 200 coupled to a single BL can be arranged side by side with each other. Figure 4 The transistor T coupled to the shared BL1 is shown 1,1,1 and T 1,4,2 The channel region thereof may be in layer 434-1 above and parallel to support structure 402. Similarly, Figure 4 The transistor T coupled to the shared BL2 is shown 2,2,1 and T 2,5,2 The transistor T 434 - 2 may have its channel region in layer 434 - 2 above and parallel to support structure 402 and coupled to shared BL3 . 3,3,1 and T 3,6,2 The channel region thereof may be in layer 434 - 3 above and parallel to support structure 402 .

[0054] Figure 4 Also shown are gate contact 428 and contact 430. Gate contact 428 can be in electrical contact with gate electrode material 408 in opening 424 and can be used to apply a signal to the gate. Contact 430 can also be in electrical contact with gate electrode material 408 in opening 424 and can be used to connect WL to a row driver transistor (not shown).

[0055] Figure 5 An IC device 500 is shown, which is implemented Figure 3 An example diagram of an array 300. Figure 5 As shown, IC device 500 includes support structure 502 and insulator material 522 on support structure 502. Support structure 502 can be an example of support structure 102 as described above. Insulator material 522 can include any suitable insulator material described above, such as any suitable ILD material described above. In addition, IC device 500 includes a plurality of nanoribbons 524, each of which includes channel material 504, shown as nanoribbons 524-1, 524-2, and 524-3, extending through insulator material 522, substantially parallel to support structure 502, and having their longitudinal axes along the y-axis of the example coordinate system shown (similar to Figure 1 As described above, each nanoribbon 524 is an example of a nanoribbon 104, and nanoribbons 524-1, 524-2, and 524-3 may be stacked vertically above each other over support structure 502. The material composition and dimensions of channel material 504 may be as described above with reference to nanoribbons 104 of transistor 110.

[0056] Similar to transistor 110, Figure 5 5 shows how the gate insulator material 512 and gate electrode material 508 of the various transistors of the floating body memory cell may wrap around portions of the nanoribbon 524. The gate material 512 and gate electrode material 508 may be similar to the gate material 112 and gate electrode material 108 described above with reference to the transistor 110. Although Figure 5The same channel material 504, gate electrode material 508, and gate insulator material 512 associated with different nanoribbons 524 are shown, but in various embodiments, the material composition of the channel material 504 of different nanoribbons 524 can be the same, but not necessarily the same, and the material composition of any one or more of the channel material 504, gate electrode material 508, and gate insulator material 512 associated with different nanoribbons 524 can be the same, but not necessarily the same.

[0057] Figure 5 Also shown is an S / D contact 526 coupled to the S / D regions in the nanoribbon 524. The S / D contact 526 may be similar to the S / D interface material 426 described above. Figure 5 Also shown is a via 528 between an S / D contact 526 and the corresponding BL or SL to which the S / D contact 526 is coupled. The via 528 is an example of an electrical interconnect that can be used to connect the S / D contact 526 to the corresponding BL or SL. In other embodiments of the IC device 500, there may be no S / D contact 526 and / or via 528, or other types and geometries of interconnects may be provided to ensure electrical connectivity between the S / D regions of various transistors provided based on the nanoribbon 524 and the corresponding BL and SL.

[0058] Figure 5 The IC device 500 is Figure 3 An example of an array 300, and therefore, in Figure 5 Use with Figure 3 The same symbols as those used in FIG. 1 are used to label the various transistors T and the control lines (ie, BL, SL, and WL), and with respect to Figure 3 The description provided is applicable to Figure 5 , and for the sake of brevity, will not be repeated. IC device 500 includes a 2D sub-array of floating body memory cells arranged in different layers 534 , which are similar to layers 334 of array 300 . Figure 5 Different rectangles are shown to highlight the approximate boundaries of different transistors. In IC device 500, the conductive material used as gate electrode material 508 around nanoribbon 524 provides the corresponding WL. Figure 5 In the figure, only WL1-WL4 of the first layer 534-1 are individually labeled, and in order not to confuse the drawing, the WLs of the other layers 534 are not labeled, but the names of the other WLs are based on Figure 5The indexing of the various transistors labeled in is clear. For example, WL1 is formed by gate electrode material 508 around a first portion of nanoribbon 524-1, WL2 is formed by gate electrode material 508 around a second portion of nanoribbon 524-1, WL3 is formed by gate electrode material 508 around a third portion of nanoribbon 524-1, and WL4 is formed by gate electrode material 508 around a fourth portion of nanoribbon 524-1.

[0059] like Figure 5 As shown, in IC device 500, WL extends in a direction substantially parallel to support structure 502, for example, in a direction parallel to the x-axis of the illustrated example coordinate system. BL and SL also extend in a direction substantially parallel to support structure 502, but both BL and SL are substantially perpendicular to WL (thus, BL and SL are parallel to each other and extend in a direction parallel to the y-axis of the illustrated example coordinate system). Each transistor of the various floating body memory cells of IC device 500 is a horizontal transistor because the gate length (i.e., the distance between the first and second S / D regions of the transistor) is measured in the horizontal direction (i.e., in a direction substantially parallel to support structure 502).

[0060] Figure 5 It also shows how the S / D regions of some adjacent transistors can be shared to couple them to corresponding control lines, as described with reference to array 300. For example, in the first layer 534-1, Figure 5 shows that the transistor T 1,1,1 and T 1,1,2 A single shared S / D contact 526 is shown to couple the first S / D regions of these transistors to the shared BL1, and the transistors T 1,1,3 and T 1,1,4 The shared single S / D contact 526 is used to couple the first S / D regions of these transistors to the shared BL1. Similar conditions apply to the other layers 534. In some embodiments, the IC device 500 can include plugs 530 in the nanoribbon 524 to electrically disconnect the S / D regions of transistors that do not share any of their S / D regions with each other. For example, the plug 530 can be included in the transistor T 1,1,2 and T 1,1,3 Similarly, the plug 530 may be included in the nanoribbon 524-1 between the closest S / D regions of the transistor T. 2,2,6 and T 2,2,7 The nanoribbon 524-2 between the closest S / D regions and / or the plug 530 may be included in the transistor T 3,3,10 and T 3,3,11 The plug 530 may be in the nanoribbon 524-3 between the closest S / D regions. The plug 530 may include any suitable insulator material, for example, any of the insulator materials described above.

[0061] Figure 5 An embodiment is shown in which, in each layer 534, one of the BL and SL is below the channel material 504 of the layer 534 and the other is above the channel material. This means that a contact to the S / D region coupled to one of the BL and SL is made from the top of the transistor T (i.e., from the side of the channel material 504 farthest from the support structure 502), while a contact to the S / D region coupled to the other of the BL and SL is made from the bottom of the transistor T (i.e., from the side of the channel material 504 closest to the support structure 502). For example, in some embodiments, the BL may be below the channel material 504 in each layer 534 and the SL may be above the channel material 504 in each layer 534, as shown in FIG. Figure 5 In other embodiments, both the BL and the SL of a given layer 534 may be disposed above the channel material 504 of that layer or below the channel material 504 of that layer. Figure 6 , an example in which BL and SL are arranged above the channel material 504 of each layer 534 is shown, Figure 6 An IC device 600 is shown which, except for this difference, is substantially the same as IC device 500. Other descriptions provided with respect to IC device 500 are applicable to IC device 600 and, therefore, are not repeated for the sake of brevity. Figure 5 The embodiment shown may be advantageous in that it is easier to route BL and SL. Figure 6 The illustrated embodiment may be advantageous in that it is easier to manufacture.

[0062] Although Figure 5-6 An embodiment is shown in which the channel material 504 is included in the nanoribbons 524 in each layer 534, but this may be different in other embodiments. For example, Figure 7-8 They are shown respectively with Figure 5-6 , but in which the channel material 504 is not formed as a nanoribbon 524, but instead is provided as a layer 724 of the channel material 504, for example using layer transfer. In such an embodiment, the gate electrode material 508 may not wrap around the channel material 504, but rather be provided on one side of the channel material 504. An example of this is shown in Figure 7 It is shown in Figure 7 An IC device 700 is shown that is substantially the same as IC device 500 , except that the channel material 504 in each layer 534 is provided as a layer 724 of channel material 504 . Figure 7It is shown that the first layer 534-1 includes the layer 724-1 of the channel material 504, the second layer 534-2 includes the layer 724-2 of the channel material 504, and the third layer 534-3 includes the layer 724-3 of the channel material 504. Another difference is that in the IC device 700, the gate electrode material 508 is provided on the top side of the channel material 504 of each layer 724. Other descriptions provided with respect to the IC device 500 are applicable to the IC device 700 and, therefore, are not repeated for the sake of brevity.

[0063] Similar to Figure 5 , Figure 7 An embodiment is shown in which, in each layer 534, one of the BL and SL is below the channel material 504 of the layer 534 and the other is above the channel material. In other embodiments, both the BL and SL of a given layer 534 may be disposed above the channel material 504 of that layer or below the channel material 504 of that layer. Figure 8 , an example in which BL and SL are arranged above the channel material 504 of each layer 534 is shown, Figure 8 An IC device 800 is shown, which, except for this difference, is substantially the same as IC device 700. Other descriptions provided with respect to IC device 700 are applicable to IC device 800 and, therefore, are not repeated for the sake of brevity. Figure 7 The embodiment shown may be advantageous in that it is easier to route BL and SL, while Figure 8 The illustrated embodiment may be advantageous in that it is easier to manufacture.

[0064] like Figures 1 to 8 The various arrangements of IC devices shown in the drawings do not represent an exhaustive set of IC devices that can implement 3D floating body memory as described herein, but rather merely provide examples of such devices / structures / components. Figure 5 and Figure 7 SL is shown to be above the channel material 504 and BL is below the channel material 504 in each layer 534, but in other embodiments, this may be reversed for one or more layers 534 (i.e., BL may be above the channel material 504 and SL may be below the channel material 504 for one or more layers 534). Similarly, although Figure 6 and Figure 8 Both the SL and the BL are shown above the channel material 504 in each layer 534, but in other embodiments, this can be reversed for one or more layers 534 (i.e., both the SL and the BL can be below the channel material 504 for one or more layers 534). In another example, although Figure 6 and Figure 8BL is shown as being further away from the channel material 504 than SL in each layer 534, but in other embodiments, this may be reversed for one or more layers 534 (i.e., SL may be further away from the channel material 504 than BL for one or more layers 534). In yet another example, although Figure 7 and Figure 8 Top-gate transistors T are shown (i.e., for each transistor, the gate electrode material 508 is provided farther away from the support structure 502 than the corresponding channel material 504), but in other embodiments, at least some of the transistors may be bottom-gate transistors (i.e., for one or more layers 534 or for one or more transistors within a given layer 534, the gate electrode material 508 may be provided closer to the support structure 502 than the corresponding channel material 504). Figure 1-8 The numbers and positions of the various elements shown in are purely illustrative, and in various other embodiments, other numbers of these elements provided in other positions relative to each other may be used based on the general architectural considerations described herein.

[0065] An arrangement having one or more IC devices implementing a 3D floating body memory as disclosed herein may be included in any suitable electronic device. Figure 9-13 Various examples of devices and components are shown that may include one or more IC devices that implement a 3D floating body memory as disclosed herein, for example, including any of IC devices 400, 500, 600, 700, or 800, or any combination of such IC devices, and / or any IC device that implements array 200 or 300 as disclosed herein.

[0066] Fig. 9 A top view of a wafer 2000 and a die 2002 is shown, which may include one or more IC devices implementing a 3D floating memory according to any embodiment disclosed herein. In some embodiments, the die 2002 may be included in an IC package according to any embodiment disclosed herein. For example, any die 2002 may be used as Fig.10Any die 2256 in the IC package 2200 shown. Wafer 2000 can be made of semiconductor material and can include one or more die 2002 having IC structures formed on a surface of wafer 2000. Each die 2002 can be a repeating unit of a semiconductor product including any suitable IC (e.g., an IC including one or more IC devices implementing a 3D floating body memory as described herein, e.g., an IC including any of the following: IC devices 400, 500, 600, 700, or 800; or any combination of such IC devices; and / or any IC device implementing array 200 or 300 as disclosed herein). After the fabrication of the semiconductor product is completed (e.g., after fabricating any embodiment of the IC device 400, 500, 600, 700, or 800, or any combination of such IC devices, and / or implementing any IC device of the array 200 or 300 as disclosed herein), the wafer 2000 may undergo a singulation process, wherein each die 2002 is separated from each other to provide discrete "chips" of the semiconductor product. Specifically, a device including one or more IC devices implementing the 3D floating body memory as disclosed herein may take the form of a wafer 2000 (e.g., unsegmented) or a die 2002 (e.g., segmented). The die 2002 may include supporting circuits to route electrical signals to various memory cells, transistors, capacitors, and any other IC components. In some embodiments, the wafer 2000 or die 2002 may implement or include a memory device (e.g., a 3D floating body memory as described herein), a logic device (e.g., an AND gate, an OR gate, a NAND gate, or a NOR gate), or any other suitable circuit element. Multiple of these devices may be combined on a single die 2002. For example, a memory array formed of a plurality of memory devices may be associated with a processing device (e.g., Fig.12 Processing device 2402 or Fig.13 Logic 2502) or other logic configured to store information in a memory device or execute instructions stored in a memory array is formed on the same die 2002.

[0067] Fig.10 is a side cross-sectional view of an example IC package 2200 that may include one or more IC devices implementing a 3D floating body memory according to any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a system-in-package (SiP).

[0068] The packaging substrate 2252 can be formed of a dielectric material (e.g., a ceramic, a laminate film, an epoxy resin film having filler particles therein, etc.) and can have a conductive path extending through the dielectric material between surface 2272 and surface 2274, or between different locations on surface 2272, and / or between different locations on surface 2274.

[0069] The packaging substrate 2252 may include conductive contacts 2263 coupled to the conductive paths 2262 through the packaging substrate 2252, thereby allowing the circuits within the die 2256 and / or the interposer 2257 to be electrically coupled to individual ones of the conductive contacts 2264 (or to other devices included in the packaging substrate 2252, not shown).

[0070] The IC package 2200 may include an interposer 2257 coupled to a package substrate 2252 via conductive contacts 2261 of the interposer 2257 , first level interconnects 2265 , and conductive contacts 2263 of the package substrate 2252 . Fig.10 First level interconnects 2265 are shown as solder bumps, but any suitable first level interconnects 2265 may be used. In some embodiments, interposer 2257 may not be included in IC package 2200; instead, die 2256 may be coupled directly to conductive contacts 2263 at face 2272 via first level interconnects 2265.

[0071] IC package 2200 may include one or more dies 2256 coupled to interposer 2257 via conductive contacts 2254 of die 2256, first level interconnects 2258, and conductive contacts 2260 of interposer 2257. Conductive contacts 2260 may be coupled to conductive paths (not shown) through interposer 2257, thereby allowing circuitry within die 2256 to be electrically coupled to individual ones of conductive contacts 2261 (or to other devices included in interposer 2257, not shown). Fig.10 The illustrated first level interconnect 2258 is a solder bump, but any suitable first level interconnect 2258 may be used. As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., a metal) that serves as an interface between different components; a conductive contact may be recessed into a surface of a component, flush with a surface of a component, or extend away from a surface of a component, and may take any suitable form (e.g., a conductive pad or a socket).

[0072] In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first level interconnect 2265, and a mold compound 2268 may be disposed around the die 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. An example material that may be used for the underfill material 2266 and the mold compound 2268 is an epoxy resin mold material, as appropriate. The second level interconnect 2270 may be coupled to the conductive contact 2264. Fig.10 The second level interconnects 2270 shown in FIG. 2 are solder balls (e.g., for a ball grid array arrangement), but any suitable second level interconnects 2270 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second level interconnects 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and described below with reference to Fig.11 discussed.

[0073] The die 2256 may take the form of any embodiment of the die 2002 discussed herein (e.g., may include any embodiment of an IC device implementing the 3D floating body memory described herein, such as any of the IC devices 400, 500, 600, 700, or 800, or any combination of such IC devices, and / or any IC device implementing the array 200 or 300 disclosed herein). In embodiments where the IC package 2200 includes multiple die 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The die 2256 may include circuits that perform any desired functions. For example, one or more of the die 2256 may be a logic die (e.g., a silicon-based die), and one or more of the die 2256 may be a memory die (e.g., a high bandwidth memory), including an embedded memory die as described herein. In some embodiments, any die 2256 may include one or more IC devices implementing a 3D floating body memory, such as discussed above; in some embodiments, at least some of the die 2256 may not include any IC device implementing a 3D floating body memory.

[0074] Fig.10 The IC package 2200 shown may be a flip chip package, but other package architectures may be used. For example, the IC package 2200 may be a ball grid array (BGA) package, such as an embedded wafer level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer level chip scale package (WLCSP) or a panel fan-out (FO) package. Although in Fig.10Two dies 2256 are shown in the IC package 2200, but the IC package 2200 may include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package substrate 2252 or disposed on either side of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0075] Fig.11 is a cross-sectional side view of an IC device assembly 2300, which IC device assembly 2300 may include components having one or more IC devices that implement a 3D floating memory according to any embodiment disclosed herein. The IC device assembly 2300 includes a plurality of components disposed on a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components disposed on a first side 2340 of the circuit board 2302 and an opposing second side 2342 of the circuit board 2302; typically, the components may be disposed on one or both sides 2340 and 2342. Specifically, any suitable number of components of the IC device assembly 2300 may include any one of the one or more IC devices that implement a 3D floating memory according to any embodiment disclosed herein; for example, any IC package discussed below with reference to the IC device assembly 2300 may take the form described above with reference to the IC package. Fig.10 A form of any of the embodiments of IC package 2200 discussed (eg, may include one or more IC devices implementing a 3D floating body memory provided on die 2256).

[0076] In some embodiments, circuit board 2302 may be a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 2302 (optionally in combination with other metal layers). In other embodiments, circuit board 2302 may be a non-PCB substrate.

[0077] Fig.11 The illustrated IC device assembly 2300 includes a package-on-interposer structure 2336 coupled to a first side 2340 of a circuit board 2302 via a coupling component 2316. The coupling component 2316 can electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and can include solder balls (e.g., Fig.11 as shown), male and female portions of the socket, adhesive, bottom fill material and / or any other suitable electrical and / or mechanical coupling structure.

[0078] The package-on-interposer structure 2336 may include an IC package 2320 coupled to the interposer 2304 via a coupling component 2318. The coupling component 2318 may take any form suitable for the application, such as the forms discussed above with reference to the coupling component 2316. The IC package 2320 may be or include, for example, a die ( Fig. 9 2002), IC device, or any other suitable component. Specifically, IC package 2320 may include one or more IC devices that implement a 3D floating memory as described herein. Fig.11 A single IC package 2320 is shown in the figure, but multiple IC packages can be coupled to the interposer 2304; in fact, additional interposers can be coupled to the interposer 2304. The interposer 2304 can provide an intermediate substrate for bridging the circuit board 2302 and the IC package 2320. In general, the interposer 2304 can extend the connection to a wider spacing or reroute the connection to a different connection. For example, the interposer 2304 can couple the IC package 2320 (e.g., a die) to the BGA of the coupling component 2316 for coupling to the circuit board 2302. Fig.11 In the illustrated embodiment, IC package 2320 and circuit board 2302 are attached to opposite sides of interposer 2304; in other embodiments, IC package 2320 and circuit board 2302 can be attached to the same side of interposer 2304. In some embodiments, three or more components can be interconnected through interposer 2304.

[0079] The interposer 2304 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of alternative rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to through-silicon vias (TSVs) 2306. The interposer 2304 may also include embedded devices 2314, including both passive and active devices. These devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the interposer 2304. Package-on-interposer structure 2336 may take the form of any package-on-interposer structure known in the art.

[0080] IC device assembly 2300 may include an IC package 2324 coupled to first side 2340 of circuit board 2302 via coupling component 2322. Coupling component 2322 may take the form of any of the embodiments discussed above with reference to coupling component 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0081] Fig.11 The illustrated IC device assembly 2300 includes a package-on-package structure 2334 coupled to the second side 2342 of the circuit board 2302 via a coupling component 2328. The package-on-package structure 2334 may include an IC package 2326 and an IC package 2332 coupled together via a coupling component 2330, such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of any embodiment of the coupling component 2316 discussed above, and the IC packages 2326 and 2332 may take the form of any embodiment of the IC package 2320 discussed above. The package-on-package structure 2334 may be configured according to any package-on-package structure known in the art.

[0082] Fig.12 2400, which may include one or more components including a 3D floating body memory according to any of the embodiments disclosed herein. For example, any suitable number of components of the computing device 2400 may include a die having one or more IC devices implementing a 3D floating body memory as described herein (e.g., Fig. 9 Any one or more components of computing device 2400 may include Fig.10 IC package 2200 or Fig.11 The IC device 2300 or is included in Fig.10 IC package 2200 or Fig.11 In the IC device 2300.

[0083] Multiple parts in Fig.12 2400, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured on a single SoC die.

[0084] Additionally, in various embodiments, computing device 2400 may not include Fig.122400 may include one or more components shown, but the computing device 2400 may include interface circuitry for coupling to the one or more components. For example, the computing device 2400 may not include the display device 2412, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 2412 may be coupled. In another set of examples, the computing device 2400 may not include the audio input device 2416 or the audio output device 2414, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which the audio input device 2416 or the audio output device 2414 may be coupled.

[0085] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. The memory may be used as a cache memory and may include embedded DRAM (eDRAM) or spin transfer torque magnetic RAM (MRAM). In some embodiments, memory 2404 may include one or more IC devices that implement a 3D floating memory as described herein, for example, any of IC devices 400, 500, 600, 700, or 800, or any combination of such IC devices, and / or any IC device that implements array 200 or 300 as disclosed herein.

[0086] In some embodiments, computing device 2400 may include a communication chip 2406 (e.g., one or more communication chips). For example, communication chip 2406 may be configured to manage wireless communications to transmit data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not mean that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0087] The communication chip 2406 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 1402.11 series), IEEE 1402.16 standards (e.g., IEEE 1402.16-2005 amendments), Long Term Evolution (LTE) projects and any amendments, updates and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). IEEE 1402.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, which is an acronym standing for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed the IEEE 1402.16 standard conformance and interoperability testing. The communication chip 2406 can operate according to the Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA) or LTE networks. The communication chip 2406 may operate in accordance with Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2406 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. In other embodiments, the communication chip 2406 may operate in accordance with other wireless protocols. The computing device 2400 may include an antenna 2408 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0088] In some embodiments, the communication chip 2406 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2406 can include multiple communication chips. For example, the first communication chip 2406 can be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and the second communication chip 2406 can be dedicated to long-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication chip 2406 can be dedicated to wireless communications, and the second communication chip 2406 can be dedicated to wired communications.

[0089] The computing device 2400 may include a battery / power circuit 2410. The battery / power circuit 2410 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).

[0090] Computing device 2400 may include a display device 2412 (or corresponding interface circuitry, as discussed above). For example, display device 2412 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0091] Computing device 2400 may include audio output device 2414 (or corresponding interface circuitry, as discussed above). For example, audio output device 2414 may include any device that generates an audible indicator, such as a speaker, headphones, or earphones.

[0092] Computing device 2400 may include audio input device 2416 (or corresponding interface circuitry, as discussed above). Audio input device 2416 may include any device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0093] Computing device 2400 may include other output devices 2418 (or corresponding interface circuitry, as discussed above). Examples of other output devices 2418 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0094] The computing device 2400 may include other input devices 2420 (or corresponding interface circuitry, as discussed above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device (e.g., a mouse), a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0095] The computing device 2400 may include a GPS device 2422 (or corresponding interface circuitry, as discussed above). As is known in the art, the GPS device 2422 may communicate with a satellite-based system and may receive the location of the computing device 2400.

[0096] The computing device 2400 may include a security interface device 2424. The security interface device 2424 may include any device that provides security features for the computing device 2400 or any individual component therein (e.g., for the processing device 2402 or for the memory 2404). Examples of security features may include authorization, access to digital certificates, access to items in a keychain, etc. Examples of the security interface device 2424 may include a software firewall, a hardware firewall, anti-virus software, a content filtering device, or an intrusion detection device.

[0097] In some embodiments, computing device 2400 may include a temperature detection device 2426 and a temperature regulation device 2428 .

[0098] The temperature detection device 2426 may include any device capable of determining the temperature of the computing device 2400 or any individual component thereof (e.g., the temperature of the processing device 2402 or the memory 2404). In various embodiments, the temperature detection device 2426 may be configured to determine the temperature of an object (e.g., the computing device 2400, a component of the computing device 2400, a device coupled to the computing device, etc.), the temperature of an environment (e.g., a data center including the computing device 2400, controlled by the computing device 2400, or otherwise associated with the computing device 2400), and the like. The temperature detection device 2426 may include one or more temperature sensors. Different temperature sensors of the temperature detection device 2426 may have different locations within and around the computing device 2400. The temperature sensor may generate data (e.g., digital data) representing the detected temperature and provide the data to another device, for example, to the temperature regulation device 2428, the processing device 2402, the memory 2404, and the like. In some embodiments, the temperature sensor of the temperature detection device 2426 may be turned on or off, for example, by the processing device 2402 or an external system. The temperature sensor detects temperature when turned on and does not detect temperature when turned off. In other embodiments, the temperature sensor of the temperature detection device 2426 can detect temperature continuously and automatically, or detect temperature at a predefined time or at a time triggered by an event associated with the computing device 2400 or any component therein.

[0099] The temperature regulating device 2428 may include any device configured to change (e.g., reduce) the temperature, for example, based on one or more target temperatures and / or based on temperature measurements performed by the temperature detection device 2426. The target temperature may be a preferred temperature. The target temperature may depend on the setting in which the computing device 2400 operates. In some embodiments, the target temperature may be 200 degrees Kelvin or less. In some embodiments, the target temperature may be 20 degrees Kelvin or less, or 5 degrees Kelvin or less. The target temperatures of different objects and different environments of or associated with the computing device 2400 may be different. In some embodiments, the cooling provided by the temperature regulating device 2428 may be a multi-stage process with a temperature range from room temperature to 4K or less.

[0100] In some embodiments, the temperature adjustment device 2428 may include one or more cooling devices. Different cooling devices may have different locations in and around the computing device 2400. The cooling device of the temperature adjustment device 2428 may be associated with one or more temperature sensors of the temperature detection device 2426, and may be configured to operate based on the temperature detected by the temperature sensor. For example, the cooling device may be configured to determine whether the detected ambient temperature is higher than the target temperature, or whether the detected ambient temperature is higher than the target temperature by a predetermined value, or whether any other temperature-related conditions associated with the temperature of the computing device 2400 are met. In response to determining that one or more temperature-related conditions associated with the temperature of the computing device 2400 are met (for example, in response to determining that the detected ambient temperature is higher than the target temperature), the cooling device may trigger its cooling mechanism and begin to reduce the ambient temperature. Otherwise, the cooling device will not trigger any cooling. The cooling device of the temperature adjustment device 2428 may operate with various cooling mechanisms, such as evaporative cooling, radiative cooling, conductive cooling, convection cooling, other cooling mechanisms, or any combination thereof. The cooling device of the temperature adjustment device 2428 may include a coolant, such as water, oil, liquid nitrogen, liquid helium, etc. In some embodiments, the temperature regulating device 2428 can be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator. In some embodiments, the temperature regulating device 2428 or any portion thereof (e.g., one or more separate cooling devices) can be connected very closely (e.g., less than about 1 meter) to the computing device 2400, or can be provided in a separate housing in which a dedicated heat exchanger (e.g., a compressor, a heating, ventilation, and air conditioning (HVAC) system, liquid helium, liquid nitrogen, etc.) can reside.

[0101] By maintaining the target temperature, the energy consumption of the computing device 2400 (or its components) can be reduced, and computing efficiency can be improved. For example, when the computing device 2400 (or its components) is operated at a lower temperature, energy dissipation (e.g., heat dissipation) can be reduced. In addition, the energy consumed by the semiconductor components (e.g., the energy required to switch the transistors of any component of the computing device 2400) can also be reduced. Various semiconductor materials can have lower resistivity and / or higher mobility at lower temperatures. In this way, the current per unit power supply voltage can be increased by reducing the temperature. Conversely, for the same current that will be required, the power supply voltage can be reduced by reducing the temperature. Since energy is related to the power supply voltage, the energy consumption of the semiconductor components can also be reduced. In some implementations, the energy saved due to reducing heat dissipation and reducing the energy consumed by the semiconductor components of the computing device or its components may exceed (sometimes significantly exceed) the cost associated with the energy required for cooling.

[0102] The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

[0103] Fig.13 2500, which may include one or more components including a 3D floating body memory according to any of the embodiments disclosed herein. For example, any suitable number of components of the processing device 2500 may include a die having one or more IC devices implementing a 3D floating body memory as described herein (e.g., Fig. 9 Any one or more components of the processing device 2500 may include the IC device 2300 ( Fig.11 ) or is included in the IC device 2300 ( Fig.11 Any one or more components of the processing device 2500 may include Fig.10 IC package 2200 or Fig.11 The IC device 2300 or is included in Fig.10 IC package 2200 or Fig.11 Any one or more components of the processing device 2500 may include Fig.12 The computing device 2400 or is included in Fig.12In the computing device 2400; for example, the processing device 2500 can be the processing device 2402 of the computing device 2400.

[0104] Multiple parts in Fig.13 2500, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the processing device 2500 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single SoC die or coupled to a single support structure, such as a single carrier substrate.

[0105] Additionally, in various embodiments, the processing device 2500 may not include Fig.13 The processing device 2500 may include one or more components shown, but the processing device 2500 may include interface circuits for coupling to the one or more components. For example, the processing device 2500 may not include the memory 2504, but may include display device interface circuits (e.g., connectors and driver circuits) to which the memory 2504 may be coupled.

[0106] Processing device 2500 may include logic circuitry 2502 (eg, one or more circuits configured to implement logic / computational functions). Examples of such circuitry include ICs that implement one or more of input / output (I / O) functions, arithmetic operations, data pipelining, and the like.

[0107] In some embodiments, logic circuit 2502 may include one or more circuits responsible for reading / writing data stored in memory 2504. To this end, logic circuit 2502 may include one or more I / O ICs configured to control access to data stored in memory 2504.

[0108] In some embodiments, the logic circuit 2502 may include one or more high-performance computing dies configured to perform various operations on the data stored in the memory 2504 (e.g., arithmetic and logic operations, pipelining of data from one or more memory dies of the memory 2504, and possibly pipelining of data from external devices / chips). In some embodiments, the logic circuit 2502 may be configured to only control I / O access to the data, but not perform any operations on the data. In some embodiments, the logic circuit 2502 may implement an IC configured to implement I / O control of the data stored in the memory 2504, assemble data from the memory 2504 for transmission (e.g., transmission via a central bus) to a device / chip inside or outside the processing device 2500, etc. In some embodiments, the logic circuit 2502 may not be configured to perform any operations on the data other than I / O and assembly for transmission to the memory 2504.

[0109] Processing device 2500 may include memory 2504, which may include one or more ICs configured to implement memory circuits (e.g., ICs implementing one or more of a memory device, a memory array, control logic configured to control the memory device and array, etc.). In some embodiments, memory 2504 may be substantially as described above with reference to memory 2404 ( Fig.12 ). In some embodiments, memory 2504 may be a designated device configured to provide storage functions (e.g., local) for components of processing device 2500, while memory 1604 may be configured to provide system-level storage functions (e.g., global) for the entire computing device 2400. In some embodiments, memory 2504 may include a memory that shares a die with logic circuit 2502. In some embodiments, memory 2504 may include one or more IC devices that implement a 3D floating body memory as described herein, for example, any of IC devices 400, 500, 600, 700, or 800, or any combination of such IC devices, and / or any IC device that implements array 200 or 300 as disclosed herein.

[0110] In some embodiments, memory 2504 may include flat memory (sometimes also referred to as "flat hierarchy memory" or "linear memory"), and therefore may also be referred to as "basin memory". As is known in the art, flat memory or linear memory refers to a memory addressing paradigm in which memory may appear to a program as a single continuous address space in which the processor may directly and linearly address all available memory locations without having to resort to memory segmentation or paging schemes. Thus, the memory implemented in memory 2504 may be a memory that is not divided into hierarchical layers or levels with respect to access to its data.

[0111] In some embodiments, memory 2504 may include hierarchical memory. In this context, hierarchical memory refers to a concept in computer architecture where computer storage is divided into levels based on memory characteristics, such as response time, complexity, capacity, performance, and control techniques. Designs for high performance may need to consider limitations of the memory hierarchy, such as the size and capabilities of each component. With hierarchical memory, each of the various memory components can be viewed as a memory hierarchy (m1, m2, ..., m3). n ), where each member m i Usually higher than the next highest member of the hierarchy m i+1 Smaller and faster. To limit the latency of higher levels, the lower levels of the hierarchical memory structure can respond by filling the buffer and then signaling to activate the transfer. For example, in some embodiments, the hierarchical memory implemented in memory 2504 can be divided into four main storage levels: 1) internal storage (e.g., processor registers and cache), 2) main memory (e.g., system RAM and controller cards), and 3) online bulk storage (e.g., secondary storage), and 4) offline bulk storage (e.g., tertiary and offline storage). However, because the number of levels in the memory hierarchy and the performance at each level have increased over time and may continue to increase in the future, this example hierarchical division only provides a non-limiting example of how memory 2504 can be arranged.

[0112] The processing device 2500 may include a communication device 2506, which may be substantially as described above with reference to the communication chip 2406 ( Fig.12 In some embodiments, the communication device 2506 may be a designated device configured to provide communication functions (e.g., local) to components of the processing device 2500, while the communication chip 2406 may be configured to provide system-level communication functions (e.g., global) to the entire computing device 2400.

[0113] The processing device 2500 may include an interconnect 2508, which may include any element or device including a conductive material for providing electrical connectivity to one or more components of or associated with the processing device 2500 and / or between various such components. Examples of the interconnect 2508 include conductive lines / lines (also sometimes referred to as “lines” or “metal lines” or “trench”) and conductive vias (also sometimes referred to as “vias” or “metal vias”), metallization stacks, redistribution layers, MIM structures, and the like.

[0114] The processing device 2500 may include a temperature detection device 2510, which may be substantially as described above with reference to Fig.12 The temperature sensing device 2426 may be implemented as described above, but is configured to determine temperature on a more local scale, such as the temperature of a component of the processing device 2500. In some embodiments, the temperature sensing device 2510 may be a designated device configured to provide temperature sensing functionality for a component of the processing device 2500 (e.g., local), while the temperature sensing device 2426 may be configured to provide system-level temperature sensing functionality for the entire computing device 2400 (e.g., global).

[0115] The processing device 2500 may include a temperature regulating device 2512, which may be substantially as described above with reference to Fig.12 2500, but is configured to regulate temperature on a more local scale, e.g., the temperature of a component of processing device 2500. In some embodiments, temperature regulation device 2512 may be a designated device configured to provide temperature regulation functionality for a component of processing device 2500 (e.g., local), while temperature regulation device 2428 may be configured to provide system-level temperature regulation functionality for the entire computing device 2400 (e.g., global).

[0116] The processing device 2500 may include a battery / power circuit 2514, which may be substantially as described above with reference to Fig.12 In some embodiments, the battery / power circuit 2514 may be a designated device configured to provide battery / power functions (e.g., local) for components of the processing device 2500, while the battery / power circuit 2410 may be configured to provide system-level battery / power functions (e.g., global) for the entire computing device 2400.

[0117] The processing device 2500 may include a hardware security device 2516, which may be substantially as described above with reference to Fig.12The hardware security device 2516 may be implemented as described in the security interface device 2424 of the embodiment of the present invention. In some embodiments, the hardware security device 2516 may be a physical computing device configured to protect and manage digital keys, perform encryption and decryption functions of digital signatures, authentication and other cryptographic functions. In some embodiments, the hardware security device 2516 may include one or more secure cryptographic processor chips.

[0118] The following paragraphs provide various examples of the embodiments disclosed herein.

[0119] Example 1 provides an IC device including a support structure (e.g., a substrate, a wafer, a die, or a chip) and a floating memory cell on the support structure, the floating memory cell including a transistor having a first region, a second region, and a gate on a channel portion between the first region and the second region, wherein one of the first region and the second region is a source region, and the other of the first region and the second region is a drain region. The IC device also includes a bit line coupled (e.g., directly connected) to the first region and parallel to a first axis of a Cartesian coordinate system; a select line coupled (e.g., directly connected) to the second region and parallel to a second axis of the coordinate system; and a word line coupled (e.g., directly connected) to the gate or a portion of the gate and parallel to a third axis of the coordinate system.

[0120] Example 2 provides an IC device according to Example 1, wherein the floating memory cell is a first floating memory cell among a plurality of floating memory cells, the IC device also includes a second floating memory cell, the word line is also coupled (e.g., directly connected) to a gate of a transistor of the second floating memory cell or is a portion thereof, and the transistor of the second floating memory cell is stacked above the transistor of the first floating memory cell.

[0121] Example 3 provides an IC device according to Example 2, further including: an insulator material above a support structure; an opening extending through the insulator material toward the support structure; and a channel material in the sidewalls of the opening, wherein the channel region of the transistor of the first floating memory cell is a first portion of the channel material, and the channel region of the transistor of the second floating memory cell is a second portion of the channel material.

[0122] Example 4 provides the IC device according to Example 3, wherein the second portion and the first portion are materially contiguous portions of the channel material.

[0123] Example 5 provides the IC device according to Example 3 or 4, wherein the opening is a through-hole substantially perpendicular to the support structure.

[0124] Example 6 provides the IC device of any of Examples 3-5, further comprising a conductive material in the opening, wherein the conductive material in the opening is part of a word line.

[0125] Example 7 provides the IC device of Example 6, further comprising a gate dielectric in the opening, wherein the gate dielectric is located between the conductive material and the channel material in the opening.

[0126] Example 8 provides an IC device according to Example 6 or 7, wherein the opening is a first opening, the conductive material is a first conductive material, the word line is a first word line, and the IC device also includes a second word line, a third floating memory cell and a second opening extending through the insulating material to the support structure, the second opening includes a second conductive material, wherein the bit line is also coupled (e.g., directly connected) to the source region or drain region of the transistor of the third floating memory cell, the second conductive material in the second opening is part of the second word line, and the second word line is coupled (e.g., directly connected) to the gate of the transistor of the third floating memory cell or is part of it.

[0127] Example 9 provides an IC device comprising an insulator material over a support structure (e.g., a substrate, wafer, die, or chip); a first opening extending through the insulator material toward the support structure and having a first channel material on sidewalls of the first opening; a second opening extending through the insulator material toward the support structure and having a second channel material on sidewalls of the second opening; a first transistor having a channel region in a first portion of the first channel material; a second transistor having a channel region in a second portion of the first channel material, the second portion being farther away from the support structure than the first portion; and a third transistor having a channel region in a portion of the second channel material, wherein a first source or drain (S / D) region of the first transistor is coupled (e.g., directly connected) to a first control line, a first S / D region of the second transistor is coupled (e.g., directly connected) to a second control line, a first S / D region of the third transistor is coupled (e.g., directly connected) to a third control line, and a second S / D region of the first transistor, a second S / D region of the second transistor, and a second S / D region of the third transistor are coupled (e.g., directly connected) to a fourth control line.

[0128] Example 10 provides an IC device according to Example 9, wherein the first opening is at least partially filled with a first conductive material, the second opening is at least partially filled with a second conductive material, the first conductive material is part of a gate stack of a first transistor and part of a gate stack of a second transistor, and the second conductive material is part of a gate stack of a third transistor.

[0129] Example 11 provides the IC device according to Example 10, wherein the first conductive material in the first opening is a fifth control line, and the second conductive material in the second opening is a sixth control line.

[0130] Example 12 provides the IC device according to Example 11, wherein the fifth control line and the sixth control line are substantially perpendicular to the support structure.

[0131] Example 13 provides the IC device of any of Examples 9-12, wherein the first control line, the second control line, and the third control line are substantially parallel to each other and to the support structure.

[0132] Example 14 provides the IC device according to Example 13, wherein the fourth control line is substantially perpendicular to the first control line and substantially parallel to the support structure.

[0133] Example 15 provides the IC device of any of Examples 9-14, wherein the first control line and the fourth control line are substantially perpendicular to the first opening and substantially perpendicular to each other.

[0134] Example 16 provides the IC device of any of Examples 9-15, wherein the first transistor is a first floating body memory cell, the second transistor is a second floating body memory cell, and the third transistor is a third floating body memory cell.

[0135] Example 17 provides an IC device comprising a support structure (e.g., a substrate, a wafer, a die, or a chip); a semiconductor material in a layer substantially parallel to the support structure; first, second, third, and fourth transistors having channel regions in different portions of the semiconductor material; first, second, third, and fourth control lines (e.g., corresponding WLs) coupled (e.g., directly connected) to gates of the first, second, third, and fourth transistors, respectively; a fifth control line (e.g., a shared BL) coupled (e.g., directly connected) to a first region of each of the first, second, third, and fourth transistors; and a sixth control line (e.g., a shared SL) coupled (e.g., directly connected) to a second region of each of the first, second, third, and fourth transistors, wherein one of the first region and the second region is a source region and the other of the first region and the second region is a drain region.

[0136] Example 18 provides the IC device according to Example 17, wherein the first, second, third, and fourth control lines are substantially parallel to each other and to the support structure.

[0137] Example 19 provides the IC device of Example 17 or 18, wherein the fifth and sixth control lines are substantially parallel to each other and to the support structure, and substantially perpendicular to the first control line.

[0138] Example 20 provides the IC device of any of Examples 17-19, wherein the fifth control line is closer to the support structure than the semiconductor material, and the semiconductor material is closer to the support structure than the sixth control line.

[0139] Example 21 provides an IC package comprising: an IC die including an IC device; and further components coupled to the IC die, wherein the IC device is an IC device according to any of the preceding examples.

[0140] Example 22 provides the IC package of Example 21, wherein the additional component is one of a package substrate, an interposer, or an additional IC die.

[0141] Example 23 provides an electronic device comprising: a carrier substrate; and one or more IC devices according to any of the preceding examples and / or an IC package according to any of the preceding examples coupled to the carrier substrate.

[0142] Example 24 provides an electronic device according to Example 23, wherein the carrier substrate is a motherboard.

[0143] Example 25 provides an electronic device according to Example 23, wherein the carrier substrate is a PCB.

[0144] Example 26 provides an electronic device according to any one of Examples 23-25, wherein the electronic device is a wearable electronic device (e.g., a smart watch) or a handheld electronic device (e.g., a mobile phone).

[0145] Example 27 provides an electronic device according to any one of Examples 23-26, wherein the electronic device further comprises one or more communication chips and an antenna.

[0146] Example 28 provides an electronic device according to any of Examples 23-27, wherein the electronic device is a memory device.

[0147] Example 29 provides an electronic device according to any one of Examples 23-27, wherein the electronic device is one of an RF transceiver, a switch, a power amplifier, a low noise amplifier, a filter, a filter bank, a duplexer, an upconverter, or a downconverter of an RF communication device (e.g., an RF transceiver).

[0148] Example 30 provides an electronic device according to any of Examples 23-27, wherein the electronic device is a computing device.

[0149] Example 31 provides an electronic device according to any one of Examples 23-30, wherein the electronic device is included in a base station of a wireless communication system.

[0150] Example 32 provides an electronic device according to any one of Examples 23-30, wherein the electronic device is included in a user equipment device (ie, a mobile device) of a wireless communication system.

[0151] The above description of the implementations illustrated in the present disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Although specific implementations and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure as will be appreciated by those skilled in the relevant art. These modifications may be made to the present disclosure in light of the above detailed description.

Claims

1. An integrated circuit (IC) device, comprising: a floating body memory cell comprising a transistor having a first region, a second region, and a gate over a channel portion between the first region and the second region, wherein one of the first region and the second region is a source region and the other of the first region and the second region is a drain region; a bit line coupled to the first region and parallel to a first axis of the coordinate system; a selection line coupled to the second region and parallel to a second axis of the coordinate system; and A word line is coupled to the gate or is a part of the gate and is parallel to the third axis of the coordinate system.

2. An IC device according to claim 1, wherein the floating memory cell is a first floating memory cell among a plurality of floating memory cells, the IC device further comprises a second floating memory cell, the word line is also coupled to or is a portion of a gate of a transistor of the second floating memory cell, and the transistor of the second floating memory cell is stacked above the transistor of the first floating memory cell.

3. The IC device according to claim 2, further comprising: Support structure; Insulator material on the support structure; an opening extending through the insulator material toward the support structure; as well as The channel material in the sidewalls of the opening, Wherein a channel region of a transistor of a first floating body memory cell is a first portion of a channel material, and a channel region of a transistor of a second floating body memory cell is a second portion of a channel material. The IC device of claim 3 , wherein the second portion and the first portion are materially continuous portions of the channel material.

5. The IC device of claim 3, wherein the opening is a through hole substantially perpendicular to the support structure.

6. The IC device of any one of claims 3-5, further comprising a conductive material in the opening, wherein the conductive material in the opening is a portion of a word line. 7 . The IC device of claim 6 , further comprising a gate dielectric in the opening, wherein the gate dielectric is located between the conductive material in the opening and the channel material.

8. The IC device of claim 6, wherein the opening is a first opening, the conductive material is a first conductive material, the word line is a first word line, and the IC device further comprises a second word line, a third floating body memory cell, and a second opening extending through the insulator material toward the support structure, the second opening comprising a second conductive material, wherein: The bit line is also coupled to a source region or a drain region of a transistor of a third floating body memory cell, The second conductive material in the second opening is part of a second word line, and The second word line is coupled to or is a portion of a gate of a transistor of a third floating body memory cell.

9. An integrated circuit (IC) device comprising: an insulator material on the substrate; a first opening extending through the insulator material toward the substrate and having a first channel material on sidewalls of the first opening; a second opening extending through the insulator material toward the substrate and having a second channel material on sidewalls of the second opening; a first transistor having a channel region in a first portion of a first channel material; a second transistor having a channel region in a second portion of the first channel material, the second portion being further away from the substrate than the first portion; as well as a third transistor having a channel region in a portion of the second channel material, Wherein a first source or drain (S / D) region of the first transistor is coupled to a first control line, a first S / D region of the second transistor is coupled to a second control line, a first S / D region of the third transistor is coupled to a third control line, and a second S / D region of the first transistor, a second S / D region of the second transistor, and a second S / D region of the third transistor are coupled to a fourth control line.

10. The IC device of claim 9, wherein the first opening is at least partially filled with a first conductive material, the second opening is at least partially filled with a second conductive material, the first conductive material is part of a gate stack of a first transistor and part of a gate stack of a second transistor, and the second conductive material is part of a gate stack of a third transistor. 11 . The IC device of claim 10 , wherein the first conductive material in the first opening is a fifth control line, and the second conductive material in the second opening is a sixth control line.

12. The IC device of claim 11, wherein the fifth control line and the sixth control line are substantially perpendicular to the substrate.

13. The IC device of any one of claims 9-12, wherein the first control line, the second control line, and the third control line are substantially parallel to each other and to the substrate.

14. The IC device of claim 13, wherein the fourth control line is substantially perpendicular to the first control line and substantially parallel to the substrate.

15. The IC device of any one of claims 9 to 12, wherein the first control line and the fourth control line are substantially perpendicular to the first opening and substantially perpendicular to each other.

16. The IC device of any of claims 9-12, wherein the first transistor is a first floating body memory cell, the second transistor is a second floating body memory cell, and the third transistor is a third floating body memory cell.

17. An integrated circuit (IC) device comprising: Die; semiconductor material in a layer substantially parallel to the die; first, second, third and fourth transistors having channel regions in different portions of the semiconductor material; first, second, third and fourth control lines coupled to the gates of the first, second, third and fourth transistors, respectively; a fifth control line coupled to the first region of each of the first, second, third, and fourth transistors; as well as A sixth control line is coupled to a second region of each of the first, second, third, and fourth transistors, wherein one of the first and second regions is a source region and the other of the first and second regions is a drain region.

18. The IC device of claim 17, wherein the first, second, third, and fourth control lines are substantially parallel to each other and to the die.

19. The IC device of claim 17 or 18, wherein the fifth and sixth control lines are substantially parallel to each other and to the die, and substantially perpendicular to the first control line.

20. The IC device of claim 17 or 18, wherein the fifth control line is closer to the die than the semiconductor material, and the semiconductor material is closer to the die than the sixth control line.

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