Semiconductor memory device and semiconductor memory apparatus

Abstract

The application provides a semiconductor memory device and a semiconductor storage device, and relates to the technical field of semiconductors. The semiconductor memory device comprises a substrate, a capacitor structure, a semiconductor conductive layer, a cover layer and a plurality of voids; the capacitor structure is arranged on the substrate; the capacitor structure comprises a plurality of capacitors; the semiconductor conductive layer comprises a first part and a second part, the first part covers the capacitor structure and directly contacts the capacitor structure; the second part is filled between adjacent capacitors; the cover layer is located on the first part and directly contacts the first part; the surface of the cover layer towards the semiconductor conductive layer has a relief surface profile, the surface profile has a wave crest and a wave trough, and the first part extends into the wave trough; at least one void is located in the first part in the wave trough. The application can reduce or even avoid delamination between the semiconductor conductive layer and the cover layer, and improves the performance of the semiconductor memory device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a semiconductor memory device and a semiconductor memory apparatus. BACKGROUND

[0002] With the continuous development of semiconductor technology, the application of semiconductor memory devices, such as dynamic random access memory (DRAM) or static random access memory (SRAM), is more and more widely, and has been widely applied in the fields of computers, communications and the like.

[0003] In the related art, the laminated film layer of the semiconductor memory device is prone to delamination or fracture, which reduces the performance of the semiconductor memory device. SUMMARY

[0004] In view of the above problems, the present application provides a semiconductor memory device and a semiconductor memory apparatus, which can reduce or even avoid delamination between the semiconductor conductive layer and the cap layer, and improve the performance of the semiconductor memory device.

[0005] In order to achieve the above purpose, the embodiments of the present application provide the following technical solutions:

[0006] The first aspect of the embodiments of the present application provides a semiconductor memory device, which comprises:

[0007] a substrate;

[0008] a capacitor structure, the capacitor structure being arranged on the substrate; the capacitor structure comprising a plurality of capacitors;

[0009] a semiconductor conductive layer, the semiconductor conductive layer comprising a first part and a second part, the first part covering the capacitor structure and directly contacting the capacitor structure; the second part being filled between adjacent capacitors;

[0010] a cap layer, the cap layer being located on the first part and directly contacting the first part; wherein the surface of the cap layer towards the semiconductor conductive layer has a relief surface profile, the surface profile having a wave crest and a wave trough, the first part extending into the wave trough; the material of the cap layer being different from the material of the semiconductor conductive layer;

[0011] a plurality of voids, the plurality of voids being arranged in the first part in a spaced manner, and at least one void being located in the first part in the wave trough.

[0012] In a possible implementation, the at least one gap is located between the adjacent wave peak and the surface of the cap layer away from the substrate.

[0013] In a possible implementation, the at least one gap has a minimum distance D1 between the top surface of the cap layer away from the substrate and the capacitor structure.

[0014] The distance between two adjacent capacitors in the capacitor structure is D2; the D1 is greater than the D2.

[0015] In a possible implementation, the plurality of gaps includes a first gap, a second gap and a third gap, and the third gap is located in the first part of the wave valley.

[0016] In the first direction, the first gap is located on one side of the third gap, and the second gap is located on the other side of the third gap.

[0017] The first gap has a first distance D3 with the third gap, and the second gap has a second distance D4 with the third gap; the first distance D3 is less than or equal to the second distance D4.

[0018] In a possible implementation, the width of the gap gradually decreases in the direction of the semiconductor conductive layer of the cap layer.

[0019] In a possible implementation, the longitudinal section shape of the gap is a taper or a trapezoid in the longitudinal section perpendicular to the substrate.

[0020] In a possible implementation, the longitudinal section shape of the gap is a semicircle or an arc in the longitudinal section perpendicular to the substrate.

[0021] In a possible implementation, the material of the semiconductor conductive layer includes silicon germanium.

[0022] In a possible implementation, the material of the cap layer is an insulating material; the insulating material is selected from at least one of HDP oxide, TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ, silicon nitride and silicon oxynitride.

[0023] In a possible implementation, the material of the cap layer is a conductive material; the conductive material is selected from at least one of tungsten, titanium nitride and tungsten nitride.

[0024] In a possible implementation, the capacitor includes a first electrode plate, a second electrode plate and a dielectric layer between the first electrode plate and the second electrode plate.

[0025] The semiconductor conductive layer is disposed on the second electrode plate.

[0026] A second aspect of the embodiments of the present application provides a semiconductor storage device, comprising: a semiconductor storage device including a package and the first aspect; and the package encapsulating the semiconductor storage device.

[0027] The semiconductor storage device and the semiconductor storage device provided by the embodiments of the present application have a plurality of gaps between the semiconductor conductive layer and the cover layer, and the plurality of gaps can block the transmission of stress generated in the shrinkage or expansion process of the semiconductor conductive layer and / or the cover layer, so as to avoid stress concentration at the interface between the semiconductor conductive layer and the cover layer, and further avoid delamination of the semiconductor conductive layer and the cover layer, thereby improving the performance of the semiconductor storage device.

[0028] The surface of the cover layer facing the semiconductor conductive layer has a wavy surface profile, and the surface profile has a wave crest and a wave trough. The first part extends into the wave trough, so that the first part is embedded with the cover layer, and the bonding strength of the cover layer and the semiconductor conductive layer can be improved. In addition, the part of the first part extending into the wave trough forms a sharp part, where the stress is the largest. Therefore, the at least one gap is located in the first part in the wave trough, so as to avoid stress concentration at the interface between the semiconductor conductive layer and the cover layer as much as possible.

[0029] In addition to the technical problems solved by the embodiments of the present application described above, the technical features constituting the technical solutions, and the beneficial effects brought by these technical features, other technical problems solved by the semiconductor storage device and the semiconductor storage device provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought by these technical features will be further described in detail in the specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without any creative labor.

[0031] Figure 1 The structure schematic diagram of the semiconductor storage device provided by the embodiments of the present application;

[0032] Figure 2 The schematic diagram of forming the capacitor contact structure in the preparation process of the semiconductor storage device provided by the embodiments of the present application;

[0033] Figure 3A schematic view of forming a support structure in a preparation process of a semiconductor memory device provided by an embodiment of the present application;

[0034] Figure 4 A schematic view of forming a capacitor hole in a preparation process of a semiconductor memory device provided by an embodiment of the present application;

[0035] Figure 5 A schematic view of forming a first electrode plate in a preparation process of a semiconductor memory device provided by an embodiment of the present application;

[0036] Figure 6 A schematic view of forming a photoresist layer in a preparation process of a semiconductor memory device provided by an embodiment of the present application;

[0037] Figure 7 A schematic view of removing part of a support structure in a preparation process of a semiconductor memory device provided by an embodiment of the present application;

[0038] Figure 8 A schematic view of forming a dielectric layer in a preparation process of a semiconductor memory device provided by an embodiment of the present application;

[0039] Figure 9 A schematic view of forming a second electrode plate in a preparation process of a semiconductor memory device provided by an embodiment of the present application Figure 1 ;

[0040] Figure 10 A schematic view of forming a second electrode plate in a preparation process of a semiconductor memory device provided by an embodiment of the present application Figure 2 ;

[0041] Figure 11 A schematic view of forming a semiconductor conductive layer in a preparation process of a semiconductor memory device provided by an embodiment of the present application Figure 1 ;

[0042] Figure 12 A schematic view of forming a semiconductor conductive layer in a preparation process of a semiconductor memory device provided by an embodiment of the present application Figure 2 ;

[0043] Figure 13 A schematic view of forming a cover layer in a preparation process of a semiconductor memory device provided by an embodiment of the present application Figure 1 ;

[0044] Figure 14 A schematic view of forming a cover layer in a preparation process of a semiconductor memory device provided by an embodiment of the present application Figure 2 ;

[0045] Figure 15 A schematic view of forming a conductive plug in a preparation method of a semiconductor memory device provided by an embodiment of the present application Figure 1 ;

[0046] Figure 16 Schematic diagram of forming conductive plug in preparation method of semiconductor storage device provided by embodiments of the present application Figure 2 .

[0047] Explanation of reference signs:

[0048] 100: substrate;

[0049] 200: capacitor; 210: first electrode plate; 220: second electrode plate; 221: barrier layer; 222: conductive layer; 230: dielectric layer;

[0050] 300: semiconductor conductive layer; 310: first part; 320: second part;

[0051] 400: cover layer; 410: peak; 420: valley;

[0052] 500: void;

[0053] 600: capacitor contact structure;

[0054] 710: medium layer; 720: insulating layer; 730: conductive plug;

[0055] 800: support structure; 810: first support layer; 820: second support layer; 830: third support layer; 840: first sacrificial layer; 850: second sacrificial layer;

[0056] 900: photoresist layer; 910: mask opening. DETAILED DESCRIPTION

[0057] As described in the background, the laminated film layer of the semiconductor storage device in the related art is prone to delamination or fracture. The inventor has found that the reason for this problem is that the film layer expands and contracts during use of the semiconductor storage device, and the thermal expansion coefficients of the laminated film layers are different, so that the deformation degrees of the laminated film layers are also different, which further causes the laminated film layer to be prone to delamination or fracture, and reduces the performance of the semiconductor storage device.

[0058] To solve the above technical problem, embodiments of the present application provide a semiconductor storage device and a semiconductor storage apparatus, and the semiconductor conductive layer and the cover layer have a plurality of voids therebetween. The plurality of voids can block the stress transmission generated in the shrinkage or expansion process of the semiconductor conductive layer and / or the cover layer, avoid stress concentration at the interface between the semiconductor conductive layer and the cover layer, and further avoid delamination of the semiconductor conductive layer and the cover layer, thereby improving the performance of the semiconductor storage device.

[0059] The surface of the cap layer facing the semiconductor conductive layer has a surface profile with undulations, and the surface profile has wave crests and wave troughs. The first portion extends into the wave troughs, so that the first portion is embedded in the cap layer, and the bonding strength of the cap layer and the semiconductor conductive layer can be improved. In addition, the portion of the first portion extending into the wave troughs forms a sharp portion, where the stress is the largest. Therefore, the at least one void is located in the first portion in the wave troughs, so that stress concentration at the interface between the semiconductor conductive layer and the cap layer can be avoided as much as possible.

[0060] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0061] Please refer to the accompanying Figure 1 The embodiments of the present application provide a semiconductor memory device, which can be a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0062] The semiconductor memory device includes a substrate 100, which is a main bearing component of a semiconductor structure and is used to bear components arranged thereon. The substrate 100 can be any substrate suitable for manufacturing semiconductor elements, such as a silicon (Si) substrate, an epitaxial silicon (epi-Si) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto.

[0063] The semiconductor memory device further includes a capacitor structure arranged on the substrate 100. The capacitor structure includes a plurality of capacitors 200 arranged on the substrate 100 in a spaced manner. The capacitors 200 are used to store electric charges, thereby realizing the functions of storing and reading data.

[0064] Each of the capacitors 200 includes a first electrode plate 210, a second electrode plate 220, and a dielectric layer 230 disposed between the first electrode plate 210 and the second electrode plate 220 for achieving an insulating arrangement between the first electrode plate 210 and the second electrode plate 220. Among them, one of the first electrode plate 210 and the second electrode plate 220 serves as the lower electrode of the capacitor, and the other of the first electrode plate 210 and the second electrode plate 220 serves as the upper electrode of the capacitor. The following embodiments are described by taking the first electrode plate 210 as the lower electrode and the second electrode plate 220 as the upper electrode as an example.

[0065] Please continue to refer to the accompanying drawings Figure 1 The first electrode plate 210 of each of the capacitors 200 is independent of each other, and each of the first electrode plates 210 can be electrically connected to the source region or the drain region of the substrate 100 through the capacitor contact structure 600.

[0066] In the present embodiment, please refer to the accompanying drawings Figure 1 The first electrode plate 210 is a columnar body perpendicular to the substrate 100, which can increase the volume of the first electrode plate 210, thereby improving the strength of the first electrode plate 210, and further preventing the capacitors 200 from collapsing and improving the yield of the semiconductor structure.

[0067] The material of the first electrode plate 210 and the second electrode plate 220 can include conductive materials such as tungsten and titanium nitride. The material of the dielectric layer 230 can be a dielectric material with high dielectric constant, for example, the dielectric material can include at least one of ZrO x , HfO x , ZrTiO x , RuO x , SbO x , AlO x , that is, the material of the dielectric layer 230 can be selected from any one or more of the above materials, and optionally, the dielectric layer 230 can be a laminated structure, for example, the dielectric layer 230 can include a three-layer structure, and the materials of the three-layer structure are zirconium oxide-aluminum oxide-zirconium oxide, respectively.

[0068] The semiconductor memory device further includes a semiconductor conductive layer 300 and a cover layer 400. Among them, the semiconductor conductive layer 300 includes a first part 310 and a second part 320, the first part 310 covers the capacitor structure and directly contacts the capacitor structure; the second part 320 is filled between adjacent capacitors 200. Or, the semiconductor conductive layer 300 is disposed on the second electrode plate 220 and contacts and electrically connects with the second electrode plate 220 of the capacitor 200.

[0069] The cover layer 400 is arranged on the first portion 310 and directly contacts the first portion 310. The cover layer 400 has a surface profile with undulations towards the surface of the semiconductor conductive layer 300, the surface profile has wave crests 410 and wave troughs 420, and the first portion 310 extends into the wave troughs 420; or in other words, the first portion 310 also has a protruding region which can be embedded in the wave troughs 420 to improve the fit between the semiconductor conductive layer 300 and the cover layer 400.

[0070] In the embodiment, the semiconductor conductive layer 300 can be made of silicon germanium or polysilicon, and the cover layer 400 is made of an insulating material or a conductive material. In an example, the cover layer 400 is made of an insulating material, and the insulating material is selected from at least one of HDP oxide, TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ, silicon nitride, silicon oxynitride. In the example, TEOS is the abbreviation of Tetraethyl orthosilicate; USG is the abbreviation of Undoped Silicate Glass; PSG is the abbreviation of Phosphosilicate Glass; BSG is the abbreviation of Borosilicate Glass; BPSG is the abbreviation of BoroPhosphosilicate Glass; FSG is the abbreviation of Fluorinated Silicate Glass; SOG is the abbreviation of Spin-On Glass; and TOSZ is the abbreviation of Tetraorthosilicate Zirconium.

[0071] In another example, the cover layer 400 is made of a conductive material, and the conductive material is selected from at least one of tungsten, titanium nitride, and tungsten nitride.

[0072] The capacitor structure is connected to the conductive plug 730 through the semiconductor conductive layer 300, or the capacitor structure is connected to the conductive plug 730 through the semiconductor conductive layer 300 and the cover layer 400, so as to electrically connect the capacitor structure to the peripheral circuit, and then realize the storage or reading of data.

[0073] It should be understood that, please refer to the accompanying drawings Figure 1 When the cover layer 400 is an insulating material, the capacitor structure is connected to the conductive plug 730 through the semiconductor conductive layer 300; please refer to the accompanying drawings Figure 15 and the accompanying drawings Figure 16 When the cover layer 400 is a conductive material, the capacitor structure is connected to the conductive plug 730 through the semiconductor conductive layer 300 and the cover layer 400.

[0074] The semiconductor conductive layer 300 and the cover layer 400 have a large difference in the coefficient of thermal expansion, and thus the semiconductor memory device is prone to delamination or fracture during operation. Therefore, the semiconductor memory device provided in the embodiment further comprises a plurality of voids 500, and at least one void 500 is located in the first portion 310 in the trough 420. Alternatively, the plurality of voids 500 are arranged in the first portion 310, and at least one void 500 is arranged in the first portion 310 in the trough 420. The distance between any adjacent voids 500 can be equal or unequal, and the specific arrangement can be determined according to the actual situation.

[0075] In this way, the plurality of voids 500 can block the transmission of stress generated during the shrinkage or expansion of the semiconductor conductive layer 300 and / or the cover layer 400, avoid stress concentration at the interface between the semiconductor conductive layer 300 and the cover layer 400, and thus avoid delamination of the semiconductor conductive layer 300 and the cover layer 400, thereby improving the performance of the semiconductor memory device.

[0076] The surface of the cover layer 400 facing the semiconductor conductive layer 300 has a wavy surface profile, and the surface profile has a wave crest 410 and a wave trough 420. The first portion 310 extends into the wave trough 420, so that the first portion 310 is embedded in the cover layer 400, which can improve the bonding strength between the cover layer 400 and the semiconductor conductive layer 300. In addition, the portion of the first portion 310 extending into the wave trough 420 forms a sharp portion, where the stress is the largest. Therefore, at least one void 500 is located in the first portion 310 in the wave trough 420, which can avoid stress concentration at the interface between the semiconductor conductive layer 300 and the cover layer 400 as much as possible.

[0077] It should be noted that the number of voids 500 in the first portion 310 in the wave trough 420 in the embodiment can be one, two or even more. The specific arrangement needs to be determined according to the size of the first portion 310 in the wave trough 420. In addition, in addition to the at least one void 500 in the first portion 310 in the wave trough 420, the remaining voids 500 can be arranged between the semiconductor conductive layer 300 and the cover layer 400.

[0078] The plurality of voids 500 can also serve as thermal insulation components under the premise of blocking stress transmission. Since the thermal conductivity of air is much lower than that of solid materials, these voids 500 can significantly reduce the conduction of heat from the cover layer 400 to the semiconductor conductive layer 300, thereby improving the thermal stability of the entire capacitor structure, and thus improving the thermal stability of the semiconductor memory device.

[0079] In a possible implementation, the at least one gap 500 is located between the adjacent wave crest 410 and the surface of the cover layer 400 away from the substrate 100, and is close to the bottom of the substrate 100; in other words, the distance between the at least one gap 500 and the surface of the cover layer 400 away from the substrate 100 is a first distance L1, and the distance between any wave crest 410 adjacent to the at least one gap 500 and the surface of the cover layer 400 away from the substrate 100 is a second distance L2, and the first distance L1 is less than the second distance L2. In this way, the at least one gap 500 can effectively reduce the local stress concentration, and the size of the at least one gap 500 in the direction perpendicular to the cover layer 400 can be reduced, the influence of the at least one gap 500 on the conductivity of the semiconductor conductive layer 300 can be reduced, and the performance of the semiconductor memory device can be ensured.

[0080] It should be understood that the relationship between the first distance L1 and the second distance L2 is not limited to the above description. The first distance L1 can be equal to the second distance L2, and can be changed according to the performance requirements of the semiconductor memory device or the control of the process parameters.

[0081] Please continue to refer to the accompanying drawings Figure 1 The second electrode plate 220 surrounds a filling area in the dielectric layer 230, so that the semiconductor conductive layer 300 can not only cover the second electrode plate 220, but also fill in the filling area, increase the contact area of the semiconductor conductive layer 300 and the second electrode plate 220, and reduce the contact resistance of the semiconductor conductive layer 300 and the second electrode plate 220.

[0082] The at least one gap 500 has a minimum distance D1 from the top surface of the capacitor structure away from the substrate 100; that is, the at least one gap 500 has a minimum distance D1 from the top surface of the second electrode plate 220 away from the substrate 100.

[0083] The distance D2 between the adjacent two capacitors 200 in the capacitor structure; that is, the width of the filling area surrounded by the second electrode plate 220 between the adjacent first electrode plates 210 constitutes D2. It should be noted that the width in the embodiment is the size of the first direction M. Figure 1

[0084] In the embodiment, D1 is greater than D2, which can ensure that the thickness of the semiconductor conductive layer 300 located on the top surface of the capacitor structure away from the substrate 100 is greater than the thickness of the semiconductor conductive layer 300 located in the filling area. In this way, the thickness of the first part 310 can be increased, and a better heat dissipation path can be provided, which can help to reduce the heat generated in the working process of the capacitor structure, thereby improving the stability and durability of the entire capacitor structure.

[0085] ​For the convenience of describing the relative relationship between at least one gap 500 in the first part 310 in the wave trough 420 and its adjacent gap 500 in detail, the number of gaps 500 in the first part 310 in the wave trough 420 is taken as an example.

[0086] Exemplarily, the plurality of gaps 500 includes a first gap 510, a second gap 520 and a third gap 530, and the third gap 530 is located in the first part 310 in the wave trough 420. In the first direction M, the first gap 510 is located on one side of the third gap 530, and the second gap 520 is located on the other side of the third gap 530. That is, the first gap 510 and the second gap 520 are respectively located on both sides of the third gap 530 and are arranged at intervals.

[0087] The first gap 510 and the third gap 530 have a first distance D3, and the second gap 520 and the third gap 530 have a second distance D4. Wherein, the first distance D3 is less than or equal to the second distance D4.

[0088] Through reasonable layout of the first gap 510, the second gap 520 and the third gap 530, the embodiment can affect the flow path of the current in the semiconductor conductive layer 300. Through the first distance D3 being less than or equal to the second distance D4, the current in the semiconductor conductive layer 300 is more inclined to flow through the relatively narrow channel between the first gap 510 and the second gap 520, which helps to realize the uniform distribution or directional guidance of the current and improve the conductive efficiency and stability of the semiconductor storage device.

[0089] In addition, the semiconductor storage device will generate heat when working, thereby forming thermal expansion. Because the thermal expansion coefficients of the cover layer 400 and the semiconductor conductive layer 300 are different, thermal stress will be generated between the two. Through reasonable layout of the gap 500, especially by placing the third gap 530 in the wave trough 420, the stress concentration caused by the difference in thermal expansion can be reduced. At the same time, the layout of the first distance D3 being less than or equal to the second distance D4 helps to disperse these stresses and prevent local stress from being too large to cause material failure.

[0090] In a possible implementation, the width of the gap 500 gradually decreases in the direction of the cover layer 400 pointing to the semiconductor conductive layer 300. Wherein, the direction of the cover layer 400 pointing to the semiconductor conductive layer 300 is the second direction N shown in the Figure 1 The width of the gap 500 can be the size of the gap 500 in the first direction M.

[0091] The material of the cap layer 400 and the semiconductor conductive layer 300 is different, and the thermal expansion difference will occur when the temperature changes. The thermal stress is mainly concentrated at the interface between the cap layer 400 and the semiconductor conductive layer 300, so the width of the gap 500 near the interface between the two is the largest, which helps to provide a better stress buffer zone and better alleviate the stress at the interface between the cap layer 400 and the semiconductor conductive layer 300, thereby better avoiding the delamination of the cap layer 400 and the semiconductor conductive layer 300, and improving the performance of the semiconductor storage device.

[0092] In addition, along the second direction N and towards the substrate 100, the width of the gap 500 gradually decreases. This structure can effectively disperse and absorb stress when the semiconductor storage device is subjected to external factors such as temperature changes and mechanical vibrations without sacrificing overall strength, thereby avoiding damage caused by excessive local stress.

[0093] It should be understood that the shape of the gap 500 can have multiple options. In an example, the longitudinal cross-sectional shape of the gap 500 is tapered or trapezoidal in the cross section perpendicular to the substrate 100. In this way, the wider gap part can absorb more stress changes, and the narrower part can further limit stress transmission, thereby effectively alleviating the stress concentration at the interface between the cap layer 400 and the semiconductor conductive layer 300. In another example, the longitudinal cross-sectional shape of the gap 500 is semicircular or arc-shaped in the cross section perpendicular to the substrate 100. Among them, the semicircular or arc-shaped gap shape provides a smooth transition edge in the longitudinal cross section, which helps to reduce the sudden change of stress at the interface and can guide the stress to propagate along a more smooth path, reducing the possibility of stress concentration.

[0094] The longitudinal cross-sectional shape of the gap 500, whether tapered, trapezoidal, semicircular or arc-shaped, has the common characteristic that it can cleverly guide and disperse the stress between the cap layer 400 and the semiconductor conductive layer 300 due to the thermal expansion difference, thereby reducing the stress concentration at the interface. When the stress is effectively dispersed, the risk of delamination of the cap layer 400 and the semiconductor conductive layer 300 will be greatly reduced. Therefore, under the premise of being able to reduce the risk of delamination, the selectability of the longitudinal cross-sectional shape of the gap 500 can be increased.

[0095] The semiconductor memory device provided by the embodiment of the present application can further include a transistor, a word line structure and a bit line structure. For example, the substrate 100 in the embodiment already includes a semiconductor device, for example, the substrate 100 is provided with a transistor (not shown in the figure) and a word line structure (not shown in the figure), the word line structure is connected to the gate of the transistor and is used to control the opening or closing of the transistor. The transistor further includes a source and a drain. One of the source and the drain is connected to the capacitor structure, and the other is used to be connected to the bit line structure. The voltage signal on the word line structure can control the opening or closing of the transistor, and then the data information stored in the capacitor structure is read through the bit line structure, or the data information is written into the capacitor structure through the bit line structure for storage.

[0096] It should be noted that the capacitor structure in the embodiment can be connected to one of the source and the drain through the capacitor contact structure 600. In order to further describe the structure of the semiconductor memory device in detail, the following will be explained by describing the preparation method of the semiconductor memory device.

[0097] For example, the capacitor contact structure 600 is formed on the substrate 100 and is connected to one of the source and the drain. For example, please refer to the following figure. Figure 2 The dielectric layer 710 can be formed on the substrate 100 through a deposition process; then the dielectric layer 710 is patterned to form a contact hole in the dielectric layer 710, the contact hole is used to expose at least part of the source or at least part of the drain; then the conductive material is deposited in the contact hole through a deposition process to form the capacitor contact structure 600. The top surface of the capacitor contact structure 600 is flush with the top surface of the dielectric layer 710.

[0098] For example, the capacitor contact structure 600 is formed on the substrate 100 and is connected to one of the source and the drain. For example, please refer to the following figure. Figure 3 The support structure 800 is formed on the dielectric layer 710, wherein the support structure 800 is a laminated structure. For example, the support structure 800 includes a first support layer 810, a first sacrificial layer 840, a second support layer 820, a second sacrificial layer 850 and a third support layer 830 which are sequentially laminated, and the first support layer 810 is arranged on the substrate 100.

[0099] The materials of the first support layer 810, the second support layer 820 and the third support layer 830 can all include insulating materials such as silicon nitride; the materials of the first sacrificial layer 840 and the second sacrificial layer 850 can all include insulating materials such as silicon oxide.

[0100] For example, the capacitor contact structure 600 is formed on the substrate 100 and is connected to one of the source and the drain. For example, please refer to the following figure. Figure 4 The support structure 800 is patterned to form a capacitor hole 860 in the support structure 800, the capacitor hole 860 penetrates the support structure 800 along the direction perpendicular to the substrate 100, so that the capacitor hole 860 exposes the capacitor contact structure 600.

[0101] Referring to FIG. 8A, a first electrode plate 210 is formed in the capacitor hole 860 by a deposition process. The first electrode plate 210 fills the capacitor hole 860, and a top surface of the first electrode plate 210 is flush with a top surface of the support structure 800. Figure 5 Referring to FIG. 8A, a first electrode plate 210 is formed in the capacitor hole 860 by a deposition process. The first electrode plate 210 fills the capacitor hole 860, and a top surface of the first electrode plate 210 is flush with a top surface of the support structure 800.

[0102] It is noted that the capacitor hole 860 divides the support structure 800 into a plurality of columnar structures. After the first electrode plate 210 is formed, a portion of the support structure 800 needs to be removed.

[0103] Referring to FIG. 8A, a first electrode plate 210 is formed in the capacitor hole 860 by a deposition process. The first electrode plate 210 fills the capacitor hole 860, and a top surface of the first electrode plate 210 is flush with a top surface of the support structure 800. Figure 6 Referring to FIG. 8A, a first electrode plate 210 is formed in the capacitor hole 860 by a deposition process. The first electrode plate 210 fills the capacitor hole 860, and a top surface of the first electrode plate 210 is flush with a top surface of the support structure 800.

[0104] Referring to FIG. 8A, a first electrode plate 210 is formed in the capacitor hole 860 by a deposition process. The first electrode plate 210 fills the capacitor hole 860, and a top surface of the first electrode plate 210 is flush with a top surface of the support structure 800. Figure 7 Referring to FIG. 8A, a first electrode plate 210 is formed in the capacitor hole 860 by a deposition process. The first electrode plate 210 fills the capacitor hole 860, and a top surface of the first electrode plate 210 is flush with a top surface of the support structure 800.

[0105] Referring to FIG. 8A, a first electrode plate 210 is formed in the capacitor hole 860 by a deposition process. The first electrode plate 210 fills the capacitor hole 860, and a top surface of the first electrode plate 210 is flush with a top surface of the support structure 800. Figure 8 Referring to FIG. 8A, a first electrode plate 210 is formed in the capacitor hole 860 by a deposition process. The first electrode plate 210 fills the capacitor hole 860, and a top surface of the first electrode plate 210 is flush with a top surface of the support structure 800.

[0106] In an example, referring to FIG. 8A, a second electrode plate 220 is formed on the dielectric layer 230 by a deposition process. The second electrode plate 220 is a single film layer. Figure 9 In another example, referring to FIG. 8A, a barrier layer 221 and a conductive layer 222 are formed on the dielectric layer 230 by a deposition process. The barrier layer 221 and the conductive layer 222 constitute the second electrode plate 220. The material of the barrier layer 221 includes titanium nitride, and the material of the conductive layer 222 includes polysilicon.

[0107] Figure 10 The second electrode plate 220, the first electrode plate 210 in one of the capacitor holes, and the dielectric layer 230 constitute a capacitor 200. In this way, the first electrode plates 210 of the plurality of capacitors 200 are relatively independent, and each first electrode plate 210 is connected to the source or the drain of the transistor through the capacitor contact structure 600. The second electrode plate 220 connects the plurality of capacitors 200 together, facilitating electrical contact between the plurality of capacitors 200 and the semiconductor conductive layer 300.

[0108] The second electrode plate 220, the first electrode plate 210 in one of the capacitor holes, and the dielectric layer 230 constitute a capacitor 200. In this way, the first electrode plates 210 of the plurality of capacitors 200 are relatively independent, and each first electrode plate 210 is connected to the source or the drain of the transistor through the capacitor contact structure 600. The second electrode plate 220 connects the plurality of capacitors 200 together, facilitating electrical contact between the plurality of capacitors 200 and the semiconductor conductive layer 300.

[0109] ​The second electrode plate 220 is formed by a uniform deposition process, which greatly simplifies the manufacturing process, reduces the production steps and costs, compared with a process of separately manufacturing the second electrode plate 220 for each capacitor. Meanwhile, since the second electrode plate 220 is continuous, defects and variations that can be introduced due to separate manufacturing are reduced, improving the yield and reliability of the semiconductor memory device.

[0110] Please refer to the accompanying drawings Figure 11 and the accompanying drawings Figure 12 , a semiconductor conductive layer 300 is formed, the semiconductor conductive layer 300 is disposed on the second electrode plate 220 and fills the area surrounded by the second electrode plate 220; wherein the top surface of the semiconductor conductive layer 300 is higher than the top surface of the second electrode plate 220. Wherein, the area filled in the area surrounded by the second electrode plate 220 constitutes a first part 310, and the part above the support structure constitutes a second part 320. The first part 310 of the semiconductor conductive layer 300 covers the capacitor structure and directly contacts the capacitor structure;

[0111] It should be noted that the semiconductor conductive layer 300 obtained by the deposition process has a top surface that is not flat, i.e. the semiconductor conductive layer 300 has a surface profile that is uneven.

[0112] Please refer to the accompanying drawings Figure 13 and the accompanying drawings Figure 14 , continue to form a cap layer 400 by a deposition process, the cap layer 400 is located on the first part 310 and directly contacts the first part 310; wherein the surface of the cap layer 400 towards the semiconductor conductive layer 300 has a surface profile with undulations, the surface profile has a wave crest 410 and a wave trough 420, and the first part 310 extends into the wave trough 420.

[0113] By adjusting the process parameters of the semiconductor conductive layer 300 and the cap layer 400, the semiconductor memory device includes a plurality of voids 500, at least one void 500 is located in the first part 310 in the wave trough 420. In this way, the plurality of voids 500 can block the stress generated during the shrinkage or expansion of the semiconductor conductive layer 300 and / or the cap layer 400, avoiding stress concentration at the interface between the semiconductor conductive layer 300 and the cap layer 400, thereby avoiding delamination of the semiconductor conductive layer 300 and the cap layer 400, and improving the performance of the semiconductor memory device.

[0114] Please refer to the accompanying drawings Figure 1 , the accompanying drawings Figure 15 and the accompanying drawings Figure 16 , an insulating layer 720 is formed by a deposition process, the insulating layer 720 covers the cap layer 400. It should be understood that the semiconductor memory device usually includes an array region and a peripheral circuit region, wherein the array region is used to form a storage unit, the storage unit includes a transistor and a capacitor structure. The peripheral circuit region is disposed on one side of the array region and connected with the array region.

[0115] The insulating layer 720 not only covers the cap layer 400, but also covers the first support layer 810 exposed on the peripheral circuit region.

[0116] The conductive plug 730 is formed in the insulating layer 720. The conductive plug 730 extends in a direction perpendicular to the substrate 100, and the end of the conductive plug 730 on the array region close to the substrate 100 is freely arranged according to the material of the cap layer 400. For example, refer to Fig. 4A, the material of the cap layer 400 is a conductive material, the end of the conductive plug 730 on the array region close to the substrate 100 is arranged in the cap layer 400. Figure 15 And refer to Fig. 4B, the material of the cap layer 400 is an insulating material, the end of the conductive plug 730 on the array region close to the substrate 100 is arranged in the semiconductor conductive layer 300. Figure 16 Figure 1 And refer to Fig. 4C, the material of the cap layer 400 is a conductive material, the end of the conductive plug 730 on the array region close to the substrate 100 is arranged in the semiconductor conductive layer 300.

[0117] The embodiment of the present application also provides a semiconductor storage device, which comprises a package and the semiconductor storage device described in any of the above embodiments.

[0118] The package encapsulates the semiconductor storage device, or in other words, the package is wrapped outside the semiconductor storage device, for protecting the semiconductor storage device. On the one hand, the package prevents the moisture in the air from entering the semiconductor storage device, thereby affecting the normal use of the semiconductor storage device. On the other hand, the packaged semiconductor storage device is convenient for transportation and installation.

[0119] In the embodiment, the top surface of the package is slightly higher than the top surface of the semiconductor storage device, so that the semiconductor storage device can be prevented from being damaged in the subsequent chemical mechanical polishing process, and the performance of the semiconductor storage device is ensured. The material of the package includes but is not limited to resin.

[0120] Since the semiconductor storage device in the embodiment has the semiconductor storage device in any of the above embodiments, the semiconductor storage device in the embodiment has the beneficial effects of the semiconductor storage device in the above embodiments, and the embodiment will not be described here.

[0121] The embodiments or implementations in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the embodiments can be referred to each other.

[0122] ​It should be noted that, as the specification mentions "one embodiment", "an embodiment", "the exemplary embodiment", "some embodiments", and the like, it is meant that a particular feature, structure, or characteristic described in connection with the embodiment can be included in some embodiments, but not necessarily every embodiment. Furthermore, such phrases or phrases of similar meaning are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one of ordinary skill in the art to effect such feature, structure, or characteristic in connection with an alternative embodiment whether or not further

[0123] Finally, it should be noted that the above-described embodiments are merely intended for describing and illustrating, but not limiting, the technical solutions of the present application; even though the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some or all of the technical features; and such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor memory device, characterized by comprising: The semiconductor memory device comprises: a substrate; a capacitor structure disposed on the substrate; the capacitor structure comprises a plurality of capacitors; a semiconductor conductive layer comprising a first portion and a second portion, the first portion covering and directly contacting the capacitor structure, and the second portion filling between adjacent capacitors; a cap layer on the first portion and directly contacting the first portion; wherein the cap layer has a relief surface profile toward a surface of the semiconductor conductive layer, the surface profile has a peak and a valley, and the first portion extends into the valley; the cap layer has a material different from that of the semiconductor conductive layer; a plurality of voids spaced in the first portion, and at least one void in the first portion in the valley toward the bottom of the substrate between adjacent peaks and a surface of the cap layer away from the substrate.

2. The semiconductor memory device according to claim 1, wherein The at least one void has a minimum distance D1 from a top surface of the capacitor structure away from the substrate; 3. The semiconductor memory device according to claim 1, wherein two adjacent capacitors in the capacitor structure have a distance D2; the D1 is greater than the D2. The plurality of voids comprises a first void, a second void, and a third void in the first portion in the valley; 4. The semiconductor memory device according to any one of claims 1 to 3, wherein in a first direction, the first void is on one side of the third void, and the second void is on the other side of the third void; the first void and the third void have a first distance D3, and the second void and the third void have a second distance D4; the first distance D3 is less than or equal to the second distance D4. In a direction of the cap layer pointing to the semiconductor conductive layer, the width of the void gradually decreases.

5. The semiconductor memory device according to any one of claims 1 to 3, wherein In a cross section perpendicular to the substrate as a longitudinal section, the longitudinal section shape of the void is a taper or a trapezoid.

6. The semiconductor memory device according to claim 5, wherein In a cross section perpendicular to the substrate as a longitudinal section, the longitudinal section shape of the void is a semicircle or an arc.

7. The semiconductor memory device according to claim 5, wherein The material of the semiconductor conductive layer comprises silicon germanium.

8. The semiconductor memory device according to any one of claims 1 to 3, wherein The material of the cap layer is an insulating material; 9. The semiconductor memory device according to any one of claims 1 to 3, wherein the insulating material is selected from at least one of HDP oxide, TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ, silicon nitride, and silicon oxynitride. The material of the cap layer is a conductive material; 10. The semiconductor memory device according to any one of claims 1 to 3, wherein the conductive material is selected from at least one of tungsten, titanium nitride, and tungsten nitride. The capacitor comprises a first electrode plate, a second electrode plate, and a dielectric layer between the first electrode plate and the second electrode plate; 11. The semiconductor memory device according to any one of claims 1 to 3, wherein the semiconductor conductive layer is disposed on the second electrode plate. The semiconductor memory device comprises a package and any one of claims 1-11; 12. A semiconductor memory device, characterized by comprising: the package encapsulates the semiconductor memory device. ​

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