Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the steps that a plurality of bit line structures are formed, first contact plugs are formed between the adjacent bit line structures, and the top surfaces of the first contact plugs are lower than the top surfaces of the bit line structures; forming an isolation layer having a plurality of openings on top surfaces of the plurality of bit line structures, each opening exposing a portion of the bit line structure and exposing the first contact plug; and forming a plurality of second contact plugs on the plurality of first contact plugs along the plurality of openings, one part of each second contact plug being located between the adjacent bit line structures, and the other part being located on the top surfaces of the plurality of bit line structures. The semiconductor structure can reduce the problem of short circuit between the contact plugs.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for preparing the same, and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared with static memory, DRAM memory has the advantages of simpler structure, lower manufacturing cost and higher capacity density. With the development of technology, DRAM memory is increasingly used.

[0003] A dynamic random access memory device (DRAM) is a type of volatile memory. DRAM devices generally include a memory array region consisting of memory cells, and a peripheral region consisting of logic control circuits. A typical memory cell includes a switch structure (such as a transistor) and a storage structure (such as a capacitor). The logic control circuit in the peripheral region can address each memory cell in the memory array region through multiple word lines (word lines) and multiple bit lines (bit lines) that pass through the memory array region, and open the switch structure to electrically connect the storage structure to perform data reading, writing, or access.

[0004] As the size of dynamic random access memory devices continues to shrink, the technical barriers faced by the patterning process are becoming more and more significant, and the requirements for photolithography process alignment are becoming increasingly strict. For example, due to the reduction in the size of the memory cell, it is difficult for the switch transistor in the 6F2 architecture to form a good electrical contact with the upper structure (such as the bit line or capacitor), or some over-etching occurs, resulting in a short circuit when filling the contact plug, causing yield loss. Summary of the invention

[0005] According to a first aspect of an embodiment of the present disclosure, a method for preparing a semiconductor structure is provided, comprising: forming a plurality of bit line structures, and forming a first contact plug between adjacent bit line structures, wherein a top surface of the first contact plug is lower than a top surface of the bit line structure; forming an isolation layer having a plurality of openings on the top surfaces of the plurality of bit line structures, wherein each opening exposes a portion of the bit line structure and the first contact plug; and forming a plurality of second contact plugs on the plurality of first contact plugs along the plurality of openings, wherein a portion of each second contact plug is located between adjacent bit line structures, and another portion is located on the top surfaces of the plurality of bit line structures.

[0006] In some embodiments, the openings are in a diamond shape, and the diamond-shaped openings are arranged in a hexagonal close-packed structure on top surfaces of the plurality of bit line structures.

[0007] In some embodiments, before forming the second contact plug, the method further includes: forming a plurality of sidewall protection layers along the plurality of openings, respectively, the sidewall protection layers conformally covering the sidewalls of the isolation layer and the sidewalls of the bit line structure exposed by the openings.

[0008] In some embodiments, the isolation layer, the sidewall protection layer, and the outermost layer of the bit line structure are made of the same material.

[0009] In some embodiments, the isolation layer having the plurality of openings is formed by an inverse self-aligned double imaging process.

[0010] In some embodiments, the step of forming an isolation layer having multiple openings includes: forming a lower filling layer on multiple first contact plugs, the lower filling layer being located between the bit line structures, and the top surface of the lower filling layer being flush with the top surface of the bit line structure; forming an upper filling layer on the top surface of the bit line structure and the top surface of the lower filling layer; forming multiple first isolation layers extending along a first direction in the upper filling layer; forming multiple second isolation layers extending along a second direction in a layer composed of the remaining upper filling layers and the first isolation layers, the second direction intersecting with the first direction, and the multiple second isolation layers intersecting with the multiple first isolation layers in the upper filling layer; using the multiple first isolation layers and the multiple second isolation layers that intersect with each other as etching barriers, etching downward the upper filling layer and the lower filling layer to form an isolation layer having multiple openings.

[0011] In some embodiments, before forming the second contact plug, the method further includes: forming a plurality of third contact plugs along the plurality of openings, respectively, the third contact plugs being located between adjacent bit line structures and between top surfaces of the first contact plug and bottom surfaces of the second contact plug.

[0012] In some embodiments, the preparation method further includes: forming a plurality of capacitors on surfaces of the plurality of third contact plugs, the capacitors being cylindrical or columnar capacitors.

[0013] In some embodiments, before forming multiple bit line structures, the method also includes: providing a substrate, the substrate including multiple active areas; forming multiple word line structures in the substrate, the word line structures electrically connected to the active areas; forming multiple bit line contact plugs on the substrate, the bit line structures electrically connected to the active areas in the substrate through the bit line contact plugs.

[0014] According to a second aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: a plurality of bit line structures; a plurality of first contact plugs, each of which is located between adjacent bit line structures, and a top surface of the first contact plug is lower than a top surface of the bit line structure; an isolation layer having a plurality of openings, the isolation layer of the plurality of openings being located on the top surfaces of the plurality of bit line structures, wherein each opening exposes a portion of the bit line structure and exposes the first contact plug; a plurality of second contact plugs are formed in the plurality of openings, a portion of each second contact plug is located between adjacent bit line structures and contacts the first contact plug, and another portion is located on the top surfaces of the plurality of bit line structures.

[0015] In the embodiment of the present disclosure, an isolation layer having multiple openings is formed on the top surfaces of multiple bit line structures, and then the openings are backfilled to form contact plugs with a portion located between adjacent bit line structures and another portion located on the top surfaces of the bit line structures. A method for reversely forming contact plugs is provided, which improves the phenomenon of contact plugs diffusing in the gaps between adjacent bit line structures, thereby avoiding short circuits in the contact plugs. The embodiment of the present disclosure can overcome the obstacle of high alignment requirements for the photolithography process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The present invention is a flow chart of a method for preparing a semiconductor structure according to an exemplary embodiment.

[0017] Figures 2 to 28 is a schematic diagram showing a semiconductor structure manufacturing process according to an exemplary embodiment.

[0018] Fig.29 The diagram is a schematic structural diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0019] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0020] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0021] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0022] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0023] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0024] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0025] Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same. Figure 1 is a flow chart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure; Figures 2 to 28 is a schematic diagram of a semiconductor structure preparation process according to an embodiment of the present disclosure, wherein: Figure 2 , Figure 5 , Figure 8 , Fig.12 , Fig.14 , Fig.16 , Fig. 20 , Fig.26 They are planar schematic diagrams of each stage in the preparation of semiconductor structures. Figure 3 , Figure 4 , Figure 6 , Figure 7 , Fig. 9 , Fig.10 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.18 , Fig.19 , Fig.21 , Fig. 27 They are cross-sectional views taken along line AA' and line BB' at various stages in the preparation of the semiconductor structure. Figure 22 to Figure 25 ,as well as Fig.28The following are cross-sectional views taken along the A-A' line at each stage in the preparation of the semiconductor structure. Figures 1 to 28 The semiconductor structure and its preparation process provided by the embodiment of the present disclosure are described in detail. Figure 1 As shown, the preparation method comprises at least the following steps:

[0026] S10: forming a plurality of bit line structures, and forming a first contact plug between adjacent bit line structures, wherein a top surface of the first contact plug is lower than a top surface of the bit line structure;

[0027] S20: forming an isolation layer having a plurality of openings on top surfaces of the plurality of bit line structures, each opening exposing a portion of the bit line structure and exposing the first contact plug;

[0028] S30: forming a plurality of second contact plugs on the plurality of first contact plugs along the plurality of openings, respectively, wherein a portion of each second contact plug is located between adjacent bit line structures, and another portion of each second contact plug is located on top surfaces of the plurality of bit line structures.

[0029] It should be understood that Figure 1 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 1 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0030] Please refer to Figures 1 to 3 , providing a substrate 10, and etching the substrate 10 to form a plurality of active regions 12 arranged in an array and isolated from each other by shallow trench isolation structures 11 (STI), wherein source regions, drain regions and channel regions are sequentially formed in the active regions 12, and transistors of the memory cells are formed on the active regions 12. In the embodiment of the present disclosure, 6F 2 A dynamic random access memory (DRAM) device with an architecture of 100 MHz to 80 MHz, where “F” corresponds to the feature size of the cell.

[0031] The material of the substrate 10 includes a semiconductor material, for example, a single-element semiconductor material (for example, silicon (Si) or germanium (Ge), etc.), a III-V compound semiconductor material (for example, gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc.), a II-VI compound semiconductor material (for example, zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), an organic semiconductor material or other semiconductor materials known in the art.

[0032] Please continue to refer to Figure 2 and Figure 3 , Figure 2 It is a planar schematic diagram including a bit line structure and a word line structure. Figure 3 is along Figure 2 , and a cross-sectional view taken along line A-A' and line B-B' in FIG. A plurality of word line structures 100, such as buried word line structures, are formed in the substrate 10. The buried word line structures are located in the substrate 10 and extend in the X direction parallel to the surface of the substrate 10, respectively. Each word line structure 100 connects a plurality of active regions 12 in the extension direction X. Each word line structure 100 includes a gate dielectric layer (not shown in the figure), a gate conductive layer 110, and a gate insulating layer 120. The gate dielectric layer is located between the substrate 10 and the gate conductive layer 110, and can be selected from at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and a high-k dielectric film having a dielectric constant greater than that of silicon oxide. The gate conductive layer 110 can be selected from at least one of polysilicon (Poly), metal (such as tungsten (W)), or metal nitride (such as titanium nitride (TiN)). The gate insulating layer 120 covers the surface of the gate conductive layer 110 and may be selected from at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON) to protect the word line structure 100 .

[0033] Please continue to refer to Figures 1 to 3 A plurality of bit line contact plugs 13 and a plurality of bit line structures 200 are formed on the substrate 10, that is, in a direction Z perpendicular to the surface of the substrate 10. The bit line structures 200 are electrically connected to the active area 12 in the substrate 10 through the bit line contact plugs 13. The plurality of bit line structures 200 are located above the substrate 10 and extend in a Y direction parallel to the surface of the substrate 10, and are perpendicular to the extension direction X of the word line structure 100. The bit line structure 200 includes a first conductive layer 210, a second conductive layer 220, a bit line insulating layer 230 located on the bit line contact plugs 13, and a spacer layer 240 covering the bit line conductive layers 210, 220 and the bit line insulating layer 230. The first conductive layer 210 and the second conductive layer 220 are respectively, for example, at least one selected from polysilicon (Poly), metal (such as tungsten (W)) or metal nitride (such as titanium nitride (TiN)). Further, for example, the first conductive layer 210 is a polysilicon layer, and the second conductive layer 220 is a metal layer. Of course, the bit line conductive layer can also include a stacked layer formed by more layers. The bit line insulating layer 230 is located on the bit line conductive layers 210 and 220, and is, for example, a silicon nitride (SiN) material. The sidewall layer 240 covers the sidewalls of the bit line conductive layers 210, 220 and the bit line insulating layer 230. The sidewall layer 240 can form a NON structure, that is, a sidewall layer composed of silicon nitride (SiN)-silicon oxide (SiO)-silicon nitride (SiN), protecting the bit line structure 200. The bit line contact plug 13 is connected to the first conductive layer 210 in the bit line conductive layer, and the material thereof is the same as that of the first conductive layer 210, and is exemplarily, for example, polysilicon (Poly).

[0034] Please continue to refer to Figures 1 to 3 A first contact plug 14 is formed between adjacent bit line structures, and the top surface of the first contact plug 14 is lower than the top surface of the bit line structure 200. The first contact plug 14 contacts the active area 12 and can be formed by epitaxial growth on the surface of the active area 12 or by a deposition process. The first contact plug can be doped silicon (Si), silicon germanium (SiGe) or polysilicon (Poly). Please continue to refer to Figure 3 , a lower filling layer material is formed on the plurality of first contact plugs 14, the lower filling layer material covers the top surface of the bit line structure 200 and the top surface of the first contact plugs 14, and then, the bit line structure 200 is used as a grinding stop layer to planarize the lower filling layer material to form a lower filling layer 201 flush with the top surface of the bit line structure 200. The lower filling layer material may include an insulating material, such as silicon oxide (SiO), which has a low dielectric constant and a high etching selectivity relative to the bit line structure 200. Of course, in other embodiments, the top surface of the lower filling layer 240 may also be higher than the top surface of the bit line structure 200 and cover the bit line structure 200 and the first contact plugs 14, and the portion higher than the top surface of the bit line structure 200 may be used as an upper filling layer 301, thereby avoiding the formation of the upper filling layer 301 and reducing the process steps.

[0035] Please refer back to Figure 1 An isolation layer 300 having a plurality of openings 300 a is formed on top surfaces of the plurality of bit line structures 200 , each opening 300 a exposing a portion of the bit line structure 200 and the first contact plug 14 .

[0036] For example, please refer to Figure 4 An upper filling layer 301 is formed on the top surface of the bit line structure 200 and the top surface of the lower filling layer 201 , and a first initial mask layer 302 ′ and a second initial mask layer 303 ′ are sequentially deposited on the surface of the upper filling layer 301 .

[0037] The upper filling layer 301 can be formed on the surface formed by the bit line structure 200 and the lower filling layer 201 by a deposition process, such as an ALD process. The upper filling layer 301 can be made of the same material as the lower filling layer, such as silicon oxide (SiO). By removing part of the lower filling layer material to form the upper filling layer 301 located on the surface of the lower filling layer 201, the uniformity of the material can be improved and etching damage to the surface of the filling layer material can be avoided. Furthermore, the density of the formed upper filling layer 301 can be greater than the density of the lower filling layer 201 to provide relatively good support.

[0038] The first initial mask layer 302' can be formed on the surface of the upper filling layer 301 by a deposition process, such as an ALD process, and can be made of a material with a higher etching selectivity relative to the upper filling layer 301 and has a greater hardness to ensure that the pattern maintains the expected morphology during the transfer process, for example, at least one selected from an amorphous carbon (C) layer, a silicon (Si) layer, a spin-on carbon (SOC) layer, a spin-on hard mask (SOH) layer, a silicon nitride (SiN) layer, and a silicon oxynitride (SiON) layer. The first initial mask layer 302' can be a single layer or multiple layers.

[0039] The second initial mask layer 303' is formed on the first initial mask layer 302', and may include, for example, a spin-on hard mask (SOH) layer, which may provide good fluidity and filling properties. The second initial mask layer 303' may be a single layer or multiple layers. The multi-layer second initial mask layer 303' may include a silicon oxynitride (SiON) layer, a spin-on hard mask (SOH) layer, and a silicon oxynitride (SiON) layer stacked in sequence, and the multi-layer second initial mask layer 303' has a higher etching selectivity relative to the first initial mask layer 302', and may provide good anti-reflection properties.

[0040] Afterwards, please refer to Figures 5 to 7 , Figure 5 is a schematic plan view of forming a plurality of photoresist layers 304 extending along a first direction a on the second initial mask layer 303 ′, Figure 6 is along Figure 5 The cross-sectional views taken along the A-A' line and the B-B' line in the figure are shown in Figure 1. Figure 5 and Figure 6 , a photoresist is spin-coated on the initial second mask layer 303', and after exposure and development, a plurality of photoresist layers 304 extending along the first direction a are formed. Figure 7 The initial second mask layer 303' is etched downward using the photoresist layer 304 as a mask to form a second mask layer 303 extending along a first direction a. The first direction a is parallel to the surface of the substrate 10 and intersects with the extension direction X of the word line and the extension direction Y of the bit line.

[0041] Please refer to Figure 8 and Fig. 9 , Figure 8 3 is a schematic plan view of forming a third mask layer 305 and a fourth mask layer 306 between the second mask layer 303. Fig. 9 is along Figure 8 A third mask layer 305 is formed on the sidewall of the second mask layer 303, and a fourth mask layer 306 is backfilled between the third mask layers 305. Please continue to refer to Figure 7, forming a third initial mask layer 305' on the surface of the second mask layer 303, backfilling the fourth initial mask layer 306', and the fourth initial mask layer 306' can cover the top surface of the third initial mask layer 305'. Figure 8 and Fig. 9 , the fourth initial mask layer 306' and the third initial mask layer 305' located on the surface of the second mask layer 303 are etched to retain the third initial mask layer 305' located on the sidewall of the second mask layer 303 to form the third mask layer 305. The fourth initial mask layer 306' remaining between the third mask layers 305 forms the fourth mask layer 306. The material of the third mask layer 305 may include silicon oxide, for example. The material of the fourth mask layer 306 is the same as that of the second mask layer 303, so as to facilitate etching the third mask layer 305 downwards using the second mask layer 303 and the fourth mask layer 305 as etching masks.

[0042] Please refer to Fig.10 , using the second mask layer 303 and the fourth mask layer 306 as etching barriers, the third mask layer 305 is etched downwards, and then the first initial mask layer 302' is continuously etched downwards to form a first mask layer 302 extending along the first direction a. At this time, since the width of the third mask layer 305 is smaller than the width of the second mask layer 303 located between the third mask layers 305, and is also smaller than the width of the fourth mask layer 306, after the third mask layer 305 and the first initial mask layer 302' are removed by etching, the spacing between adjacent first mask layers 302 is smaller than the spacing between adjacent second mask layers 303, the spacing is reduced, and the pattern density is doubled.

[0043] Please refer to Fig.11 After removing the second mask layer 303, the third mask layer 305 and the fourth mask layer 306, the upper filling layer 301 is etched downwards with the first mask layer 302 as an etching barrier until the top surface of the bit line structure 200 is exposed, forming a plurality of first isolation trenches 310a extending along the first direction a. Subsequently, the first mask layer 302 is removed. The upper filling layer 301 is located on the top surface of the bit line structure 200 and the top surface of the lower filling layer 201. Therefore, when the upper filling layer 301 is etched to expose a portion of the top surface of the bit line structure 200, a portion of the top surface of the lower filling layer 201 is also necessarily exposed.

[0044] Please refer to Fig.12 and Fig.13 , Fig.12 is a schematic plan view of a first isolation layer 310 extending along a first direction a formed in the upper filling layer 301, Fig.13 is along Fig.12, a cross-sectional view taken along line A-A' and line BB' in FIG. A first isolation layer material is filled in a plurality of first isolation trenches 310a to form a first isolation layer 310, the first isolation layer 310 is located in the upper filling layer 301 and extends along the first direction a. The first isolation layer 310 is continuously located on the bit line structure 200 and the lower filling layer 201. Adjacent first isolation layers 310 are isolated from each other by the upper filling layer 301, and the upper filling layer 303 also extends along the first direction a.

[0045] In an exemplary embodiment of the present disclosure, the first reverse self-aligned double patterning (R-SADP) process is performed through the above process to form a plurality of first isolation layers 310 extending along the first direction a on the top surface of the bit line structure 200. The plurality of first isolation layers 310 are located in the upper filling layer 301, and the pattern density is doubled. The plurality of first isolation layers 310 reserve deposition space for the subsequent formation of the second contact plug 16, thereby reducing the high-precision alignment requirements of the photolithography process.

[0046] Please refer to Fig.14 and Fig.15 , Fig.14 is a schematic plan view of forming a plurality of photoresist layers 304 extending along a second direction b on the second initial mask layer 303 ′, Fig.15 is along Fig.14 , and a cross-sectional view taken along line AA' and line BB' in FIG. 4 . For example, a first initial mask layer 302' and a second initial mask layer 303' are formed again on the layer composed of the remaining upper filling layer 301 and the first isolation layer 310, so as to facilitate patterning again in the second direction b. Fig.14 and Fig.15 , photoresist is spin-coated on the surface of the second initial mask layer 303 ′, and then exposed and developed to form a plurality of photoresist layers 304 extending along the second direction b.

[0047] Please refer to Fig.16 and Fig.17 , Fig.16 3 is a schematic plan view of forming a third mask layer 305 and a fourth mask layer 306 between the second mask layer 303. Fig.17 is along Fig.16 The second initial mask layer 303' is etched downward using the photoresist layer 304 as a mask to form a second mask layer 303 extending along a second direction b. The second direction b is parallel to the surface of the substrate 10 and intersects with the extension direction X of the word line and the extension direction Y of the bit line. The second direction b intersects with the first direction a, for example, perpendicularly or obliquely, and can be adjusted according to actual process requirements.

[0048] Please continue to refer to Fig.16 and Fig.17 , a third mask layer 305 is formed on the sidewall of the second mask layer 303, and a fourth mask layer 306 is backfilled between the third mask layers 305. Similar to the formation process in the first direction a, a third initial mask layer is formed on the surface of the second mask layer 303, and a fourth initial mask layer is backfilled, and the fourth initial mask layer can cover the top surface of the third initial mask layer. Afterwards, the fourth initial mask layer and the third initial mask layer located on the surface of the second mask layer 303 are etched to retain the third initial mask layer located on the sidewall of the second mask layer 303 to form the third mask layer 305, and the fourth initial mask layer is left between the third mask layers 305 to form the fourth mask layer 306. The top surfaces of the second mask layer 303, the third mask layer 305, and the fourth mask layer 306 are flush.

[0049] Please refer to Fig.18 , using the second mask layer 303 and the fourth mask layer 306 as etching barriers, the third mask layer 305 is etched downwards, and then the first initial mask layer 302' is continuously etched downwards to form a first mask layer 302 extending along the second direction a. The spacing between adjacent first mask layers 302 is smaller than the spacing between adjacent second mask layers 303.

[0050] Please refer to Fig.19 After removing the remaining second mask layer 303, third mask layer 305 and fourth mask layer 306 on the first mask layer 302, the second mask layer 302 is used as an etching barrier layer to etch downward the layer composed of the first mask layer 301 and the first isolation layer 310 until the top surface of the bit line structure 200 is exposed, forming a second isolation trench 320a. The second isolation trench 320a extends along the second direction b, and is also where the sidewall portion of the third mask layer 305 deposited along the second direction b is located. It is worth noting that during the downward etching process, the second isolation trench 320a will not only cut off the upper filling layer 301 along the second direction b, but also cut off the first isolation layer 310. Fig.19 As shown in the screenshot of the A-A' line in FIG, the first isolation layer 310 located in the upper filling layer 301 is partially etched to form a second isolation trench 320a. After the second isolation trench 320a is subsequently filled to form the second isolation layer 320, the first isolation layer 310 and the second isolation layer 320 intersect with each other in the upper filling layer 301 on the top surface of the bit line structure 200 through this intersection.

[0051] Please refer to Fig. 20 and Fig.21 , Fig. 203 is a schematic plan view of a second isolation layer 320 extending along a second direction b formed in a layer composed of an upper filling layer 301 and a first isolation layer 310. Fig.21 is along Fig. 20 The cross-sectional view taken along the line A-A' and the line B-B' in the figure. The isolation material is backfilled in the second isolation groove 320a, and a plurality of second isolation layers 320 extending along the second direction b are formed in the layer composed of the remaining upper filling layer 301 and the first isolation layer 310. The plurality of second isolation layers 320 and the plurality of first isolation layers 310 intersect with each other in the upper filling layer 301. The space enclosed by the second isolation layer 320 and the first isolation layer 310 is filled by the upper filling layer 301. In the embodiment of the present disclosure, by performing the second R-SADP process, a plurality of second isolation layers 320 extending along the second direction b are formed on the top surface of the bit line structure 200, and the plurality of second isolation layers 320 reserve deposition space for the subsequent formation of the second contact plug 16.

[0052] Please refer to Fig. 22 , using the multiple first isolation layers 310 and the multiple second isolation layers 320 that cross each other as etching barriers, the upper filling layer 301 and the lower filling layer 201 are etched downward to form an isolation layer 300 having multiple openings 300a. Each opening 300a exposes a portion of the bit line structure 200 and the first contact plug 14. Please refer to Fig. 20 and Fig. 22 , a part of the isolation layer 300 is located on the bit line structure 200, and another part is located on the lower filling layer 201. When the isolation layer 300 is used as a mask, after the upper filling layer 301 is etched, when the lower filling layer 201 is etched downward, the top surface of the bit line structure 200 is partially etched, and the part of the lower filling layer 201 located between the bit line structures 200 and blocked by the isolation layer 300 is retained. At this time, a deposition space for the second contact plug 16 is formed between adjacent bit line structures 200 and on the top surface of the bit line structure 200, and the deposition space is in an inverted "L" shape. The multiple openings 300a of the isolation layer 300 refer to the horizontal line part in the inverted "L", that is, the openings located on the top surface of the bit line structure 200.

[0053] Please refer back to Figure 1 and Fig. 22 In an exemplary embodiment provided in the present disclosure, an isolation layer 300 is formed by enclosing a first isolation layer 310 and a second isolation layer 320 together, and an isolation layer 300 having a plurality of openings 300a is formed on the top surfaces of a plurality of bit line structures 200, each opening 300a exposing a portion of the bit line structure 200 and exposing the first contact plug 14, and exemplarily shows that the isolation layer 300 having a plurality of openings 300a can be formed by an R-SADP process.

[0054] Please continue to refer to Fig. 22 In an exemplary embodiment, the first isolation layer 310 and the second isolation layer 320 are mutually enclosed to form an isolation layer 300, and the opening 300a is a parallelogram. In some exemplary embodiments, it can be a rhombus or a rectangular shape. These openings 300a are offset in opposite directions between the i-th row and the i+1-th row, for example, along the direction X in which the word line extends. For example, these openings 300a can be arranged in a hexagonal close packed (HCP) structure on the top surface of the bit line structure 200, that is, the projection of the six adjacent openings 300a on the plane of the substrate 10 is arranged in a regular hexagon, and each vertex of the regular hexagon is provided with an opening 300a, and the center of the regular hexagon is provided with an opening 300a. Subsequently, after filling the second contact plug 16, the plurality of capacitors 400 respectively connected to the plurality of second contact plugs 16 also have a hexagonal close packed structure, forming the most densely arranged capacitors, thereby improving the integration.

[0055] The materials of the first isolation layer 310 and the second isolation layer 320 can be selected from nitrogen-containing material layers, such as at least one of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbide (SiOC). The materials of the first isolation layer 310 and the second isolation layer 320 can be the same as each other, or they can be different from each other. Based on improving the adhesion between materials and avoiding peeling or gaps in subsequent processes, the materials of the two can be the same as each other, and further, the materials between the outermost layers of the bit line structure (i.e., the sidewall layer 240) can be the same, and both can be silicon nitride.

[0056] Please refer to Fig.23 and Fig.24 In an exemplary embodiment of the present disclosure, a plurality of sidewall protection layers 330 may be deposited along the plurality of openings 300a, respectively, and the sidewall protection layers 330 conformally cover the sidewalls of the isolation layer 300 and the sidewalls of the bit line structure 200 exposed by the openings. Specifically, Fig.23 As shown, a protective layer material 330' is deposited along the opening in the inverted "L"-shaped deposition space by a deposition process, such as an ALD process, and the protective layer material 330' covers the top surface of the isolation layer 300, the sidewalls of the isolation layer 300, the top surface of the bit line structure 200, the sidewalls of the bit line structure 200, the top surface of the first contact plug 13, and the remaining sidewalls of the lower filling layer 201. Then, as shown in Fig.24As shown, the protective layer material 330' located on the top surface of the isolation layer 300, the top surface of the bit line structure 200, and the top surface of the first contact plug 13 is etched back to remove, forming a sidewall protection layer 330. The sidewall protection layer 330 can prevent the etching damage to the bit line structure 200 when the opening 300a is formed, and further avoid the interface gap caused by multiple depositions of the sidewall layer of the bit line structure 200, which causes the subsequent deposition of the second contact plug 16 to diffuse, that is, the second contact plug 16 diffuses into the inside of the bit line structure 200, and the second contact plugs 16 diffuse between each other, causing a short circuit phenomenon and reducing the product yield. Similarly, in the exemplary embodiments of the present disclosure, in order to improve the adhesion between materials and reduce the interface gap, the material of the sidewall protection layer 330 can be the same as the material between the outermost layers of the bit line structure 200 and the material of the isolation layer 300, for example, silicon nitride.

[0057] Please refer to Fig.25 , a third contact plug 15 is formed along the opening 300a. The third contact plug 15 is located at the bottom of the deposition space, specifically, between adjacent bit line structures 200, and on the top surface of the first contact plug 14. As before, the first contact plug 13 is a contact plug that directly contacts the active area in the substrate 10, and is a doped semiconductor material, such as doped polysilicon. The second contact plug 16 deposited subsequently is a metal conductive material. In order to reduce the contact resistance between the two, the third contact plug 15 is formed between the first contact plug 13 and the second contact plug 16 deposited subsequently, such as a metal silicide, such as cobalt silicide (CoSi). For example, a metal layer of cobalt (Co) can be deposited on the surface of the first contact plug 14, and then annealed to form cobalt silicide. Of course, in other embodiments, the third contact plug 15 may not be formed, and the second contact plug 16 may be directly formed.

[0058] Please refer back to Figure 1 , and please refer to Fig.26 and Fig. 27 , Fig.26 is a schematic plan view of forming the second contact plug 16, Fig. 27 is along Fig.26, which are cross-sectional views taken along the lines A-A' and BB'. A plurality of second contact plugs 16 are formed by filling along the plurality of openings 300a, a portion of each second plug 16 is located between adjacent bit line structures 200, and another portion is located on the top surfaces of the plurality of bit line structures 200. The second contact plug 16 includes a metal barrier layer and a metal conductive layer. Specifically, a metal barrier layer may be deposited along the surface of the sidewall protection layer 330 and the surface of the first contact plug 14 (or the third contact plug 15), and then the metal conductive layer is backfilled in the remaining space. The metal barrier layer is located between the bit line structure 200 (and the isolation layer 300) and the metal conductive layer to prevent diffusion of the metal conductive layer. For the convenience of display, only the second contact plug 16 is shown in the drawings in the embodiments of the present disclosure.

[0059] The metal barrier layer in the second contact plug 16 can be selected from at least one of titanium (Ti), molybdenum (Mo), tungsten (W) or nitrides thereof, titanium nitride (TiN), molybdenum nitride (MoN), or nitride (WN). The metal conductive layer can be selected from at least one of titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta), ruthenium (Ru) and iridium (Ir).

[0060] Afterwards, please refer to Fig.28 A capacitor 400 is formed above the bit line structure 200. The capacitor 400 is connected to the active region of the substrate 10 through the second contact plug 16, the third contact plug 15, and the first contact plug 14 to achieve data storage. The capacitor 400 may be a cylinder or pillar capacitor.

[0061] In the embodiment of the present disclosure, an isolation layer 300 having a plurality of openings is pre-formed on the top surface of the bit line structure 200, and then contact plugs are deposited along the openings after removing the filling layers 201 and 301. This provides a method for reversely forming contact plugs. This method can avoid the phenomenon that short circuits (shorts) occur between the plurality of contact plugs due to high alignment or etching defects in the photolithography process during the process of first forming a metal conductive layer and then back-etching to form the plurality of contact plugs 14 and 16. In addition, in an exemplary embodiment of the present disclosure, the sidewalls of the isolation layer 300 and the sidewalls of the bit line structure 200 exposed by the opening 300a of the isolation layer 300 form a sidewall protection layer 330. The sidewall protection layer 330 can protect the surface of the bit line structure 200 and the isolation layer 300, reduce the interface gap caused by etching damage of the multiple layers of capping layers and the sidewall layer on the bit line structure 200, and avoid the thickness of the isolation layer 300 being too narrow, thereby avoiding the diffusion of the metal barrier layer in the contact plugs 14 and 16, especially the second contact plug 16, which may cause a short circuit between multiple contact plugs.

[0062] Please continue to refer to Figure 26 to Figure 28The semiconductor structure prepared by the above-mentioned method for preparing a semiconductor structure includes a substrate 10, a plurality of word line structures 100, a plurality of bit line contact plugs 13, a plurality of bit line structures 200, a plurality of first contact plugs 14, a plurality of second contact plugs 16, a plurality of third contact plugs 15, an isolation layer 300 having a plurality of openings, and a plurality of capacitors 400. The word line structure 100 is located in the substrate 10 as a buried word line, and the bit line structure 200 is located above the substrate and is electrically connected to the substrate 10 through the bit line contact plugs 13. The isolation layer 300 having a plurality of openings is located on the top surfaces of the plurality of bit line structures 200, and each opening exposes a portion of the bit line structure 200 and exposes the first contact plug 14. The first contact plug 14 is located between adjacent bit line structures 200, and the top surface of the first contact plug 14 is lower than the top surface of the bit line structure 200. A portion of the second contact plug 16 is located between adjacent bit line structures 200 and is isolated from each other by the bit line structures 200, and another portion is located on the top surfaces of the plurality of bit line structures 200 and is isolated from each other by the isolation layer 300. The third contact plug is located between adjacent bit line structures 200 and between the top surface of the first contact plug 14 and the bottom surface of the second contact plug 16. The capacitor 400 is located above the bit line structure 200 and is electrically connected to the substrate 10 through the second contact plug 16, the third contact plug 15, and the first contact plug 14 in sequence.

[0063] Please refer to Fig.29 The present disclosure also provides an electronic device 1 having a storage function, the electronic device comprising a processor 2 and a storage device 3 electrically connected to the processor, the storage device comprising the above Figures 1 to 28 The semiconductor structure 4 described in the embodiment of the present disclosure can be a terminal device, such as a personal computer, a mobile phone, a tablet computer, a consumer electronics product, such as a smart home appliance, an autonomous driving device, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR) device, or a server, a data center, etc. The memory device 3 can be, for example, a dynamic random access memory (DRAM), and the semiconductor structure provided by the embodiment of the present disclosure can be formed in addition to 6F 2 The DRAM device of the architecture can also form a phase change memory or a ferroelectric memory, etc. The storage function in the electronic device 1 can be realized by these storage devices 3.

[0064] In some embodiments, the processor 2 and the memory 3 can be two independent chips to form an independent memory. In other embodiments, the memory 3 and the processor 2 can also be integrated into the same chip to form an embedded memory. Figures 1 to 28 The described semiconductor structure 4 can solve the same technical problem and achieve the same expected effect.

[0065] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: forming a plurality of bit line structures, and forming a first contact plug between adjacent bit line structures, wherein a top surface of the first contact plug is lower than a top surface of the bit line structure; forming an isolation layer having a plurality of openings on top surfaces of the plurality of bit line structures, each of the openings exposing a portion of the bit line structure and the first contact plug; A plurality of second contact plugs are formed on the plurality of first contact plugs along the plurality of openings, respectively, wherein a portion of each of the second contact plugs is located between adjacent bit line structures, and another portion of each of the second contact plugs is located on top surfaces of the plurality of bit line structures.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The opening is in a rhombus shape, and the rhombus-shaped openings are arranged in a hexagonal close-packed structure on top surfaces of the plurality of bit line structures.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before forming the second contact plug, the method further includes: A plurality of sidewall protection layers are respectively formed along the plurality of openings, and the sidewall protection layers conformally cover the sidewalls of the isolation layer and the sidewalls of the bit line structure exposed by the openings.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The isolation layer, the sidewall protection layer, and the outermost layer of the bit line structure are made of the same material.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: An isolation layer having a plurality of openings is formed by an inverse self-aligned double imaging process.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 5, characterized in that: The step of forming an isolation layer having a plurality of openings comprises: forming a lower filling layer on the plurality of first contact plugs, wherein the lower filling layer is located between the bit line structures, and a top surface of the lower filling layer is flush with a top surface of the bit line structure; forming an upper filling layer on a top surface of the bit line structure and a top surface of the lower filling layer; forming a plurality of first isolation layers extending along a first direction in the upper filling layer; forming a plurality of second isolation layers extending along a second direction in the layer composed of the remaining upper filling layer and the first isolation layer, wherein the second direction intersects with the first direction, and the plurality of second isolation layers and the plurality of first isolation layers intersect with each other in the upper filling layer; The upper filling layer and the lower filling layer are etched downwards with the first isolation layers and the second isolation layers intersecting each other as etching barrier layers to form an isolation layer having the plurality of openings.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before forming the second contact plug, the method further includes: A plurality of third contact plugs are respectively formed along the plurality of openings, wherein the third contact plugs are located between adjacent bit line structures and between top surfaces of the first contact plugs and bottom surfaces of the second contact plugs.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: The preparation method further comprises: A plurality of capacitors are formed on the surfaces of the plurality of third contact plugs, and the capacitors are cylindrical or columnar capacitors.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before forming a plurality of the bit line structures, the method further comprises: providing a substrate, the substrate comprising a plurality of active regions; forming a plurality of word line structures in the substrate, the word line structures electrically connecting the active areas; A plurality of bit line contact plugs are formed on the substrate, and the bit line structure is electrically connected to the active area in the substrate through the bit line contact plugs.

10. A semiconductor structure, characterized in that: include: Multiple bit line structures; A plurality of first contact plugs, each located between adjacent bit line structures, wherein a top surface of the first contact plug is lower than a top surface of the bit line structure; an isolation layer having a plurality of openings, wherein the isolation layer having the plurality of openings is located on top surfaces of the plurality of bit line structures, wherein each of the openings exposes a portion of the bit line structure and the first contact plug; A plurality of second contact plugs are formed in the plurality of openings, a portion of each of the second contact plugs is located between adjacent bit line structures and contacts the first contact plug, and another portion of each of the second contact plugs is located on top surfaces of the plurality of bit line structures.

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