Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. The semiconductor device may include: a gate structure including insulating layers and conductive layers alternately stacked; a real channel structure extending through the gate structure; the slit structure extends in a first direction along the side wall of the gate structure; a contact structure extending through the gate structure and electrically connected to at least one of the conductive layers; and a pair of first supports extending in an arcuate form along a side wall of the contact structure, and including a concave portion and a convex portion on a side wall of the first support.

Description

Technical Field

[0001] Various embodiments of the present invention relate generally to electronic devices and methods of manufacturing electronic devices, and more particularly, to semiconductor devices and methods of manufacturing semiconductor devices. Background Art

[0002] The integration degree of a semiconductor device is basically determined by the area occupied by a unit memory cell. As the improvement of the integration degree of a semiconductor device in which a memory cell is formed as a single layer on a substrate has recently reached its limit, a three-dimensional semiconductor device in which memory cells are stacked in a three-dimensional arrangement over a substrate has been proposed. In addition, in order to improve the operating characteristics and reliability of such a 3D semiconductor device, various structures, materials, and manufacturing methods are being developed. Summary of the invention

[0003] The present invention generally relates to an improved 3D semiconductor device (hereinafter referred to as a semiconductor device) and a method of manufacturing the semiconductor device.

[0004] In one embodiment of the present disclosure, a semiconductor device may include: a gate structure including alternately stacked insulating layers and conductive layers; a real channel structure extending through the gate structure; a slit structure extending in a first direction along a side wall of the gate structure; a contact structure extending through the gate structure and electrically connected to at least one of the conductive layers; and a pair of first support members extending in an arc shape along the side wall of the contact structure and including recesses and protrusions on the side walls of the first support members.

[0005] In one embodiment, a method for manufacturing a semiconductor device may include the following steps: forming a stack by alternately stacking a first material layer and a second material layer; forming a first opening extending through the stack, the first openings being spaced apart from each other and arranged in an arc form; forming a second opening extending in an arc form by connecting the first openings; forming a pair of first support members in the second opening, the pair of first support members extending in an arc form and having recesses and protrusions on the side walls of the pair of first support members; and forming a contact structure, the contact structure being arranged between the pair of first support members and connected to at least one second material layer among the second material layers.

[0006] These and other features and advantages of the present invention will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A and Figure 1Bis a diagram for describing a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A and Fig. 11B is a diagram for describing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0009] Hereinafter, embodiments according to the technical spirit of the present disclosure are described with reference to the accompanying drawings.

[0010] Embodiments of the present disclosure provide an improved semiconductor device and a method of manufacturing the semiconductor device.

[0011] Provided is a semiconductor device that may have a stable resilient structure, improved reliability, and improved performance characteristics.

[0012] Figure 1A and Figure 1B is a diagram for describing a semiconductor device according to an embodiment of the present disclosure. Figure 1A is a plan view of a semiconductor device, and Figure 1B yes Figure 1A sectional view of .

[0013] Reference Figure 1A and Figure 1B The semiconductor device may include a gate structure 110, a real channel structure 120R, a dummy channel structure 120D, a first support 130, a second support 140, a contact structure 150, a separation structure 160, and a slit structure 170. The semiconductor device may also include an insulating structure 180, a contact through hole 190, a mask pattern M, and an interlayer insulating layer IL.

[0014] The gate structure 110 may include an insulating layer 110A and a conductive layer 110B alternately stacked. The gate structure 110 may include a cell region CR and a contact region CTR. A cell array including a real channel structure 120R may be disposed in the cell region CR. A contact structure 150 connected to the cell array may be disposed in the contact region CTR. The semiconductor device may include a plurality of plane regions. A plurality of memory blocks may be disposed in each plane region. The memory blocks may each include a gate structure 110. The cell region CR and the contact region CTR of the gate structure 110 may be included in a plane central region PLC. The plane edge region PLE may be disposed at both ends of the plane central region PLC. For reference, the gate structure 110 of the plane edge region PLE may include a stack in which a sacrificial layer (not shown) is retained and not replaced by the conductive layer 110B in the process of forming the gate structure. That is, the gate structure 110 and the stack may coexist in the plane edge region PLE. The conductive layer 110B may be a word line, a bit line, or a selection line, respectively. The insulating layers 110A may each include, for example, an insulating material such as oxide. The conductive layers 110B may each include, for example, a conductive material such as tungsten or polysilicon.

[0015] The slit structure 170 may extend through the gate structure 110. The slit structure 170 may be disposed in the cell region CR and the contact region CTR of the gate structure 110, as shown in FIG. Figure 1A The slit structure 170 may generally have an elongated linear form and may extend in the first direction I along the sidewall of the gate structure 110. For example, the slit structure 170 may have a linear form extending along the cell region CR and the contact region CTR. However, the slit structure 170 may not be a straight line, but may include a plurality of concave portions and a plurality of convex portions, such as Figure 1A As shown. The slit structure 170 may include, for example, an insulating material such as oxide. In addition, the slit structure 170 may include a conductive material or a semiconductor material.

[0016] The separation structure 160 may extend through the gate structure 110. The separation structure 160 may be disposed in the plane edge region PLE of the gate structure 110. In the process of manufacturing a semiconductor device, when a plurality of gate structures 110 are formed by replacing a sacrificial layer with a slit conductive layer 110B for forming a slit structure 170, the separation structure 160 may be used to prevent the plurality of gate structures 110 from being electrically connected to each other through the plane edge region PLE. The separation structure 160 may have a concave portion and a convex portion on its sidewall. For example, the separation structure 160 may have a linear form in which the separation structure 160 extends in the first direction I, and may include a concave portion and a convex portion on the sidewall of the separation structure 160. The separation structure 160 may, for example, include an insulating material such as an oxide.

[0017] The separation structure 160 and the slit structure 170 may extend in the first direction I along the sidewall of the gate structure 110 and may be connected to each other. For example, the slit structure 170 may protrude into the separation structure 160. The separation structure 160 and the slit structure 170 may be one layer, or may be separate layers formed by separate processes. Therefore, there may or may not be an interface between the separation structure 160 and the slit structure 170.

[0018] The real channel structure 120R may extend through the gate structure 110. The real channel structure 120R may be disposed in the cell region CR of the gate structure 110. The real channel structure 120R may be disposed between a pair of slit structures 170 adjacent to each other along the second direction II. The second direction II may intersect the first direction I at 90 degrees, for example. Figure 1A As shown. Inside the cell region CR, the real channel structure 120R may be arranged in a zigzag pattern, for example, in the first direction I, and may also be arranged in a zigzag pattern in the second direction II. Alternatively, the real channel structure 120R may be arranged in a staggered form in which the center of the real channel structure 120R has been dislocated. For example, the first direction I and the second direction II may be orthogonal to each other. The real channel structure 120R may include a channel layer 120A. The real channel structure 120R may also include a memory layer 120B surrounding the channel layer 120A and an insulating core (not shown) within the channel layer 120.

[0019] The dummy channel structure 120D may extend through the gate structure 110. The dummy channel structure 120D may be disposed between a pair of separation structures 160 adjacent to each other along the second direction II. The dummy channel structure 120D may be arranged along the first direction I and the second direction II. The dummy channel structure 120D may have a structure similar to that of the real channel structure 120R. For example, the dummy channel structure 120D may include a dummy channel layer, a dummy memory layer, and a dummy insulating core.

[0020] The insulating structure 180 may extend through the gate structure 110. For example, the insulating structure 180 may extend through the mask pattern M into the gate structure 110. For example, the mask pattern M may be a mask pattern that is retained and not removed in the process of manufacturing the semiconductor device. The insulating structure 180 may have a linear form and may extend along the first direction I. The insulating structure 180 may be disposed between adjacent dummy channel structures 120D in the first direction. The insulating structure 180 may be disposed at the center between the real channel structures 120R. For example, the insulating structure 180 may penetrate a portion of at least one of the dummy channel structures 120D. In a variation of the described embodiment, the insulating structure 180 may penetrate a portion of at least one of the real channel structures 120R. The insulating structure 180 may have a height smaller than the separation structure 160 or the slit structure 170. The insulating structure 180 may be disposed within the gate structure 110 and may have a height that penetrates the source selection line or the drain selection line. The insulating structure 180 may, for example, include an insulating material such as an oxide.

[0021] The contact via 190 may be disposed on the gate structure 110 and may pass through the mask pattern M and the interlayer insulating layer IL sequentially stacked on the gate structure 110. For example, the interlayer insulating layer IL may be disposed on the mask pattern M. The interlayer insulating layer IL may, for example, include an insulating material such as an oxide or a nitride. The contact via 190 may be electrically connected to the real channel structure 120R and may be electrically connected to the contact structure 150. For example, the contact via 190 may extend through the mask pattern M and the interlayer insulating layer IL and may be connected to the real channel structure 120R. The contact via 190 may extend through the interlayer insulating layer IL and may be connected to the contact structure 150. The contact via 190 may be used to interconnect a structure disposed within the gate structure 110 with a structure disposed on the gate structure 110. The contact via 190 may, for example, include a conductive material such as tungsten.

[0022] The contact structure 150 may extend through the gate structure 110. The contact structure 150 may be disposed in the contact region CTR of the gate structure 110. The contact structure 150 may extend through the gate structure 110 and may be electrically connected to at least one conductive layer 110B among the conductive layers 110B. The contact structure 150 may include an insulating spacer 150P on a sidewall of the contact structure 150. The insulating spacer 150P may be connected to the contact structure 150 and may be disposed at a height corresponding to the remaining conductive layer 110B. The insulating spacer 150P prevents the remaining conductive layer 1110B other than the conductive layer 110B electrically connected to the contact structure 150 from being electrically connected to the contact structure 150. The contact structure 150 may, for example, include a conductive material such as tungsten. The insulating spacers 150P may, for example, each include an insulating material such as an oxide.

[0023] The first support member 130 may extend through the gate structure 110. The first support member 130 may be disposed in the contact region CTR of the gate structure 110. The first support member 130 may extend in an arc-shaped form along the sidewall of the contact structure 150. The first support member 130 may include a recess and a protrusion on its sidewall. For example, the first support member 130 may be configured as an arc-shaped form in which a plurality of columns are connected to each other. Since the curved sidewalls of the columns are connected, the sidewalls of the first support member 130 may include recesses and protrusions. A pair of first support members 130 may be spaced apart from each other in the first direction I. The contact structure 150 may be disposed between the pair of first support members 130. For example, the pair of first support members 130 may have a symmetrical form.

[0024] If the first support member 130 has a form in which the first support member 130 extends in an arc form, the first support member 130 can support the gate structure 110 more stably than the first support member 130 having a columnar form. The higher the height of the gate structure 110, the higher the height of the contact structure 150 needs to be. In addition, considering the process characteristics, the higher the height of the contact structure 150, the greater the width of the contact structure 150 needs to be. In this case, considering the increase in the width of the contact structure 150, the interval between a pair of first support members 130 may also need to be increased. For example, if the interval between a pair of first support members 130 increases, the supporting force of supporting the gate structure 110 may be reduced. If the first support members 130 each have a columnar form, the supporting force of the first support member 130 supporting the gate structure 110 may be limited. Therefore, according to an embodiment of the present disclosure, a first support member 130 having a form in which the first support member 130 extends in an arc form by considering the increase in the width of the contact structure 150 can be formed. The pair of first support members 130 may extend in an arc form, wherein the pair of first support members 130 surrounds a region where the contact structure 150 is to be formed. Therefore, the bending of the gate structure 110 in the region where the contact structure 150 is to be formed may be reduced.

[0025] In the process of manufacturing the semiconductor device, the first support member 130 and the separation structure 160 may be formed simultaneously. Therefore, the first support member 130 may have substantially the same height as the separation structure 160, or may include substantially the same material as the separation structure 160. For example, the first support member 130 may have substantially the same height as the separation structure 160. In addition, the first support member 130 may include substantially the same material as the separation structure 160. For example, the first support member 130 may include an oxide. However, the present disclosure is not limited to such an example, and the first support member 130 and the separation structure 160 may not be formed simultaneously. For example, the first support member 130 and the separation structure 160 may have different heights and may include different materials.

[0026] For reference, although Figure 1A and Figure 1B Although not shown in the figure, the semiconductor device may include several pairs of first support members 130 and may include a plurality of contact structures 150. The plurality of contact structures 150 may be respectively disposed between a pair of first support members 130. The plurality of contact structures 150 may be respectively electrically connected to the conductive layer 110B of the gate structure 110. Therefore, the heights of the plurality of contact structures 150 may be different from each other.

[0027] The second support member 140 may extend through the gate structure 110. The second support member 140 may be disposed in the contact region CTR of the gate structure 110. The second support member 140 may be disposed by being spaced apart from the first support member 130. Similar to the first support member 130, the second support member 140 may be used to reduce the bending of the gate structure 110. The second support member 140 may be arranged along the first direction I and the second direction II. The second support member 140 may be arranged in a staggered form in which the center of the second support member 140 has been misaligned. Unlike the first support member 130, the second support member 140 may be regularly arranged. The second support member 140 may have a columnar form. The second support member 140 may, for example, include an insulating material such as an oxide.

[0028] According to the above structure, the first support member 130 can extend in an arc form and can support the gate structure 110 more stably than the first support member 130 having a columnar form. Therefore, the first support member 130 can prevent the gate structure 110 from bending in the process of manufacturing the semiconductor device. That is, the height of the gate structure 110 can be increased, and the height of the contact structure 150 connected to the conductive layer 110B provided at the lower portion of the gate structure 110 can also be increased.

[0029] In addition, in the process of manufacturing the semiconductor device, the first support member 130 and the separation structure 160 can be formed at the same time. The first support member 130 and the separation structure 160 can have substantially the same height. The first support member 130 and the separation structure 160 can include substantially the same material. That is, by simplifying the process of forming the first support member 130 and the process of forming the separation structure 160, the process of forming the semiconductor device can be simplified.

[0030] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A and Fig. 11B is a diagram for describing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A and Fig.11A Each of the figures is a plan view of a semiconductor device. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B and Fig. 11B Each of Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A and Fig.11A Hereinafter, descriptions of contents overlapping with the above contents may be omitted.

[0031] Reference Figure 2A and Figure 2B , a first sub-stack 211 may be formed by alternately stacking a first material layer 210A and a second material layer 210B. A first sacrificial contact structure 250A may be formed in the first sub-stack 211. The first sacrificial contact structure 250A may penetrate a portion of the first sub-stack 211. The first sacrificial contact structure 250A may, for example, include a sacrificial material such as polysilicon or carbon. For reference, although not shown in the figure, a plurality of first sacrificial contact structures 250A may be formed. The first sacrificial contact structures 250A may have different heights, so that the first sacrificial contact structures 250A are respectively connected to at least one of the first material layers 210A of the first sub-stack 211.

[0032] Next, the second sub-stack 212 may be formed by alternately stacking the first material layer 210A and the second material layer 210B on the first sub-stack 211. Thus, a stack 210 including the first sub-stack 211 and the second sub-stack 212 may be defined. Thus, the stack 210 may include the first material layer 210A and the second material layer 310B alternately stacked. The stack 210 may include a cell region CR and a contact region CTR. The cell region CR and the contact region CTR of the stack 210 may be included in the planar central region PLC. The planar edge region PLE may be disposed at both ends of the planar central region PLC.

[0033] A first opening OP1 extending through the stack 210 may be formed. The first opening OP1 may be formed in the contact region CTR. The first opening OP1 may extend through the stack 210, and may be formed so that the first opening OP1 is arranged in an arc form by being spaced apart from each other. For example, by considering the area where the contact structure (not shown) will be formed, the first opening OP1 may be arranged in an arc form. The first opening OP1 may be divided into a first group G1 and a second group G2, the first group G1 including the first opening OP1 arranged at a first interval r1, and the second group G2 having been spaced apart from the first group G1 at a second interval r2. The second group G2 may be formed when the first group G1 is formed. The first interval r1 may refer to the interval between the first openings OP1 constituting the first group G1 and the second group G2. The second interval r2 may refer to the interval r2 between the first group G1 and the second group G2. The second interval r2 may be greater than the first interval r1. By forming the second interval r2 to be greater than the first interval r1, the first group G1 and the second group G2 may be prevented from being connected in subsequent processes. The first group G1 and the second group G2 may be spaced apart from each other in the first direction I. The first group G1 and the second group G2 may have a symmetrical form. Next, first sacrificial supporters 230A may be formed in the first openings OP1, respectively. The first sacrificial supporters 230A may each include a sacrificial material such as carbon or polysilicon, for example.

[0034] A third opening OP3 extending through the laminate 210 may be formed. The third opening OP3 may be formed in the contact region CTR. The third opening OP3 may extend through the laminate 210 and may be arranged along a first direction I and a second direction II intersecting the first direction I. For example, the second direction II may be orthogonal to the first direction I. In addition, the third opening OP3 may be arranged in a staggered form in which the center of the third opening OP3 has been misaligned. Unlike the first opening OP1, the third opening OP3 may be regularly arranged. Next, second support members 240 each having a columnar form may be formed in the third opening OP3, respectively. The second support members 240 may, for example, each include an insulating material such as an oxide.

[0035] A fourth opening OP4 extending through the stack 210 may be formed. A fourth opening OP4 extending through the stack 210 and arranged by being spaced apart from each other in the first direction I may be formed. The fourth opening OP4 may be formed when the first opening OP1 is formed. The fourth opening OP4 may be formed in the planar central region PLC and the planar edge region PLE. Next, a sacrificial separation structure 260A may be formed in the fourth opening OP4 formed in the planar edge region PLE, respectively. A sacrificial slit structure 270A may be formed in the fourth opening OP4 formed in the planar central region PLC, respectively. The sacrificial separation structure 260A and the sacrificial slit structure 270A may be formed simultaneously. The sacrificial separation structure 260A and the sacrificial slit structure 270A may each include a sacrificial material such as carbon or polysilicon, for example.

[0036] A real channel structure 220R extending through the stack 210 may be formed. The real channel structure 220R may be formed in the cell region CR. The real channel structure 220R may be formed between the fourth opening OP4 of the planar central region PLC. A dummy channel structure 220D may be formed when the real channel structure 220R is formed. The dummy channel structure 220D may be formed between the fourth opening OP4 of the planar edge region PLE. The real channel structures 220R may each include a channel layer 220A and a memory layer 220B surrounding the channel layer 220A. The real channel structures 220R may also each include an insulating core within the channel layer 220A. The dummy channel structures 220D may each have a form similar to that of each of the real channel structures 220R. For example, the dummy channel structures 220D may each include a dummy channel layer, a dummy memory layer, and a dummy insulating core.

[0037] Reference Figure 3A and Figure 3B, a second sacrificial contact structure 250B extending through the stack 210 may be formed. First, a first mask pattern M1 may be formed on the stack 210. For example, the first mask pattern M1 may cover the remaining area except the first sacrificial contact structure 250A, and may expose the area corresponding to the first sacrificial contact structure 250A. Next, a sixth opening OP6 exposing the first sacrificial contact structure 250A may be formed by the first mask pattern M1. Next, the first sacrificial contact structure 250A may be removed through the sixth opening OP6. Next, an insulating spacer 250P may be formed by etching some of the second material layer 210B that has been exposed through the sixth opening OP6. The insulating spacers 250P may, for example, each include an insulating material such as an oxide. Next, a second sacrificial contact structure 250B may be formed within the sixth opening OP6. The second sacrificial contact structure 250B may, for example, include a sacrificial material such as polysilicon or carbon.

[0038] For reference, although not shown in the figure, a plurality of sacrificial contact structures may be formed in the second sub-stack 212. In the same manner as the first sacrificial contact structure 250A, the sacrificial contact structures in the second sub-stack 212 may be formed to have different heights so that the sacrificial contact structures are respectively connected to the first material layers 210A in the second sub-stack 212. In the process of forming the second sacrificial contact structure 250B, the first sacrificial contact structure 250A in the first sub-stack 211 and the sacrificial contact structure in the second sub-stack 212 may be removed. Therefore, the second sacrificial contact structure 250B may be formed to have different heights so that the second sacrificial contact structure 250B is respectively connected to the first material layers 210A in the stack 210.

[0039] Next, the first opening OP1 may be opened again. First, a second mask pattern M2 exposing the first opening OP1 may be formed on the first mask pattern M1. Next, the first opening OP1 may be opened again by removing the first sacrificial support 230A using the second mask pattern M2. The fourth opening OP4 may be opened again when the first opening OP1 is opened again. For example, the fourth opening OP4 may be the fourth opening OP4 of the planar edge region PLE. The second mask pattern M2 may expose the fourth opening OP4 of the planar edge region PLE. The fourth opening OP4 may be opened again by removing the sacrificial separation structure 260A using the second mask pattern M2. The second mask pattern M2 may expose the first opening OP1 and the fourth opening OP4 of the planar edge region PLE, and may cover the third opening OP3 and the sixth opening OP6.

[0040] Reference Figure 4A and Figure 4B, the second opening OP2 can be formed by connecting the first opening OP1. For example, the second opening OP2 can extend in an arc form and can be formed by selectively expanding the first opening OP1. For example, the arc form can refer to a form in which the first openings OP1 each having a columnar form are connected. The first opening OP1 can be expanded by etching the first material layer 210A and / or the second material layer 210B exposed by the first opening OP1. The first group G1 and the second group G2 can each be composed of a second opening OP2 extending in an arc form. The first opening OP1 can be expanded at a distance greater than the first interval r1 and less than the second interval r2. The reason is that if the first opening OP1 is expanded at a distance greater than the second interval r2, since the first group G1 and the second group G2 are connected, subsequent processes cannot be performed. A pair of second openings OP2 can have a form in which the pair of second openings OP2 extend in an arc form, and can have a symmetrical form in which the pair of second openings OP2 are already spaced apart from each other in the first direction I.

[0041] The fifth opening OP5 may be formed by connecting the fourth openings OP4 of the planar edge region PLE. For example, the fifth openings OP5 extending in the first direction I and each having a linear form may be formed by selectively expanding the fourth openings OP4. The fourth openings OP4 may be expanded by etching the first material layer 210A and / or the second material layer 210B exposed by the fourth openings OP4.

[0042] The fourth opening OP4 may be enlarged when the first opening OP1 is enlarged. For example, when the first opening OP1 is enlarged by the second mask pattern M2, the fourth opening OP4 may also be enlarged at the same time. Therefore, the manufacturing process may be simplified by unifying the process of enlarging the first opening OP1 and the fourth opening OP4.

[0043] Reference Figure 5A and Figure 5B , a pair of first support members 230 each extending in an arc form may be formed in the second opening OP2. For example, a pair of first support members 230 may include a first support member and a second support member positioned symmetrically to each other. Each first support member 230 may include a concave portion and a convex portion forming its sidewall. In order to improve the integration of semiconductor devices, the form of the support members used to prevent the stack 210 from bending as the height of the stack 210 increases is diversified. According to one embodiment of the present disclosure, the first support members 230 can support the stack 210 more stably than the support members each having a columnar form, because the first support members 230 are formed in the second openings OP2 extending in an arc form respectively by connecting the first openings OP1 each having a columnar form. Therefore, even if the height of the stack 210 increases, the stack 210 can be prevented from bending. The first support members 230 may, for example, each include an insulating material such as an oxide.

[0044] A separation structure 260 extending in the first direction I and having a linear form may be formed in each of the fifth openings OP5. For example, the separation structure 260 may extend in a linear form and may have concave and convex portions forming sidewalls of the separation structure 260. The separation structure 260 may include, for example, an insulating material such as oxide.

[0045] The separation structure 260 may be formed when forming the first support member 230. After forming the first support member 230 and the separation structure 260, the second mask pattern M2 may be removed.

[0046] Next, the fourth opening OP4 of the plane central area PLC may be opened again. First, a third mask pattern M3 may be formed on the first mask pattern M1. For example, the third mask pattern M3 may expose the fourth opening OP4 of the plane central area PLC among the fourth opening OP4, and may cover the remaining area. Next, the sacrificial slit structure 270A may be exposed through the third mask pattern M3. Next, the fourth opening OP4 of the plane central area PLC may be opened again by removing the sacrificial slit structure 270A.

[0047] Reference Fig. 6A and Figure 6B , the slit SL may be formed by connecting the fourth opening OP4 of the planar central area PLC. For example, the slit SL extending in the first direction I and having a linear form may be formed by selectively expanding the fourth opening OP4 of the planar central area PLC. For example, the sidewall of the separation structure 260 may be exposed through the slit SL.

[0048] Next, the second material layer 210B may be replaced with the third material layer 210C through the slit SL. For example, the third material layer 210C may each include a conductive material such as tungsten. Therefore, a gate structure 210G including the first material layer 210A and the third material layer 210C stacked alternately may be formed. However, if each of the second material layers 210B includes a conductive material, the process of replacing the second material layer 210B with the third material layer 210C may be omitted. For example, the stack 210 may be used as the gate structure 210G. In addition, the stack 210 between the separation structures 260 may not be replaced by the gate structure 210G. The reason is that in the process of replacing the second material layer 210B with the third material layer 210C through the slit SL, the second material layer 210B that has been set at a relatively long distance from the slit SL and has been formed at the end of the plane edge region PLE may not be removed.

[0049] In the process of forming the gate structure 210G, the first support member 230 and the second support member 240 can reduce the bending of the stack 210. The first support member 230 having an arc form can support the stack 210 more stably than the first support member 230 having a columnar form because the first support member 230 is formed in a form in which the first support member 230 extends in an arc form. In addition, in the process of removing the second material layer 210B through the slit SL of the plane center region PLC and forming the third material layer 210C, a portion of the second material layer 210B of the plane edge region PLE can remain in the separation structure 260 that has been previously formed in the plane edge region PLE. Therefore, the separation structure 260 can be prevented from being electrically connected to each other through the plane edge region PLE between the memory blocks.

[0050] Reference Fig. 7A and Figure 7B , the slit structure 270 may be formed within the slit SL. The slit structure 270 may be connected to the separation structure 260. For example, the slit structure 270 may protrude into the separation structure 260. The slit structure 270 and the separation structure 260 may be separate layers formed by separate processes, but there may or may not be an interface between the slit structure 270 and the separation structure 260. The slit structure 270 may, for example, include an insulating material such as an oxide. Next, the third mask pattern M3 may be removed.

[0051] The insulating structure 280 may be formed within the gate structure 210G. For example, the insulating structure 280 extending into the gate structure 210G may be formed by the first mask pattern M1. The insulating structure 280 may extend in the first direction I and may be disposed between the dummy channel structures 220D or between the real channel structures 220. For example, the insulating structure 280 may penetrate a portion of at least one of the dummy channel structures 220D or a portion of at least one of the real channel structures 220R. The insulating structure 280 may have a smaller height than the separation structure 260 or the slit structure 270. The insulating structure 280 may have a height that penetrates the source selection line or the drain selection line. The insulating structure 280 may, for example, include an insulating material such as an oxide.

[0052] Reference Fig. 8A and Figure 8B , the sixth opening OP6 may be opened again by removing the second sacrificial contact structure 250B. Next, the sixth opening OP6 may be enlarged by removing the first material layer 210A exposed at the bottom of the sixth opening OP6. Thus, the third material layer 210C may be exposed.

[0053] Reference Fig.9A and Fig. 9B, the contact structure 250 may be formed in the sixth opening OP6. The contact structure 250 may be disposed between a pair of first support members 230 and may be connected to at least one of the third material layers 210C. The contact structure 250 may include, for example, a conductive material such as tungsten. If the second material layer 210B includes a conductive material, the contact structure 250 may be connected to at least one of the second material layers 210B because the process of replacing the second material layer 210B with the third material layer 210C may be omitted.

[0054] For reference, although Fig.9A and Fig. 9B Although not shown in the figure, sixth openings OP6 respectively exposing the third material layer 210C and having different heights may be formed in the gate structure 210G. Therefore, contact structures 250 may be respectively formed in the sixth openings OP6. For example, the contact structures 250 may have different heights and may be respectively connected to the third material layer 210C.

[0055] Reference Fig. 10A and Fig. 10B , an interlayer insulating layer IL may be formed on the first mask pattern M1. For example, the interlayer insulating layer IL may, for example, include an insulating material such as an oxide or a nitride. A seventh opening OP7 exposing the real channel structure 220R or the contact structure 250 may be formed through the interlayer insulating layer IL. First, a seventh opening OP7 exposing the contact structure 250 may be formed. For example, the seventh opening OP7 may also be formed at a position corresponding to the real channel structure 220R. Next, the seventh opening OP7 may be enlarged by using the contact structure 250 as an etching barrier to expose the real channel structure 220R.

[0056] Reference Fig.11A and Fig. 11B , contact vias 290 may be formed in the seventh openings OP7, respectively. Therefore, the contact vias 290 may be electrically connected to the real channel structure 220R or may be electrically connected to the contact structure 250. The contact vias 290 may interconnect a structure disposed in the gate structure 210G and a structure disposed on the gate structure 210G. The contact vias 290 may include, for example, a conductive material such as tungsten.

[0057] According to the above manufacturing method, the fourth opening OP4 of the plane edge area PLE can be formed when the first opening OP1 is formed. In addition, the fifth opening OP5 can be formed by expanding the fourth opening OP4 of the plane edge area PLE when the second opening OP2 is formed by expanding the first opening OP1. Therefore, the manufacturing process can be simplified by simplifying the process of forming and expanding the openings OP1 and OP4.

[0058] In addition, the second opening OP2 extending in an arc form can be formed by connecting the first openings OP1 arranged in an arc form. Since the first support member 230 extending in an arc form is formed in the second opening OP2, the stack 210 can be supported more stably than the support member having a columnar form. Therefore, even if the height of the stack 210 increases, the stack 210 or the gate structure 210G can be prevented from bending in the process of forming the gate structure 210G or the process of forming the contact structure 250.

[0059] Although the embodiments according to the technical spirit of the present disclosure have been described above with reference to the accompanying drawings, these embodiments are provided only to describe the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to these embodiments. A person of ordinary skill in the art to which the present disclosure belongs may replace, modify and change the embodiments in various ways without departing from the technical spirit of the present disclosure as described in the attached claims. Such replacement, modification and change may be considered to belong to the scope of the present disclosure. In addition, these embodiments may be combined to form other embodiments.

[0060] CROSS-REFERENCE TO RELATED APPLICATIONS

[0061] This application claims priority to Korean Patent Application No. 10-2023-0082735, filed on Jun. 27, 2023, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device, comprising: A gate structure, the gate structure comprising insulating layers and conductive layers stacked alternately; a real channel structure extending through the gate structure; a slit structure extending in a first direction along a sidewall of the gate structure; a contact structure extending through the gate structure and electrically connected to at least one of the conductive layers; as well as A pair of first support members extends in an arc form along the sidewall of the contact structure and includes a concave portion and a convex portion on the sidewall of the first support member.

2. The semiconductor device according to claim 1, wherein The pair of first support members has a symmetrical form.

3. The semiconductor device according to claim 1, further comprising second support members extending through the gate structure, each second support member having a columnar form, wherein The second support members are arranged along the first direction and a second direction intersecting the first direction.

4. The semiconductor device according to claim 1, further comprising: a separation structure disposed in the planar edge region and connected to the slit structure in the first direction; as well as A dummy channel structure extends through the gate structure and is disposed between a pair of separation structures that are adjacent to each other in a second direction that intersects the first direction.

5. The semiconductor device according to claim 4, wherein: Each of the separation structures includes a concave portion and a convex portion on a side wall.

6. The semiconductor device according to claim 1, wherein The slit structure includes a concave portion and a convex portion on a side wall.

7. The semiconductor device according to claim 1, wherein The gate structure includes a cell region and a contact region, The real channel structure is disposed in the cell region, and At least one pair of the pairs of first support members and at least one of the contact structures are disposed in the contact region.

8. The semiconductor device according to claim 7, wherein: The slit structure has a linear form extending from the cell region to the contact region.

9. The semiconductor device according to claim 4, wherein: The pair of first support members has a height substantially the same as a height of the separation structure.

10. The semiconductor device according to claim 4, wherein The pair of first support members includes a first support member having a material that is the same as or substantially the same as a material of the separation structure.

11. The semiconductor device according to claim 10, wherein The first support member includes an oxide.

12. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a stack by alternately stacking layers of a first material and layers of a second material; forming first openings extending through the stack, the first openings being spaced apart from one another and arranged in an arcuate form; forming a second opening extending in an arc shape by connecting the first openings; A pair of first support members are formed in the second opening, the pair of first support members extend in an arc form and have concave portions and convex portions on side walls; as well as A contact structure is formed, the contact structure being disposed between the pair of first support members and connected to at least one second material layer among the second material layers.

13. The method according to claim 12, wherein: The step of forming the first opening comprises the following steps: forming a first group including the first openings arranged at a first interval; and A second group is formed, the second group being spaced apart from the first group by a second interval greater than the first interval.

14. The method according to claim 13, wherein: The first group and the second group have a symmetrical form.

15. The method according to claim 13, wherein: When the first group is formed, the second group is formed.

16. The method according to claim 12, further comprising the steps of: forming third openings extending through the stack, the third openings being arranged in a first direction and in a second direction intersecting the first direction; as well as Second support members each having a cylindrical form are formed in the third openings, respectively.

17. The method according to claim 16, wherein: When the first opening is formed, the third opening is formed.

18. The method according to claim 16, further comprising the steps of: forming a mask pattern on the stack that covers the third opening and exposes the first opening, The first opening is selectively enlarged by using the mask pattern.

19. The method according to claim 18, further comprising the steps of: forming fourth openings extending through the stack, the fourth openings being spaced apart from one another and arranged along the first direction; forming a fifth opening extending in the first direction by selectively enlarging the fourth openings disposed in the plane edge region among the fourth openings; as well as A separation structure is formed in the fifth opening.

20. The method according to claim 19, wherein: The mask pattern exposing the first opening includes a mask pattern exposing a fourth opening disposed in the planar edge region.

21. The method according to claim 20, wherein: The first opening and the fourth opening are selectively enlarged by using the mask pattern.

22. The method according to claim 19, wherein: When the first support member is formed, the separation structure is formed.

23. The method according to claim 19, further comprising the steps of: forming a slit by connecting remaining fourth openings among the fourth openings, the slit extending in the first direction and exposing the separation structure; replacing the second material layer with a third material layer through the slit; as well as A slit structure is formed in the slit.

24. The method according to claim 12, further comprising the steps of: forming a real channel structure extending through the stack, The stack includes a unit region and a contact region, the real channel structure is formed in the unit region, and at least one pair of first support members and at least one contact structure are formed in the contact region.

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