Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate having a plurality of active structures; the plurality of storage structures are arranged on the first side wall and the second side wall of each active structure at intervals along the first direction; wherein the first direction is perpendicular to the upper surface of the substrate; the first side wall and the second side wall extend along a second direction; the second direction is parallel to the upper surface of the substrate; a plurality of bit lines; the bit lines extend in the third direction, are located above the active structures and are correspondingly connected with the active structures; wherein the third direction is parallel to the upper surface of the substrate and intersects with the second direction; the plurality of active structures arranged along the third direction are connected with the same bit line; and the plurality of storage structures on the first side wall and the second side wall of the same active structure share the same bit line. The semiconductor structure can effectively improve the storage density and improve the storage performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the development of communication technology and digital technology, people continue to pursue products with lower power consumption, lighter weight and better performance. NAND Flash is a non-volatile memory based on non-volatile memory (NAND) technology. It can adopt a three-dimensional structure to have higher storage density and lower cost. It has become one of the important development trends in the field of storage technology.

[0003] In the related art, the basic storage unit of NAND Flash is a storage transistor. At present, the size reduction of storage transistors has reached the shrinkage limit, resulting in the storage density of NAND Flash being limited. Therefore, how to improve the storage density is an urgent problem to be solved. Summary of the invention

[0004] Based on this, the present application provides a semiconductor structure and a method for preparing the same, which can effectively improve storage density and simplify the process flow to improve the production yield and storage performance of the semiconductor structure.

[0005] According to some embodiments, the present application provides a semiconductor structure, including:

[0006] a substrate having a plurality of active structures;

[0007] A plurality of storage structures are arranged at intervals on the first side wall and the second side wall of each of the active structures along a first direction; wherein the first direction is perpendicular to the upper surface of the substrate; the first side wall and the second side wall extend along a second direction; and the second direction is parallel to the upper surface of the substrate;

[0008] A plurality of bit lines; the bit lines extend along a third direction and are located above the active structure and are correspondingly connected to the active structure; wherein the third direction is parallel to the upper surface of the substrate and intersects with the second direction; the plurality of active structures arranged along the third direction are connected to the same bit line; the plurality of storage structures located on the first side wall and the second side wall of the same active structure share the same bit line.

[0009] In some embodiments, the storage structure includes: a first gate dielectric layer, a capture layer, a second gate dielectric layer, and a gate electrode stacked in sequence in a direction away from a corresponding side wall of the active structure.

[0010] In some embodiments, the capture layer has a band gap width greater than or equal to 3.0 electron volts.

[0011] In some embodiments, the acquisition layer is made of a material comprising titanium oxide.

[0012] In some embodiments, the semiconductor structure further comprises: a plurality of word lines; the word lines extend along the second direction and are disposed on side walls of the corresponding storage structure away from the active structure;

[0013] Part of the word line constitutes a gate corresponding to the storage structure.

[0014] In some embodiments, the storage structure includes: a first gate dielectric layer, a capture layer, a second gate dielectric layer and the gate which are sequentially stacked in a direction away from the corresponding side wall of the active structure;

[0015] The semiconductor structure further includes: a support isolation structure; the support isolation structure is located between the capture layers adjacent in the first direction, between the second gate dielectric layers adjacent in the first direction, between the word lines adjacent in the first direction, and between the word lines adjacent in the three directions.

[0016] In some embodiments, the dielectric constant of the support isolation structure is less than 3.0 Farad / meter.

[0017] In some embodiments, the supporting isolation structure is formed of a material including silicon carbonitride.

[0018] In some embodiments, the plurality of storage structures on the first sidewall of the active structure and the plurality of storage structures on the second sidewall respectively constitute storage structure columns;

[0019] The semiconductor structure further comprises:

[0020] A plurality of first selection signal lines; the first selection signal lines extend along the second direction, are located at the top of the corresponding storage structure column, and are located at the corresponding side wall of the active structure;

[0021] A plurality of second selection signal lines; the second selection signal lines extend along the second direction, are located at the bottom of the corresponding storage structure column, and are located at the corresponding side wall of the active structure.

[0022] In some embodiments, a plurality of the memory structure columns arranged in the second direction share the same first selection signal line and the same second selection signal line.

[0023] In some embodiments, the plurality of storage structures on the first sidewall of the active structure and the plurality of storage structures on the second sidewall respectively constitute storage structure columns;

[0024] The semiconductor structure further comprises:

[0025] A plurality of source lines; the source lines are located at the bottom of the corresponding storage structure column and connected to the side walls of the corresponding active structure.

[0026] In some embodiments, a plurality of the memory structure columns arranged in the second direction share the same source line;

[0027] The semiconductor structure further includes: a third selection signal line correspondingly connected to each of the source lines.

[0028] According to some embodiments, the present application further provides a method for preparing a semiconductor structure, comprising:

[0029] Providing a substrate, and forming a plurality of active structures in the substrate;

[0030] A plurality of storage structures are respectively formed on the first sidewall and the second sidewall of each of the active structures and are arranged in a first direction at intervals; wherein the first direction is perpendicular to the upper surface of the substrate; the first sidewall and the second sidewall extend along a second direction; and the second direction is parallel to the upper surface of the substrate;

[0031] A plurality of bit lines are formed above each of the active structures; the bit lines extend along a third direction and are connected to the corresponding active structures; wherein the third direction is parallel to the upper surface of the substrate and intersects with the second direction; the plurality of active structures arranged along the third direction are connected to the same bit line; the plurality of storage structures located on the first side wall and the second side wall of the same active structure share the same bit line.

[0032] In some embodiments, the method for preparing the semiconductor structure further includes:

[0033] A word line extending along the second direction is formed on a side wall of the storage structure away from the active structure; a portion of the word line constitutes a gate corresponding to the storage structure.

[0034] In some embodiments, the plurality of storage structures spaced apart along the first direction are formed on the first sidewall and the second sidewall of each of the active structures, respectively, and include:

[0035] A first gate dielectric layer, a capture layer, a second gate dielectric layer and the gate are sequentially formed in a direction away from the corresponding side wall of the active structure; the first gate dielectric layer, the capture layer, the second gate dielectric layer and the gate together constitute the storage structure;

[0036] The method for preparing the semiconductor structure further comprises:

[0037] A support isolation structure is formed between the capture layers adjacent to each other in the first direction, between the second gate dielectric layers adjacent to each other in the first direction, between the word lines adjacent to each other in the first direction, and between the word lines adjacent to each other in the three directions.

[0038] The semiconductor structure and the preparation method thereof provided in the present application can / at least have the following beneficial effects:

[0039] In an embodiment of the present application, a plurality of storage structures are arranged at intervals on the first side wall and the second side wall of each active structure along a first direction perpendicular to the upper surface of the substrate, thereby realizing three-dimensional storage, solving the density limitation of the planar semiconductor structure in the related art, and improving the storage capacity. In an embodiment of the present application, a plurality of active structures arranged along a third direction are connected to the same bit line, and a plurality of storage structures located on the first side wall and the second side wall of the same active structure share the same bit line, which is conducive to improving the storage density and improving the storage performance of the semiconductor structure. In addition, in an embodiment of the present application, each bit line is arranged above the active structure, so there is no need to occupy additional space, which is conducive to further reducing the occupied area of ​​the semiconductor structure.

[0040] In addition, the semiconductor structure preparation method provided in the embodiment of the present application is simple and easy to implement, which is conducive to simplifying the process flow to improve the production yield of the semiconductor structure.

[0041] In some embodiments of the present application, the storage structure is composed of a first gate dielectric layer, a capture layer, a second gate dielectric layer and a gate which are sequentially stacked in a direction away from the corresponding side wall of the active structure. Since the capture layer has a high energy band width and depth, it can effectively capture and store charges and has higher capacitance performance. By setting the capture layer, a higher storage density and a larger storage capacity can be achieved, which is conducive to breaking through the storage capacity expansion limit of the semiconductor structure. In addition, since the capture layer has a high capacitance performance, it can also reduce the loss of charge, thereby improving the data reliability and stability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 A schematic diagram of a three-dimensional structure of a semiconductor structure provided in some embodiments of the present application;

[0044] Figure 2 A schematic diagram of a top view of a semiconductor structure provided in some embodiments of the present application;

[0045] Figure 3 Figure (a) is a schematic diagram of a cross-sectional structure of a semiconductor structure provided in some embodiments of the present application in a third direction; Figure 3 Figure (b) is a schematic diagram of a cross-sectional structure of a semiconductor structure provided in some embodiments of the present application in the second direction;

[0046] Figure 4 A schematic diagram of a process for preparing a semiconductor structure provided in some embodiments of the present application;

[0047] Figure 5 FIG. (a) is a schematic diagram of a cross-sectional structure in a third direction of a structure obtained after forming a plurality of initial active structures in a method for preparing a semiconductor structure provided in some embodiments of the present application; Figure 5 Figure (b) is Figure 5 (a) is a schematic diagram of a cross-sectional structure of the structure shown in the second direction;

[0048] Figure 6 Figure (a) is a schematic diagram of a cross-sectional structure in a third direction of a structure obtained after forming multiple layers of doped material layers and multiple layers of dielectric material layers alternately stacked in a method for preparing a semiconductor structure provided in some embodiments of the present application; Figure 6 Figure (b) is Figure 6 (a) is a schematic diagram of a cross-sectional structure of the structure shown in the second direction;

[0049] Figure 7 Figure (a) is a schematic diagram of a cross-sectional structure in a third direction of a structure obtained after an etching groove is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application; Figure 7 Figure (b) is Figure 7 (a) is a schematic diagram of a cross-sectional structure of the structure shown in the second direction;

[0050] Figure 8 FIG. (a) is a schematic diagram of a cross-sectional structure in a third direction of a structure obtained after forming a capture layer, a second gate dielectric layer and a gate in a receiving groove in a method for preparing a semiconductor structure provided in some embodiments of the present application; Figure 8 Figure (b) is Figure 8 (a) is a schematic diagram of a cross-sectional structure of the structure shown in the second direction;

[0051] Fig. 9 FIG. (a) is a schematic diagram of a cross-sectional structure in a third direction of a structure obtained after forming a plurality of storage structures in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig. 9 Figure (b) is Fig. 9 (a) is a schematic diagram of a cross-sectional structure of the structure shown in the second direction;

[0052] Fig.10 Figure (a) is a schematic diagram of a cross-sectional structure in a third direction of a structure obtained after a doped semiconductor layer is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig.10 Figure (b) is Fig.10 (a) is a schematic diagram of a cross-sectional structure of the structure shown in the second direction;

[0053] Fig.11 FIG. (a) is a schematic diagram of a cross-sectional structure in a third direction of a structure obtained after forming a plurality of bit lines in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig.11 Figure (b) is Fig.11 The structure shown in Figure (a) is a schematic diagram of the cross-sectional structure in the second direction.

[0054] Description of reference numerals:

[0055] 1. Substrate; 1A. Patterned mask layer; 10. Initial active structure; 11. Active structure; 12. Doping material layer; 13. Dielectric material layer; 14. Doping region; 15. Doped semiconductor layer; 2. Storage structure; 21. First gate dielectric layer; 22. Capturing layer; 23. Second gate dielectric layer; 24. Gate; 3. Bit line; 31. Bit line contact structure; 32. Isolation layer; 4. Word line; 5. Support isolation structure; 6. First selection signal line; 7. Second selection signal line; 8. Source line; 9. Third selection signal line; T1. First trench; S. Storage structure column. DETAILED DESCRIPTION

[0056] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0058] It should be understood that when an element or layer is referred to as being "above" or "adjacent to" other elements or layers, it may be directly above or adjacent to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first selection signal line may be referred to as the second selection signal line, and similarly, the second selection signal line may be referred to as the first selection signal line; the first selection signal line and the second selection signal line are different selection signal lines.

[0059] Spatial relationship terms such as "located above..." may be used here to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "located above..." will be oriented "below" other elements or features. Therefore, the exemplary term "located above..." can include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0060] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0061] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, and variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques, and the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0062] In the related art, the basic storage unit of NAND Flash is a storage transistor. At present, the size reduction of storage transistors has reached the shrinkage limit, resulting in the storage density of NAND Flash being limited. Therefore, how to improve the storage density is an urgent problem to be solved.

[0063] In view of the above shortcomings in the prior art, the present application provides a semiconductor structure and a method for manufacturing the same, which can improve storage density and simplify the process flow to improve the production yield and storage performance of the semiconductor structure. The details will be described in the subsequent embodiments.

[0064] According to some embodiments, the present application provides a semiconductor structure on the one hand, which can be used to manufacture various types of storage devices, such as volatile memory (VM) and non-volatile memory (NVM), and in particular, it is used to manufacture flash memory storage (NAND, also called flash memory) in non-volatile memory.

[0065] See also Figures 1 to 3 In some embodiments, the semiconductor structure includes: a substrate 1 , a plurality of memory structures 2 , and a plurality of bit lines 3 .

[0066] like Figure 1 and Figure 3 As shown in FIG. 1 (a), the substrate 1 has a plurality of active structures 11. A plurality of storage structures 2 are arranged along a first direction at intervals on the first sidewall and the second sidewall of each active structure 11; the first sidewall and the second sidewall extend along a second direction. Each bit line 3 extends along a third direction and is located above the active structure 11 and connected to the active structure 11 accordingly.

[0067] In the embodiment of the present application, a plurality of active structures 11 arranged along the third direction are connected to the same bit line 3 , and a plurality of storage structures 2 located on the first side wall and the second side wall of the same active structure 11 share the same bit line 3 .

[0068] It should be noted that, in the embodiment of the present application, the first direction, the second direction and the third direction intersect with each other. For ease of understanding, the following description is made by taking the first direction being perpendicular to the upper surface of the substrate 1 (for example, the Z direction), the second direction being parallel to the upper surface of the substrate 1 (for example, the Y direction), and the third direction being parallel to the upper surface of the substrate 1 and intersecting with the second direction (for example, the X direction) as an example.

[0069] It should also be noted that, for the sake of illustration, Figure 1 The structures for supporting and / or insulating between adjacent storage structures 2 and between adjacent bit lines 3 are omitted, and the structures will be described in subsequent embodiments.

[0070] In the semiconductor structure provided in the above embodiment, a plurality of storage structures 2 are arranged at intervals on the first side wall and the second side wall of each active structure 11 along a first direction (e.g., Z direction) perpendicular to the upper surface of the substrate, thereby realizing three-dimensional storage, solving the density limitation of the planar semiconductor structure in the related art, and being able to improve the storage capacity when applied to the memory. In the above semiconductor structure, a plurality of active structures 11 arranged along a third direction (e.g., X direction) are connected to the same bit line 3, and a plurality of storage structures 2 located on the first side wall and the second side wall of the same active structure 11 share the same bit line 3, which is conducive to further improving the storage density, so as to improve the storage performance of the memory when applied to the memory. In addition, the above semiconductor structure sets each bit line 3 above the active structure 11, so there is no need to occupy additional space, which is conducive to further reducing the occupied area of ​​the semiconductor structure.

[0071] In addition, the preparation process of the semiconductor structure provided by the above embodiment is simple and easy to implement, which is conducive to simplifying the process flow to improve the production efficiency and production yield of the semiconductor structure.

[0072] See also Figure 3 As shown in FIG. 5( a ), in some embodiments, the storage structure 2 may specifically include: a first gate dielectric layer 21 , a capture layer 22 , a second gate dielectric layer 23 and a gate 24 which are sequentially stacked in a direction away from the corresponding side wall of the active structure 11 .

[0073] In the related art, the storage transistor in NAND Flash is usually formed into a planar structure, including a floating gate layer arranged between the control gate and the substrate. However, there are some limitations in the traditional floating gate layer, such as the difficulty in further miniaturization, the challenges in reading speed and energy consumption. In the semiconductor structure provided in the above embodiment, the storage structure 2 is composed of a first gate dielectric layer 21, a capture layer 22, a second gate dielectric layer 23 and a gate 24 stacked in sequence in a direction away from the corresponding side wall of the active structure 11. Since the capture layer 22 has a high energy band width and depth, it can effectively capture and store charges and has higher capacitance performance. By setting the capture layer 22, the semiconductor structure can achieve a higher storage density and a larger storage capacity when applied to a memory, which is conducive to breaking through the memory storage capacity expansion limit. In addition, since the capture layer 22 has a high capacitance performance, it can also reduce the loss of charge, thereby improving the data reliability and stability of the semiconductor structure.

[0074] The present application embodiment does not specifically limit the constituent materials of the capture layer 22. In some embodiments, the band gap width of the capture layer 22 is greater than or equal to 3.0 electron volts (eV). This ensures that the capture layer 22 has a sufficiently high energy band width and depth, and can more effectively capture and store charges, thereby improving the charge retention performance of the semiconductor structure, which is conducive to improving the data retention time of the semiconductor structure. Based on the advantages of the above-mentioned energy band width and depth, the capture layer 22 can also provide a higher noise margin and a lower data error rate, thereby improving the data reliability and stability of the semiconductor structure.

[0075] For example, the material of the acquisition layer 22 may include titanium oxide (TiO 2 ).

[0076] The band gap width of TiO2 is about 3.0eV to 3.2eV, which is a wide bandgap semiconductor material. Using TiO2 as the constituent material of the capture layer 22 can ensure effective capture and storage of charges, which is conducive to further improving the data retention time of the semiconductor structure, as well as the data reliability and stability of the semiconductor structure.

[0077] Please continue reading Figure 1 In some embodiments, the semiconductor structure may further include a plurality of word lines 4. Each word line 4 extends along the second direction (eg, the Y direction) and is disposed on a side wall of the corresponding storage structure 2 away from the active structure 11.

[0078] Please combine Figure 1 and Figure 3 As can be understood from FIG. 2 (a), illustratively, a gate 24 of a corresponding storage structure 2 may be formed by a portion of a word line 4 .

[0079] See also Figure 1 and Figure 3 In (b) of FIG. 1 , in some embodiments, the semiconductor structure may further include a support isolation structure 5. The support isolation structure 5 is located between adjacent capture layers 22 in a first direction (e.g., Z direction), between adjacent second gate dielectric layers 23 in the first direction (e.g., Z direction), between adjacent word lines 4 in the first direction (e.g., Z direction), and between adjacent word lines 4 in a third direction (e.g., X direction).

[0080] The embodiments of the present application do not specifically limit the constituent materials of the support isolation structure 5. In some embodiments, the dielectric constant of the support isolation structure 5 is less than 3.0 farads / meter (F / m). That is, the support isolation structure 5 has a lower dielectric constant, which is beneficial to reducing the resistance-capacitance (RC) delay of the storage structure 2 to improve the reading and writing speeds of the semiconductor structure, thereby improving the storage performance of the semiconductor structure. The lower dielectric constant is also beneficial to reducing the spacer coupling ratio effect, that is, reducing the impact of the capacitive coupling between different layers in the multilayer structure on the electrical properties of the semiconductor structure.

[0081] Exemplarily, the material forming the support isolation structure 5 may include silicon carbonitride (SiCN).

[0082] The dielectric constant of SiCN can be as low as 2.5, which is a low dielectric constant material. Using SiCN as the constituent material of the support isolation structure 5 can effectively reduce RC delay and further reduce the spacing coupling ratio effect in the semiconductor structure.

[0083] In some embodiments, the semiconductor structure may further include a plurality of bit line contact structures (BLC) 31. The bit line contact structures 31 may be located above the active structure 11 and connected to the active structure 11 accordingly. Based on this, each bit line 3 may be electrically connected to the active structure 11 through the bit line contact structures 31.

[0084] Please continue reading Figure 3 Figure (a) and Figure 3 As shown in FIG. 2( b ), in some embodiments, the semiconductor structure may further include an isolation layer 32 . The isolation layer 32 may be located between the bit line 3 and the active structure 11 , and the bit line contact structure 31 may penetrate the isolation layer 32 .

[0085] In the semiconductor structure provided in the above embodiment, the isolation layer 32 can be provided to prevent the electrical signal on the bit line 3 from affecting the charge state of the active structure 11; at the same time, the isolation layer 32 has good insulation properties, and the isolation layer 32 can also be provided to effectively prevent the flow of current and the leakage of charge, provide good electrical insulation, and further protect the electrical connection between the active structure 11 and the bit line 3 from interference from the external environment, thereby improving the stability and reliability of the semiconductor structure.

[0086] As an example, Figure 1 , Figure 3 Figure (a) and Figure 3 As shown in FIG. 8( b ), a doped semiconductor layer 15 may be provided on the active structure 11 on the top of the substrate 1 , which may be used to electrically connect with the bit line 3 .

[0087] In the semiconductor structure provided in the above embodiment, the bit line contact structure 31 may extend into the doped semiconductor layer 15 , and each bit line 3 may be connected to the doped semiconductor layer 15 through the bit line contact structure 31 to achieve electrical connection with the active structure 11 .

[0088] For ease of understanding, it is defined below that a plurality of storage structures 2 on the first side wall and a plurality of storage structures 2 on the second side wall of the active structure 11 are respectively constituted as storage structure columns S, and some optional embodiments of the present application are described.

[0089] Please continue reading Figure 1 , Figure 2 and Figure 3 In (a) of FIG. 1 , in some embodiments, the semiconductor structure may further include a plurality of first selection signal lines 6 and a plurality of second selection signal lines 7. Each of the first selection signal lines 6 extends along the second direction (e.g., the Y direction), is located at the top of the corresponding storage structure column S, and is located at the corresponding side wall of the active structure 11; each of the second selection signal lines 7 extends along the second direction (e.g., the Y direction), is located at the bottom of the corresponding storage structure column S, and is located at the corresponding side wall of the active structure 11.

[0090] Please continue reading Figure 1 to Figure 2 In some embodiments, a plurality of storage structure columns S arranged in the second direction (eg, Y direction) share the same first selection signal line 6 and the same second selection signal line 7. This is beneficial to further improve the storage density of the semiconductor structure, so as to improve the storage performance of the semiconductor structure.

[0091] The embodiment of the present application does not specifically limit the types of the first selection signal line 6 and the second selection signal line 7. In some embodiments, a portion of the first selection signal line 6 may constitute a drain select gate (DSG) of the corresponding storage structure column S; correspondingly, a portion of the second selection signal line 7 may constitute a source select gate (SSG) of the corresponding storage structure column S.

[0092] Please continue reading Figure 2 In some embodiments, the semiconductor structure may further include a plurality of source lines 8. The source line 8 is located at the bottom of the corresponding storage structure column S and is connected to the sidewall of the corresponding active structure 11.

[0093] In some embodiments, Figure 2 As shown, a plurality of storage structure columns S arranged in the second direction (eg, the Y direction) share the same source line 8. This is beneficial to further improve the storage density of the semiconductor structure, thereby improving the storage performance of the semiconductor structure.

[0094] Please continue reading Figure 1 , Figure 2 and Figure 2As shown in FIG. 5( a ), in some embodiments, the semiconductor structure may further include: a third selection signal line 9 correspondingly connected to each source line 8 .

[0095] According to some embodiments, the present application further provides a method for preparing a semiconductor structure, which is used to prepare the semiconductor structure as described in some of the above embodiments.

[0096] See also Figure 4 In some embodiments, the method for preparing the semiconductor structure may specifically include the following steps:

[0097] S100: providing a substrate, and forming a plurality of active structures in the substrate.

[0098] S200: forming a plurality of storage structures spaced apart along a first direction on the first side wall and the second side wall of each active structure; wherein the first direction is perpendicular to the upper surface of the substrate; the first side wall and the second side wall extend along a second direction; and the second direction is parallel to the upper surface of the substrate.

[0099] S300: forming a plurality of bit lines above each active structure; the bit lines extend along a third direction and are connected to corresponding active structures; wherein the third direction is parallel to the upper surface of the substrate and intersects with the second direction; a plurality of active structures arranged along the third direction are connected to the same bit line; a plurality of storage structures located on the first side wall and the second side wall of the same active structure share the same bit line.

[0100] In the preparation method provided in the above embodiment, a plurality of bit lines extending along the third direction and connected to the corresponding active structures are formed above each active structure, so that a plurality of active structures arranged along the third direction can be connected to the same bit line, and a plurality of storage structures located on the first side wall and the second side wall of the same active structure can share the same bit line, which is beneficial to improving the storage density and thus improving the storage performance of the semiconductor structure.

[0101] Furthermore, the preparation method provided by the above embodiment is simple and easy to implement, which is helpful to simplify the process flow to improve the production efficiency and production yield of the semiconductor structure.

[0102] It should be understood that although Figure 4 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 4At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0103] In order to more clearly illustrate the preparation methods in some of the above embodiments, Figures 5 to 11 Understand some embodiments of the present disclosure. It should be noted that, Figures 5 to 11 Figure (b) is Figures 5 to 11 The cross-sectional structure of the structure shown in Figure (a) is in the aa' direction. Figure 5 As shown in Figure (a).

[0104] See also Figures 5 to 9 In step S100 , a substrate 1 is provided, and a plurality of active structures 11 are formed in the substrate 1 .

[0105] The embodiments of the present application do not specifically limit the constituent materials of the substrate 1. As an example, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductor material, or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI), or a silicon germanium on an insulator.

[0106] As an example, the following steps may be used to form a plurality of active structures 11 in the substrate 1, for example:

[0107] like Figure 5 Figure (a) and Figure 5 As shown in FIG. (b), a patterned mask layer 1A is formed on a substrate 1, and the patterned mask layer 1A has a mask pattern, and the mask pattern can be used to define the position and shape of the initial active structure 10. Then, the substrate 1 is etched based on the patterned mask layer 1A to form a plurality of first trenches T1 extending along the second direction in the substrate 1, and the plurality of first trenches T1 separate a plurality of initial active structures 10 in the substrate 1. Next, ion implantation (IMP) is performed on the substrate 1 to implant a well region (Well) into the substrate 1.

[0108] like Figure 6 As shown in Figure (a) and Figure 6 As shown in FIG. 2( b ), multiple layers of doping material layers 12 and multiple layers of dielectric material layers 13 are alternately stacked in the first trench T1. Then, as shown in FIG. Figures 6 to 9 As shown, the obtained structure is annealed, and a plurality of second grooves extending along the third direction are formed in the substrate 1, and the plurality of second grooves separate each initial active structure 10 into a plurality of active structures 11. Annealing the obtained structure can cause the ions in the substrate 1 to rearrange and activate in the lattice, thereby improving the conductivity of the obtained structure.

[0109] The embodiment of the present application does not specifically limit the type of ions injected into the substrate 1 in the above step, and the type of ions injected into the substrate 1 can be adaptively selected according to actual needs. For example, if an N-type semiconductor structure is to be prepared, a P-type well needs to be implanted; correspondingly, if a P-type semiconductor structure is to be prepared, an N-type well needs to be implanted.

[0110] The present application embodiment does not specifically limit the widths of the first trench T1 and the second trench formed in the above steps. Figure 5 and Fig. 9 As shown, the width of the first trench T1 is greater than the width of the second trench, which is beneficial for providing sufficient space for forming a plurality of storage structures 2 spaced apart along a first direction (e.g., Z direction) on the first side walls and the second side walls of each active structure 11 in subsequent processes, thereby improving the production yield of the semiconductor structure.

[0111] Furthermore, the present embodiment of the present application does not specifically limit the constituent material of the dielectric material layer 13 formed in the first trench T1 in the above step. As an example, the constituent material of the dielectric material layer 13 may include but is not limited to silicon nitride (Si3N4).

[0112] In some embodiments, each active structure 11 may have doped regions 14 formed on both sides of the first direction (eg, Z direction). For example, for any active structure 11, the doped regions 14 on both sides of the first direction (eg, Z direction) may serve as source regions and drain regions, respectively.

[0113] In some embodiments, after forming a plurality of active structures 11 in step S100 and before step S200 , the preparation method may further include the following step: removing the multi-layer doping material layer 12 and the multi-layer dielectric material layer 13 formed in the first trench T1 .

[0114] Please continue reading Figures 7 to 9In step S200, a plurality of storage structures 2 are formed on the first sidewall and the second sidewall of each active structure 11 and are arranged in a first direction (eg, Z direction) at intervals. The first sidewall and the second sidewall extend in a second direction (eg, Y direction).

[0115] Regarding step S200, in some embodiments, step S200 forms a plurality of storage structures 2 spaced apart along a first direction (eg, Z direction) on the first sidewall and the second sidewall of each active structure 11, respectively, which can be specifically performed as follows:

[0116] like Figures 7 to 9 As shown, a first gate dielectric layer 21 , a capture layer 22 , a second gate dielectric layer 23 and a gate 24 are sequentially formed in a direction away from the corresponding side wall of the active structure 11 .

[0117] In the preparation method provided in the above embodiment, the first gate dielectric layer 21, the capture layer 22, the second gate dielectric layer 23 and the gate 24 can together constitute a storage structure 2. Based on the band gap theory, the capture layer 22 can be used as an alternative structure of a floating gate layer. The capture layer 22 has higher capacitance performance and can store more charges, thereby achieving higher storage density and larger storage capacity, which is conducive to breaking through the storage capacity expansion limit of the semiconductor structure. In addition, the capture layer 22 can also reduce the loss of charge due to its higher capacitance performance, thereby improving the data reliability and stability of the semiconductor structure.

[0118] The embodiment of the present application does not specifically limit the constituent materials of the first gate dielectric layer 21 and the second gate dielectric layer 23. In some embodiments, the constituent materials of the first gate dielectric layer 21 and the second gate dielectric layer 23 may be the same or similar. As an example, the first gate dielectric layer 21 and the second gate dielectric layer 23 may both be formed of materials with high dielectric constants. For example, the constituent materials of the first gate dielectric layer 21 and the second gate dielectric layer 23 may include: silicon oxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3), etc.

[0119] As an example, the first gate dielectric layer 21, the capture layer 22, the second gate dielectric layer 23 and the gate 24 may be formed in sequence by the following steps, for example:

[0120] like Figure 7 Figure (a) and Figure 7As shown in FIG. (b), a first gate dielectric layer 21 is formed to cover the first sidewall and the second sidewall of each active structure 11. Then, multiple layers of supporting material layers 25 and multiple layers of sacrificial material layers 26 are alternately stacked on the surface of the first gate dielectric layer 21 in the first trench T1; wherein the sacrificial material layer 26 can be used to define the formation area of ​​the storage structure 2. Next, an etching groove T2 is formed along a first direction (e.g., Z direction) to penetrate each supporting material layer 25 and each sacrificial material layer 26.

[0121] The sacrificial material layer 26 is removed based on the etching groove T2 to form a receiving groove. Figure 8 Figure (a) and Figure 8 As shown in FIG. 2( b ), a capture layer 22 , a second gate dielectric layer 23 and a gate electrode 24 are sequentially formed in the receiving groove.

[0122] Please continue reading Fig. 9 Figure (a) and Fig. 9 In (b) of FIG. 1 , in some embodiments, the preparation method may further include the following steps:

[0123] A support isolation structure 5 is formed between adjacent capture layers 22 in the first direction (e.g., Z direction), between adjacent second gate dielectric layers 23 in the first direction (e.g., Z direction), between adjacent word lines 4 in the first direction (e.g., Z direction), and between adjacent word lines 4 in the third direction (e.g., X direction).

[0124] In the preparation method provided in the above embodiment, a low dielectric constant material can be used to form the support isolation structure 5, so as to reduce the RC delay of the storage structure 2, thereby improving the read and write speed of the semiconductor structure, and further improving the storage performance of the semiconductor structure. The use of a low dielectric constant material to form the support isolation structure 5 is also conducive to reducing the spacing coupling ratio effect and reducing the impact of the capacitive coupling between different layers in the multilayer structure on the electrical performance of the semiconductor structure.

[0125] Please continue reading Figures 7 to 9 In some embodiments, the preparation method may further include the following step: filling the supporting isolation structure 5 in the aforementioned second trench.

[0126] It should be noted that, in some optional embodiments, the support isolation structure 5 filled in the second trench may be made of a material different from that of the other support isolation structures 5, for example Fig. 9 Figure (a) and Fig. 9 As shown in Figure (b).

[0127] In some embodiments, the preparation method may further include the following steps:

[0128] A word line 4 extending along a second direction (eg, the Y direction) is formed on a sidewall of the storage structure 2 away from the active structure 11 .

[0129] In some embodiments, a portion of the word line 4 may constitute the gate 24 of the corresponding memory structure 2 .

[0130] See also Figure 10 to Figure 11 In step S300, a plurality of bit lines 3 are formed above each active structure 11. The bit lines 3 extend along a third direction (e.g., X direction) and are connected to corresponding active structures 11. A plurality of active structures 11 arranged along the third direction (e.g., X direction) are connected to the same bit line 3, and a plurality of storage structures 2 located on the first sidewall and the second sidewall of the same active structure 11 share the same bit line 3.

[0131] As an example, Fig.10 Figure (a) and Fig.10 As shown in FIG. 2( b ), before forming a plurality of bit lines 3 above each active structure 11 in step S300 , the preparation method may further include the following step: forming a doped semiconductor layer 15 on the active structure 11 on the top of the substrate 1 .

[0132] In the above example, the doped semiconductor layer 15 can be used to electrically connect with the bit line 3 formed in step S300 .

[0133] In some embodiments, Figure 10 to Figure 11 As shown, before forming a plurality of bit lines 3 above each active structure 11 in step S300, the preparation method may further include the following steps, such as:

[0134] An isolation material layer is formed on the substrate 1, the doped semiconductor layer 15 and the support isolation structure 5. Then, a contact hole is formed in the isolation material layer using processes such as photolithography and / or wet etching, the contact hole penetrates the isolation material layer and correspondingly exposes a portion of the top surface of the doped semiconductor layer 15, and the reserved isolation material layer serves as the isolation layer 32. Next, a bit line contact structure 31 is formed by filling the contact hole.

[0135] In the preparation method provided in the above embodiment, an isolation layer 32 can be formed to prevent the electrical signal on the bit line 3 from affecting the charge state of the active structure 11; at the same time, the isolation layer 32 has good insulation properties, and can also effectively prevent the flow of current and the leakage of charge by forming the isolation layer 32, providing good electrical insulation, thereby protecting the electrical connection between the active structure 11 and the bit line 3 from interference from the external environment, thereby improving the stability and reliability of the semiconductor structure.

[0136] It should be noted that in the preparation method provided in the above embodiment, the bit line contact structure 31 extends into the doped semiconductor layer 15. Therefore, each bit line 3 formed in step S300 can be connected to the doped semiconductor layer 15 through the bit line contact structure 31 to achieve electrical connection with the active structure 11.

[0137] The present embodiment of the application does not specifically limit the constituent material of the isolation layer 32. As an example, the constituent material of the isolation layer 32 may include silicon oxide.

[0138] Please combine Fig.11 As shown in Figure (a), in some embodiments, the preparation method may further include the following steps:

[0139] A first selection signal line 6 extending along the second direction (for example, the Y direction) is correspondingly formed at the top of each storage structure column S, and each first selection signal line 6 is located at the corresponding side wall of the active structure 11; and, a second selection signal line 7 extending along the second direction (for example, the Y direction) is correspondingly formed at the bottom of each storage structure column S, and each second selection signal line 7 is also located at the corresponding side wall of the active structure 11.

[0140] It should be noted that there is no order restriction for the above steps of forming the first gate signal line 6 and the step of forming the second gate signal line 7. That is, it is allowed to perform either of them first or simultaneously.

[0141] In some embodiments, the step of forming the first gate signal line 6 and the step of forming the second gate signal line 7 may be performed during the execution of the aforementioned step S200 .

[0142] Please continue reading Fig.11 In (a) of FIG. 1 , in some embodiments, a plurality of storage structure columns S arranged in the second direction (eg, the Y direction) share the same first selection signal line 6 and the same second selection signal line 7. This is beneficial to further improve the storage density of the semiconductor structure, so as to improve the storage performance of the semiconductor structure.

[0143] Please combine Figure 2 It is understood that, in some embodiments, the preparation method may further include the following steps:

[0144] A source line 8 is correspondingly formed at the bottom of the storage structure row S, and the source line 8 is connected to the sidewall of the corresponding active structure 11 .

[0145] Please continue reading Figure 2 In some embodiments, a plurality of storage structure columns S arranged in the second direction (eg, the Y direction) share the same source line 8. This is beneficial to further improve the storage density of the semiconductor structure, thereby improving the storage performance of the semiconductor structure.

[0146] Please continue to combine Fig.11 As shown in Figure (a), in some embodiments, the preparation method may further include the following steps:

[0147] A third gate signal line 9 is formed to be connected corresponding to each source line 8 .

[0148] In some embodiments, the step of forming the third gate signal line 9 may be performed before performing the aforementioned step S200 .

[0149] It should be noted that the preparation methods of the semiconductor structures provided in the embodiments of the present application can be used to prepare corresponding semiconductor structures. Therefore, the technical features between the method embodiments and the structural embodiments can be replaced and supplemented with each other without causing conflicts, so that technical personnel in this field can understand the technical content of the present application.

[0150] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0151] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: a substrate having a plurality of active structures; A plurality of storage structures are arranged at intervals on the first side wall and the second side wall of each of the active structures along a first direction; wherein the first direction is perpendicular to the upper surface of the substrate; the first side wall and the second side wall extend along a second direction; and the second direction is parallel to the upper surface of the substrate; A plurality of bit lines; the bit lines extend along a third direction and are located above the active structure and are correspondingly connected to the active structure; wherein the third direction is parallel to the upper surface of the substrate and intersects with the second direction; the plurality of active structures arranged along the third direction are connected to the same bit line; the plurality of storage structures located on the first side wall and the second side wall of the same active structure share the same bit line.

2. The semiconductor structure according to claim 1, characterized in that: The storage structure comprises: a first gate dielectric layer, a capture layer, a second gate dielectric layer and a gate electrode which are sequentially stacked in a direction away from the corresponding side wall of the active structure.

3. The semiconductor structure according to claim 2, characterized in that: The band gap width of the capture layer is greater than or equal to 3.0 electron volts.

4. The semiconductor structure according to claim 2, characterized in that: The acquisition layer is made of titanium oxide.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: Also includes: multiple word lines; The word line extends along the second direction and is disposed on a side wall of the corresponding storage structure away from the active structure; Part of the word line constitutes a gate corresponding to the storage structure.

6. The semiconductor structure according to claim 5, characterized in that: The storage structure comprises: a first gate dielectric layer, a capture layer, a second gate dielectric layer and the gate which are sequentially stacked in a direction away from the corresponding side wall of the active structure; The semiconductor structure further includes: a support isolation structure; the support isolation structure is located between the capture layers adjacent in the first direction, between the second gate dielectric layers adjacent in the first direction, between the word lines adjacent in the first direction, and between the word lines adjacent in the three directions.

7. The semiconductor structure according to claim 6, characterized in that: The dielectric constant of the support isolation structure is less than 3.0 farad / meter.

8. The semiconductor structure according to claim 6, characterized in that: The supporting isolation structure is made of a material including silicon carbonitride.

9. The semiconductor structure according to claim 1, characterized in that: The plurality of storage structures on the first side wall of the active structure and the plurality of storage structures on the second side wall respectively constitute storage structure columns; The semiconductor structure further comprises: A plurality of first selection signal lines; the first selection signal lines extend along the second direction, are located at the top of the corresponding storage structure column, and are located at the corresponding side wall of the active structure; A plurality of second selection signal lines; the second selection signal lines extend along the second direction, are located at the bottom of the corresponding storage structure column, and are located at the corresponding side wall of the active structure.

10. The semiconductor structure according to claim 9, characterized in that: A plurality of the memory structure columns arranged in the second direction share the same first strobe signal line and the same second strobe signal line.

11. The semiconductor structure according to claim 1, characterized in that: The plurality of storage structures on the first side wall of the active structure and the plurality of storage structures on the second side wall respectively constitute storage structure columns; The semiconductor structure further comprises: A plurality of source lines; the source lines are located at the bottom of the corresponding storage structure column and connected to the side walls of the corresponding active structure.

12. The semiconductor structure according to claim 11, characterized in that: A plurality of the storage structure columns arranged in the second direction share the same source line; The semiconductor structure further includes: a third selection signal line correspondingly connected to each of the source lines.

13. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, and forming a plurality of active structures in the substrate; A plurality of storage structures are respectively formed on the first sidewall and the second sidewall of each of the active structures and are arranged in a first direction; wherein the first direction is perpendicular to the upper surface of the substrate; the first sidewall and the second sidewall extend along a second direction; and the second direction is parallel to the upper surface of the substrate; A plurality of bit lines are formed above each of the active structures; the bit lines extend along a third direction and are connected to the corresponding active structures; wherein the third direction is parallel to the upper surface of the substrate and intersects with the second direction; the plurality of active structures arranged along the third direction are connected to the same bit line; the plurality of storage structures located on the first side wall and the second side wall of the same active structure share the same bit line.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that: Also includes: forming a word line extending along the second direction on a side wall of the storage structure away from the active structure; Portions of the word lines constitute gates corresponding to the memory structures.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that: The plurality of storage structures arranged at intervals along the first direction are respectively formed on the first sidewall and the second sidewall of each of the active structures, including: A first gate dielectric layer, a capture layer, a second gate dielectric layer and the gate are sequentially formed in a direction away from the corresponding side wall of the active structure; the first gate dielectric layer, the capture layer, the second gate dielectric layer and the gate together constitute the storage structure; The method for preparing the semiconductor structure further comprises: A support isolation structure is formed between the capture layers adjacent to each other in the first direction, between the second gate dielectric layers adjacent to each other in the first direction, between the word lines adjacent to each other in the first direction, and between the word lines adjacent to each other in the three directions.

Images