A vertical stack 1t1m-based mram memory device and a method of fabricating the same

Abstract

The application provides a MRAM storage device based on vertical 1T1M and a preparation method thereof. The device is composed of a field effect transistor (FET) vertically stacked on a magnetic tunnel junction (MTJ). The magnetic tunnel junction is composed of a multilayer stack of magnetic materials grown on a Si / SiO2 substrate, and each layer from bottom to top is sequentially a bottom electrode, a pinning layer, a reference layer, a barrier layer, a free layer and a top electrode, which are surrounded by a first passivation layer. The field effect transistor is a vertical channel FET in a surround channel around (CAA) configuration, and is vertically stacked from bottom to top by a first metal layer, an isolation layer and a second metal layer. The first metal layer of the field effect transistor is connected to the top electrode of the magnetic tunnel junction through an interconnection layer, thereby forming a 1T1M vertically stacked structure storage device, which can effectively improve the MRAM storage density.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and particularly relates to a MRAM storage device based on vertical stacked 1T1M and a preparation method thereof. BACKGROUND

[0002] Magnetic Random Access Memory (MRAM) is a non-volatile storage technology for data storage by using magnetoresistance effect. The core of MRAM is a magnetic tunnel junction (MTJ) composed of two ferromagnetic layers and a non-magnetic isolation layer. One ferromagnetic layer has a fixed magnetization direction, which is called a fixed layer; the other ferromagnetic layer has a variable magnetization direction, which is called a free layer. Data is stored in the magnetization direction of the free layer, and data is read by detecting the resistance change of the MTJ. When the magnetization directions of the two layers are consistent, the resistance is low, and when the magnetization directions are inconsistent, the resistance is high. MRAM usually includes a 1T1M structure composed of a magnetic tunnel junction and a driving transistor connected to each other. In the existing 1T1M structure, the driving transistor adopts a traditional planar transistor. Due to the structure of the transistor itself, the size (6F2-20F2) cannot be further reduced, which also restricts the scaling of MRAM, and thus high-density MRAM cannot be realized. Therefore, how to reduce the size of the transistor to improve the storage density of MRAM is a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0003] Therefore, the present application aims to provide a MRAM storage device based on vertical stacked 1T1M and a preparation method thereof, which effectively improves the storage density of MRAM.

[0004] To achieve the above-mentioned purpose, the present application adopts the following technical solution: a MRAM storage device based on vertical stacked 1T1M, comprising a vertical structure formed by stacking a magnetic tunnel junction (MTJ) and a field effect transistor (FET) upward and downward, wherein the magnetic tunnel junction (MTJ) is composed of a plurality of layers of stacked magnetic materials grown on a Si / SiO2 substrate, and each layer from bottom to top is sequentially a bottom electrode (2), a pinned layer (3), a reference layer (4), a barrier layer (5), a free layer (6), and a top electrode (8); and the magnetic tunnel junction (MTJ) is surrounded by a first passivation layer (7) on the outside; and the field effect transistor (FET) is a vertical channel FET in a channel around array (CAA) configuration.

[0005] In a preferred embodiment, an interconnection layer (9) is arranged above the top electrode (8).

[0006] In a preferred embodiment, the field effect transistor is prepared above the magnetic tunnel junction MTJ, and the field effect transistor comprises: a stack structure comprising a first metal layer (10), a second passivation layer (11), and a second metal layer (12).

[0007] In a preferred embodiment, a groove is formed in the stack structure, the groove penetrating through the first metal layer (10), the second passivation layer (11), and the second metal layer (12), and the groove partially penetrating through the first metal layer (10), and a channel layer (13), a gate dielectric layer (14), and a gate electrode layer (15) are arranged in the groove; the channel layer (13) is in source-drain contact with the first metal layer (10) and the second metal layer (12), one of the first metal layer (10) and the second metal layer (12) being a source electrode and the other being a drain electrode; the channel layer (13) is in contact with the first metal layer (10) and the second metal layer (12), and the gate dielectric layer (14) is arranged between the semiconductor channel layer (13) and the gate electrode layer (15).

[0008] In a preferred embodiment, the first metal layer (10) of the field effect transistor is connected to the top electrode (8) of the magnetic tunnel junction MTJ through an interconnection layer (9).

[0009] In a preferred embodiment, the feature size area of the MRAM storage device based on the vertical stack 1T1M is 4F 2 .

[0010] In a preferred embodiment, the MRAM storage device based on the vertical stack 1T1M uses the drain current of the vertical channel FET in the top CAA configuration as the driving current to control the magnetization state flipping of the lower magnetic tunnel junction MTJ free layer, and due to the vertical stack structure, the planar size reaches 4F 2 , improving the integration level.

[0011] The application also provides a preparation method of the MRAM storage device based on the vertical stack 1T1M, and the MRAM storage device based on the vertical stack 1T1M is prepared; the method comprises the following steps:

[0012] Step S1: cleaning the Si / SiO2(1) insulating substrate;

[0013] Step S2: defining a bottom electrode area on the substrate by electron beam lithography, and depositing a bottom electrode (2) by physical vapor deposition

[0014] Step S3: growing an MTJ film stack including a pinning layer (3), a reference layer (4), a barrier layer (5), and a free layer (6) by magnetron sputtering based on step S2;

[0015] Step S4: define the etching area by electron beam lithography on the basis of step S3, and etch a columnar magnetic tunnel junction (MTJ) by dry etching;

[0016] Step S5: deposit a first passivation layer (7) by physical vapor deposition on the basis of step S4, and then remove the photoresist and the passivation layer thereon;

[0017] Step S6: define a stripping area by electron beam lithography on the basis of step S5, and deposit a top electrode (8) and an interconnection layer (9) by physical vapor deposition;

[0018] Step S7: prepare a first metal layer (10) of a vertical surrounding channel field effect transistor by magnetron sputtering on the basis of step S6, and connect the top electrode of the magnetic tunnel junction (MTJ) through the interconnection layer;

[0019] Step S8: deposit a second passivation layer (11) by physical vapor deposition on the basis of step S7;

[0020] Step S9: prepare a second metal layer (12) of the vertical surrounding channel field effect transistor by magnetron sputtering on the basis of step S8;

[0021] Step S10: spin-coat photoresist, define the etching area by electron beam lithography, etch a groove by dry etching, and then remove the photoresist on the basis of step S9;

[0022] Step S11: deposit a channel layer (13) on the surface and sidewall of the groove by atomic layer deposition on the basis of step S10;

[0023] Step S12: spin-coat photoresist, define the etching area by electron beam lithography, and perform device isolation by wet etching on the basis of step S11, and then remove the photoresist;

[0024] Step S13: deposit a gate dielectric layer (14) on the surface and sidewall of the groove by atomic layer deposition on the basis of step S12;

[0025] Step S14: deposit a gate electrode layer (15) on the surface and sidewall of the groove by atomic layer deposition on the basis of step S13.

[0026] In a preferred embodiment, in step S3, the material of the pinning layer (3) includes Ru, Co, [Pt / Co] x , Pt, Ta; the material of the reference layer (4) includes CoFeB, Ta, W, [Co / Pt] x , Co; the material of the barrier layer (5) is MCO; and the material of the free layer (6) includes MCO, CoFeB, Ta.

[0027] In a preferred embodiment, the materials of the first passivation layer (7) and the second passivation layer (11) are one or more of SiN, SiO2, Al2O3, and HfO2; the first passivation layer (7) isolates the sidewall of the magnetic tunnel junction MTJ; and the second passivation layer (11) isolates the source and drain.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] The present invention uses a vertical oxide semiconductor transistor with a surround channel (CAA) configuration connected to the MTJ, which has a smaller occupied area (4F2) compared to the traditional 1T1M using a planar transistor, thereby improving integration and storage density.

[0030] The present invention uses atomic layer deposition technology to deposit the channel layer, gate dielectric layer and gate electrode layer. The atomic layer deposition technology has excellent three-dimensional conformality, so that the channel layer, gate dielectric layer and gate layer can be uniformly deposited on the groove surface.

[0031] The present invention uses oxide semiconductor as the channel material of the transistor. Oxide semiconductor has the characteristics of wide bandgap, high mobility, low leakage current and low-temperature deposition. It not only exhibits excellent stability and response speed in high-performance display technology, but also can achieve more compact device design in the field of three-dimensional storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Attachment Figure 1 This is a schematic diagram of the MTJ thin film stack structure grown on a substrate according to the present invention;

[0033] Attachment Figure 2 Schematic diagram of the etched columnar MTJ structure of the present invention;

[0034] Attachment Figure 3 This is a schematic diagram of the device structure after depositing the first passivation layer of the present invention;

[0035] Attachment Figure 4 This is a schematic diagram of the device structure after depositing the top electrode and interconnection layer of the present invention;

[0036] Attachment Figure 5 This is a schematic diagram of the device structure after depositing the first metal layer of the present invention;

[0037] Attachment Figure 6 This is a schematic diagram of the device structure after depositing the second passivation layer of the present invention;

[0038] Attachment Figure 7 This is a schematic diagram of the device structure after depositing the second metal layer of the present invention;

[0039] Attachment Figure 8 This is a schematic diagram of the device structure after etching the channel groove in the present invention;

[0040] Figure 2 shows a device structure after depositing a bottom electrode layer according to the present application; Figure 9 Figure 3 shows a device structure after depositing a pinned layer according to the present application;

[0041] Figure 4 shows a device structure after depositing a reference layer according to the present application; Figure 10 Figure 5 shows a device structure after depositing a barrier layer according to the present application;

[0042] Figure 6 shows a device structure after depositing a free layer according to the present application; Figure 11 Figure 7 shows a device structure after depositing a top electrode layer according to the present application;

[0043] In the figure: 1 - Si / SiO2 substrate; 2 - bottom electrode; 3 - pinned layer; 4 - reference layer; 5 - barrier layer; 6 - free layer; 7 - first passivation layer; 8 - top electrode; 9 - interconnection layer; 10 - first metal layer; 11 - second passivation layer; 12 - second metal layer; 13 - channel layer; 14 - gate dielectric layer; 15 - gate electrode layer. DETAILED DESCRIPTION

[0044] The application will be further described below in conjunction with the accompanying drawings and examples.

[0045] It should be noted that the following detailed description is illustrative only and is intended to provide further description of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0046] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application; as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, and it is further to be understood that the terms "comprising", "including", and / or "containing" when used herein, specify the presence of stated features, steps, operations, devices, components and / or combinations thereof.

[0047] As shown in Figure 1, a MRAM memory device based on a vertical stack of 1T1M includes a vertical structure formed by stacking a magnetic tunnel junction (MTJ) and a field effect transistor (FET) on top of each other, the magnetic tunnel junction is composed of a multi-layer stack of magnetic materials grown on a Si / SiO2 substrate, the layers from bottom to top are in order a bottom electrode, a pinned layer, a reference layer, a barrier layer, a free layer, and a top electrode, which are surrounded by a first passivation layer; the field effect transistor is a vertical channel FET in a CAA configuration. Figures 1-11 The magnetic tunnel junction (MTJ), as shown in Figure 1, is composed of a multi-layer stack of magnetic materials grown on a Si / SiO2 substrate, the layers from bottom to top are in order a bottom electrode, a pinned layer, a reference layer, a barrier layer, a free layer, and a top electrode, which are surrounded by a first passivation layer.

[0048] Figure 3 ​The magnetic material is composed of a multilayer stack grown on a Si / SiO2 substrate and formed by a series of micro-nanofabrication processes to form a vertical internal multilayer material, and the layers from bottom to top are sequentially a bottom electrode (2), a pinning layer (3), a reference layer (4), a barrier layer (5), a free layer (6), and a top electrode (8). The outside is a first passivation layer (7), the internal multilayer magnetic material is in contact with the outside first passivation layer to form a magnetic tunnel junction MTJ, and the top electrode is above an interconnection layer (9).

[0049] The field effect transistor is a vertical channel FET in a surround channel (CAA) configuration, prepared above the MTJ, and the transistor structure includes: a stack structure including a first metal layer (10), a second passivation layer (11), and a second metal layer (12); a groove is etched in the stack structure, the groove passes through the first metal layer, the second passivation layer, and the second metal layer, and the groove partially passes through the first metal layer, and a channel layer (13), a gate dielectric layer (14), and a gate electrode layer (15) are arranged in the groove; the channel layer is in source-drain contact with the first metal layer and the second metal layer, one of the first metal layer and the second metal layer is a source, and the other is a drain; the channel layer is in contact with the first metal layer and the second metal layer, and the gate dielectric layer is arranged between the semiconductor channel layer and the gate electrode layer.

[0050] The first metal layer of the field effect transistor is connected to the top electrode of the magnetic tunnel junction through an interconnection layer.

[0051] The feature size area of the MRAM storage unit of the vertically stacked 1T1M is 4F 2 .

[0052] The vertically stacked 1T1M storage unit has a vertical structure, and the drain current of the top surround channel (CAA) configuration vertical channel FET is used as the driving current to control the magnetization state flip of the lower magnetic tunnel junction MTJ free layer. Due to the vertical stacking structure, the planar size can reach 4F 2 , improving the integration.

[0053] The preparation method of the MRAM storage device based on the vertically stacked 1T1M is used to prepare the vertically stacked 1T1M storage device as described above, including the following steps:

[0054] Step S1: cleaning a Si / SiO2 (1) insulating substrate;

[0055] Step S2: defining a bottom electrode area on the substrate using electron beam lithography, and physically vapor depositing a bottom electrode (2)

[0056] Step S3: On the basis of step S2, MTJ film stack including pinning layer (3), reference layer (4), barrier layer (5), free layer (6) is grown by magnetron sputtering;

[0057] Step S4: On the basis of step S3, etching area is defined by electron beam lithography, and columnar magnetic tunnel junction is etched by dry etching;

[0058] Step S5: On the basis of step S4, first passivation layer (7) is deposited by physical vapor deposition, and then photoresist adhesive and passivation layer thereon are removed;

[0059] Step S6: On the basis of step S5, stripping area is defined by electron beam lithography, and top electrode (8) and interconnection layer (9) are deposited by physical vapor deposition;

[0060] Step S7: On the basis of step S6, vertical surrounding channel type field effect transistor first metal layer (10) is prepared by magnetron sputtering, and is connected with MTJ top electrode through interconnection layer;

[0061] Step S8: On the basis of step S7, second passivation layer (11) is deposited by physical vapor deposition;

[0062] Step S9: On the basis of step S8, vertical surrounding channel type field effect transistor second metal layer (12) is prepared by magnetron sputtering;

[0063] Step S10: On the basis of step S9, photoresist is spin-coated, etching area is defined by electron beam lithography, groove is etched by dry etching, and then photoresist adhesive is removed;

[0064] Step S11: On the basis of step S10, channel layer (13) is deposited on the surface and sidewall of the groove by atomic layer deposition;

[0065] Step S12: On the basis of step S11, photoresist is spin-coated, etching area is defined by electron beam lithography, device isolation is carried out by wet etching, and then photoresist adhesive is removed;

[0066] Step S13: On the basis of step S12, gate dielectric layer (14) is deposited on the surface and sidewall of the groove by atomic layer deposition;

[0067] Step S14: On the basis of step S13, gate electrode layer (15) is deposited on the surface and sidewall of the groove by atomic layer deposition;

[0068] The pinning layer material in step S3 includes: Ru, Co, [Pt / Co] x , Pt, Ta; the reference layer material includes: CoFeB, Ta, W, [Co / Pt] xCo; the barrier layer material is MCO; the free layer material includes: MCO, CoFeB, Ta.

[0069] The first passivation layer and the second passivation layer material in steps S5 and S8 are one or more of SiN, SiO2, Al2O3, HfO2, the first passivation layer insulates the MTJ sidewall, and the second passivation layer insulates the source and drain.

[0070] The first metal layer and the second metal layer material in steps S7 and S9 are one or more of Ti, Mo, Au, ITO, TiN.

[0071] The channel layer material in step S11 includes one or more of an oxide semiconductor, polysilicon, and amorphous silicon; the oxide semiconductor is one or more of zinc oxide ZnO, indium oxide In2O3, tin oxide SnO2, gallium oxide Ga2O3, indium tin oxide ITO, indium zinc oxide IZO, indium gallium oxide IGO, indium gallium zinc oxide IGZO, and indium aluminum zinc oxide IAZO.

[0072] The gate dielectric layer in step S13 includes one or more of Al2O3, HfO2, ZrO2, La2O3, HfAlO x , HfSiO x , HfLaO x , HfZrO x , and HfSiON.

[0073] The gate layer material in step S14 is one of IZO and ITO.

[0074] Further, the specific process steps for preparing the above device are as follows:

[0075] Step 1: Place the Si / SiO2 substrate in a cleaning agent at 70°C for 10 min, the cleaning agent is a mixed solution of deionized water / hydrogen peroxide / ammonium hydroxide at a volume ratio of 5:1:1, then rinse in deionized water for 1 min to remove surface organic particles and adsorbates, and finally dry the sample surface with a nitrogen gun.

[0076] Step 2: Prepare MTJ bottom electrode above the substrate, including uniform glue, baking, exposure, deposition, stripping and other processes. (1) On the basis of step 1, spin PMMA A4 photoresist, spin coating parameters are 3000 rpm / 60 s, and spin coating is baked at 180 ℃ for 90 s; (2) Use Raith150 electron beam exposure system to define the bottom electrode area, so that the electron beam glue of the exposed area is denatured; (3) Development: The developing solution is MIBK:IPA=1:3, the developing time is 50 s, and the IPA fixing time is 40 s. At this time, the denatured glue in the exposed area is dissolved in the developing solution, and the non-exposed area glue is retained, and the layout pattern is transferred to the sample; (4) Use electron beam evaporation coating instrument to deposit 60 nm bottom electrode; (5) In the glue remover NMP, 100 ℃ hot bath for 1 h, and finally soak in IPA for 5 min, and dry with nitrogen.

[0077] Step 3: On the basis of step 2, deposit 150 nm thick MTJ film stack including pinning layer (3), reference layer (4), barrier layer (5), and free layer (6) multilayer metal by magnetron sputtering.

[0078] Step 4: Make a cylindrical magnetic tunnel junction structure, including uniform glue, baking, exposure, etching and other process steps. (1) On the basis of step 3, spin the mask ZEP electron beam glue, the spin coating parameters are 500 rpm / 5 s+2000 rpm / 2 min, and the spin coating is baked at 180 ℃ for 3 min; (2) Use Raith150 electron beam exposure system to define the etching area, that is, make the electron beam glue of the exposed area denatured; (3) Development: The developing solution is amyl acetate, the developing time is 70 s, the IPA fixing time is 40 s, and the nitrogen is dried. At this time, the denatured glue in the exposed area is dissolved in the developing solution, and the non-exposed area glue is retained, and the layout pattern is transferred to the sample; (4) Use ion beam etching IBE to etch 40 nm high and 100 nm~5 μm cylindrical magnetic tunnel junction.

[0079] Step 5: On the basis of step 4, use electron beam evaporation coating instrument to deposit 50 nm first passivation layer to wrap the cylindrical magnetic tunnel junction to make the sidewall insulating and facilitate subsequent process steps; In the glue remover NMP, 100 ℃ hot bath for 1 h, remove the ZEP glue and strip off the passivation layer above the ZEP glue, and finally soak in IPA for 5 min, and dry with nitrogen.

[0080] Step 6: Deposition of MTJ top electrode and interconnect layer on the basis of step 5, including processes such as spin coating, baking, exposure, deposition, stripping, etc. (1) On the basis of step 1, spin-coat PMMA A4 photoresist with spin-coating parameters of 3000 rpm / 60 s, and then bake at 180 °C for 90 s; (2) Use Raith150 electron beam exposure system to define the bottom electrode area, so that the electron beam resist in the exposed area is denatured; (3) Development: the developing solution is MIBK:IPA=1:3, the developing time is 50 s, and the IPA fixing time is 40 s. At this time, the denatured resist in the exposed area dissolves in the developing solution, while the resist in the non-exposed area remains, and the layout pattern is transferred to the sample; (4) Use electron beam evaporation to deposit 60 nm bottom electrode and 60 nm interconnect layer; (5) Hot bath in NMP stripper at 100 °C for 1 h, and then soak in IPA for 5 min, and dry with nitrogen.

[0081] Step 7: Preparation of the first metal layer of vertical surrounding channel type field effect transistor above the interconnect layer, including processes such as spin coating, baking, exposure, deposition, stripping, etc. (1) On the basis of step 4, spin-coat PMMA A4 photoresist with spin-coating parameters of 3000 rpm / 60 s, and then bake at 180 °C for 90 s; (2) Use Raith150 electron beam exposure system to define the etching area, so that the electron beam resist in the exposed area is denatured; (3) Development: the developing solution is MIBK:IPA=1:3, the developing time is 50 s, and the IPA fixing time is 40 s. At this time, the denatured resist in the exposed area dissolves in the developing solution, while the resist in the non-exposed area remains, and the layout pattern is transferred to the sample; (4) Use magnetic sputtering to deposit 50 nm first metal layer; (5) Hot bath in NMP stripper at 100 °C for 1 h, and then soak in IPA for 5 min, and dry with nitrogen.

[0082] Step 8: Preparation of the second passivation layer, including processes such as spin coating, baking, exposure, deposition, etc. (1) On the basis of step 7, spin-coat PMMA A4 photoresist with spin-coating parameters of 2000 rpm / 60 s, and then bake at 180 °C for 90 s; (2) Use Raith150 electron beam exposure system to define the etching area, so that the electron beam resist in the exposed area is denatured; (3) Development: the developing solution is MIBK:IPA=1:3, the developing time is 50 s, and the IPA fixing time is 40 s. At this time, the denatured resist in the exposed area dissolves in the developing solution, while the resist in the non-exposed area remains, and the layout pattern is transferred to the sample; (4) Use magnetic sputtering to deposit 50-100 nm second passivation layer.

[0083] Step 9: Deposition of the second metal layer of vertical surrounding channel type field effect transistor above the second passivation layer. On the basis of step 8, use magnetic sputtering to deposit 50 nm second metal layer; hot bath in NMP stripper at 100 °C for 1 h, soak in IPA for 5 min, and dry with nitrogen.

[0084] Step 10: Preparation of etching groove, including uniform coating, baking, exposure, deposition, and stripping process. (1) On the basis of step 7, spin-coat ZEP520A photoresist, spin-coating parameters are 500 rpm / 5 s + 2000 rpm / 2 min, and after spin-coating, 180 ℃ baking for 1 min; (2) Use Raith150 electron beam exposure system to define the etching area, i.e. make the electron beam glue in the exposure area denatured; (3) Development: the developing solution is amyl acetate, the developing time is 70 s, the IPA fixing time is 40 s, and the nitrogen blowing dry, at this time, the denatured glue in the exposure area is dissolved in the developing solution, and the non-exposure area glue is reserved, and the layout pattern is transferred to the sample; (4) Use ion beam etching IBE and inductively coupled plasma etching ICP to etch the exposure area, the etching depth is 125~175 nm, i.e. etching through the second metal layer and the second passivation layer to part of the first metal layer to form a groove structure; (5) Hot bath in NMP stripping solution at 100 ℃ for 1 h, soak in IPA for 5 min, and dry with nitrogen.

[0085] Step 11: On the basis of step 10, use atomic layer deposition technology to deposit channel layer on the groove surface and sidewall, in an optional case, the channel material is ITO, which is composed of In2O3 and Sn2O3 in a certain proportion, the selected precursor source of In source is DimethylAminopropyl-Dimethyl Indium (DADI), the selected precursor source of Sn source is Tetrakis(dimethylamino)tin (TDMASn), and the oxygen source is O2 into the ozone generator to generate O3 as the oxygen source, and the deposition temperature is 300 ℃.

[0086] Step 12: On the basis of step 11, etch the channel layer for device isolation, including uniform coating, baking, exposure, etching, and stripping process. (1) On the basis of step 11, spin-coat PMMA A4 electron beam glue as a mask, spin-coating parameters are 500 rpm / 5 s + 2000 rpm / 2 min, and after spin-coating, 180 ℃ baking for 90 s; (2) Use Raith150 electron beam exposure system to define the etching area, i.e. make the electron beam glue in the exposure area denatured; (3) Development: the developing solution is MIBK:IPA=1:3, the developing time is 50 s, the IPA fixing time is 40 s, and the nitrogen blowing dry, at this time, the denatured glue in the exposure area is dissolved in the developing solution, and the non-exposure area glue is reserved, and the layout pattern is transferred to the sample; (4) Use wet solution to etch the exposure area; (5) Hot bath in NMP stripping solution at 100 ℃ for 1 h, soak in IPA for 5 min, and dry with nitrogen.

[0087] Step 13: On the basis of step 12, use atomic layer deposition to deposit gate dielectric layer, which has the advantage of good sidewall coverage.

[0088] Step 14: Atomic layer deposition of the gate electrode layer on the basis of step 13, which has the advantage of good sidewall coverage.

Claims

1. A MRAM memory device based on a vertical stack of 1T1M, characterized in that, A vertical structure formed by stacking a magnetic tunnel junction (MTJ) and a field effect transistor (FET) upside down, the magnetic tunnel junction (MTJ) being composed of a multilayer stack of magnetic materials grown on a Si / SiO2 substrate, the layers from bottom to top being a bottom electrode (2), a pinned layer (3), a reference layer (4), a barrier layer (5), a free layer (6) and a top electrode (8) in sequence, the magnetic tunnel junction (MTJ) being surrounded by a first passivation layer (7) on the outside; the field effect transistor being a vertical channel FET of the CAA configuration; The field effect transistor is prepared above the magnetic tunnel junction (MTJ), and the field effect transistor comprises a stack structure including a first metal layer (10), a second passivation layer (11) and a second metal layer (12); A groove is etched in the stack structure, the groove passing through the first metal layer (10), the second passivation layer (11) and the second metal layer (12), and the groove partially passing through the first metal layer (10), and a channel layer (13), a gate dielectric layer (14) and a gate electrode layer (15) are arranged in the groove; the channel layer (13) is in source-drain contact with the first metal layer (10) and the second metal layer (12), one of the first metal layer (10) and the second metal layer (12) being a source electrode and the other being a drain electrode; the channel layer (13) is in contact with the first metal layer (10) and the second metal layer (12), and the gate dielectric layer (14) is arranged between the semiconductor channel layer (13) and the gate electrode layer (15).

2. The MRAM memory device based on vertical stack 1T1M of claim 1, wherein, An interconnection layer (9) is arranged above the top electrode (8).

3. The MRAM memory device based on vertical stack 1T1M of claim 1, wherein, The first metal layer (10) of the field effect transistor is connected to the top electrode (8) of the magnetic tunnel junction (MTJ) through the interconnection layer (9).

4. The MRAM memory device based on vertical stack 1T1M of claim 1, wherein, The feature size area of the MRAM memory device based on the vertical stack 1T1M is 4F 2 .

5. The MRAM memory device based on vertical stack 1T1M of claim 1, wherein, The vertical stack 1T1M-based MRAM storage device uses the drain current of the vertical channel FET in the upper surrounding channel CAA configuration as the driving current to control the magnetization state flip of the lower magnetic tunnel junction MTJ free layer. Due to the vertical stack structure, the planar size reaches 4F 2 , and the integration is improved.

6. A method for preparing an MRAM storage device based on vertical stacking 1T1M, characterized in that A MRAM storage device based on a vertical stack 1T1M is prepared according to any one of the above claims 1-5, comprising the following steps: Step S1: cleaning a Si / SiO2 (1) insulating substrate; Step S2: defining a bottom electrode area on the substrate by electron beam lithography, and depositing a bottom electrode (2) by physical vapor deposition; Step S3: growing an MTJ film stack including a pinned layer (3), a reference layer (4), a barrier layer (5) and a free layer (6) on the basis of step S2 by magnetron sputtering; Step S4: defining an etching area by electron beam lithography on the basis of step S3, and etching a columnar magnetic tunnel junction (MTJ) by dry etching; Step S5: depositing a first passivation layer (7) by physical vapor deposition on the basis of step S4, and then removing the photoresist and the passivation layer thereon; Step S6: defining a stripping area by electron beam lithography on the basis of step S5, and depositing a top electrode (8) and an interconnection layer (9) by physical vapor deposition; Step S7: preparing a first metal layer (10) of a vertical CAA field effect transistor by magnetron sputtering on the basis of step S6, and connecting the top electrode of the magnetic tunnel junction (MTJ) through the interconnection layer; Step S8: depositing a second passivation layer (11) by physical vapor deposition on the basis of step S7; Step S9: On the basis of step S8, a second metal layer (12) of the vertical surrounding channel type field effect transistor is prepared by magnetron sputtering; Step S10: On the basis of step S9, photoresist is spin-coated, and an etching area is defined by electron beam lithography, a groove is etched by dry etching, and then the photoresist mask is removed; Step S11: On the basis of step S10, a channel layer (13) is deposited on the surface and sidewall of the groove by atomic layer deposition; Step S12: On the basis of step S11, photoresist is spin-coated, and an etching area is defined by electron beam lithography, device isolation is performed by wet etching, and then the photoresist mask is removed; Step S13: On the basis of step S12, a gate dielectric layer (14) is deposited on the surface and sidewall of the groove by atomic layer deposition; Step S14: On the basis of step S13, a gate electrode layer (15) is deposited on the surface and sidewall of the groove by atomic layer deposition.

7. The method of claim 6, wherein the method further comprises: In step S3, the material of the pinning layer (3) includes: Ru, Co, [Pt / Co] x , Pt and Ta; the material of the reference layer (4) includes: CoFeB, Ta, W, [Co / Pt] x and Co; the material of the barrier layer (5) is MCO; and the material of the free layer (6) includes: MCO, CoFeB and Ta.

8. The method of claim 7, wherein the method further comprises: The material of the first passivation layer (7) and the second passivation layer (11) is one or more of SiN, SiO2, Al2O3, and HfO2, the first passivation layer (7) insulates the sidewall of the magnetic tunnel junction (MTJ), and the second passivation layer (11) insulates the source and drain.

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