Driver arrangement comprising power factor correction circuit arrangement

Abstract

A mechanism for controlling a supply voltage of a switched mode power supply is designed to compensate for AC mains ripple in a PFC output signal generated by a power factor converter. The regulation circuit is used to synchronize an amplitude of the supply voltage with an amplitude of an offset signal generated by the switched mode power supply, the offset signal being used to compensate for AC mains ripples in the PFC output signal. The synchronization adjusts the difference between the voltage amplitude of the adjusted supply voltage and the voltage amplitude of the offset signal, thereby controlling the power loss of the switched mode power supply.

Description

Technical Field

[0001] The present invention relates to the field of driver devices, in particular to a driver device comprising a power factor correction circuit device. Background Art

[0002] Driver devices are typically used to power a load, such as a light emitting element. Typically, the driver device will be capable of converting an (e.g., AC) input power to an (e.g., DC) output power suitable for powering the load. Some driver devices include power factor correction circuitry to modify or adjust the power factor of a power factor correction (PFC) output signal that defines the output power provided to the load or on a bus.

[0003] The PFC output signal may be a signal across the output capacitor of the power factor correction circuit device so that it is smoothed to simulate a DC signal. However, the power factor correction circuit device is a slow response conversion circuit device that regulates its output by sensing the average output. Therefore, the PFC output signal will maintain a ripple (voltage or current) of approximately 100 / 120Hz, with the exact frequency depending on the ripple of the AC input power supply (typically approximately 50 / 60Hz). Reducing or attenuating the magnitude of the ripple in the PFC output signal would be advantageous, such as eliminating or compensating for the ripple, particularly for LED lighting, because the output luminous flux of the LED lighting device is highly sensitive to the power supplied to the LED lighting device. If not regulated, the ripple of the PFC output signal will cause a corresponding ripple in the brightness of the light output by the LED, which will cause a perceptible flicker to be perceived by humans or capture devices (such as cameras).

[0004] A common approach in the art to overcome this problem is to use a second conversion circuit arrangement cascaded from the power factor correction circuit arrangement. This topology can be labeled a two-stage conversion circuit arrangement. The second conversion circuit arrangement conditions the PFC output signal into a further stabilized signal. One disadvantage of such a two-stage conversion circuit arrangement is the high material cost and high space requirement, since the second conversion circuit arrangement must process the entire PFC output signal, which means that its power rating is quite high, requiring large and materially expensive components.

[0005] It has been proposed to use a switching converter circuit device or a switch mode power supply at the output of the power factor correction circuit device, wherein the switching converter circuit device is used to compensate only the AC component of the PFC output signal, rather than the entire PFC output signal. This means that the switching converter circuit device has a relatively small power rating and is also low in cost and size compared to a two-stage conversion circuit device. US20140252973A1 and US2017 / 0288557 A1 describe a suitable prior art example. Compared to the above-mentioned two-stage, this topology is usually called / labeled as a 1.5-stage or 1.25-stage conversion circuit device.

[0006] There is a continuing desire for improved drive devices. Summary of the invention

[0007] The invention is defined by the claims.

[0008] For LED applications, the driver device may be a universal driver and connected to a specific one of various potential / possible LED loads / modules with different LED forward voltages. Even after the driver device is connected to a specific LED module, the LED forward voltage of the module may be dynamically changed, for example for dimming or color changing, when one or more LEDs in the LED module are short-circuited or bypassed. In this case, the output voltage of the driver device and, in fact, the output voltage of the switching circuit device may vary at least due to the selection of the LED module, or even in the dynamic operation of the driver device and the LED module.

[0009] The inventors have determined that the average difference between the supply voltage of the switch mode power supply and the voltage of the offset signal (generated by the switch mode power supply to compensate for the AC component of the PFC output signal) may be large, especially in the case where the load powered by the driver requires a lower voltage, such as, for example, when the LED module acting as the load is a low voltage LED module but the input of the supply voltage of the switch mode power supply is very large. It has been recognized that this will significantly affect the power efficiency of the switch mode power supply.

[0010] The inventors have also determined that the supply voltage of the switched mode power supply will inherently be out of phase with the offset signal generated by the switched mode power supply to compensate for the AC component of the PFC output signal. This is because the offset signal may be out of phase with the PFC output signal, causing them to superimpose into a smooth signal, and because the PFC output signal may be in phase with the input of the switched mode power supply, particularly where the supply voltage is generated using magnetic coupling to a winding providing AC mains. As the input voltage and output voltage are out of phase, there is a significant impact on the power loss of the switched mode power supply.

[0011] One or both of these problems may be overcome by using the method proposed by the present disclosure, i.e. providing a regulation circuit to regulate the voltage supply of a switched mode power supply. The regulation may be performed to synchronize the voltage source (e.g. in terms of average voltage and / or instantaneous voltage (in other words, phase)) with an offset signal generated by the switched mode power supply. This may significantly reduce power losses in the switched mode power supply and improve the efficiency of the drive device.

[0012] According to an example of one aspect of the present invention, a driver device is provided, which includes a power factor correction (PFC) converter, the PFC converter including: a first input interface, configured to receive AC mains; a PFC conversion circuit device, configured to perform power factor correction on the AC mains and generate a PFC output signal having a ripple corresponding to the ripple of the AC mains; and a first output interface, configured to provide the PFC output signal.

[0013] The driver device also includes a power supply for providing a power supply voltage from the AC mains; and a switch mode power supply device, which includes: a second input interface coupled to the power supply and configured to receive the power supply voltage from the power supply; a second output interface electrically connected in series with the first output interface; and a switch mode power supply configured to convert the power supply voltage into an offset signal provided to the second output interface, the offset signal being configured to superimpose the PFC output signal to generate a superimposed signal and compensate for the ripple corresponding to the AC mains.

[0014] More importantly, the driver device also includes a regulation circuit, which is electrically coupled between the power supply and the second input interface and is configured to regulate the power supply voltage provided to the second input interface to be synchronized with the offset signal, thereby regulating the difference between the voltage amplitude of the regulated power supply voltage and the voltage amplitude of the offset signal.

[0015] Embodiments provide a mechanism for regulating or modifying the supply voltage used by a switch mode power supply to provide an offset signal for synchronization or otherwise align with an offset signal. Since the input and output of the switch mode power supply are synchronized, the voltage difference across the switch mode power supply is reduced, and these methods can significantly reduce the power loss caused by the switch mode power supply, thereby providing a more efficient driver device.

[0016] An embodiment utilizes a regulation circuit coupled between the power supply and an input interface of the switch mode power supply to regulate a voltage provided by the power supply. The regulation circuit thereby controls the voltage of the voltage source.

[0017] The superimposed signal is a combination of the PFC output signal and the offset signal, that is, the PFC output signal superimposed with the offset signal. In other words, the superimposed signal is a superposition of the PFC output signal and the offset signal.

[0018] The regulating circuit may be adapted to regulate the supply voltage synchronously with the offset signal so that the voltage amplitude of the regulated supply voltage and the voltage amplitude of the offset signal are regulated, preferably reduced, thereby controlling, preferably reducing, the power loss of the switched mode power supply. The method provides an effective mechanism for controlling or modifying the power loss of the switched mode power supply by controlling the difference between the input voltage and the output voltage.

[0019] The regulation circuit may include a sensing circuit for sensing the voltage of the offset signal and / or the voltage of the superimposed signal and the offset signal. The regulation circuit may be configured to adjust the supply voltage in response to the sensed voltage of the offset signal and / or the voltage of the superimposed signal. In this way, the regulation circuit is able to adapt and respond to changes in the offset signal or changes in the voltage drawn by the load powered by the driver device. This provides a method for dynamically and automatically responding to actively control or reduce power losses in a switched mode power supply. Please note that there may be alternatives to this embodiment. For example, the driver device may be provided with a user interface for receiving (via user input from a user) settings related to the amplitude of the offset signal or the superimposed signal, and the regulation circuit may be adapted to adjust the supply voltage according to the settings.

[0020] The regulation circuit can be configured to: provide a regulated supply voltage of a second voltage for a first voltage of one of the offset signal or the superimposed signal; and provide a regulated supply voltage of a fourth voltage for a third voltage of one of the offset signal or the superimposed signal, wherein the first voltage is greater than the third voltage and the second voltage is greater than the fourth voltage. This method provides a reactive or dynamically responsive regulation circuit that reacts to any continuous changes in the offset signal and / or the power consumed by the load, thereby improving the power efficiency of the entire driver device. If the required output voltage is larger, the supply voltage will be regulated to a larger input voltage so that the switch mode power supply can operate; and if the required output voltage is smaller, the supply voltage will be regulated to a smaller input voltage so that the power loss on the switch mode power supply is smaller.

[0021] The first voltage, the second voltage, the third voltage, and the fourth voltage may be instantaneous voltages or average voltages.

[0022] In some more specific examples, the regulation circuit is adapted to regulate the average value of the supply voltage to be synchronized with the average value of the offset signal. Thus, the embodiment regulates the average value of the supply voltage in synchronization with the average value of the offset signal. This can reduce the difference between the average values / voltages at the input and output of the switched mode power supply, thereby improving the efficiency of the switched mode power supply. In particular, if the average voltage of the offset signal is lower, the losses in the switched mode power supply can be reduced.

[0023] In some examples, the PFC conversion circuit device includes a transformer having a primary winding electrically coupled to a first input interface and a first secondary winding magnetically coupled to the primary winding and electrically coupled to a first output interface; and the power supply includes a second secondary winding magnetically coupled to the primary winding.

[0024] The regulation circuit may be configured to provide an adjustable ratio or proportion of the average voltage across the second secondary winding to the second input interface as the average voltage of the supply voltage. This provides an effective and space efficient mechanism to control the average voltage of the supply voltage, for example, for synchronizing the average voltage of the supply voltage with the average voltage of the offset signal for improving the power efficiency of the switch mode power supply.

[0025] The regulation circuit may include a switching device coupled between the second secondary winding and the second input interface, the switching device being configured to switch between at least two configurations, the at least two configurations comprising: a first configuration, in which an average voltage across the second secondary winding at a first ratio or proportion is provided to the second input interface as an average voltage of the power supply voltage in the first configuration; and a second configuration, in which an average voltage across the second secondary winding at a second ratio or proportion lower than the first ratio or proportion is provided to the second input interface as an average voltage of the power supply voltage in the second configuration.

[0026] The switching device provides an efficient and energy-saving mechanism for controlling or varying the average voltage of the supply voltage. In particular, the power losses in such a switching device are extremely low. This is achieved by providing a corresponding ratio or portion of the secondary winding to provide a corresponding regulated supply voltage for the second input interface.

[0027] The regulation circuit can be configured to regulate the average value of the power supply voltage synchronously with the average value of the offset signal in the following manner: in response to the voltage of the offset signal being at or above a first predetermined voltage, operating the switching device in a first configuration so that the average voltage of the regulated power supply voltage is higher; and in response to the voltage of the offset signal being lower than the first predetermined voltage, operating the switching device in a second configuration so that the average voltage of the regulated power supply voltage is lower.

[0028] This provides a mechanism to reduce the average voltage of the supply voltage when the offset signal has a lower voltage. This reduces the difference between the supply voltage and the voltage of the offset signal, thereby providing a more efficient switched mode power supply, while also allowing the supply voltage to be increased when the offset signal requires more voltage (e.g., to ensure that the required voltage requirements can be met). This provides a supply voltage that reacts dynamically to increase the efficiency of the switched mode power supply while still ensuring that the voltage requirements of the SMPS are met.

[0029] The regulating circuit can be configured to increase the average voltage of the power supply voltage as the average voltage of the superimposed signal and / or the offset signal increases. In this way, the average voltage of the power supply voltage can track the average voltage of the offset signal. The advantages of this approach have been previously identified.

[0030] As an alternative or in addition to synchronously regulating the average voltage, the regulating circuit can be adapted to regulate the instantaneous value of the supply voltage to be synchronous or in phase with the instantaneous value of the offset signal. Thus, the phase of the voltage source can track or be synchronized with the phase of the offset signal, and the real-time input / output voltage difference is reduced. This improves the efficiency of the switch mode power supply by ensuring a consistent difference between the input and output of the SMPS.

[0031] The regulation circuit may include: a buffer circuit electrically coupled to the power supply and adapted to generate a bias voltage having a substantially stable amplitude; and an inverting circuit configured to subtract a voltage proportional to a voltage of the PFC output signal from the bias voltage to produce a regulated supply voltage for the second input interface.

[0032] If present, the switching device can provide a regulated average voltage of the supply voltage (by defining the magnitude of the bias voltage) and store it in the buffer circuit, for example, to track the average voltage of the offset signal, while the inverter circuit can provide a regulated instantaneous voltage of the supply voltage, for example, to track the instantaneous voltage of the offset signal. This combination significantly improves the power efficiency of the SMPS.

[0033] As previously described, in some examples, the PFC conversion circuit device includes a transformer having a primary winding electrically coupled to a first input interface and a first secondary winding magnetically coupled to the primary winding and electrically coupled to a first output interface; and the power supply includes a second secondary winding magnetically coupled to the primary winding, so that a voltage across the second secondary winding varies in proportion to a voltage of the PFC output signal.

[0034] In such an example, the inverting circuit can be configured to subtract a voltage proportional to the voltage across the second secondary winding from the bias voltage to produce the supply voltage for the second input interface. This approach means that the phase of the supply voltage will be different from the phase of the PFC output signal and therefore synchronized or in phase with the offset signal.

[0035] Also proposed is an electronic device comprising a driver device as proposed and / or claimed herein; and a load connected to the first output interface and the second output interface and configured to be powered by the superimposed signal.

[0036] The load may include a light emitting device, which may optionally include one or more light emitting diodes.

[0037] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] For a better understanding of the invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0039] Figure 1 The figure shows the existing drive device;

[0040] Figure 2 The figure shows the waveform of the existing driving device;

[0041] Figure 3 The proposed driver device is illustrated;

[0042] Figure 4 illustrates the waveforms of the proposed driver device in the first scenario; and

[0043] Figure 5 The waveforms of the proposed driver device in the second scenario are illustrated. DETAILED DESCRIPTION

[0044] The present invention will be described with reference to the accompanying drawings.

[0045] It should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the apparatus, system and method, are for illustrative purposes only and are not intended to limit the scope of the invention. These and other features, aspects and advantages of the apparatus, system and method of the invention will be better understood through the following description, the appended claims and the accompanying drawings. It should be understood that the drawings are merely schematic and not drawn to scale. It should also be understood that the same reference numerals are used throughout the drawings to indicate the same or similar components.

[0046] The present invention provides a mechanism for controlling the supply voltage of a switch mode power supply, which is designed to compensate for the AC mains ripple in the PFC output signal generated by a power factor converter. A regulating circuit is used to synchronize the amplitude of the supply voltage with the amplitude of an offset signal generated by the switch mode power supply, which offset signal is used to compensate for the AC mains ripple in the PFC output signal.

[0047] To better understand the context, Figure 1 A conventional driver device 100 is illustrated. The driver device 100 is configured to provide a load power supply signal, which may optionally be marked as a superimposed signal, to a load LED separate from the driver device.

[0048] The driver device 100 may form part of an electronic device 10 comprising the driver device 100 and a load LED. For example, the load LED may comprise one or more light emitting diodes or light emitting diode devices. Other suitable loads will be clear to those skilled in the art.

[0049] The driver device 100 includes a power factor correction converter 110 , a switch mode power supply device 120 and a regulation circuit 130 .

[0050] The power factor correction converter 110 comprises a first input interface 111 configured to receive AC mains AC+, AC-.

[0051] The power factor correction converter 110 further includes a PFC conversion circuit arrangement 112 configured to perform power factor correction on the AC mains to generate a PFC output signal V( C1 ).

[0052] The power factor correction converter 110 further comprises a first output interface 113 configured to provide a PFC output signal V(C1). For a better understanding of the context, it is assumed that the average amplitude of the PFC output signal V(C1) is constant.

[0053] The PFC output signal V(C1) will have a (voltage) ripple corresponding to the ripple of the AC mains. Thus, the ripple may follow the inherent 50 / 60 Hz sinusoidal waveform of the AC mains. Typically, a power factor correction converter is configured to correct or account for distortion in the power supplied to or drawn by the load. Typically, the output of the power factor correction circuit device follows the inherent 50 / 60 Hz sinusoidal waveform of the AC mains, resulting in AC mains ripple in the PFC output signal V(C1).

[0054] In order to at least partially reduce the high frequency switching signal in the PFC output signal V(C1), the power factor conversion circuit device may include a first output capacitor C1 connected across the first output interface 113, so that the PFC output signal V(C1) is a nearly continuous signal that can be drawn by the load connected to the first output interface 112. However, the PFC output signal V(C1) will still have a low frequency ripple, representing the residual periodic variation caused by the AC mains (which has not been suppressed). In fact, the PFC converter is designed to maintain a low frequency ripple, otherwise the output will not follow the input.

[0055] In the example shown, the PFC conversion circuit arrangement comprises a flyback converter, which is an example of a buck-boost converter. P and the first secondary winding W S1 The diode D1 connects the first secondary winding W S1 is coupled to the first output interface, and thereby coupled to the first output capacitor C1. P The current is controlled by the switching element S1.

[0056] However, other suitable PFC conversion circuit device layouts for embodiments are well known in the art. For example, the PFC conversion circuit device 112 may be or include a boost converter, a buck converter and / or a buck-boost converter. Those skilled in the art will appreciate that any other type of converter is also applicable as long as it can provide a PFC function.

[0057] In any case, the PFC conversion circuit device includes a primary winding W P and the first secondary winding W S1 The transformer is formed, for example, to electrically isolate at least the AC mains AC+, AC- from the rest of the driver device and / or the load LED.

[0058] The switch mode power supply device 120 includes a power supply W coupled to the S2 The second input interface 121 is configured to receive a power supply voltage V(C3) from a power supply. Therefore, the power supply voltage V(C3) is a voltage between a first terminal 121A of the second input interface 121 and a second terminal 121B of the second input interface 121. Here, the power supply W S2 The primary winding W is magnetically coupled to the power conversion circuit device 112. P Due to the magnetic coupling of the windings, the supply voltage V(C3) tends to be in phase with the PFC output voltage V(C1).

[0059] The switch mode power supply device 120 further includes a second output interface 122 electrically connected in series with the first output interface 121 .

[0060] The switch mode power supply device 120 further comprises a switch mode power supply 123 configured to convert the power supply voltage into an offset signal V(C2) provided to the second output interface 122. The offset signal is configured to superimpose the PFC output signal V(C1) and compensate for ripple corresponding to the AC mains.

[0061] The switch mode power supply 123 is configured to compensate for ripples in the PFC output signal V(C1). More specifically, the switch mode power supply is configured to generate an offset signal V(C2), which is then superimposed with the PFC output signal V(C1) to produce a superimposed signal, which is here equal to V(C1)+V(C2). The superimposed signal is provided to or drawn by the load LED and can thus be alternatively labeled as a load supply signal. The offset signal V(C2) thereby compensates for the ripples (of the AC mains) in the PFC output signal V(C1), thereby smoothing the power provided to the load LED.

[0062] The offset signal V(C2) is provided to the second output interface 122. In the example shown, the second output interface is connected in series with the first output interface 112. A load LED may be connected or connected across the first output interface 112 and the second output interface 122. Thus, the superimposed signal may be a signal across the first output interface and the second output interface.

[0063] A second output capacitor C2 may be connected between the terminals of the second output.

[0064] The switch mode power supply can be implemented by a current control loop for controlling its output according to a sensed current flowing through a load LED powered by a load power signal. More specifically, the operation of the switch mode power supply 120 can be responsive to the current through the load LED, for example, the voltage across a sense resistor (not shown) connected in series with the load LED. The offset signal V(C2) shown is the resultant voltage of the current control loop.

[0065] In this way, the driver device may comprise a current control loop adapted to sense the current of the superimposed signal and to control the switched mode power supply to adjust the offset signal V(C2) such that the sensed current follows a current reference, which is optionally substantially constant.

[0066] In particular, the switch mode power supply can be configured to control the offset signal V(C2) so that the current through the load LED is aligned with the current reference. The current reference is preferably constant or nearly constant, i.e. substantially constant. This process is called constant current regulation. This means that the offset signal V(C2) will track the AC mains ripple in the PFC output signal V(C1), thereby compensating for this ripple in the PFC output signal.

[0067] The control of the switch mode power supply 120 may be a high speed control loop to ensure that the offset signal V( C2 ) varies with the ripple in the PFC output signal V( C1 ).

[0068] In one example, if a load with a smaller forward voltage (e.g., a first LED) is replaced with a load with a larger forward voltage (e.g., a second LED with a larger forward voltage), first, the load current will be less than the current reference value, and then the switch mode power supply 120 will increase its output voltage. The system will converge to a state where the PFC output signal and the offset signal together output the same load current equal to the current reference.

[0069] Examples of suitable switched mode power supplies include a buck converter or a buck-boost converter.Other examples will be clear to those skilled in the art.

[0070] Methods for controlling a switched mode power supply to compensate for AC mains ripple in a PFC output signal are established in the art, for example as shown in US 2017 / 0288557 A1.

[0071] In the prior art, the regulating circuit 130 includes a rectifying diode D5 and an input capacitor C3 connected across the terminals of the second input interface 121. The input capacitor C3 is configured to smooth the rectified signal provided by the rectifying diode, for example, to attenuate high frequencies. The size of the input capacitor C3 will not be sufficient to attenuate the AC mains voltage ripple.

[0072] For better understanding, Figure 2 Waveforms of a driver device 100 known in the art are shown.

[0073] The first waveform 210 illustrates the voltage of the PFC output signal V(C1). The second waveform 220 illustrates the voltage of the supply voltage V(C3) across the second input terminal. The third waveform illustrates the voltage of the offset signal V(C2) across the second output terminal.

[0074] like Figure 2 As shown, for example, when the switch mode power supply is a buck converter, the voltage of the supply voltage V(C3) and the voltage of the offset signal V(C2) are out of phase with each other. In particular, the supply voltage V(C3) will follow the PFC output signal V(C1). Therefore, when the PFC output signal V(C1) and therefore the supply voltage V(C3) are at a valley or trough 210, the offset signal V(C2) is at a peak 220 to compensate for the ripple in the PFC output signal.

[0075] It has been recognized that this will significantly affect the efficiency of the switched mode power supply because the input and output of the switched mode power supply have large voltage differences at peaks and valleys, and the difference between the input and output is not consistent.

[0076] In addition, since the average voltage of the PFC output signal voltage is usually fixed, the average voltage of the power supply voltage V(C3) is almost constant. Therefore, the change in the average voltage required by the offset signal will significantly affect the average voltage difference between the power supply voltage V(C3) and the offset signal V(C2), which will significantly increase the power loss of the switch mode power supply.

[0077] When the second LED (having a relatively large forward voltage) is connected, the offset signal V(C2) shown by the waveform 230 (and the load power supply signal or superimposed signal shown by the waveform 200) is relatively large. Therefore, the difference between the power supply voltage 220V(C3) and the offset signal 230 is still small or within the acceptable boundary. However, when the first LED (having a relatively low forward voltage) is connected, the offset signal V(C2) shown by the waveform 230' (and the load power signal shown by the waveform 200') is small, the difference between the power supply voltage 220V(C3) and the offset signal 230' becomes large, and causes a larger / more significant power loss in the switch mode power supply, e.g., outside the acceptable boundary.

[0078] Another problem is that the power supply voltage 220 and the offset signal 230 or 230 ′ are out of phase when the power supply voltage 220 is at a peak value and the offset signal 230 or 230 ′ is at a valley value, so it causes power loss in the switch mode power supply.

[0079] The proposed technique provides a mechanism for overcoming these problems. In particular, it is suggested to use a regulation circuit that is capable of modifying or changing the supply voltage V(C3) input to the switch mode power supply synchronously or synchronously (e.g., in terms of phase and / or average voltage) with an offset signal V(C2) output by the switch mode power supply.

[0080] The present disclosure proposes a new regulation circuit for use with a driver device. The regulation circuit is configured to substantially regulate the supply voltage V(C3) provided to the second input interface of the switch mode power supply device in synchronization with an offset signal. Thus, the phase and / or amplitude of the supply voltage can be modified or changed in synchronization with the change of the phase and / or amplitude of the offset signal. The term "substantially regulated" here means that the amplitude of the supply voltage is regulated by more than 10%, preferably more than 25%, excluding insignificant filtering or smoothing.

[0081] Figure 3 A driving device 300 according to an embodiment is illustrated. As previously described, the driver device 300 is configured to provide a load power supply signal (or a superimposed signal) to a load LED that is separate from the driver device.

[0082] The driver device 300 may form part of an electronic device 30 including the driver device 300 and a load LED. The electronic device 30 is another embodiment. For example, the load LED may include one or more light emitting diodes or light emitting diode devices. Other suitable loads will be clear to those skilled in the art.

[0083] The driving device 300 differs from the previously described driving devices by the configuration of the regulating circuit 330. The regulating circuit 330 allows both the (average) magnitude of the supply voltage V(C3) and / or the phase of the supply voltage V(C3) to be regulated.

[0084] Therefore, the regulation circuit 330 is configured to regulate the supply voltage provided by the power supply 340 to generate a regulated supply voltage (which is received by the second input interface 121 (121A and 121B)).

[0085] More specifically, the regulating circuit 330 is adapted to regulate the supply voltage V(C3) synchronously with the offset signal V(C2) so that the difference between the voltage amplitude of the regulated supply voltage and the voltage amplitude of the offset signal is regulated. This allows controlling the power loss of the controlled switched mode power supply.

[0086] The regulation circuit is configured to regulate an average value of the power supply voltage such that the average value of the regulated power supply voltage is synchronized with an average value of the offset signal.

[0087] Additionally or alternatively, the regulation circuit is configured to invert a phase of the supply voltage such that a phase of the regulated supply voltage is synchronized with a phase of the offset signal.

[0088] The power supply 340 of the regulating circuit includes a first terminal W E1 and the second end W E2 The second secondary winding W S21 , W S22 The second secondary winding is magnetically coupled to the primary winding W of the PFC conversion circuit device 112 P As previously described, the voltage across the second secondary winding and any tapped portion thereof will be the same as the voltage across the first secondary winding W of the PFC conversion circuit device 112. S1 The voltages change in phase.

[0089] The second secondary winding consists of (at least) two secondary winding sections connected in series (ie, the first secondary winding section W S21 and the second secondary winding part W S23 )form.

[0090] In order to regulate the supply voltage synchronously with the offset signal in terms of average value, the regulation circuit 330 is configured to modify or change the effective number of turns / ratio of the second secondary winding that contributes to the supply voltage provided to the second input interface. This approach effectively provides an adjustable ratio or proportion of the magnitude of the voltage across the second secondary winding to the magnitude of the regulated supply voltage provided to the second input interface.

[0091] In order to adjust the magnitude of the power supply voltage provided to the second input interface 121, the adjustment circuit 330 includes a second secondary winding W coupled to the second secondary winding W. S21, W S22 A switch device 331 between the first input interface and the second input interface.

[0092] The switching arrangement comprises a switched capacitor C4. The voltage across the switched capacitor C4 defines or controls the average voltage of the (regulated) supply voltage provided to the second input interface. Hence, the voltage V(C4) across the switched capacitor may be labeled as a bias voltage.

[0093] A first plate C4A of the switched capacitor C4 is connected to a first terminal 121A of the second input interface 121. A second, different plate C4B of the switched capacitor C4 is connected to a second secondary winding W S21 , W S22 The second end W E2 .

[0094] The switch device 331 includes a first switch diode pair S2, D2 and a second switch diode pair S3, D3. The two switch diode pairs are connected from the second secondary winding W S21 , W S22 Connected to the first plate C4A of the switched capacitor C4. Each switching diode pair is controllable (e.g., by a switch controller) to controllably allow or prevent current from flowing from the second secondary winding to the first plate C4A of the switched capacitor (via the switching diode pair). Each diode in the diode pair prevents or limits current from flowing back from the first plate of the switched capacitor to the second secondary winding.

[0095] The first switch diode pair S2, D2 connects the second secondary winding W S21 , W S22 The first end W E1 The first terminal W is connected to the first plate C4A of the switched capacitor. Compared to the second end connected to the second plate C4B of the switched capacitor C4, the first terminal W E1 is the second secondary winding W S21 , W S22 the other end.

[0096] The second switch diode pair S3, D3 connects the second secondary winding W S21 , W S22 From the second secondary winding W located between the first end and the second end of the second secondary winding S21 , W S22 Middle position / middle tap W IP Connected to the first plate C4A of the switched capacitor C4. In the example shown, the intermediate position W IP is the first winding part W located in the second secondary winding S21 The position between the two ends.

[0097] The average voltage across the switch capacitor C5 is larger when only the first switch diode pair S2, D2 conducts current than when only the second switch diode pair S3, D3 conducts current. This is because the second secondary winding W is larger when only the first switch diode pair S2, D2 conducts current than when only the second switch diode pair S3, D3 conducts current. S21 , W S22 The effective turns ratio of the second secondary winding (ie, the number of turns that contribute to the voltage provided to the switched capacitor C5) is larger. Therefore, by controlling which switching diode pair is active, the effective turns ratio of the second secondary winding (and thereby its voltage) can be modified.

[0098] In other words, depending on which switching diode pair is active and allowing current to flow, different ratios or proportions of the (maximum potential average) voltage across the second secondary winding may be provided to the first plate C4A of the switched capacitor.

[0099] Thus, the magnitude of the average voltage across the switched capacitor can be controlled by controlling which switching diode pair is active (ie, allowing current to flow).

[0100] The operation of switches S2, S3 may be controlled by a switch controller 335. In particular, the switch controller may control which switching diode pair conducts current in response to the voltage of the offset signal or the superimposed signal.

[0101] Thus, the switching device can be configured to switch between at least two configurations, the at least two configurations comprising: a first configuration, in which a first ratio or proportion of the magnitude of the voltage across the second secondary winding is provided to the second input interface as the magnitude of the regulated power supply voltage; and a second configuration, in which the magnitude of the voltage across the second secondary winding of a second ratio or proportion lower than the first ratio or proportion is provided to the second input interface as the magnitude of the regulated power supply voltage.

[0102] In other words, the switching device is configured to be able to switch between a first configuration and a second configuration, in which the average voltage across the second secondary winding of a first ratio or proportion is provided to the second input interface as the average voltage of the power supply voltage; in the second configuration, the average voltage across the second secondary winding of a second ratio or proportion lower than the first ratio or proportion is provided to the second input interface as the average voltage of the power supply voltage.

[0103] The switch device may include a sensing circuit 336, 336' to sense the voltage of the offset signal and / or the voltage of the superimposed signal. In the example shown, the sensing circuit 336 senses the voltage of the offset signal. Alternatively, the sensing circuit 336' senses the voltage of the superimposed signal.

[0104] The regulation circuit (via the switch controller) may be configured to regulate the supply voltage in response to the sensed voltage of the offset signal and / or the voltage of the superimposed signal.

[0105] The regulation circuit (via the switch controller) can be configured to: provide a regulated supply voltage of a second voltage for a first voltage of one of the offset signal or the superimposed signal; and provide a regulated supply voltage of a fourth voltage for a third voltage of one of the offset signal or the superimposed signal.

[0106] The first voltage is greater than the third voltage and the second voltage is greater than the fourth voltage.

[0107] In this way, the average value of the power supply voltage can be adjusted in synchronization with the average value of the offset signal.Therefore, the first voltage, the second voltage, the third voltage and the fourth voltage can be average voltages.

[0108] In some examples, the switching device is configured to: operate in a first configuration in response to a voltage of the offset signal being equal to or higher than a first predetermined voltage so that the regulated power supply voltage is higher; and operate in a second configuration in response to a voltage of the offset signal being lower than the first predetermined voltage so that the regulated power supply voltage is lower.

[0109] As previously described, the operation of the switching device may be performed by the switch controller 335 .

[0110] For example, when the switch controller 335 senses a larger voltage (e.g., a voltage greater than a threshold) from circuit 336 or 336', it closes switch S2 and opens switch S3 to provide a regulated larger supply voltage; otherwise, it opens switch S2 and closes switch S3 to provide a regulated smaller supply voltage.

[0111] The capacitance of the switched capacitor C4 is large enough so that when only one of the switched diode pairs allows current to flow, the voltage across the switched capacitor has a substantially constant / stable amplitude. It will be appreciated that the value of this substantially constant / stable amplitude will change if the active switched diode pair is switched. Thus, the term "constant / stable" simply means that the amplitude is fixed relative to a corresponding selected ratio of the voltage on the secondary winding.

[0112] In this way, the switching device and the switched capacitor act as a buffer circuit which is electrically coupled to the second secondary winding and is adapted to generate a bias voltage V(C4) having a substantially constant amplitude in synchronization with the offset signal or the average value of the superimposed signal.

[0113] In addition, it is desirable to adjust the phase of the power supply voltage to match or align with the phase of the offset signal, wherein the phase of the power supply voltage on the secondary winding is originally out of phase with the offset signal, or even inversely phased. The present application proposes to invert the phase of the power supply voltage, and the regulating circuit includes an inverting circuit 332. The inverting circuit is configured to subtract a voltage proportional to the voltage across the second secondary winding from a constant bias voltage (generated by a switching device or a buffer circuit) to generate a regulated power supply voltage for the second input interface. Therefore, the regulated power supply voltage is in phase with the offset signal.

[0114] In the example shown, the inverting circuit includes a diode D4, a capacitor C5 and an inverting capacitor C3. A first plate C5A of the capacitor C5 is connected to the second terminal 121B of the second input interface 121. A second plate C5B of the capacitor C5 is connected to the second end W of the second secondary winding. E2 , and is therefore connected to the second plate C4B of the switched capacitor C4. The second secondary winding W S21 , W S22 The second end W E2 Also the second winding part W S22 The anode of the inverting capacitor C3 is connected to the anode or first plate C4A of the capacitor C4; and the cathode of the inverting capacitor is connected to the anode or first plate C5A of the capacitor C5. The voltage between the terminals of the second input interface 121 (i.e., the inverting capacitor C3) (i.e., the regulated power supply voltage) is equal to V(C4)-V(C5).

[0115] Diode D4 connects the second winding section W S22 The first end W E3 (with the second end W E2 The other end of the second winding (different from the first) is connected to the first plate C5A of the capacitor C5. The capacitance of the capacitor C5 (e.g., <100 μF) is sized small enough so that the instantaneous voltage across the capacitor follows the PFC output signal or is in phase with it (e.g., with the AC mains ripple), i.e., it is not smoothed to a constant voltage as performed by the switched capacitor C4. The size of the inverting capacitor C3 is also small enough so that the voltage V(C4) across the capacitor C3 still carries the inverted phase of V(C5), and therefore V(C4)-V(C5) follows the phase of the offset signal.

[0116] Since the voltage between the terminals of the second input interface (i.e., the regulated supply voltage) is equal to V(C4)-V(C5), this results in the regulated supply voltage having an anti-phase relative to the PFC output signal. Therefore, the regulated supply voltage is in phase with the offset signal V(C2).

[0117] Typically, the switch device 331 allows the average voltage of the (regulated) supply voltage at the second input interface 121 to follow or be synchronized with at least the average voltage of the offset signal. Thus, if the average voltage of the offset signal increases (e.g., exceeds a predetermined threshold), the average voltage of the regulated supply voltage may increase. Similarly, if the average voltage of the offset signal decreases (e.g., is below a predetermined threshold), the average voltage of the regulated supply voltage may decrease.

[0118] Furthermore, the inversion circuit 321 also allows the instantaneous voltage of the (regulated) supply voltage at the second input interface 121 to follow or be synchronized with the instantaneous voltage of at least the offset signal. In other words, the inversion circuit allows the phase of the (regulated) supply voltage to match the phase of at least the offset signal.

[0119] For better understanding, Figure 4 and Figure 5 A collection of waveforms in different scenarios are illustrated. The scale of the two figures is the same and can therefore be compared to each other to illustrate that the average value of the regulated supply voltage V(C3) follows the average value of the offset signal.

[0120] Both figures illustrate: a first waveform 410 representing the voltage of the PFC output signal V(C1) across the first output interface 113; a second waveform 420 representing the voltage V(C4) across the switch capacitor C4; a third waveform 430 representing the voltage V(C5) across the capacitor C5; a fourth waveform 440, 440' representing the voltage V(C3) of the power supply voltage provided to the second input interface; and a fifth waveform 450, 450' representing the voltage V(C2) of the offset signal. Also waveform 200 or 200' shows the voltage of the superimposed signal.

[0121] Figure 4 A scenario is illustrated where the (average) voltage drawn by the load LED is higher, causing the average voltage of the offset signal V(C2) to be correspondingly higher.

[0122] Figure 5 The diagram shows a scenario where the (average) voltage drawn by the load LED is low ( Figure 4 ), so that the average voltage of the offset signal V(C2) is correspondingly lower.

[0123] In both cases, the phase of the power supply voltage V(C3) is adjusted to be synchronized with the voltage of the offset signal.

[0124] When the average voltage V(C3) of the offset signal is lower, the average voltage of the regulated supply voltage will also be reduced, for example, by switching from causing the first switch diode pair S2, D2 to conduct current to causing the second switch diode pair S3, D3 to conduct current. This will reduce the average value of the voltage V(C4) across the switch capacitor C4, thereby reducing the average value V(C3) of the regulated supply voltage (which is equal to V(C4)-V(C5)). Therefore, the difference between V(C3) and V(C2) is limited, and power losses are reduced.

[0125] Reference again Figure 3 In some embodiments, the inverting circuit may be omitted. In such an example, the second terminal 121B of the second input interface 121 may be directly connected to the second end W of the secondary winding. E2 In such an example, the switched capacitor C4 may also be omitted. This approach would result in an embodiment in which the average voltage of the supply voltage V(C3) could be varied (via the switching arrangement), for example, to track or synchronize with the average voltage of the offset signal. However, the phase of the supply voltage V(C3) would not be synchronized with the phase of the offset signal, so this approach is less advantageous.

[0126] Similarly, in some embodiments, the switching diode pair may be omitted. In this scenario, the first plate C4A of the switching capacitor will be directly connected to the first terminal W of the secondary winding. E1 , for example via a diode. This would produce a supply voltage that has a phase that tracks the offset signal or is synchronized with it, but would not have an adjustable average voltage. This is also less advantageous than the electronic arrangement shown, since there would be greater power losses.

[0127] An electronic device 30 is also proposed, comprising any driver device 300 described herein and a load LED configured to be powered by a load power supply signal generated by such a driver device. Thus, the load is connected to the first output interface 113 and the second output interface 122 of the driver device.

[0128] For example, the load may include one or more light emitting diodes or light emitting diode devices.Other suitable loads will be clear to those skilled in the art.

[0129] Variations to the disclosed embodiments may be understood and effected by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality.

[0130] The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0131] If the term "suitable for" is used in the claims or the specification, it should be noted that "suitable for" is intended to be equivalent to "configured to". If the term "arrangement" is used in the claims or the specification, it should be noted that the term "arrangement" is intended to be equivalent to the term "system", and vice versa.

[0132] Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. A driver device (300), comprising: A power factor correction (PFC) converter (110) comprises: A first input interface (111) configured to receive AC mains power (AC+, AC-); A PFC conversion circuit device (112) is configured to perform power factor correction on the AC mains and generate a PFC output signal (V(C1)), the PFC output signal having a ripple corresponding to the ripple of the AC mains; and A first output interface (113), configured to provide the PFC output signal; A power supply (340) for providing a power supply voltage (V(C3)) from the AC mains; A switch mode power supply device (120), comprising: a second input interface (121), coupled to the power supply and configured to receive the power supply voltage from the power supply; A second output interface (122), electrically connected in series with the first output interface; and a switch mode power supply (123) configured to convert the power supply voltage into an offset signal (V(C2)) provided to the second output interface, the offset signal being configured to superimpose the PFC output signal to generate a superimposed signal and to compensate for the ripple corresponding to the AC mains; and A regulating circuit (330) is electrically coupled between the power supply and the second input interface and is configured to regulate the power supply voltage provided to the second input interface to be synchronized with the offset signal so as to regulate the difference between the voltage amplitude of the regulated power supply voltage and the voltage amplitude of the offset signal.

2. A driver device according to claim 1, wherein the regulation circuit is adapted to regulate the supply voltage synchronously with the offset signal so that the difference between the voltage amplitude of the regulated supply voltage and the voltage amplitude of the offset signal is regulated, preferably reduced, thereby controlling, preferably reducing, the power loss of the switched mode power supply.

3. The driver device according to claim 1 or 2, further comprising: a sensing circuit (336) for sensing the voltage of the offset signal and / or the voltage of the superimposed signal, The regulation circuit is configured to regulate the supply voltage in response to the sensed voltage of the offset signal and / or a superimposed voltage of the PFC output signal and the offset signal.

4. The driver device according to claim 3, wherein the regulating circuit is configured to: providing an adjusted supply voltage of a second voltage for a first voltage of one of the offset signal or the superimposed signal; and providing, for a third voltage of said one of said offset signal or said superimposed signal, an adjusted said supply voltage of a fourth voltage, The first voltage is greater than the third voltage and the second voltage is greater than the fourth voltage. 5 . The driver device according to claim 4 , wherein the first voltage, the second voltage, the third voltage, and the fourth voltage are instantaneous voltages or average voltages.

6. The driver device according to any one of claims 1 to 5, wherein the regulating circuit is adapted to regulate an average value of the supply voltage to be synchronized with an average value of the offset signal.

7. The driver device according to any one of claims 1 to 6, wherein: The PFC conversion circuit device (112) comprises a transformer having a primary winding (W P ) and the first secondary winding (W S1 ), the primary winding is electrically coupled to the first input interface (111), the first secondary winding is magnetically coupled to the primary winding and electrically coupled to the first output interface (113); and The power supply (340) includes a second secondary winding (W) magnetically coupled to the primary winding S21 , W S22 ), The regulation circuit is configured to provide an adjustable ratio or proportion of the average voltage across the second secondary winding to the second input interface as the average voltage of the supply voltage.

8. The driver device according to claim 7, wherein the regulating circuit comprises a S21 , W S22 ) and the second input interface (121), the switch device being configured to switch between at least two configurations, the at least two configurations comprising: a first configuration in which an average voltage across the second secondary winding of a first ratio or proportion is provided to the second input interface as the average voltage of the supply voltage; as well as A second configuration in which an average voltage across the second secondary winding at a second ratio or ratio lower than the first ratio or ratio is provided to the second input interface as the average voltage of the supply voltage.

9. The driver device according to claim 8, wherein the regulating circuit is configured to regulate the average value of the power supply voltage in synchronization with the average value of the offset signal by: In response to the voltage of the offset signal being equal to or higher than a first predetermined voltage, operating the switch device in the first configuration so that the average voltage of the regulated power supply voltage is higher; and In response to the voltage of the offset signal being lower than the first predetermined voltage, the switching device is operated in the second configuration such that the average voltage of the regulated supply voltage is lower. 10 . The driver device according to claim 1 , wherein the regulating circuit is configured to increase an average voltage of the power supply voltage as an average voltage of the superimposed signal and / or the offset signal increases.

11. The driver device according to any one of claims 1 to 10, wherein the regulating circuit is adapted to regulate the instantaneous value of the supply voltage to be synchronized or in phase with the instantaneous value of the offset signal.

12. The driver device according to any one of claims 1 to 11, wherein the regulating circuit comprises: a buffer circuit electrically coupled to the power supply and adapted to generate a bias voltage having a substantially stable amplitude; as well as An inverter circuit is configured to subtract a voltage proportional to a voltage of the PFC output signal from the bias voltage to generate the regulated supply voltage of the second input interface.

13. The driver device according to claim 12, wherein: The PFC conversion circuit device (112) comprises a transformer having a primary winding (W P ) and the first secondary winding (W S1 ), the primary winding is electrically coupled to the first input interface (111), the first secondary winding is magnetically coupled to the primary winding and electrically coupled to the first output interface (113); The power supply (340) includes a second secondary winding (W) magnetically coupled to the primary winding S21 , W S22 ), so that the voltage across the second secondary winding varies in proportion to the voltage of the PFC output signal; The inverter circuit is configured to subtract a voltage proportional to a voltage across the second secondary winding from the bias voltage to generate the supply voltage of the second input interface.

14. An electronic device comprising: A driver device according to any one of claims 1 to 13; as well as A load is connected to the first output interface and the second output interface and is configured to be powered by the superimposed signal.

15. The electronic device according to claim 14, wherein the load comprises a light emitting device, and the light emitting device optionally comprises one or more light emitting diodes.

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