Device for testing elements of display panel

Abstract

The invention relates to a device for testing elements of a display panel. According to one or more embodiments of the present disclosure, an element testing device includes: a display panel on which an electrical element including a thin film transistor is disposed; a test panel extending from the display panel or integrated with the display panel, and on which the test electrical element is disposed by the same manufacturing process as a manufacturing process of the electrical element; and a test signal processor configured to supply the first driving voltage and the second driving voltage to the test electrical elements substantially simultaneously using the first channel and the second channel, respectively, and detect an electrical output characteristic of the test electrical elements using k channels, the number of which is equal to the number of the test electrical elements.

Description

Technical Field

[0001] The present disclosure relates to an apparatus for testing elements of a display panel. Background Art

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices are applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. Among these flat panel display devices, the light emitting display device includes a light emitting element that enables each pixel of the display panel to emit light itself. Therefore, the light emitting display device can display an image without a backlight unit that provides light to the display panel.

[0004] The display panel is manufactured by forming pixels, driving circuits, etc. in a unit area of ​​a mother glass according to resolution and separating and modularizing the unit area. In a state before each display panel is made into a product, the electrical characteristics of electrical elements such as thin film transistors formed on the display panel cannot be directly tested.

[0005] In order to test and check the electrical characteristics of the electrical components formed on the display panel, the test electrical components may be formed on test panels respectively extending from the unit regions (i.e., the display panels) by the same manufacturing process as the manufacturing process of the electrical components of the display panel. Accordingly, after the display panel and the test panel are separated from the mother glass together, the electrical characteristics of the electrical components formed on the display panel may be checked by detecting the electrical characteristics of the test electrical components formed on the test panel. Summary of the invention

[0006] Aspects of the present disclosure provide an apparatus for testing elements of a display panel by concurrently or substantially simultaneously supplying driving voltages to test elements of the test panel and detecting output signals of the test elements by using a reduced (eg, minimal) number of contact pins and channels.

[0007] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to one or more embodiments of the present disclosure, a component testing device includes: a display panel, on which an electrical component including a thin film transistor is arranged; a test panel, which extends from the display panel or is integrated with the display panel, and on which the test electrical component is arranged by a manufacturing process that is the same as a manufacturing process of the electrical component; and a test signal processor, which is configured to supply a first driving voltage and a second driving voltage to the test electrical component substantially simultaneously using a first channel and a second channel, respectively, and to detect electrical output characteristics of the test electrical component using k channels whose number is equal to the number of the test electrical components.

[0009] The component testing device may further include: a loader for receiving a display panel and a test panel; a power supply configured to generate a first driving voltage and a second driving voltage to be supplied to the test electrical component; and a contact terminal unit including contact terminals for respectively contacting a first electrode, a second electrode, and a third electrode of the test electrical component.

[0010] The test signal processor can be configured to supply a first driving voltage to a first electrode of the test electrical component substantially simultaneously through a first channel line of the contact terminal unit, supply a second driving voltage to a second electrode of the test electrical component substantially simultaneously through a second channel line of the contact terminal unit, and detect electrical characteristics including voltage and current amounts of electrical signals respectively output from third electrodes of the test electrical component through k channel lines and k channels of the contact terminal unit.

[0011] The contact terminals may include: first electrode contact terminals respectively contacting first electrodes of the test electrical components; second electrode contact terminals respectively contacting second electrodes of the test electrical components; and third electrode contact terminals respectively contacting third electrodes of the test electrical components.

[0012] The contact terminal unit may further include: a first channel line connecting the first electrode contact terminal to a first channel in a parallel structure; a second channel line connecting the second electrode contact terminal to a second channel in a parallel structure; and k channel lines connecting the third electrode contact terminal to k channels in a one-to-one manner.

[0013] The test signal processor can be configured to supply a first driving voltage having a first voltage level to the first channel line, supply a second driving voltage having a gradually changing voltage level to the second channel line, and detect electrical signals output from the third electrode of the test electrical element respectively through k channel lines during a first time period, and can be configured to supply a first driving voltage having a second voltage level different from the first voltage level to the first channel line, supply a second driving voltage having a gradually changing voltage level to the second channel line, and detect electrical signals output from the third electrode of the test electrical element respectively through k channel lines during a second time period.

[0014] The test signal processor may include: a source voltage supply unit configured to alternately generate a first driving voltage of approximately 0.1V and a first driving voltage of approximately 5.1V during a first period and a second period, respectively; a gate voltage supply unit configured to generate a second driving voltage that gradually changes from approximately 8.0V to approximately -13V by approximately 0.25V or gradually changes from approximately -15V to approximately 15V by approximately 0.25V; and a voltage supply control unit configured to control the source voltage supply unit to output the first driving voltage of approximately 0.1V to the first channel line during the first period, control the source voltage supply unit to output the first driving voltage of approximately 5.1V to the first channel line during the second period, and control the gate voltage supply unit to output the second driving voltage to the second channel line during the first period and the second period.

[0015] The contact terminals may include: four first electrode contact terminals, respectively contacting the first electrodes of the first thin film transistor to the fourth thin film transistor in the test electrical element; four second electrode contact terminals, respectively contacting the second electrodes of the first thin film transistor to the fourth thin film transistor; and four third electrode contact terminals, respectively contacting the third electrodes of the first thin film transistor to the fourth thin film transistor.

[0016] The contact terminal unit may further include: a first channel line connecting four first electrode contact terminals to one first channel in a parallel structure; a second channel line connecting four second electrode contact terminals to one second channel in a parallel structure; and k channel lines connecting four third electrode contact terminals to k channels in a one-to-one manner.

[0017] According to one or more embodiments of the present disclosure, a component testing device includes: a display panel, on which an electrical component including a thin film transistor is arranged; a test panel, which extends from the display panel or is integrated with the display panel, and the test electrical component is arranged on the test panel by a manufacturing process that is the same as a manufacturing process of the electrical component; a loader, configured to receive the display panel and the test panel; a power supply, configured to generate a first driving voltage and a second driving voltage to be supplied to the test electrical component; a contact terminal unit, including contact terminals that respectively contact a first electrode, a second electrode, and a third electrode of the test electrical component; and a test signal processor, configured to supply the first driving voltage and the second driving voltage to the test electrical component substantially simultaneously using a first channel and a second channel, respectively, and to detect electrical output characteristics of the test electrical component using k channels whose number is equal to the number of the test electrical components.

[0018] According to one or more embodiments of the present disclosure, the device for testing the elements of the display panel can use a reduced (e.g., minimum) number of channels and connection pins to concurrently or substantially simultaneously detect and check the electrical characteristics of multiple test elements. Accordingly, the element characteristics of the test panel and the display panel can be tested quickly, and the total test period can be shortened.

[0019] In addition, the apparatus for testing elements of a display panel according to one or more embodiments may improve the efficiency of testing element characteristics of a display panel by concurrently or substantially simultaneously detecting electrical characteristics of a plurality of test elements formed on a test panel group by group.

[0020] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] These and / or other aspects will become apparent and more easily understood through the following description of embodiments in conjunction with the accompanying drawings, in which:

[0022] Figure 1 is a diagram illustrating the construction of a display panel and a test panel separated on a mother glass;

[0023] Figure 2 It is a detailed diagram Figure 1 Any one of the display panels and test panel construction block diagram;

[0024] Figure 3 The diagram is formed in Figure 2 A block diagram of a configuration of an arrangement structure of thin film transistors on a test panel;

[0025] Figure 4 The diagram is formed in Figure 2 A block diagram of the arrangement structure of thin film transistors and other electrical components on a test panel;

[0026] Figure 5 is a configuration diagram illustrating an apparatus for testing an element of a display panel and a process of testing a test panel according to one or more embodiments;

[0027] Figure 6 is a detailed block diagram illustrating each component of an apparatus for testing an element of a display panel according to one or more embodiments;

[0028] Figure 7 It is a detailed diagram Figure 6 A structural diagram of a channel contact structure of a contact terminal unit shown in FIG.

[0029] Figure 8 is a monitoring screen showing a test panel test sequence according to one or more embodiments;

[0030] Fig. 9 is a graph illustrating changes in output current detected from a thin film transistor of a test panel; and

[0031] Fig.10 is a table illustrating the variation in time suitable for testing a test panel according to one or more embodiments. DETAILED DESCRIPTION

[0032] By referring to the detailed description and drawings of the embodiments, it is easier to understand various aspects of some embodiments of the present disclosure and their implementation methods. The described embodiments are provided as examples so that the present disclosure will be comprehensive and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Accordingly, redundant, irrelevant or unrelated to the description of the embodiments or processes, elements and techniques that are not necessary for a complete understanding of the aspects of the present disclosure by those of ordinary skill in the art can be omitted. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore their repeated descriptions can be omitted.

[0033] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown herein. The use of "can", "may" or "may not" when describing an embodiment corresponds to one or more embodiments of the present disclosure. The present disclosure covers all modifications, equivalents and substitutions within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be partially or entirely combined with each other, and various interlocks and drives are technically possible. Each embodiment may be implemented independently of one another, or may be implemented together in conjunction.

[0034] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or coupled to, or indirectly formed on, indirectly on, indirectly connected to, or coupled to, such that there may be one or more intervening elements, layers, regions, or components. Additionally, this may collectively represent direct or indirect coupling or connection, as well as integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or coupled to, or there may be one or more intervening layers, regions, or components. One or more intermediate components may include switches, resistors and / or capacitors, etc. When describing the embodiments, unless explicitly described as directly connected, the expression of connection indicates electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component or on another component without intermediate components.

[0035] For the purposes of this disclosure, expressions such as "at least one of" or "any one of" or "one or more of" when following a list of elements modify the entire list of elements without modifying the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ, or any variation thereof. Similarly, expressions such as "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, expressions such as "A and / or B" can include A, B, or A and B. Similarly, expressions such as "at least one of", "a plurality of", "one of", and other prepositional phrases, when preceding or following a list of elements, modify the entire list of elements without modifying the individual elements in the list.

[0036] It will be understood that although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or advantage, and are only used to distinguish an element, member, component, zone, region, layer, segment or part from another element, member, component, zone, region, layer, segment or part. Therefore, the first element, component, zone, layer or segment described below can be referred to as the second element, component, zone, layer or segment without departing from the spirit and scope of the present disclosure. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish elements of different categories or sets. For simplicity, the terms "first", "second", etc. can respectively represent "first category (or first set)", "second category (or second set)", etc.

[0037] The terms used herein are only used for the purpose of describing the embodiments, and are not intended to limit the present disclosure. As used herein, the singular form "a" is intended to also include the plural form, and the plural form is also intended to include the singular form, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and its variants, "have" and its variants and "include" and its variants when used in this specification indicate the presence of stated features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or groups thereof.

[0038] As used herein, the terms "substantially," "approximately," "approximately," and similar terms are used as approximate terms rather than terms of degree, and are intended to illustrate the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. Taking into account the measurement in question and the errors associated with the measured values ​​of a particular quantity (i.e., the limitations of the measurement system), "approximately" or "approximately" as used herein include the stated value and mean within an acceptable deviation range for that particular value determined by a person of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0039] In some embodiments, known structures and devices may be described in the accompanying drawings with respect to one or more functional blocks (e.g., block diagrams), units and / or modules to avoid unnecessary blurring of various embodiments. It will be understood by those skilled in the art that such blocks, units and / or modules are physically implemented by logic circuits, separate components, microprocessors, hard-wired circuits, storage elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform various functions discussed herein, and may be optionally driven by firmware and / or software. In addition, each block, unit and / or module may be implemented by a combination of dedicated hardware or dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from those of the dedicated hardware. In addition, in some embodiments, blocks, units and / or modules may be physically separated into two or more interacting separate blocks, units and / or modules without departing from the scope of the present disclosure. In addition, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly so defined herein.

[0041] Figure 1 2 is a diagram illustrating a structure of a display panel DP and a test panel TP separated on the mother glass MG.

[0042] refer to Figure 1 , a plurality of regions that can be appropriately separated may be provided in the mother glass MG, and unit regions to be manufactured into a plurality of display panels DP may be defined in the mother glass MG. Here, the unit regions of the mother glass MG are separated to form display panels DP, respectively. For example, the display panel DP may be manufactured by forming pixels, integrated circuits, etc. in the unit regions of the mother glass MG according to a resolution (e.g., a preset resolution) and separating and modularizing the unit regions. A drive circuit in the form of a microprocessor may be additionally formed on each display panel DP.

[0043] As described above, before each modular display panel DP is manufactured into a product, it is impossible to physically contact the electrical components such as thin film transistors, resistors, and capacitors formed on the display panel DP. There is a risk of damage to the display panel DP or the electrical components during the physical contact process. Accordingly, it is impossible to directly test the electrical characteristics such as input / output voltage or current of the electrical components (e.g., thin film transistors) formed on each display panel DP through physical contact.

[0044] In order to test and check the electrical characteristics of the electrical components formed on the display panel DP, the test electrical components are formed on the test panels TP respectively extending from the display panels DP by the same manufacturing process as the manufacturing process of the electrical components of the display panel DP. Here, the test panels TP may extend from the display panels DP respectively, or may be formed integrally with the display panels DP respectively. The test electrical components are formed on the front surface of each test panel TP by the same manufacturing process as the manufacturing process of the electrical components of each display panel DP. The electrical components of each display panel DP and the test electrical components of each test panel TP are formed simultaneously by the same process. The electrical components of each display panel DP and the test electrical components of each test panel TP may include a plurality of thin film transistors, a plurality of resistors, and a plurality of capacitors. An example of testing the electrical characteristics of the thin film transistors among the test electrical components will be described below. That is, the electrical components or the test electrical components are not limited to thin film transistors.

[0045] In order to detect and test the electrical characteristics of the thin film transistor formed on each display panel DP, the display panel DP and the test panel TP separated from the mother glass MG are placed on the element testing device. Then, the electrical characteristics of the thin film transistor formed on the display panel DP can be checked by detecting and testing the electrical characteristics of the test thin film transistor formed on the test panel TP.

[0046] Figure 2 It is a detailed diagram Figure 1 A structural block diagram of any one of the display panels DP and the test panel TP.

[0047] refer to Figure 2 , a display area DA and a non-display area NDA are defined in the display panel DP. The display area DA is an area for displaying an image and may be defined as a central area of ​​the display panel DP. The display area DA may include a plurality of pixels SP, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines VL.

[0048] The pixels SP are respectively located at the intersection of the gate lines GL extending parallel to each other in the X-axis direction and the data lines DL extending parallel to each other in the Y-axis direction. Here, each of the pixels SP can be defined as a minimum unit of light output for displaying an image. Each of the pixels SP includes at least one light-emitting element that emits light and at least one thin film transistor for applying a driving current to the at least one light-emitting element. In addition, at least one capacitor can be further formed in each of the pixels SP.

[0049] In the manufacturing process for forming a thin film transistor in each of the separated unit regions to respectively form the display panels DP, a test thin film transistor is also formed on the test panel TP by the same manufacturing process as the thin film transistor of each display panel DP. Accordingly, the test thin film transistor formed on the test panel TP has the same electrical characteristics as the thin film transistor formed on each display panel DP.

[0050] The gate lines GL supply gate signals received from separate gate driving integrated circuits to the pixels SP. The gate lines GL may extend in an X-axis direction and may be spaced apart from each other in a Y-axis direction crossing the X-axis direction.

[0051] The data lines DL may supply data voltages received from a separate display driving circuit to the pixels SP. The data lines DL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

[0052] The power lines VL may supply a power voltage received from a power source (e.g., a power supply unit) or a display driving circuit to the pixels SP. Here, the power voltage may be at least one of a driving voltage, an initialization voltage, and a reference voltage. The power lines VL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

[0053] The non-display area NDA may surround the display area DA (eg, in a plan view). A gate driving integrated circuit, a fan-out line, a gate control line, etc. are formed in the non-display area NDA.

[0054] The gate driving integrated circuit formed in the non-display area NDA may generate a plurality of gate signals based on a gate control signal received from a display driving circuit, etc. Then, the gate signals may be sequentially supplied to the gate lines GL according to a set order.

[0055] Figure 3 The diagram is formed in Figure 2 A block diagram of a configuration of an arrangement structure of thin film transistors Tr (also referred to as test thin film transistors Tr) on a test panel TP.

[0056] refer to Figure 3The test thin film transistor Tr is formed on the test panel TP by the same manufacturing process as the thin film transistor of each display panel DP. The test thin film transistor Tr formed on the test panel TP has the same electrical characteristics as the thin film transistor of the pixel SP formed on each display panel DP. Each of the test thin film transistors Tr includes a first electrode SE (e.g., source electrode) exposed on the surface so that it can be physically contacted, a second electrode GE (e.g., gate electrode), and a third electrode DE (e.g., drain electrode).

[0057] The test thin film transistors Tr formed on the test panel TP may be formed and arranged side by side in a vertical direction or a horizontal direction. In addition, the test thin film transistors Tr may be formed and arranged at equal intervals. For example, the test thin film transistors Tr may be formed and arranged in any one of 1×2, 1×4, 2×2, 2×4, 4×4, ..., n×m arrays (n and m are positive integers that are the same or different from each other).

[0058] The test thin film transistors Tr may be formed and arranged in a 2×4 or 4×4 array, and a group of four test thin film transistors Tr adjacent to each other in the horizontal direction or the vertical direction may be formed. The electrical characteristics of each of the four test thin film transistors Tr arranged side by side in the horizontal direction or the vertical direction may be tested concurrently or substantially simultaneously. The following will describe the concurrent or substantially simultaneous testing of the electrical characteristics of the four test thin film transistors Tr arranged side by side in the horizontal direction or the vertical direction. Figure 3 An example of electrical characteristics of every four test thin film transistors Tr arranged side by side in the horizontal direction of FIG. The arrangement structure and number of the test thin film transistors Tr tested concurrently or substantially simultaneously are not limited to the embodiments described below, and various modifications may be made.

[0059] Figure 4 The diagram is formed in Figure 2 A block diagram of the arrangement structure of the thin film transistors Tr and other electrical components on the test panel TP.

[0060] refer to Figure 4 , the test thin film transistors Tr may be formed and arranged side by side in a vertical direction or a horizontal direction on the test panel TP. The test thin film transistors Tr may be formed and arranged in an n×m array such as 2×2 or 2×4. For example, the test thin film transistors Tr may be formed and arranged in a 2×4 array. The electrical characteristics of every four test thin film transistors Tr arranged side by side in the horizontal direction may be tested concurrently or substantially simultaneously using a separate element testing device.

[0061] In addition, a test resistor Rr that can be simultaneously formed by the same manufacturing process as the manufacturing process of the resistor formed on each display panel DP may be further provided on the test panel TP. The test resistor Rr may be formed and provided in an area different from the area in which the test thin film transistor Tr is formed. For example, the test resistor Rr may be formed and provided in an n×m array such as 2×2 or 2×4. For example, the test resistor Rr may be formed and provided in a 2×10 array. The electrical characteristics of every ten test resistors Rr arranged side by side in the horizontal direction may be tested concurrently or substantially simultaneously using a separate element testing device.

[0062] A test capacitor Cp that can be simultaneously formed by the same manufacturing process as the manufacturing process of the capacitor formed on each display panel DP may be further provided on the test panel TP. The test capacitor Cp may be formed and provided in a region different from the region in which the test thin film transistor Tr and the test resistor Rr are formed. For example, the test capacitor Cp may be formed and provided in an n×m array such as 1×2 or 2×4. For example, the test capacitor Cp may be formed and provided in a 1×10 array. The electrical characteristics of every ten test capacitors Cp arranged side by side in the horizontal direction may be tested concurrently or substantially simultaneously using a separate element testing device.

[0063] Figure 5 is a configuration diagram illustrating an apparatus for testing elements of a display panel DP and a process of testing a test panel TP according to one or more embodiments. Figure 6 is a detailed block diagram illustrating each component of an apparatus for testing elements of a display panel DP according to one or more embodiments.

[0064] refer to Figure 5 and Figure 6 , the display panel DP and the test panel TP extending from the display panel DP are loaded on the device testing apparatus.

[0065] The element testing device supplies a driving voltage to the thin film transistor Tr of the test panel TP and detects the amount of output current of the thin film transistor Tr. To this end, the element testing device includes a loader (e.g., a loading unit) 101, a power supply (e.g., a power supply unit) 110, a contact terminal unit TMU having a plurality of contact terminals Tm, and a test signal processor (e.g., a test signal processing unit) MCU.

[0066] The loader 101 may be formed in the form of a flat plate on which the display panel DP and the test panel TP extended from the display panel DP are loaded. The loader 101 fixes at least any one side of the display panel DP or the test panel TP loaded on the flat plate.

[0067] The power supply 110 generates a driving voltage to be supplied to the thin film transistor Tr of the test panel TP. For example, the power supply 110 may generate a direct current (DC) and an alternating current (AC) driving voltage to be supplied to the display panel DP or the test panel TP. In addition, the power supply 110 generates a first driving voltage to be supplied to the first electrode SE of the thin film transistor Tr formed on the test panel TP, a second driving voltage to be supplied to the second electrode GE of the thin film transistor Tr, and a third driving voltage to be supplied to the third electrode DE of the thin film transistor Tr.

[0068] The contact terminal unit TMU includes a plurality of contact terminals Tm that respectively contact the electrodes of the thin film transistor Tr formed on the test panel TP (i.e., the first electrode SE, the second electrode GE, and the third electrode DE of the thin film transistor Tr). For example, a plurality of first electrode contact terminals among the contact terminals Tm may respectively contact the first electrodes SE of the first to fourth thin film transistors Tr. In addition, a plurality of second electrode contact terminals among the contact terminals Tm may respectively contact the second electrodes GE of the first to fourth thin film transistors Tr. On the other hand, a plurality of third electrode contact terminals among the contact terminals Tm may respectively contact the third electrodes DE of the first to fourth thin film transistors Tr.

[0069] In an example in which electrical characteristics of each first to fourth thin film transistor Tr arranged side by side on the test panel TP are detected concurrently or substantially simultaneously, the contact terminal unit TMU may include a plurality of contact terminals Tm respectively contacting a first electrode SE, a second electrode GE, and a third electrode DE of each first to fourth thin film transistor Tr among the thin film transistors Tr formed on the test panel TP. Here, the first electrode SE of each of the thin film transistors Tr may be a source electrode, the second electrode GE may be a gate electrode, and the third electrode DE may be a drain electrode.

[0070] The contact terminal unit TMU includes a first channel line that connects a first electrode contact terminal of a first electrode SE of a thin film transistor Tr formed on a test panel TP to a channel in a parallel structure. The contact terminal unit TMU also includes a second channel line that connects a second electrode contact terminal to another channel in a parallel structure. In addition, the contact terminal unit TMU further includes k channel lines that connect a third electrode contact terminal to k other channels in a one-to-one manner. Here, k is the same number as the number of thin film transistors Tr contacted concurrently or substantially simultaneously by the third electrode contact terminal. The first drive voltage can be supplied to the first electrode SE of the thin film transistor Tr concurrently or substantially simultaneously through a first channel line. In addition, the second drive voltage can be supplied to the second electrode GE of the thin film transistor Tr concurrently or substantially simultaneously through a second channel line. The output currents outputted from the third electrode DE of the thin film transistor Tr can be transmitted to the test signal processor MCU through the k channel lines respectively.

[0071] The test signal processor MCU may include a gate voltage supply unit (e.g., a gate voltage supply unit) 201, a source voltage supply unit (e.g., a source voltage supply unit) 202, a voltage supply control unit (e.g., a voltage supply control unit) 203, an analog-to-digital (AD) converter (e.g., an AD conversion unit) 204 and a test result output unit 205.

[0072] For example, the source voltage supply unit 202 may alternately generate a first driving voltage of about 0.1 V and a first driving voltage of about 5.1 V in different time periods. Accordingly, under the control of the voltage supply control unit 203, the source voltage supply unit 202 may output a first driving voltage of about 0.1 V during a first time period (e.g., a preset first time period). On the other hand, under the control of the voltage supply control unit 203, the source voltage supply unit 202 may output a first driving voltage of about 5.1 V during a second time period (e.g., a preset second time period).

[0073] The gate voltage supply part 201 may generate the second driving voltage gradually changing from about 8.0 V to about -13 V by about 0.25 V. Alternatively, the gate voltage supply part 201 may generate the second driving voltage gradually changing from about -15 V to about 15 V by about 0.25 V.

[0074] The voltage supply control section 203 controls the source voltage supply section 202 to output a first driving voltage of about 0.1V to the first channel line during a first period (e.g., a preset first period). In addition, the voltage supply control section 203 may control the source voltage supply section 202 to output a first driving voltage of about 5.1V to the first channel line during a second period (e.g., a preset second period). In addition, the voltage supply control section 203 controls the gate voltage supply section 201 to output a second driving voltage to the second channel line during the first period and the second period.

[0075] The analog-to-digital converter 204 receives the output currents respectively output from the third electrodes DE of the thin film transistors Tr through k channel lines. The AD converter 204 filters the output currents respectively output from the third electrodes DE of the thin film transistors Tr, and detects and converts the current amount and voltage level.

[0076] The test result output unit 205 transmits information on the current amount and the voltage level of the output current respectively output from the third electrode DE of the thin film transistor Tr to an external display device such as a monitor.

[0077] The test signal processor MCU concurrently or substantially simultaneously supplies the first driving voltage to the first electrodes SE of the first to fourth thin film transistors Tr through the first channel line formed in the contact terminal unit TMU and the first electrode contact terminal among the contact terminals Tm.

[0078] In addition, the test signal processor MCU concurrently or substantially simultaneously supplies the second driving voltage to the second electrodes GE of the first to fourth thin film transistors Tr through the second channel line and the second electrode contact terminal among the contact terminals Tm.

[0079] In addition, the test signal processor MCU detects output currents respectively output from the third electrodes DE of the first to fourth thin film transistors Tr through the k channel lines and the third electrode contact terminal among the contact terminals Tm.

[0080] Figure 7 It is a detailed diagram Figure 6 FIG. 4 is a structural diagram of a channel contact structure of a contact terminal unit TMU shown in FIG.

[0081] refer to Figure 7 The contact terminal unit TMU includes first electrode contact terminals Ts1, Ts2, Ts3 and Ts4, second electrode contact terminals Tg1, Tg2, Tg3 and Tg4, third electrode contact terminals Td1, Td2, Td3 and Td4, and first to kth channel lines SLL, GLL, DLL1, DLL2, DLL3 and DLL4.

[0082] The first electrode contact terminals Ts1 to Ts4 contact the first electrodes SE of the first to fourth thin film transistors Tr, respectively.

[0083] The second electrode contact terminals Tg1 to Tg4 contact the second electrodes GE of the first to fourth thin film transistors Tr, respectively.

[0084] The third electrode contact terminals Td1 to Td4 contact the third electrodes DE of the first to fourth thin film transistors Tr, respectively.

[0085] The first channel line SLL is connected in parallel between first electrode contact terminals Ts1 to Ts4 contacting first electrodes SE of first to fourth thin film transistors Tr respectively and one first channel Ch1. The first channel line SLL allows the first electrode contact terminals Ts1 to Ts4 to be electrically connected to the test signal processor MCU through one first channel Ch1.

[0086] The second channel line GLL is connected in parallel between the second electrode contact terminals Tg1 to Tg4 contacting the second electrodes GE of the first to fourth thin film transistors Tr, respectively, and one second channel Ch2. The second channel line GLL allows the second electrode contact terminals Tg1 to Tg4 to be electrically connected to the test signal processor MCU through one second channel Ch2.

[0087] The k channel wires DLL1 to DLL4 are connected one-to-one between the third electrode contact terminals Td1 to Td4 contacting the third electrodes DE of the first to fourth thin film transistors Tr, respectively, and the k channels Ch3, Ch4, Ch5, and Ch6. The k channel wires DLL1 to DLL4 allow the third electrode contact terminals Td1 to Td4 to be electrically connected to the test signal processor MCU through the k channels Ch3 to Ch6.

[0088] Figure 8 is a monitoring screen illustrating a test panel test sequence according to one or more embodiments.

[0089] refer to Figure 8 When the display panel DP and the test panel TP extending from the display panel DP are loaded on the loader 101 of the element testing apparatus and aligned, the first electrode contact terminals Ts1 to Ts4 of the contact terminal unit TMU contact the first electrodes SE of the first to fourth thin film transistors Tr, respectively.

[0090] In addition, the second electrode contact terminals Tg1 to Tg4 contact the second electrodes GE of the first to fourth thin film transistors Tr, respectively, and the third electrode contact terminals Td1 to Td4 contact the third electrodes DE of the first to fourth thin film transistors Tr, respectively.

[0091] The test signal processor MCU concurrently or substantially simultaneously supplies the first driving voltage to the first electrodes SE of the first to fourth thin film transistors Tr through the first channel line SLL and the first electrode contact terminals Ts1 to Ts4 formed in the contact terminal unit TMU.

[0092] The test signal processor MCU may concurrently or substantially simultaneously supply a first driving voltage of about 0.1V to the first electrodes SE of the first to fourth thin film transistors Tr through the first channel Ch1 during a first period (eg, a preset first period).

[0093] In addition, the test signal processor MCU can concurrently or substantially simultaneously supply a second driving voltage gradually changing from about 8.0 V to about -13 V by about 0.25 V to the second electrodes GE of the first to fourth thin film transistors Tr through the second channel Ch2 during a first period (e.g., a preset first period).

[0094] When the first to fourth test thin film transistors Tr to Tr formed on the test panel TP are of the PMOS type, the test signal processor MCU supplies the second driving voltage gradually changing from about 8.0 V to about -13 V by about 0.25 V to the second electrodes GE of the first to fourth thin film transistors Tr to Tr. On the contrary, when the first to fourth test thin film transistors Tr to Tr formed on the test panel TP are of the NMOS type, the test signal processor MCU may supply the second driving voltage gradually changing from about -15 V to about 15 V by about 0.25 V to the second electrodes GE of the first to fourth thin film transistors Tr to Tr.

[0095] During a first period in which the test signal processor MCU supplies a first driving voltage to the first electrodes SE of the first to fourth thin film transistors Tr and supplies a second driving voltage to the second electrodes GE of the first to fourth thin film transistors Tr, the test signal processor MCU detects output currents respectively output from the third electrodes DE of the first to fourth thin film transistors Tr through k channel lines DLL1 to DLL4.

[0096] Then, the test signal processor MCU may concurrently or substantially simultaneously supply the first driving voltage of about 5.1V to the first electrodes SE of the first to fourth thin film transistors Tr through the first channel Ch1 during a second period (eg, a preset second period).

[0097] In addition, the test signal processor MCU can concurrently or substantially simultaneously supply a second driving voltage gradually changing from about 8.0 V to about -13 V by about 0.25 V to the second electrodes GE of the first to fourth thin film transistors Tr through the second channel Ch2 during a second period (e.g., a preset second period).

[0098] When the first to fourth test thin film transistors Tr formed on the test panel TP are of PMOS type, the test signal processor MCU supplies a second driving voltage gradually varying by about 0.25V from about 8.0V to about -13V to the second electrodes GE of the first to fourth thin film transistors Tr.

[0099] When the first to fourth test thin film transistors Tr formed on the test panel TP are of NMOS type, the test signal processor MCU may supply a second driving voltage gradually varying from about -15V to about 15V by about 0.25V to the second electrodes GE of the first to fourth thin film transistors Tr.

[0100] During a second period in which the test signal processor MCU supplies a first driving voltage to the first electrodes SE of the first to fourth thin film transistors Tr and a second driving voltage to the second electrodes GE of the first to fourth thin film transistors Tr, the test signal processor MCU detects output currents respectively output from the third electrodes DE of the first to fourth thin film transistors Tr through k channel lines DLL1 to DLL4.

[0101] The output currents of the first to fourth thin film transistors Tr detected through the k channel lines DLL1 to DLL4 may be displayed in real time on a separate monitor device through the test result output unit 205 .

[0102] Fig. 9 is a graph illustrating changes in output current detected from the thin film transistor Tr of the test panel TP.

[0103] refer to Fig. 9During the first period, the test signal processor MCU supplies a first driving voltage of approximately 0.1 V to the first electrodes SE of the first to fourth thin film transistors Tr, and supplies a second driving voltage that gradually changes from approximately 8.0 V to approximately -13 V by approximately 0.25 V to the second electrodes GE of the first to fourth thin film transistors Tr.

[0104] During the first period, the output currents ID1, ID2, ID3, and ID4 respectively output from the third electrodes DE of the first to fourth thin film transistors Tr are detected through the k channel lines DLL1 to DLL4. During the first period, the output currents ID1 to ID4 respectively output from the third electrodes DE of the first to fourth thin film transistors Tr to Tr vary according to the variation of the second driving voltage.

[0105] During the second period, the test signal processor MCU supplies a first driving voltage of approximately 5.1 V to the first electrodes SE of the first to fourth thin film transistors Tr, and supplies a second driving voltage that gradually changes from approximately 8.0 V to approximately -13 V by approximately 0.25 V to the second electrodes GE of the first to fourth thin film transistors Tr.

[0106] During the second period, the output currents ID1 to ID4 respectively outputted from the third electrodes DE of the first to fourth thin film transistors Tr are detected through the k channel lines DLL1 to DLL4. During the second period, the output currents ID1 to ID4 respectively outputted from the third electrodes DE of the first to fourth thin film transistors Tr are changed according to the change of the second driving voltage.

[0107] Fig.10 is a table showing a change in time suitable for testing the test panel TP according to one or more embodiments.

[0108] refer to Fig.10 , when the first electrode SE, the second electrode GE, and the third electrode DE of the test thin film transistor Tr are respectively contacted with the first electrode contact terminal to the third electrode contact terminal to detect the output current of the test thin film transistor Tr, the electrode contact terminals, channels, and channel lines three times the number of the test thin film transistors Tr may be suitable for operation. That is, the electrode contact terminals, channels, and channel lines for supplying the first drive voltage and the second drive voltage to each test thin film transistor Tr and for detecting the output current may be suitable for operation. The second drive voltage is provided by gradually changing the second drive voltage by about 0.25V from about 8.0V to about -13V or from about -15V to about 15V.

[0109] Six electrode contact terminals, six channels and six channel lines can be used to detect the output current and electrical characteristics of each two test thin film transistors Tr. If the time suitable for detecting the output current of two test thin film transistors Tr is about 24 seconds, the time suitable for detecting the output current of four test thin film transistors Tr can be about 48 seconds.

[0110] On the other hand, the element testing device according to one or more embodiments of the present disclosure can detect the output current and electrical characteristics of four test thin film transistors Tr at a time by using the contact terminal unit TMU having six channels Ch1 to Ch6. Therefore, the output current of the four test thin film transistors Tr can be detected and checked during the same 24-second period as before.

[0111] As described above, the device for testing the elements of the display panel DP according to one or more embodiments of the present disclosure can use a reduced (e.g., minimum) number of channels and electrode contact terminals to concurrently or substantially simultaneously detect and check the electrical characteristics of a plurality of test elements such as thin film transistors Tr. Accordingly, the element characteristics of the test panel TP and the display panel DP can be tested relatively quickly, and the total test period can be shortened.

[0112] In addition, the apparatus for testing the elements of the display panel DP according to one or more embodiments detects the electrical characteristics of a plurality of test elements (e.g., thin film transistors Tr) formed on the test panel TP concurrently or substantially simultaneously in groups of four test elements. Therefore, the efficiency of testing the element characteristics of the display panel DP can be improved.

[0113] According to one or more embodiments of the present disclosure, the device for testing the elements of the display panel can use a reduced (e.g., minimum) number of channels and connection pins to concurrently or substantially simultaneously detect and check the electrical characteristics of multiple test elements. Accordingly, the element characteristics of the test panel and the display panel can be tested quickly, and the total test period can be shortened.

[0114] In addition, the apparatus for testing elements of a display panel according to one or more embodiments can improve the efficiency of testing element characteristics of a display panel by concurrently or substantially simultaneously detecting electrical characteristics of a plurality of test elements formed on a test panel group by group.

[0115] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the claims (equivalents thereof included therein).

[0116] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the aspects of the present disclosure. Therefore, the disclosed embodiments of the present disclosure are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A component testing device, comprising: A display panel, on which electrical components including thin film transistors are disposed; a test panel extending from the display panel or being integrated with the display panel, and a test electrical component being arranged on the test panel by a manufacturing process identical to that of the electrical component; as well as The test signal processor is configured to simultaneously supply a first driving voltage and a second driving voltage to the test electrical element using a first channel and a second channel respectively, and detect electrical output characteristics of the test electrical element using k channels whose number is equal to the number of the test electrical elements.

2. The component testing device according to claim 1, further comprising: A loader, configured to receive the display panel and the test panel; a power supply configured to generate the first drive voltage and the second drive voltage to be supplied to the test electrical element; as well as The contact terminal unit comprises contact terminals respectively contacting the first electrode, the second electrode and the third electrode of the test electrical component.

3. The component testing device according to claim 2, wherein: The test signal processor is configured to simultaneously supply the first drive voltage to the first electrode of the test electrical component through the first channel line of the contact terminal unit, and simultaneously supply the second drive voltage to the second electrode of the test electrical component through the second channel line of the contact terminal unit, and detect electrical characteristics including voltage and current of electrical signals respectively output from the third electrode of the test electrical component through the k channel lines and the k channels of the contact terminal unit.

4. The component testing device according to claim 2, wherein: The contact terminal comprises: first electrode contact terminals, respectively contacting the first electrodes of the test electrical components; second electrode contact terminals respectively contacting the second electrodes of the test electrical components; and The third electrode contact terminals respectively contact the third electrodes of the test electrical components.

5. The component testing device according to claim 4, wherein: The contact terminal unit further comprises: a first channel line connecting the first electrode contact terminal to a first channel in a parallel configuration; a second channel line connecting the second electrode contact terminal to a second channel in a parallel configuration; and k channel wires connect the third electrode contact terminal to the k channels in a one-to-one manner.

6. The component testing device according to claim 5, wherein: The test signal processor is configured to supply the first driving voltage having a first voltage level to the first channel line, supply the second driving voltage having a gradually changing voltage level to the second channel line, and detect the electrical signals respectively output from the third electrode of the test electrical element through the k channel lines during a first time period, and is configured to supply the first driving voltage having a second voltage level different from the first voltage level to the first channel line, supply the second driving voltage having a gradually changing voltage level to the second channel line, and detect the electrical signals respectively output from the third electrode of the test electrical element through the k channel lines during a second time period.

7. The component testing device according to claim 6, wherein: The test signal processor comprises: a source voltage supply unit configured to alternately generate the first driving voltage of 0.1V and the first driving voltage of 5.1V during the first period and the second period, respectively; a gate voltage supply unit configured to generate the second driving voltage gradually changing from 8.0V to -13V by 0.25V or gradually changing from -15V to 15V by 0.25V; and A voltage supply control unit is configured to control the source voltage supply unit to output the first driving voltage of 0.1V to the first channel line during the first period, control the source voltage supply unit to output the first driving voltage of 5.1V to the first channel line during the second period, and control the gate voltage supply unit to output the second driving voltage to the second channel line during the first period and the second period.

8. The component testing device according to claim 2, wherein: The contact terminal comprises: Four first electrode contact terminals, respectively contacting first electrodes of the first to fourth thin film transistors in the test electrical element; four second electrode contact terminals, respectively contacting the second electrodes of the first to fourth thin film transistors; and The four third electrode contact terminals respectively contact the third electrodes of the first thin film transistor to the fourth thin film transistor.

9. The component testing device according to claim 8, wherein: The contact terminal unit further comprises: a first channel line connecting the four first electrode contact terminals to one first channel in a parallel structure; a second channel line connecting the four second electrode contact terminals to one second channel in a parallel structure; and k channel wires connect the four third electrode contact terminals to the k channels in a one-to-one manner.

Images