A method and device for locating fault phase of an asymmetric half-bridge power converter

Abstract

The present invention discloses a method and device for locating a faulty phase of an asymmetric half-bridge power converter. The method divides a working cycle of each phase bridge arm into two intervals. In the power generation stage of each phase, a composite modulation method of electric energy and signal is used to generate a voltage ripple containing a specific frequency at the output port of the converter. In a data symbol period, the voltage ripple of the specific frequency represents a symbol data signal. The data signal expressed by the voltage ripple is encoded and sent to the receiving end or the detection point synchronously with the electric energy. The specific bridge arm encoding signal of a certain phase is obtained by a signal demodulation method, so that the position of a certain bridge arm of the converter where the fault occurs can be inferred. When a phase failure occurs in a certain phase, the voltage of the phase drops rapidly. Detecting the output voltage commutation ripple can determine the time of occurrence of the fault and trigger a fault identification interrupt. The present invention realizes the rapid positioning of the faulty phase of the asymmetric half-bridge converter, and has good engineering application value.

Description

Technical Field

[0001] The invention belongs to the technical field of power electronics, and in particular relates to a method and a device for locating a fault phase of an asymmetric half-bridge power converter. Background Art

[0002] With the development of DC microgrid technology, power converters for power generation systems have become a research hotspot in recent years. The asymmetric half-bridge power converter for reluctance power generation system has outstanding advantages such as simple structure, independent winding, strong fault tolerance, high reliability, and good dynamic response performance. Therefore, the asymmetric half-bridge power converter has broad application prospects in the field of microgrid power generation.

[0003] The power converter of the reluctance power generation system contains multiple power switching devices, which is also the weakest link of the entire power generation system. The power converter is prone to open circuit and short circuit faults. Existing reluctance power generation systems mostly use asymmetric half-bridge power converters. The main reason is that each phase of the asymmetric half-bridge power converter is independent and has the characteristics of being able to operate in the absence of a phase. When a phase fails and is isolated by protection, the power generation operation can still be guaranteed by other phases. However, when the phase is missing, the output voltage ripple of the converter increases, the non-faulty phase bears a larger load current, and each phase heats up seriously. The position of the faulty phase must be determined in time and corresponding measures must be taken. Therefore, it is of great significance to identify and locate the faulty phase of the power converter.

[0004] In order to determine the fault location in time, researchers have done a lot of research on the fault location of power converters. For example, by measuring the amplitude of the DC bus current and comparing it with the expected amplitude, the fault location of the power converter is detected based on the current amplitude difference; or by monitoring the current direction and voltage amplitude of each phase bridge arm, and comparing the measured voltage with the expected voltage value, the open circuit fault location of the converter's IGBT is determined based on the difference and current direction; or using a single current sensor to detect the midpoint current, using the amplitude of the harmonic component to characterize the fault location threshold, and comparing the threshold with the midpoint current to confirm the fault bridge arm location, etc. However, the existing methods all require the addition of certain voltage or current sensors, which increases the hardware cost of fault location. Summary of the invention

[0005] In order to solve the above problems, the present invention provides a method and device for locating the fault phase of an asymmetric half-bridge power converter. The fault phase locating method utilizes the composite modulation technology of electric energy and signals, generates a ripple signal of a specific frequency through the power switch in each phase bridge arm of the power converter, represents binary data with ripples of different frequencies within a data code element period, and distinguishes and encodes each phase of the power converter with two binary data, that is, in the excitation or power generation stage of each phase, modulates different voltage ripple signals, and demodulates the ripple signals at the fault monitoring point to obtain the data encoding of each phase, thereby realizing accurate positioning of each phase of the converter. When a phase fails, the fault detection and positioning mechanism is triggered by detecting the bus voltage amplitude and ripple frequency characteristics; when a phase failure fault signal is detected, the position of the fault phase is deduced by identifying the data encoding signal of the next adjacent phase of the fault phase.

[0006] To achieve the above object, the present invention is implemented according to the following technical solutions:

[0007] The present invention provides a method for locating a fault phase of an asymmetric half-bridge power converter. The bridge arms of each phase of the asymmetric half-bridge converter are turned on in sequence, and the upper and lower bridge arm switches are controlled by a PWM signal of a set frequency within a conduction period. The method comprises:

[0008] The power generation interval of each phase bridge arm in a commutation cycle is divided into two sub-intervals, and a binary code is assigned to each sub-interval to complete the encoding of each phase bridge arm;

[0009] According to the binary code corresponding to each phase bridge arm, PWM signals of different frequencies are selected to modulate the switch tube under the bridge arm, where the binary code "0" corresponds to a PWM signal with a frequency of f0, and the binary code "1" corresponds to a PWM signal with a frequency of f1;

[0010] Frequency shift keying is used to perform composite modulation of energy signals and output PWM signals with digital information;

[0011] The PWM signal with digital information and the original driving signal of the lower bridge arm switch tube of each phase are passed or processed to output a modulated signal for driving the switch tube on and off;

[0012] The output voltage of the sampling converter is used to extract the signal ripple using a bandpass filter. After discrete Fourier transform demodulation calculation, the harmonic amplitudes at the frequency points f0 and f1 are selected and compared with the set threshold value to achieve demodulation of the digital coded signal.

[0013] The demodulated digital code signal is used to determine whether the converter has a phase failure, and the two-bit code after the fault signal is output to achieve rapid and accurate positioning of the faulty phase.

[0014] In one embodiment, two sub-intervals in the power generation interval are marked as interval O and interval T respectively; in interval O, the phase current is greater than the load current flowing through the load resistor R, and the output voltage stabilizing capacitor C o In the charging stage, the output voltage U o Rise; in interval T, the phase current is less than the load current, at this time the output voltage stabilizing capacitor C o In the discharge stage, the output voltage U o decline.

[0015] In one embodiment, the corresponding coding value of A of the asymmetric half-bridge power converter is defined as "00", the corresponding coding value of B is defined as "01", the corresponding coding value of C is defined as "10", and the corresponding coding value of D is defined as "11". The position sensor feedback signal is used to determine the position angle of the SRG rotor, and the serial number of the phase bridge arm of the power converter in the power generation interval is determined. According to the coding value of the phase bridge arm, a PWM signal of corresponding frequency is selected to realize modulation of the converter, thereby completing the coding of each phase bridge arm.

[0016] In one embodiment, the specific steps of using the frequency shift keying method to perform energy signal composite modulation are:

[0017] The signal generator generates a baseband signal s(t), which contains a series of binary 0 / 1 sequences. When s(t)=1, the carrier signal 1 is selected, and the modulation frequency is f1. Therefore, the carrier signal 0 is not selected; when When , the carrier signal 0 is selected, the modulation frequency is f0, and since s(t) = 0, the carrier signal 1 is not selected; the selected carrier signal is superimposed through the adder to obtain the final output carrier signal s BFSK (t), the voltage modulation amount u p (t) and the carrier signal s BFSK (t) Through comparison by a comparator, the comparator outputs a PWM signal with digital information, specifically:

[0018] When u p (t) is greater than s BFSK At (t), the comparator outputs logic 0;

[0019] When u p (t) is less than s BFSK At (t), the comparator outputs logic 1.

[0020] In one implementation, the PWM signal with digital information and the original driving signal of the lower bridge arm switch tube of each phase are processed or output as a modulated signal:

[0021]

[0022] Among them, A is the signal carrier amplitude, f0 and f1 are the carrier signal frequencies representing the digital "0" and "1" respectively, and a n is the binary digital sequence sent, expressed as:

[0023]

[0024] for a n The inverse code is expressed as:

[0025]

[0026] In one implementation, the specific process of the discrete Fourier transform demodulation calculation is:

[0027] In a Fourier period T s Inside, with f smp The frequency is sampled, and the number of sampling points is N, then we can get:

[0028]

[0029] Among them, f s is the fundamental frequency;

[0030] For the frequency shift keying modulated signal s BFSK (t), in period T s In the Fourier series expansion, we can get:

[0031]

[0032] Among them, c k is the Fourier coefficient, which satisfies the expression:

[0033]

[0034] The carrier frequencies f0 and f1 set by the modulation coding signals "0" and "1" correspond to s BFSK (t) The m0th and m1th harmonics in (t).

[0035] Fourier period T s The expression is satisfied:

[0036]

[0037] According to Nyquist sampling theorem, the sampling frequency f smp And the carrier frequencies f0 and f1 should satisfy:

[0038] f smp ≥2max{f0,f1}

[0039] For a sampling sequence x(n) with N sampling points, its discrete Fourier transform is:

[0040]

[0041] For the m0th and m1th harmonics, that is, the carrier frequencies f0 and f1 of the selected data signal, their discrete Fourier transforms satisfy:

[0042]

[0043] Wherein, X(m0) and X(m1) are the amplitudes of the voltage ripples corresponding to the digital signals “0” and “1” respectively.

[0044] In one implementation, to prevent bit errors due to improper selection of a demodulation threshold in data demodulation, the signal ripple amplitude difference ΔX=[X(m0)-X(m1)] is selected as the data demodulation threshold to reduce the bit error rate.

[0045] In one embodiment, the demodulation of the digital coded signal is realized by selecting the harmonic amplitudes of the frequency points f0 and f1 after discrete Fourier transform demodulation calculation and comparing them with a set threshold, which includes:

[0046] When the digital signal is "0", the output signal amplitude is X(f0); when the digital signal is "1", the output signal amplitude is X(f1);

[0047] Let the signal ripple amplitude difference ΔX equal to X(f1)-X(f0), and set the demodulation threshold to X th1 and X th0 ;

[0048] When the signal ripple amplitude difference ΔX is greater than X th1 When the signal ripple amplitude difference ΔX is less than X, it is demodulated to digital "1". th0 When , it is demodulated to digital "0";

[0049] The modulated phase bridge arm coding signal is restored according to the demodulated digital information.

[0050] In one embodiment, the demodulated digital code signal is used to determine whether a phase failure occurs in the converter, and two bits of code following the fault signal are output to achieve rapid and accurate positioning of the fault phase, including:

[0051] Settings|X th1 -X th0 | is the fault identification interval. When it is detected that ΔX is continuously in the fault identification interval, the demodulated output signal 0.5 can be used as the threshold for determining the fault phase;

[0052] When it is determined that the converter fails, the data encoding signal of the next power generation cycle is collected and identified in time;

[0053] The two-bit coding signal after the fault signal is identified to determine the winding coding value of the next phase after the fault phase, and then infer the fault phase coding.

[0054] The present invention also provides a fault phase locating device for an asymmetric half-bridge power converter, the device comprising: a phase winding encoding module and a fault phase locating module;

[0055] The phase winding encoding module comprises:

[0056] The encoding module is used to divide the power generation interval of each phase bridge arm in a commutation cycle into two sub-intervals, and assign a binary code to each sub-interval to complete the encoding of each phase bridge arm; and select PWM signals of different frequencies to modulate the switch tube under the bridge arm according to the binary code corresponding to each phase bridge arm, wherein the binary code "0" corresponds to the PWM signal with a frequency of f0, and the binary code "1" corresponds to the PWM signal with a frequency of f1;

[0057] A modulation module is used to modulate the coded signal using a frequency shift keying method and output a PWM signal with digital information;

[0058] The OR operation module is used to process the PWM signal with digital information and the original driving signal of the lower bridge arm switch tube of each phase through OR processing to output a modulated signal for driving the switch tube on and off;

[0059] The fault phase locating module comprises:

[0060] The demodulation module is used to sample the output voltage of the converter and extract the signal ripple using a bandpass filter. After discrete Fourier transform demodulation calculation, the harmonic amplitudes at the f0 and f1 frequency points are selected and compared with the set threshold value to achieve demodulation of the digital coded signal.

[0061] The fault phase identification module is used to determine whether the converter has a phase failure through the demodulated digital code signal, and output the two-bit code after the fault signal to achieve rapid and accurate positioning of the fault phase.

[0062] Beneficial effects of the present invention:

[0063] The power converter fault phase location method of the present invention is applicable to the case where a converter has a phase loss fault. When operating normally, the modulation and demodulation parts of the signal in the method can still operate normally, and different coded signals are sent in the power generation stage of each phase, and the coding of each phase is identified by demodulating the voltage ripple signal, and the current working phase position is determined according to the coding obtained in real time, so as to monitor the working state of the converter in real time, save special fault monitoring sensors, and reduce costs. When a phase loss fault occurs in the converter, the fault signal can be obtained by detecting and analyzing the voltage ripple, and after identifying the phase loss fault signal, the fault phase position can be obtained by the specific coded signal. The fault phase location method can detect whether the converter has a phase loss fault, and when the converter is detected to have a phase loss fault, the fault phase position can be quickly determined, which is convenient for rapid troubleshooting and adjustment of the system, and improves the stability of system operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The accompanying drawings are part of the present invention and are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention, but do not constitute an improper limitation of the present invention. Obviously, the accompanying drawings described below are only some embodiments. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0065] Figure 1 It is a topological diagram of a four-phase asymmetric half-bridge power converter;

[0066] Figure 2 A flow chart of a method for locating a fault phase of an asymmetric half-bridge power converter provided by an embodiment of the present invention;

[0067] Figure 3 A schematic diagram of a converter coding signal modulation process provided in one embodiment of the present invention;

[0068] Figure 4 A schematic diagram of a converter signal demodulation process provided in an embodiment of the invention;

[0069] Figure 5 The output voltage and current waveforms of the converter bridge arm after encoding provided in one embodiment of the invention;

[0070] Figure 6 A converter fault phase locating signal waveform provided in an embodiment of the invention;

[0071] Figure 7 A flow chart of converter fault phase location provided in one embodiment of the invention;

[0072] Figure 8 A fault signal identification waveform when a phase B failure of a converter is provided in an embodiment of the invention;

[0073] Fig. 9 A structural block diagram of a converter system including a fault phase locating device for an asymmetric half-bridge power converter provided in one embodiment of the present invention.

[0074] It should be noted that these drawings and textual descriptions are not intended to limit the conceptual scope of the present invention in any way, but are intended to illustrate the concept of the present invention for those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0075] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0076] The object of the present invention is a four-phase asymmetric half-bridge power converter, whose topology is as follows: Figure 1 The power converter includes a DC voltage source U s , output voltage stabilizing capacitor C o , load resistance R, upper switch tube S1, lower switch tube S2 and freewheeling diodes VD1 and VD2 of the A phase bridge arm, upper switch tube S3, lower switch tube S4 and freewheeling diodes VD3 and VD4 of the B phase bridge arm, upper switch tube S5, lower switch tube S6 and freewheeling diodes VD5 and VD6 of the C phase bridge arm, upper switch tube S7, lower switch tube S8 and freewheeling diodes VD7 and VD8 of the D phase bridge arm, the gate input terminals of the switch tubes S2, S4, S6 and S8 are connected to the PWM signal output terminals corresponding to the PWM signal generator. DC voltage source U s The positive electrode is connected to the collector of the upper arm switch tubes S1, S3, S5 and S7 of the asymmetric half-bridge circuit, and the DC voltage source U s The negative electrode of the flyback diode VD1 is connected to the emitter of the lower bridge arm switch tube S2, S4, S6 and S8 of the asymmetric half-bridge circuit, the anode of the flyback diode VD1 and the cathode of VD2 are connected to the positive and negative electrodes of the A phase bridge arm, the anode of the flyback diode VD3 and the cathode of VD4 are connected to the positive and negative electrodes of the B phase bridge arm respectively, the anode of the flyback diode VD5 and the cathode of VD6 are connected to the positive and negative electrodes of the C phase bridge arm respectively, the anode of the flyback diode VD7 and the cathode of VD8 are connected to the positive and negative electrodes of the D phase bridge arm respectively, and the cathodes of the flyback diodes VD1, VD3, VD5 and VD7 are connected to the output voltage stabilizing capacitor C o The positive pole of the freewheeling diodes VD2, VD4, VD6 and VD8 is connected to the output voltage stabilizing capacitor C o The negative pole and DC voltage source U s The negative pole of the output voltage stabilizing capacitor Co The positive electrode of the load resistor R is connected to the positive electrode of the output voltage stabilizing capacitor C o The negative electrode of is connected to the negative electrode of the load resistor R.

[0077] Reference Figure 2 As shown, the embodiment of the present disclosure provides a method for locating a fault phase of an asymmetric half-bridge power converter, wherein each phase bridge arm of the asymmetric half-bridge converter is turned on in sequence, and the upper and lower bridge arm switches are controlled by a PWM signal of a set frequency within a conduction period, and the method includes:

[0078] Step S100: Divide the power generation interval of each phase bridge arm in a commutation cycle into two sub-intervals, and assign a binary code to each sub-interval to complete the encoding of each phase bridge arm.

[0079] In the embodiment of the present application, the two sub-intervals in the power generation interval are marked as interval O and interval T respectively; in interval O, the phase current is greater than the load current flowing through the load resistor R, and the output voltage stabilizing capacitor C o In the charging stage, the output voltage U o Rise; in interval T, the phase current is less than the load current, at this time the output voltage stabilizing capacitor C o In the discharge stage, the output voltage U o decline.

[0080] Furthermore, the corresponding coding value of phase A of the asymmetric half-bridge power converter is defined as "00", the corresponding coding value of phase B is defined as "01", the corresponding coding value of phase C is defined as "10", and the corresponding coding value of phase D is defined as "11". The position sensor feedback signal is used to determine the position angle of the SRG rotor, and the serial number of the phase bridge arm of the power converter in the power generation interval is determined. According to the coding value of the phase bridge arm, the PWM signal of the corresponding frequency is selected to realize the modulation of the converter, and the coding of each phase bridge arm is completed.

[0081] The bridge arms of each phase are encoded and marked by using a binary data combination method. The power generation interval in the commutation interval of each bridge arm is divided into two sub-intervals. In each sub-interval, two different frequency PWM signals are used to drive the power switch tube, and the two frequencies represent the number "0" and the number "1" respectively. Each bridge arm of each phase can be marked with a two-bit binary code modulated in two sub-intervals. In other words, the encoding of each bridge arm of each phase can be achieved through the combination of binary codes. Under this strategy, after determining the data encoding of each bridge arm of each phase, the encoding of each bridge arm of the power converter is modulated with a PWM signal of the corresponding frequency in the power generation or excitation interval, and a corresponding voltage ripple signal will be generated at the output end, thereby achieving the purpose of implementing the encoding of each bridge arm of each phase using a composite modulation strategy.

[0082] Step S200: Select PWM signals of different frequencies to modulate the switch tube under the bridge arm according to the binary code corresponding to each phase bridge arm, wherein the binary code "0" corresponds to the PWM signal with a frequency of f0, and the binary code "1" corresponds to the PWM signal with a frequency of f1.

[0083] Step S300: frequency shift keying is used to perform composite modulation of the energy signal, and a PWM signal with digital information is output.

[0084] Figure 3 The schematic diagram of the converter coding signal modulation process is shown in Figure 2. The specific steps of using frequency shift keying method to perform energy signal composite modulation are as follows:

[0085] A baseband signal s(t) is generated by a signal generator, and the baseband signal s(t) includes a series of binary 0 / 1 sequences; when s(t)=1, carrier signal 1 is selected, and the modulation frequency is f1, and since s(t)=0, carrier signal 0 is not selected; when s(t)=1, carrier signal 0 is selected, and the modulation frequency is f0, and since s(t)=0, carrier signal 1 is not selected; the selected carrier signals are superimposed through an adder to obtain the final output carrier signal s BFSK (t), the voltage modulation amount u p (t) and the carrier signal s BFSK (t) Through comparison by a comparator, the comparator outputs a PWM signal with digital information, specifically:

[0086] When u p (t) is greater than s BFSK At (t), the comparator outputs logic 0;

[0087] When u p (t) is less than s BFSK At (t), the comparator outputs logic 1.

[0088] Step S400: The PWM signal with digital information and the original driving signal of the lower bridge arm switch tube of each phase are passed or processed to output a modulated signal for driving the switch tube to turn on and off.

[0089] The binary coded signal consisting of "0" or "1" is modulated to the output voltage ripple using binary frequency shift keying (BFSK). This frequency shift keying method mainly uses a voltage ripple signal of a specific frequency as the carrier of the digital "0" or "1" signal to transmit the digital coded information to the signal receiving end or the fault status monitoring point. In the BFSK modulation method, a ripple signal with a frequency of f0 is used to represent the binary "0", and a ripple signal with a frequency of f1 is used to represent the binary "1". When the receiving end detects a voltage ripple with a frequency of f0, it indicates that a signal "0" has been received; when a signal with a frequency of f1 is detected, it indicates that a signal "1" has been received. Among them, the BFSK signal can be expressed in the time domain as:

[0090]

[0091] Among them, A is the signal carrier amplitude, f0 and f1 are the carrier signal frequencies representing the digital "0" and "1" respectively.

[0092] After step 300, the comparator finally outputs a PWM signal with digital information, and outputs a modulated signal through or processing with the original driving signal of the lower bridge arm switch tube of each phase. The signal drives the switch tube to turn on and off, and generates a voltage ripple with the same PWM frequency on the output side.

[0093] That is, when transmitting information, the voltage ripple modulated by the BFSK method is actually the superposition of two carrier signals, which can be further expressed as:

[0094]

[0095] Among them, a n is the binary digital sequence sent, which can be expressed as:

[0096]

[0097] and for a n The inverse code can be expressed as:

[0098]

[0099] The BFSK method is used to modulate the driving PWM signal of the switch tube. The frequency of the PWM signal determines the frequency of the signal carrier (voltage ripple). Therefore, by adjusting the PWM signal, a voltage ripple of a specific frequency can be modulated on the output voltage as a signal carrier.

[0100] Step S500: sampling the converter output voltage and extracting the signal ripple using a bandpass filter, selecting the harmonic amplitudes at the frequency points f0 and f1 and comparing them with the set threshold after discrete Fourier transform demodulation calculation, thereby achieving demodulation of the digital coded signal.

[0101] Figure 4 This is a schematic diagram of the converter signal demodulation process. In each sampling period, the output voltage U o Sampling, setting the passband frequency of the bandpass filter, retaining U o The voltage ripple components of the intermediate frequencies f0 and f1 are input into the DFT demodulator after filtering, and the amplitude of the carrier signal at a specific frequency point is selected for difference and compared with the set threshold, thereby realizing digital signal demodulation.

[0102] In the embodiment of the present application, the specific process of discrete Fourier transform demodulation calculation is:

[0103] In a Fourier period T s Inside, with f smp The frequency is sampled, and the number of sampling points is N, then we can get:

[0104]

[0105] Among them, f s is the fundamental frequency;

[0106] For the frequency shift keying modulated signal s BFSK (t), in period T s In the Fourier series expansion, we can get:

[0107]

[0108] Among them, c k is the Fourier coefficient, which satisfies the expression:

[0109]

[0110] The carrier frequencies f0 and f1 set by the modulation coding signals "0" and "1" correspond to s BFSK (t) The m0th and m1th harmonics in (t).

[0111] Fourier period T s The expression is satisfied:

[0112]

[0113] According to Nyquist sampling theorem, the sampling frequency f smp And the carrier frequencies f0 and f1 should satisfy:

[0114] f smp ≥2max{f0,f1}

[0115] For a sampling sequence x(n) with N sampling points, its discrete Fourier transform is:

[0116]

[0117] For the m0th and m1th harmonics, that is, the carrier frequencies f0 and f1 of the selected data signal, their discrete Fourier transforms satisfy:

[0118]

[0119] Wherein, X(m0) and X(m1) are the amplitudes of the voltage ripples corresponding to the digital signals “0” and “1” respectively.

[0120] In a preferred embodiment, in order to prevent data demodulation from causing bit errors due to improper selection of a demodulation threshold, the signal ripple amplitude difference ΔX=[X(m0)-X(m1)] is selected as the data demodulation threshold to reduce the bit error rate.

[0121] In the embodiment of the present application, after discrete Fourier transform demodulation calculation, the harmonic amplitudes at the frequency points f0 and f1 are selected and compared with the set threshold value, thereby realizing demodulation of the digital coded signal, including:

[0122] When the digital signal is "0", the output signal amplitude is X(f0); when the digital signal is "1", the output signal amplitude is X(f1);

[0123] Let the signal ripple amplitude difference ΔX equal to X(f1)-X(f0), and set the demodulation threshold to X th1 and X th0 ;

[0124] When the signal ripple amplitude difference ΔX is greater than X th1 When the signal ripple amplitude difference ΔX is less than X, it is demodulated to digital "1". th0 When , it is demodulated to digital "0";

[0125] The modulated phase bridge arm coding signal is restored according to the demodulated digital information.

[0126] The present invention adopts a composite modulation strategy of electric energy and signals to generate a voltage ripple loaded with data information on the output side of the power converter, and adopts a DFT algorithm to demodulate the voltage ripple signal loaded with data information. That is, within a set time period, a PWM signal of a specific frequency is used to drive the switch tube below in the power generation interval of each phase bridge arm, and while ensuring that the output voltage of the converter dynamically tracks a given value, a high-frequency voltage ripple consistent with the frequency of the specific PWM signal can be formed on the output power bus, and the voltage ripple of the specific frequency is used to represent data "1" or "0"; data "1" or "0" can be represented by two voltage ripple signals of specific frequencies respectively.

[0127] Specifically, two PWM signals of different frequencies are used to drive the switch tube under the bridge arm in the power generation interval of each phase bridge arm, and the switching frequency information is loaded into the output side voltage ripple. The signal ripple with the same frequency as the PWM signal driving the switch tube can be detected in the output voltage, and the two frequencies represent the digital "0" and the digital "1" respectively; according to the fast discrete Fourier transform (Discrete Fourier Transform, DFT) algorithm, the output voltage is demodulated, and the amplitude of the two frequency components is compared with the set threshold value, and the signal ripple is restored to the digital "0" and the digital "1". Thus, the phase bridge arm coding signal modulated in step S100 and step S200 is restored.

[0128] Figure 5 is the output voltage and current waveform of the converter phase bridge arm after encoding, where Figure 5 (a) is the output voltage waveform and the digital coding signal of the phase bridge arm. When the binary signal "0" is encoded, the signal carrier s0(t) with a signal frequency of f0 is selected for modulation. It can be seen that the output voltage contains a ripple with a frequency of f0. When the binary signal "1" is encoded, the signal carrier s1(t) with a frequency of f1 is selected for modulation. It can be seen that the output voltage contains a signal ripple with a frequency of f1. Figure 5 (b) is the output current waveform. Taking phase B as an example, the phase bridge arm cut-off angle is θ offB , the commutation angle is θ com , corresponding to the four-phase asymmetric half-bridge converter, the conduction angle of each phase is θ com Generally, it is set to 15°. offB ≤θ<θ offB +θ com When S4 is turned off, the B phase is in the power generation stage. At this time, the upper bridge arm switch tube S3 is naturally turned off, and the lower bridge arm switch tube S4 is driven by the signal carrier s0(t) in the first half of the commutation cycle, and the switch tube is driven on and off at a frequency of f0. When S4 is turned off, the output voltage at both ends of the B phase is negative, and the B phase current i B Normal output; when S4 is turned on, i B The zero voltage loop is formed by S4 and the switch tube D4 connected in parallel at both ends, and the output is zero. The second half of the commutation cycle is driven by the signal carrier s1(t), which drives the switch tube on and off at the frequency f1. When S4 is turned off, the output voltage at both ends of phase B is negative, and the current i B Normal output; when S4 is turned on, i B A zero voltage loop is formed by S4 and the switch tube D4 connected in parallel at both ends thereof, and the output is zero.

[0129] Figure 6 is the relevant signal waveform for implementing the converter fault phase location strategy, where Figure 6(a) is the output voltage waveform and the code value corresponding to each phase bridge arm. Different code values ​​correspond to voltage ripples of different frequencies. Phase A is coded 00, so s0(t) is used to drive the entire commutation cycle; Phase C is coded 10, so s1(t) is used to drive the first half of the commutation cycle and s0(t) is used to drive the second half; Phase D is coded 11, so s1(t) is used to drive the entire commutation cycle. Assuming that a phase failure occurs in Phase B, the lower switch tube S4 has no driving signal, and the phase voltage cannot be established during the excitation stage. Modulation coding cannot be performed through the switch tube S4, and the voltage of Phase B is in a reduced state. Figure 6 (b) is the amplitude of the fundamental component of the output voltage. When the digital signal is "0", the output signal amplitude is X(f0); when the digital signal is "1", the output signal amplitude is X(f1). Figure 6 (c) is the signal ripple amplitude difference ΔX, which is equal to X(f1)-X(f0), and the demodulation threshold is set to X th1 and X th0 When the difference is greater than X th1 When the difference is less than X, it is demodulated to digital "1". th0 When , it is demodulated into digital "0".

[0130] Step S600: Determine whether a phase failure occurs in the converter by using the demodulated digital code signal, and output the two-bit code after the fault signal to achieve rapid and accurate positioning of the faulty phase.

[0131] In the embodiment of the present application, whether a phase failure occurs in the converter is determined by using the demodulated digital code signal, and the two-bit code after the fault signal is output to achieve rapid and accurate positioning of the fault phase, including:

[0132] Step 610: Set | X th1 -X th0 | is the fault identification interval. When it is detected that ΔX is continuously in the fault identification interval, the demodulation module outputs a digital signal of 0.5, indicating that a phase failure occurs in the phase.

[0133] Step 620: When it is determined that the converter fails, timely collect and identify the data encoding signal of the next power generation cycle;

[0134] Step 630: Identify the two-bit coding signal following the fault signal, determine the winding coding value of the next phase after the fault phase, and then infer the fault phase coding.

[0135] Figure 6 (d) is the demodulated digital signal, where phase A, phase C and phase D correspond to digital signals 00, 10 and 11 respectively, and phase B is the fault phase, and its corresponding digital signal is 0.5. Therefore, when the phase bridge arm with a demodulated signal of 0.5 is detected, the serial number of the faulty phase can be deduced through the serial numbers of the previous and next phases, thereby locating the faulty phase.

[0136] Figure 7 This is a flowchart for fault phase positioning. First, the power generation interval of each phase bridge arm in a commutation cycle is divided into two sub-intervals, and a binary code is assigned to each sub-interval. The signal carrier of the corresponding frequency is selected according to the selected binary code, and the frequency shift keying method is used for modulation to output a PWM signal with digital information. Secondly, the control signal is obtained by processing the PWM signal with digital information and the driving signal of the switch tube under the phase bridge arm, which is used to drive the on and off of the lower switch tube. Finally, the output voltage is sampled, and the signal ripple is extracted by a bandpass filter. The signal ripple amplitude difference ΔX is obtained by DFT calculation to determine whether ΔX is continuously in the fault judgment interval |X th0 -X th1 |, if not satisfied, it means that the converter has not suffered a phase failure. When it is determined that the converter has a fault, the two-bit coding signal after the fault signal is identified to determine the winding coding value of the next phase of the fault phase, and then infer the fault phase coding. Figure 7 The data identification method identifies the coding value of the next phase winding adjacent to the faulty phase, and it can be inferred that the faulty phase is the previous phase of the bridge arm of this phase.

[0137] Figure 8 The waveforms from top to bottom are the output voltage waveform U o , ripple amplitude difference ΔX and demodulation signal. As can be seen from the figure, when a phase failure occurs in phase B, ΔX is continuously in the fault range, and the demodulation signal output is 0.5. By identifying the faulty post-encoding signal, it is determined to be phase C, and it is inferred that the faulty phase is phase B. The experimental waveform is basically consistent with the theory, which shows the feasibility and effectiveness of this strategy.

[0138] Next, the implementation process of fault phase location of the power converter is introduced in combination with the topological structure of the four-phase asymmetric half-bridge power converter.

[0139] By means of the upper and lower switch tubes (S1~S8) of each phase arm of the asymmetric half-bridge, the duty cycle and frequency of the switch tube PWM signal are modulated, and the duty cycle of the PWM signal is adjusted to stabilize the output voltage to the target voltage. At the same time, the frequency of the output voltage ripple is modulated to express the digital "0" or "1" with the voltage ripple frequency. In other words, the binary coded signal composed of "0" or "1" is modulated to the output voltage ripple by binary frequency shift keying (BFSK). This frequency shift keying method mainly uses a voltage ripple signal of a specific frequency as the carrier of the digital "0" or "1" signal to transmit the digital coded information to the signal receiving end or the fault status monitoring point. In the BFSK modulation method, a ripple signal with a frequency of f0 is used to represent the binary "0", and a ripple signal with a frequency of f1 is used to represent the binary "1". When a voltage ripple with a frequency of f0 is detected at the fault monitoring point, it means that the signal "0" is received; when a signal with a frequency of f1 is detected, it means that the signal "1" is received. Among them, the BFSK signal can be expressed in the time domain as:

[0140]

[0141] Among them, A is the signal carrier amplitude, f0 and f1 are the carrier signal frequencies representing the digital signals "0" and "1" respectively.

[0142] According to the switching characteristics of the asymmetric half-bridge converter, the power generation interval in each switching cycle is divided into two sub-intervals, which are defined as interval O and interval T. When a phase fault occurs in the converter, in order to quickly determine the location of the faulty phase, digital encoding is performed for each phase bridge arm of the converter. For a four-phase asymmetric half-bridge power converter, a two-bit binary code is required to realize the encoding of the four-phase bridge arm. Define the corresponding encoding value of A as "00", the corresponding encoding value of B as "01", the corresponding encoding value of C as "10", and the corresponding encoding value of D as "11". According to different encoding values, in interval O and interval T, the aforementioned BFSK method is used to modulate a PWM signal of the corresponding frequency within a data code element period, wherein a PWM signal with a frequency of f0 is modulated corresponding to the encoding value "0", and a PWM signal with a frequency of f1 is modulated corresponding to the encoding value "1". According to the encoding value of the phase bridge arm, the PWM signal of the corresponding frequency is selected to realize the modulation of the converter and complete the encoding of each phase bridge arm.

[0143] Take the B-phase bridge arm as an example for explanation. As mentioned above, the encoding value of the B-phase bridge arm is "01", so in the first half interval (interval O) of the B-phase bridge arm power generation operation, a PWM signal with a frequency of f0 is selected; in the second half interval (interval T), a PWM signal with a frequency of f1 is selected. After this ripple modulated PWM signal and the PWM switch tube drive signal of the B-phase bridge arm power modulation are processed or processed, they are used to drive the on and off of the switch tube S4 under the B-phase bridge arm, and then the encoded voltage ripple signal can be modulated on the output voltage, that is, the high-frequency voltage ripple with a frequency of f0 in the first half and the high-frequency voltage ripple with a frequency of f1 in the second half. At the signal receiving end or the state monitoring point, the encoded signal "01" can be obtained by the signal demodulation method, so that it can be inferred that the phase bridge arm in the power generation interval at this time is the B phase, and the positioning of the phase bridge arm is achieved. For signal demodulation, refer to the description of step S300.

[0144] In order to prevent large errors in data demodulation, ΔX = [X(m0) - X(m1)] is generally selected as the basis for data demodulation to reduce the bit error rate. Set a suitable threshold X th1 and X th0 , when no converter fault occurs, ΔX should not exceed the threshold value X th1 and X th0 If it is detected that ΔX is greater than the threshold value X th1 When ΔX is detected to be less than the threshold value X, the demodulated signal is recognized as data "1"; th0 When , the demodulated signal is identified as data "0". Through the threshold comparison method, the phase bridge arm coding signal modulated in step S100 and step S200 is restored.

[0145] Since the fault phase has no current / power output, its corresponding output voltage and voltage ripple are zero. The fault identification mechanism is triggered by detecting the change in the output voltage of the power converter and recording the fault time. Then, the FFT algorithm is started to analyze the voltage ripple. The data encoding of the next adjacent phase bridge arm of the fault phase can be obtained by analyzing the voltage ripple, and then the position of the fault phase can be inferred. For example, taking the A-phase bridge arm fault as an example, when the A-phase fault occurs, although the voltage ripple cannot be modulated by the A-phase bridge arm to load the data encoding, the fault detection mechanism can be triggered by the voltage change; after the phase change, the B-phase is turned on and the data encoding is performed at the same time, then the voltage ripple can be analyzed to determine that this is the B-phase working interval, and then the previous phase fault, that is, the A-phase fault, can be inferred. The processing method for other phase faults is similar.

[0146] Specifically, when a phase of the converter fails, there is no current / power output in the faulty phase, and the load is mainly composed of the output capacitor C oEnergy is supplied, and the output side voltage drops rapidly during the working period of this phase, and the output side voltage gradually rises until it switches to other phases for power generation. Therefore, the voltage amplitude of this rapid drop can be used as one of the criteria for determining whether a fault has occurred. At the same time, due to the protection isolation of the faulty phase, the faulty phase can no longer achieve the composite modulation of electric energy and signals, and cannot form a voltage ripple carrying data signals, that is, the corresponding X(m0) and X(m1) in the working cycle of the faulty phase are both output as zero, then the values ​​of X(m0), X(m1) and ΔX can also be used as a basis for determining whether a fault has occurred. After receiving the fault signal, the system promptly collects and identifies the data encoding signal of the next power generation cycle, so as to accurately infer the faulty phase. Assuming that a fault occurs in phase B, the protection is activated and phase B is isolated. Phase B has no current / power output, and the encoding ("01") of phase B cannot be modulated to the output voltage ripple. X(m0) and X(m1) are both zero during the working cycle of phase B, and the fault location system can determine the occurrence of the fault through this calculation result. Phases C, D, and A are still working normally, and composite modulation of power and data can still be achieved. The fault location system collects the bus voltage ripple signal and can identify the C phase coding signal "10". Based on the C phase coding, it can be inferred that phase B has a fault.

[0147] In one embodiment, a fault phase location device for an asymmetric half-bridge power converter is proposed. Fig. 9 As shown, the device includes: a phase winding encoding module and a fault phase locating module; wherein the phase winding encoding module includes:

[0148] The encoding module is used to divide the power generation interval of each phase bridge arm in a commutation cycle into two sub-intervals, and assign a binary code to each sub-interval to complete the encoding of each phase bridge arm; and select PWM signals of different frequencies to modulate the switch tube under the bridge arm according to the binary code corresponding to each phase bridge arm, wherein the binary code "0" corresponds to the PWM signal with a frequency of f0, and the binary code "1" corresponds to the PWM signal with a frequency of f1;

[0149] A modulation module is used to perform composite modulation of energy signals using a frequency shift keying method and output a PWM signal with digital information;

[0150] The OR operation module is used to process the PWM signal with digital information and the original driving signal of the lower bridge arm switch tube of each phase through OR processing to output a modulated signal for driving the switch tube on and off;

[0151] The fault phase location module includes:

[0152] The demodulation module is used to sample the output voltage of the converter and extract the signal ripple using a bandpass filter. After discrete Fourier transform demodulation calculation, the harmonic amplitudes at the f0 and f1 frequency points are selected and compared with the set threshold value to achieve demodulation of the digital coded signal.

[0153] The fault phase identification module is used to determine whether the converter has a phase failure through the demodulated digital code signal, and output the two-bit code after the fault signal to achieve rapid and accurate positioning of the fault phase.

[0154] It should be noted that the asymmetric half-bridge power converter fault phase locating device provided in the above embodiment only uses the division of the above-mentioned functional modules as an example when executing the asymmetric half-bridge power converter fault phase locating method. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the asymmetric half-bridge power converter fault phase locating device provided in the above embodiment and the asymmetric half-bridge power converter fault phase locating method embodiment belong to the same concept, and its implementation process is detailed in the asymmetric half-bridge power converter fault phase locating method embodiment, which will not be repeated here.

[0155] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0156] In addition, those skilled in the art will understand that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments also means being within the scope of protection of the present invention and forming different embodiments. For example, in the above embodiments, those skilled in the art can use them in combination according to the known technical solutions and the technical problems to be solved by this application.

Claims

1. A method for locating a fault phase of an asymmetric half-bridge power converter, characterized in that: The bridge arms of each phase of the asymmetric half-bridge converter are turned on in sequence, and the upper and lower bridge arm switches are controlled by a PWM signal of a set frequency during a conduction period. The method includes: The power generation interval of each phase bridge arm in a commutation cycle is divided into two sub-intervals, and a binary code is assigned to each sub-interval to complete the encoding of each phase bridge arm; According to the binary code corresponding to each phase bridge arm, a PWM signal with different frequencies is selected to modulate the switch tube under the bridge arm, wherein the binary code "0" corresponds to a PWM signal with a frequency of f0, and the binary code "1" corresponds to a PWM signal with a frequency of f1; Frequency shift keying is used to perform composite modulation of energy signals and output PWM signals with digital information; The PWM signal with digital information and the original driving signal of the lower bridge arm switch tube of each phase are passed or processed to output a modulated signal for driving the switch tube on and off; The output voltage of the sampling converter is used to extract the signal ripple using a bandpass filter. After discrete Fourier transform demodulation calculation, the harmonic amplitudes at the frequency points f0 and f1 are selected and compared with the set threshold value to achieve demodulation of the digital coded signal. The demodulated digital code signal is used to determine whether the converter has a phase failure, and the two-bit code after the fault signal is output to achieve rapid and accurate positioning of the faulty phase.

2. The method for locating a fault phase of an asymmetric half-bridge power converter according to claim 1, characterized in that: The two sub-intervals in the power generation interval are marked as interval O and interval T respectively; in interval O, the phase current is greater than the load current flowing through the load resistor R, at this time the output voltage stabilizing capacitor C o In the charging stage, the output voltage U o Rise; in interval T, the phase current is less than the load current, at this time the output voltage stabilizing capacitor C o In the discharge stage, the output voltage U o decline.

3. The method for locating a fault phase of an asymmetric half-bridge power converter according to claim 2, characterized in that: Define the corresponding coding value of phase A of the asymmetric half-bridge power converter as "00", the corresponding coding value of phase B as "01", the corresponding coding value of phase C as "10", and the corresponding coding value of phase D as "11". Use the feedback signal of the position sensor to determine the position angle of the SRG rotor and the serial number of the phase bridge arm of the power converter in the power generation interval at this time. According to the coding value of the phase bridge arm, select the PWM signal of the corresponding frequency to realize the modulation of the converter and complete the coding of each phase bridge arm.

4. The method for locating a fault phase of an asymmetric half-bridge power converter according to claim 1, characterized in that: The specific steps of using the frequency shift keying method to perform energy signal composite modulation are: The signal generator generates a baseband signal s(t), which contains a series of binary 0 / 1 sequences. When s(t)=1, the carrier signal 1 is selected, and the modulation frequency is f1. Therefore, the carrier signal 0 is not selected; when When , the carrier signal 0 is selected, the modulation frequency is f0, and since s(t) = 0, the carrier signal 1 is not selected; the selected carrier signal is superimposed through the adder to obtain the final output carrier signal s BFSK (t), the voltage modulation amount u p (t) and the carrier signal s BFSK (t) Through comparison by a comparator, the comparator outputs a PWM signal with digital information, specifically: When u p (t) is greater than s BFSK At (t), the comparator outputs logic 0; When u p (t) is less than s BFSK At (t), the comparator outputs logic 1.

5. The method for locating a fault phase of an asymmetric half-bridge power converter according to claim 4, characterized in that: The PWM signal with digital information and the original driving signal of the lower bridge arm switch tube of each phase are processed or output as a modulated signal: Among them, A is the signal carrier amplitude, f0 and f1 are the carrier signal frequencies representing the digital "0" and "1" respectively, and a n is the binary digital sequence sent, expressed as: for a n The inverse code is expressed as:

6. The method for locating a fault phase of an asymmetric half-bridge power converter according to claim 1, characterized in that: The specific process of the discrete Fourier transform demodulation calculation is: In a Fourier period T s Inside, with f smp The frequency is sampled, and the number of sampling points is N, then we can get: Among them, f s is the fundamental frequency; For the frequency shift keying modulated signal s BFSK (t), in period T s In the Fourier series expansion, we can get: Among them, c k is the Fourier coefficient, which satisfies the expression: The carrier frequencies f0 and f1 set by the modulation coding signals "0" and "1" correspond to s BFSK The m0th and m1th harmonics in (t); Fourier period T s The expression is satisfied: According to Nyquist sampling theorem, the sampling frequency f smp And the carrier frequencies f0 and f1 should satisfy: f smp ≥2max{f0,f1} For a sampling sequence x(n) with N sampling points, its discrete Fourier transform is: For the m0th and m1th harmonics, that is, the carrier frequencies f0 and f1 of the selected data signal, their discrete Fourier transforms satisfy: Among them, X(m0) and X(m1) are the amplitudes of the voltage ripples corresponding to the digital signals "0" and "1" respectively.

7. The method for locating a fault phase of an asymmetric half-bridge power converter according to claim 6, characterized in that: In order to prevent the occurrence of bit errors due to improper selection of the demodulation threshold in data demodulation, the signal ripple amplitude difference ΔX=[X(m0)-X(m1)] is selected as the data demodulation threshold to reduce the bit error rate.

8. The method for locating a fault phase of an asymmetric half-bridge power converter according to claim 7, characterized in that: After discrete Fourier transform calculation, the demodulation amplitude of the frequency points f0 and f1 is selected and compared with the set threshold to realize the demodulation of the digital coded signal, including: When the digital signal is "0", the output signal amplitude is X(f0); when the digital signal is "1", the output signal amplitude is X(f1); Let the signal ripple amplitude difference ΔX equal to X(f1)-X(f0), and set the demodulation threshold to X th1 and X th0 ; When the signal ripple amplitude difference ΔX is greater than X th1 When the signal ripple amplitude difference ΔX is less than X th0 When , it is demodulated to digital "0"; The modulated phase bridge arm coding signal is restored according to the demodulated digital information.

9. The method for locating a fault phase of an asymmetric half-bridge power converter according to claim 8, characterized in that: The demodulated digital code signal is used to determine whether the converter has a phase failure, and the two-bit code of the phase after the fault signal is output to achieve rapid and accurate positioning of the fault phase, including: Settings|X th1 -X th0 | is the fault identification interval. When it is detected that ΔX is continuously in the fault identification interval, the demodulated output signal 0.5 can be used as the threshold for determining the fault phase; When it is determined that the converter fails, the data encoding signal of the next power generation cycle is collected and identified in time; The two-bit coding signal after the fault signal is identified to determine the winding coding value of the next phase after the fault phase, and then infer the fault phase coding.

10. A fault phase locating device for an asymmetric half-bridge power converter, characterized in that: The device comprises: a phase winding encoding module and a fault phase locating module; The phase winding encoding module comprises: The encoding module is used to divide the power generation interval of each phase bridge arm in a commutation cycle into two sub-intervals, and assign a binary code to each interval to complete the encoding of each phase bridge arm; and select PWM signals of different frequencies to modulate the switch tube under the bridge arm according to the binary code corresponding to each phase bridge arm, wherein the binary code "0" corresponds to the PWM signal with a frequency of f0, and the binary code "1" corresponds to the PWM signal with a frequency of f1; A modulation module is used to modulate the coded signal using a frequency shift keying method and output a PWM signal with digital information; The OR operation module is used to process the PWM signal with digital information and the original driving signal of the lower bridge arm switch tube of each phase through OR processing to output a modulated signal for driving the switch tube on and off; The fault phase locating module comprises: The demodulation module is used to sample the output voltage of the converter and extract the signal ripple using a bandpass filter. After discrete Fourier transform demodulation calculation, the harmonic amplitudes at the f0 and f1 frequency points are selected and compared with the set threshold value to achieve demodulation of the digital coded signal. The fault phase identification module is used to determine whether the converter has a phase failure through the demodulated digital code signal, and output the two-bit code after the fault signal to achieve rapid and accurate positioning of the fault phase.

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