Phase synchronization algorithm

Abstract

The invention discloses a phase synchronization algorithm, which comprises at least four AD9361 radio frequency converters used for receiving radio frequency signals from a plurality of antenna array elements; the clock synchronization module realizes clock synchronization of a plurality of AD9361 chips through the following modes: XTALN clock pins of all AD9361 chips are connected to the same clock source, and the electrical lengths of circuits for feeding reference clocks are ensured to be equal; the same frequency command is sent to each AD9361, and the same BBPLL frequency is set; generating the same internal sampling clock and DATACLK output through setting of a standard register, and writing the internal sampling clock and the DATACLK output into each AD9361; the method has the advantages that under the application condition of the music algorithm, the phase synchronization algorithm of the multiple AD9361 chips can control the phase change of the channels to be within 1 degree after correction, the phase difference between the channels in the whole working process is controlled to be within 10 degrees, the angle measurement precision of the direction finding method in the form is basically equivalent to that of a simulation result, and the method is suitable for large-scale popularization and application. The index requirement that the direction finding error is smaller than 2 degrees can be met.

Description

Technical Field

[0001] The invention belongs to the technical field of radio positioning, and in particular relates to a phase synchronization algorithm. Background Art

[0002] In order to meet the need for relative positioning during aircraft cluster transportation or coordinated operations under satellite denial conditions, the aircraft is equipped with formation position keeping equipment that can provide position information of other members in the formation relative to the aircraft. The equipment can provide the aircraft with the azimuth, slant range, lateral distance, longitudinal distance and altitude difference of other aircraft relative to the aircraft, which is used for formation position maintenance and safe distance warning.

[0003] like Figure 1 As shown, Figure 1 In the figure, the plane is taken as the origin to establish the rectangular coordinate system of the aircraft. The positive direction of the x-axis is the direction of the nose of the aircraft, the y-axis is the direction of the left wing, and the z-axis is perpendicular to the ground. Then the slant distance of aircraft 2 relative to the aircraft is The azimuth angle is θ, the lateral distance of aircraft 2 relative to this aircraft is y1, the longitudinal distance is x1, and the height difference is z1.

[0004] In order to improve the integration of the equipment, reduce power consumption, and reduce the size of the equipment to make it more adaptable to installation, the RF agile transceiver AD9361 chip is used to directly sample the RF signal, and a multi-element receiving antenna combined with the MUSIC direction-finding algorithm is used to measure the azimuth angle. The AD9361 has ultra-high integration and low power consumption. At the same time, the device's programmability, configurable bandwidth, two receiving inputs, and two transmitting outputs make it an ideal choice for multi-channel receiving systems. The use of this chip greatly simplifies the design of the receiving and transmitting channels, but at the same time, the multi-element antenna signal requires multiple AD9361 chips to complete data sampling. When there is a phase error, the amplitude and phase errors of the array signal need to be corrected before using the MUSIC algorithm for DOA estimation. This requires that the phase synchronization of the data between multiple AD9361 chips must be completed during use. Summary of the invention

[0005] The purpose of the present invention is to provide a phase synchronization algorithm, which can synchronize the clocks of multiple AD9361 chips, and use the algorithm to compensate the phase deviation after each synchronization to within 1 degree. At the same time, in order to solve the problem that the phase of AD9361 data drifts due to temperature changes, a correction method is also given, so that the phase consistency of each channel is basically guaranteed to be within 10 degrees in the full temperature range, thereby ensuring that the sampling data of multi-channel AD9361 meets the angle measurement requirements of the music algorithm.

[0006] To achieve the above object, the present invention provides the following technical solution: a phase synchronization algorithm, comprising

[0007] At least four AD9361 RF converters for receiving RF signals from multiple antenna array elements;

[0008] Clock synchronization module, which realizes the clock synchronization of multiple AD9361 chips in the following ways:

[0009] Connect the XTALN clock pins of all AD9361s to the same clock source and ensure that the electrical lengths of the lines feeding the reference clock are equal;

[0010] Send the same frequency command to each AD9361 to set the same BBPLL frequency;

[0011] Generate the same internal sampling clock and DATA_CLK output through standard register settings and write to each AD9361;

[0012] Enable the multi-chip synchronization MCS function of the BBPLL and input a synchronization pulse to the SYNC_IN pin of each AD9361 to achieve clock synchronization; after the synchronization is completed, clear the MCS-related enable bit to prevent the synchronization function from being accidentally triggered;

[0013] Phase synchronization module, which is used to obtain the phase difference of each receiving channel relative to the calibration channel in the calibration working state, and perform phase compensation in the direction finding working state. The specific steps include:

[0014] a. In the calibration working state, the phase difference of each channel relative to the self-calibration source channel is measured one by one through the self-calibration source signal and SPI bus control;

[0015] b. In the direction finding working state, according to the phase difference obtained in step a, the sampling data of each channel is phase compensated to ensure the phase synchronization between the channels.

[0016] As a preferred technical solution of the present invention, four AD9361s are used to receive signals from seven receiving channels in total, and one of the AD9361s is used to output the self-calibration source signal from the signal processing to the RF front end. The RF front end controls which channel the 8-to-1 switch and the 2-to-1 switch connect according to the SPI bus command of the received signal processing.

[0017] As a preferred technical solution of the present invention, in the direction finding working state, the signal processing does not output the self-calibration source signal, the 7-way 2-to-1 switch is turned to the antenna element end, the RF signal of the 7-way antenna element is received, and sent to the signal processing, and the phase error compensation is performed and then processed to complete the direction finding.

[0018] As a preferred technical solution of the present invention, when in the calibration working state, the signal processing outputs the self-calibration source signal, and controls the RF front end through the SPI bus to connect the 2-to-1 switch to the output of the 8-to-1 switch - the self-calibration source, and controls the 8-to-1 switch to switch 7 channels in turn, and obtains the phase difference of the 7 channels relative to the calibration source respectively.

[0019] As a preferred technical solution of the present invention, it also includes setting the MCS BBPLLEnable and MCS BB Enable bits in each AD9361, and then setting the MCS refclk Scale En bit to enable the multi-chip synchronization MCS of the BBPLL and refer to the correct internal clock.

[0020] As a preferred technical solution of the present invention, it also includes inputting a rising edge pulse to the SYNC_IN pin of each AD9361. In the case where the internal BBPLL REF_CLK is a buffered version of the external REF_CLK, there must be a delay in the rising edge of the SYNC_IN pulse from the REF_CLK input to the XTALN to ensure synchronization; after the BBPLL is synchronized, the MCS BBPLL Enable bit is cleared, and the MCS digital clock Enable bit is set, while the setting of the MCS BB Enable bit is maintained.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] When the music algorithm is applied, the phase synchronization algorithm of multiple AD9361s can control the phase change of the channel to within 1° after correction, and control the phase difference between channels to within 10° during the entire working process. The angular measurement accuracy of this direction finding method is basically equivalent to the simulation result, and the direction finding error can be less than 2 degrees. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic diagram of the relative positioning of aircraft;

[0024] Figure 2 It is a principle block diagram of the array direction finding system of the present invention;

[0025] Figure 3 This is a diagram of the clock signals (initial phase random) of two AD9361 chips before and after the second SYNC_IN pulse of the present invention;

[0026] Figure 4 It is a flowchart of the algorithm execution of the present invention;

[0027] Figure 5 A channel phase difference diagram after the self-calibration of the present invention is completed;

[0028] Figure 6 This is a simulation result diagram of the direction finding accuracy of the 7-element antenna of the present invention when the phase error is 10 degrees. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] A phase synchronization algorithm is provided. In an array direction finding system using the music algorithm, based on the hardware environment of multiple AD9361 chips, the hardware design and software configuration method for synchronizing the clocks of multiple AD9361 chips are provided. Furthermore, a data phase compensation algorithm after clock synchronization and a phase compensation method under different temperatures are provided, so that the final data phase meets the phase usage requirements of the music algorithm.

[0031] Hardware design such as Figure 2 As shown;

[0032] Design as Figure 2 In the hardware circuit shown in the figure, four AD9361s are used in the direction finding system to receive signals from seven receiving channels. One of the AD9361s is used to output the self-calibration source signal from the signal processing to the RF front end. The RF front end controls which channel the 8-to-1 switch and the 2-to-1 switch are connected to according to the SPI bus command of the received signal processing. The direction finding system has two working states: direction finding working state and calibration working state. In the direction finding working state, the signal processing does not output the self-calibration source signal, and the seven 2-to-1 switches are all turned to the antenna array element end, and the RF signals of the seven antenna array elements are received and sent to the signal processing. After phase error compensation, the direction finding is completed. In the calibration working state, the signal processing outputs the self-calibration source signal, and controls the RF front end through the SPI bus to connect the 2-to-1 switch to the output of the 8-to-1 switch - the self-calibration source, and controls the 8-to-1 switch to switch the seven channels one by one, and obtain the phase difference of the seven channels relative to the calibration source respectively.

[0033] Implementation process:

[0034] 1) Clock synchronization of multiple AD9361s

[0035] a. Connect the XTALN clock pin inputs of all AD9361s to the same buffered clock. The electrical length of the line feeding the reference clock to each AD9361 must be equal to avoid clock deviations that may cause the synchronization function to fail.

[0036] b. After power-up, set each BBPLL to the same frequency by sending the same frequency command to each AD9361;

[0037] c. Generate the same internal sampling clock and DATA_CLK output through standard register settings and write them to each AD9361;

[0038] d. Set the MCS BBPLL Enable and MCS BB Enable bits in each AD9361, and then set the MCSrefclk Scale En bit. This will enable the multichip synchronization MCS for the BBPLL and reference the correct internal clock.

[0039] e. Input a rising edge pulse to the SYNC_IN pin of each AD9361. For the case where the internal BBPLL REF_CLK is a buffered version of the external REF_CLK, please note that there must be a delay between the rising edge of the SYNC_IN pulse from the REF_CLK input to XTALN to ensure synchronization. This operation synchronizes the BBPLL of each device to the same reference clock.

[0040] f. After BBPLL is synchronized, clear the MCS BBPLL Enable bit and set the MCS Digital Clock Enable bit while keeping the MCS BB Enable bit set. This enables the MCS to synchronize the digital clock distributor.

[0041] After this register is written, another rising edge pulse is input to the SYNC_IN pin of each device at the same time. This operation synchronizes the data clock of each device to the same reference clock. The timing requirements of this signal are the same as those of the first SYNC_IN pulse. The results of this operation can be observed by monitoring the DATA_CLK output of each device and recording its relative phase before and after receiving the second SYNC_IN pulse.

[0042] g. After synchronization is complete, clear the MCSDigitalCLK Enable and MCS BB Enable bits to prevent the synchronization function from being accidentally triggered;

[0043] 2) Phase synchronization of multiple AD9361s

[0044] After completing the clock synchronization of multiple AD9361 chips, perform phase synchronization of multiple AD9361 chips. First, obtain the phase difference of the seven receiving channels relative to the calibration channel in the calibration working state, and then perform the direction finding by decreasing the phase difference compensation in the direction finding working state.

[0045] a) Calibration working status

[0046] Assume that the sampling data of the kth point of the i-th channel can be expressed as FFT i (k), then

[0047]

[0048] where b i (k) represents the modulus value of the k-th sampling data of the i-th channel after FFT, θ i (k) represents the phase of the k-th sampling data of the i-th channel after FFT, i = 1, 2, 3, 4, 5, 6, 7; k = 1, 2, 3, 4, ...,

[0049] The sampling data of the kth point of the self-calibration source channel can be expressed as G(k) after FFT.

[0050] G(k)=c(k)e jα(k) (2)

[0051] Where c(k) and α(k) are the modulus and phase of the k-th sampling data of the self-calibration source channel after FFT, respectively. The phase difference between the i-th channel and the self-calibration source channel is recorded as Under ideal conditions, the sampling data of the kth point of the self-calibration source channel can also be expressed as

[0052]

[0053] The conjugate G′(k) of the kth data of the ith channel and the kth data of the self-calibration source channel is multiplied to obtain

[0054]

[0055] The data of 2048 points in the i-th channel are respectively multiplied by the conjugate of the data of 2048 points in the self-calibration source channel and summed. The result is expressed as M i ,but

[0056]

[0057] Then the phase difference of each channel relative to the self-calibration source channel can be obtained

[0058]

[0059] b) Direction finding working status

[0060] Assuming that the initial phase of the kth data of the self-calibration source channel in this working state is δ(k), then in this state, the kth sampling data of the ith channel is FFTed and recorded as T i (k), then

[0061]

[0062] where di (k) is the modulus value of the k-th sample data of the i-th channel after FFT.

[0063] Formula (7) is multiplied by the conjugate of the result of formula 6 for phase compensation. The kth sampling data of the ith channel after compensation is:

[0064]

[0065] Then the phase of the kth sampling data of each channel after compensation is The phases between channels are synchronized;

[0066] It can be concluded that the phase of each channel can be synchronized by channel calibration.

[0067] The execution process of data phase synchronization of multiple AD9361 chips is as follows Figure 4 shown.

[0068] Figure 5 After the channel is self-calibrated, the phase difference of each channel relative to the calibration channel after calibration compensation is obtained again. Figure 5 It can be seen that after the channel self-calibration is completed, the phase difference of each channel is close to 0 degrees, and the self-calibration algorithm is effective.

[0069] Figure 6 This is the simulation result of the direction finding accuracy of the 7-element antenna when the phase error is 10 degrees. The angle measurement accuracy of this direction finding method is basically equivalent to the simulation result, and the requirement of direction finding error less than 2 degrees can be achieved.

[0070] Although the embodiments of the present invention have been shown and described, as detailed above, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A phase synchronization algorithm, characterized in that: include At least four AD9361 RF converters for receiving RF signals from multiple antenna array elements; Clock synchronization module, which realizes the clock synchronization of multiple AD9361 chips in the following ways: Connect the XTALN clock pins of all AD9361s to the same clock source and ensure that the electrical lengths of the lines feeding the reference clock are equal; Send the same frequency command to each AD9361 to set the same BBPLL frequency; Generate the same internal sampling clock and DATA_CLK output through standard register settings and write to each AD9361; Enable the multi-chip synchronization MCS function of the BBPLL and input a synchronization pulse to the SYNC_IN pin of each AD9361 to achieve clock synchronization; after the synchronization is completed, clear the MCS-related enable bit to prevent the synchronization function from being accidentally triggered; Phase synchronization module, which is used to obtain the phase difference of each receiving channel relative to the calibration channel in the calibration working state, and perform phase compensation in the direction finding working state. The specific steps include: a. In the calibration working state, the phase difference of each channel relative to the self-calibration source channel is measured one by one through the self-calibration source signal and SPI bus control; b. In the direction finding working state, according to the phase difference obtained in step a, the sampling data of each channel is phase compensated to ensure the phase synchronization between the channels.

2. A phase synchronization algorithm according to claim 1, characterized in that: Four AD9361s are used to receive signals from seven receiving channels in total. One of the AD9361s is used to output the self-calibration source signal from the signal processing to the RF front end. The RF front end controls which channel the 8-to-1 switch and the 2-to-1 switch connect to based on the SPI bus command of the received signal processing.

3. A phase synchronization algorithm according to claim 2, characterized in that: In the direction finding working state, the signal processing does not output the self-calibration source signal, and the 7-way 2-to-1 switch is turned to the antenna element end, receiving the RF signal of the 7-way antenna element and sending it to the signal processing. After phase error compensation, the signal is processed to complete the direction finding.

4. A phase synchronization algorithm according to claim 2, characterized in that: In the calibration working state, the signal processing outputs the self-calibration source signal, and controls the RF front end through the SPI bus to connect the 2-to-1 switch to the output of the 8-to-1 switch - the self-calibration source, and controls the 8-to-1 switch to switch 7 channels in turn, and obtain the phase difference of the 7 channels relative to the calibration source respectively.

5. A phase synchronization algorithm according to claim 1, characterized in that: It also involves setting the MCS BBPLL Enable and MCS BB Enable bits in each AD9361, and then setting the MCS refclk Scale En bit to enable multichip synchronization of the BBPLL and reference the correct internal clock.

6. A phase synchronization algorithm according to claim 1, characterized in that: It also includes inputting a rising edge pulse to the SYNC_IN pin of each AD9361. In the case where the internal BBPLL REF_CLK is a buffered version of the external REF_CLK, there must be a delay in the rising edge of the SYNC_IN pulse from the REF_CLK input to XTALN to ensure synchronization. After the BBPLL is synchronized, clear the MCS BBPLL Enable bit and set the MCS digital clock Enable bit while keeping the MCS BB Enable bit set.

7. A phase synchronization algorithm according to claim 1, characterized in that: In the calibration working state, it is assumed that the sampling data of the kth point of the i-th channel can be expressed as FFT i (k), then where b i (k) represents the modulus value of the k-th sampling data of the i-th channel after FFT, θ i (k) represents the phase of the k-th sampling data of the i-th channel after FFT, i = 1, 2, 3, 4, 5, 6, 7; k = 1, 2, 3, 4, ..., The sampling data of the kth point of the self-calibration source channel can be expressed as G(k) after FFT. G(k)=c(k)e jα(k) (2) Where c(k) and α( k ) are the modulus and phase of the k-th sampling data after FFT of the self-calibration source channel, and the phase difference between the ith channel and the self-calibration source channel is recorded as Under ideal conditions, the sampling data of the kth point of the self-calibration source channel can also be expressed as The conjugate G(k) of the kth data of the i-th channel and the kth data of the self-calibration source channel is multiplied to obtain The data of 2048 points in the i-th channel are respectively multiplied by the conjugate of the data of 2048 points in the self-calibration source channel and summed. The result is expressed as M i ,but Then the phase difference of each channel relative to the self-calibration source channel can be obtained 8. A phase synchronization algorithm according to claim 7, characterized in that: In the direction finding working state, assuming that the initial phase of the kth data of the self-calibration source channel in this working state is δ(k), then in this state, the kth sampling data of the ith channel is FFT-recorded as T i (k), then where d i (k) is the modulus value of the k-th sample data of the i-th channel after FFT. Formula (7) is multiplied by the conjugate of the result of formula 6 for phase compensation. The kth sampling data of the ith channel after compensation is: Then the phase of the kth sampling data of each channel after compensation is The phases between channels are synchronized.

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