Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and is used for displaying images. The display panel comprises a display area and a peripheral area surrounding the display area, the peripheral area comprises a first area, a second area, a third area and a fourth area, the first area and the second area are located on the two sides, in the first direction, of the display area respectively, the third area and the fourth area are located on the two sides, in the second direction, of the display area respectively, and the first direction is perpendicular to the second direction; the second area comprises a binding area. The display panel comprises a light sensing unit and a plurality of binding electrodes. The light sensing unit is arranged in the peripheral area of the display panel, the light sensing unit comprises a shading unit and a light leakage unit, the shading unit comprises a plurality of shading transistors, and the light leakage unit comprises a plurality of light leakage transistors; the light sensing unit is arranged in at least one of the first area, the second area, the third area and the fourth area. The plurality of binding electrodes are arranged in the binding area of the display panel, and the plurality of binding electrodes are configured to be connected with the dimming chip.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology and the improvement of energy consumption standards in the industry, the functional requirements for display screens are also getting higher and higher, such as light sensing detection function. How to apply light sensing detection function to display screens and reduce the power consumption of display screens without affecting the display effect has become one of the research hotspots at this stage. Summary of the invention

[0003] The purpose of the embodiments of the present disclosure is to provide a display panel and a display device for realizing automatic adjustment of the brightness of the display panel according to changes in the brightness of ambient light, thereby reducing the power consumption of the display panel and bringing better visual effects to users.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] On the one hand, a display panel is provided. The display panel includes a display area and a peripheral area surrounding the display area, the peripheral area includes a first area, a second area, a third area and a fourth area, the first area and the second area are respectively located on both sides of the display area along a first direction, the third area and the fourth area are respectively located on both sides of the display area along a second direction, the first direction and the second direction are perpendicular; the second area includes a binding area. The display panel includes a photosensitive unit and a plurality of binding electrodes. The photosensitive unit is arranged in the peripheral area of ​​the display panel, the photosensitive unit includes a light shielding unit and a light leakage unit, the light shielding unit includes a plurality of light shielding transistors, and the light leakage unit includes a plurality of light leakage transistors; the photosensitive unit is arranged in at least one of the first area, the second area, the third area and the fourth area. The plurality of binding electrodes are arranged in the binding area of ​​the display panel, and the plurality of binding electrodes are configured to connect a dimming chip; the plurality of binding electrodes include a first electrode, a second electrode, a third electrode, and a fourth electrode. Among them, the control electrodes of the multiple light-shielding transistors are electrically connected in sequence and electrically connected to the first electrode, the first electrodes of the multiple light-shielding transistors are electrically connected in sequence and electrically connected to the second electrode, and the second electrodes of the multiple light-shielding transistors are electrically connected in sequence and electrically connected to the third electrode; the control electrodes of the multiple leakage transistors are electrically connected in sequence and electrically connected to the first electrode, the first electrodes of the multiple leakage transistors are electrically connected in sequence and electrically connected to the third electrode, and the second electrodes of the multiple leakage transistors are electrically connected in sequence and electrically connected to the fourth electrode.

[0006] In the above-mentioned display panel, the photosensitive unit can detect changes in the brightness of ambient light. By setting a shading unit and a light leakage unit, during the operation of the light leakage unit, the light leakage transistor in the light leakage unit is affected by light and will generate a large photosensitive current, while the light shading transistor in the shading unit is not affected by ambient light. The generated dark current can be used as a reference current. The photosensitive current and the reference current are respectively transmitted to the corresponding binding electrodes, and the current signal is transmitted to the dimming chip through the binding electrodes. The dimming chip can detect the ambient light according to the difference in the current signal, and then complete the adjustment of the brightness of the display panel according to the changes in the ambient light brightness.

[0007] In some embodiments, the light sensing unit further includes a dummy unit, and the dummy unit includes a plurality of dummy transistors;

[0008] The multiple light-shielding transistors are arranged along the same direction, the multiple light-leaking transistors are arranged along the same direction, and at least some of the multiple dummy transistors are arranged along the same direction; the multiple light-shielding transistors and at least one of the multiple light-leaking transistors and the at least some of the dummy transistors are arranged along the same direction; the multiple binding electrodes also include multiple dummy electrodes, and the multiple binding electrodes are arranged at intervals along the second direction.

[0009] In some embodiments, the photosensitive unit is located in the second area; the multiple light-shielding transistors are arranged along the second direction, the multiple light-leaking transistors are arranged along the second direction, and the multiple dummy transistors are arranged along the second direction; the light-shielding unit, the dummy unit and the light-leaking unit are arranged along the second direction, and the dummy unit is located between the light-shielding unit and the light-leaking unit.

[0010] In some embodiments, multiple groups of fan-out routing are arranged between the display area and the binding area, and there is a spacing area between two adjacent groups of the multiple groups of fan-out routing, and the spacing area includes a first spacing area, a second spacing area and a third spacing area, the shading unit is located in the first spacing area, the light leakage unit is located in the second spacing area, and the virtual unit is located in the third spacing area.

[0011] In some embodiments, the first electrode includes a first sub-electrode and a second sub-electrode, and the second electrode includes a third sub-electrode and a fourth sub-electrode; the control electrodes of the plurality of shading transistors are electrically connected in sequence through a first gate line, and the first gate line is electrically connected to the first sub-electrode, the first electrodes of the plurality of shading transistors are electrically connected in sequence through a first drain line, and the first drain line is electrically connected to the third sub-electrode; the control electrodes of the plurality of leakage transistors are electrically connected in sequence through a second gate line, and the second gate line is electrically connected to the second sub-electrode, the first electrodes of the plurality of leakage transistors are electrically connected in sequence through a second drain line, and the second drain line is electrically connected to the fourth sub-electrode.

[0012] In some embodiments, the control electrodes of the multiple virtual transistors are electrically connected in sequence through virtual gate lines, and the virtual gate lines are electrically connected to a virtual electrode, the second electrodes of the multiple virtual transistors are electrically connected in sequence through virtual source lines, and the virtual source lines are electrically connected to a virtual electrode, and the first electrodes of the multiple virtual transistors are electrically connected in sequence through virtual drain lines, and the virtual drain lines are electrically connected to a virtual electrode.

[0013] In some embodiments, the photosensitive unit is located in the first area; the multiple light-shielding transistors are arranged along the second direction, the multiple light-leaking transistors are arranged along the second direction, and the multiple dummy transistors are arranged along the second direction; the light-shielding unit, the dummy unit and the light-leaking unit are arranged along the second direction, and the dummy unit is located between the light-shielding unit and the light-leaking unit.

[0014] In some embodiments, the control electrodes of the multiple light-shielding transistors and the control electrodes of the multiple light-leaking transistors are electrically connected in sequence through gate signal lines, and the gate signal lines are electrically connected to the first electrode, and the first electrodes of the multiple light-shielding transistors and the first electrodes of the multiple light-leaking transistors are electrically connected in sequence through drain signal lines, and the drain signal lines are electrically connected to the second electrode.

[0015] In some embodiments, the control electrodes of the plurality of dummy transistors are electrically connected in sequence; and the second electrodes of the plurality of dummy transistors are electrically connected in sequence.

[0016] In some embodiments, the shading unit is located in the third area, and the light leakage unit is located in the fourth area; the multiple virtual transistors of the virtual unit include multiple first virtual transistors and multiple second virtual transistors; the multiple first virtual transistors are located in the third area, and the multiple second virtual transistors are located in the fourth area; the multiple light-shading transistors are arranged along the first direction, the multiple light-leaking transistors are arranged along the first direction, the multiple first virtual transistors are arranged along the first direction, and the multiple second virtual transistors are arranged along the first direction; the shading unit and the multiple first virtual transistors are arranged along the first direction, and the light leakage unit and the multiple second virtual transistors are arranged along the first direction.

[0017] In some embodiments, the first electrode includes a first sub-electrode and a second sub-electrode, and the second electrode includes a third sub-electrode and a fourth sub-electrode; the control electrodes of the plurality of shading transistors are electrically connected in sequence through a first gate line, and the first gate line is electrically connected to the first sub-electrode, the first electrodes of the plurality of shading transistors are electrically connected in sequence through a first drain line, and the first drain line is electrically connected to the third sub-electrode; the control electrodes of the plurality of leakage transistors are electrically connected in sequence through a second gate line, and the second gate line is electrically connected to the second sub-electrode, the first electrodes of the plurality of leakage transistors are electrically connected in sequence through a second drain line, and the second drain line is electrically connected to the fourth sub-electrode.

[0018] In some embodiments, the control electrodes of the multiple first virtual transistors are electrically connected in sequence, the second electrodes of the multiple first virtual transistors are electrically connected in sequence, and the first electrodes of the multiple first virtual transistors are electrically connected in sequence; the control electrodes of the multiple second virtual transistors are electrically connected in sequence, the second electrodes of the multiple second virtual transistors are electrically connected in sequence, and the first electrodes of the multiple second virtual transistors are electrically connected in sequence.

[0019] In some embodiments, the plurality of first dummy transistors are located away from the plurality of binding electrodes relative to the plurality of light-shielding transistors; and the plurality of second dummy transistors are located away from the plurality of binding electrodes relative to the plurality of light-leaking transistors.

[0020] In some embodiments, the second electrodes of the plurality of light-shielding transistors are electrically connected to a first source line, the first source line has at least one first cutting position, and the first cutting position is located between the second electrodes of any two adjacent light-shielding transistors; and / or, the second electrodes of the plurality of light-leaking transistors are electrically connected to a second source line, the second source line has at least one second cutting position, and the second cutting position is located between the second electrodes of any two adjacent light-leaking transistors.

[0021] In some embodiments, the photosensitive unit is located in the first area, and the control electrodes of the multiple virtual transistors are electrically connected to the control electrodes of the multiple light-shielding transistors and the control electrodes of the multiple light-leaking transistors; the first electrodes of the multiple virtual transistors are electrically connected in sequence, and are electrically connected to the first electrodes of the multiple light-shielding transistors and the first electrodes of the multiple light-leaking transistors; the second electrodes of the multiple virtual transistors are electrically connected to the virtual source line; there is a first welding position between the first source line and the virtual source line, and the first source line and the virtual source line can be electrically connected at the first welding position under the action of external force; and / or there is a second welding position between the second source line and the virtual source line, and the second source line and the virtual source line can be electrically connected at the second welding position under the action of external force.

[0022] In some embodiments, the virtual source line includes at least two disconnected virtual source sub-lines, each virtual source sub-line is electrically connected to the source of at least one virtual transistor, and there is a third welding position between two adjacent virtual source sub-lines. The two adjacent virtual source sub-lines can be electrically connected at the third welding position under the action of external force.

[0023] In some embodiments, the shading unit is located in the third area, the light leakage unit is located in the fourth area, the control electrodes of the multiple first virtual transistors are electrically connected to the control electrodes of the multiple light shading transistors, and the first electrodes of the multiple first virtual transistors are electrically connected to the first electrodes of the multiple light shading transistors; the second electrodes of the multiple first virtual transistors are all electrically connected to the light shading virtual source line; there is a fourth welding position between the first source line and the light shading virtual source line, and the first source line and the light shading virtual source line can be electrically connected at the fourth welding position under the action of external force; and / or, the control electrodes of the multiple second virtual transistors are electrically connected to the control electrodes of the multiple light leakage transistors, and the first electrodes of the multiple second virtual transistors are electrically connected to the first electrodes of the multiple light leakage transistors; the second electrodes of the multiple second virtual transistors are all electrically connected to the light leakage virtual source line; there is a fifth welding position between the second source line and the light leakage virtual source line, and the second source line and the light leakage virtual source line can be electrically connected at the fifth welding position under the action of external force.

[0024] In some embodiments, the light-shielding virtual source line includes at least two disconnected light-shielding virtual source sub-lines, each light-shielding virtual source sub-line is electrically connected to at least one first virtual transistor; there is a sixth welding position between two adjacent light-shielding virtual source sub-lines, and the two adjacent light-shielding virtual source sub-lines can be electrically connected at the sixth welding position under the action of external force; and / or, the light-leaking virtual source line includes at least two disconnected light-leaking virtual source sub-lines, each light-leaking virtual source sub-line is electrically connected to at least one second virtual transistor; there is a seventh welding position between two adjacent light-leaking virtual source sub-lines, and the two adjacent light-leaking virtual source sub-lines can be electrically connected at the seventh welding position under the action of external force.

[0025] In some embodiments, the display panel further includes: a substrate; a gate layer disposed on the substrate, the gate layer including a first connecting line; an insulating layer disposed on a side of the gate layer away from the substrate; an active layer disposed on a side of the insulating layer away from the substrate; a metal layer disposed on a side of the active layer away from the substrate, the metal layer including a first electrode and a second electrode of a plurality of transistors, and a plurality of signal lines, the plurality of signal lines including: a first source line, a second source line, a virtual source line, a light-shielding virtual source line, and a light-leaking virtual source line; a passivation layer disposed on a side of the metal layer away from the substrate; a passivation layer disposed on the passivation layer A connection layer away from one side of the substrate; the connection layer includes a second connection line; two signal lines that need to be electrically connected under the action of external force are a first signal line and a second signal line, the second connection line is electrically connected to the first signal line through a first via hole penetrating the passivation layer, and the second connection line is electrically connected to the first connection line through a second via hole penetrating the passivation layer and the insulating layer; the first connection line and the second signal line at least partially overlap, and the overlapping position of the two is the welding position; the welding positions include a first welding position, a second welding position, a third welding position, a fourth welding position, a fifth welding position, a sixth welding position and a seventh welding position.

[0026] In some embodiments, the display panel includes a base substrate and also includes a light shielding layer arranged on a side of the photosensitive unit away from the base substrate; the light shielding layer is provided with a plurality of openings arranged at intervals, and each of the plurality of openings exposes a light leakage transistor.

[0027] In some embodiments, the light-draining transistor includes an active layer pattern, the active layer pattern includes a channel region; the orthographic projection of the channel region on the base substrate is located at a middle position of the orthographic projection of the opening on the base substrate.

[0028] In some embodiments, the distance between the boundary of the orthographic projection of the channel region and the boundary of the orthographic projection of the opening on the same side in the third direction is a first distance, and the first distance is 5um to 6um; the distance between the boundary of the orthographic projection of the channel region and the boundary of the orthographic projection of the opening on the same side in the fourth direction is a second distance, and the second distance is 5um to 6um; the fourth direction is the direction from the second pole of the light-leaking transistor to the first pole, and the third direction is perpendicular to the fourth direction.

[0029] In some embodiments, the light shielding layer further includes at least one light shielding strip disposed in the opening, and the light shielding strip at least partially overlaps with the second electrode and the first electrode of the light leakage transistor.

[0030] In some embodiments, the light-shielding layer includes at least two light-shielding strips, and the at least two light-shielding strips are arranged in parallel.

[0031] In some embodiments, the shading layer includes at least two shading strips, the widths of the at least two shading strips are all the first width, and the spacing between two adjacent shading strips, the spacing between the shading strip near the first boundary of the opening and the first boundary of the opening, and the spacing between the shading strip near the second boundary of the opening and the second boundary of the opening are the first spacing.

[0032] In some embodiments, the plurality of openings include at least one dummy opening, wherein the dummy opening exposes at least one dummy transistor among the plurality of dummy transistors that is adjacent to the light-leaking transistor.

[0033] In some embodiments, the plurality of transistors included in the photosensitive unit are oxide transistors.

[0034] On the other hand, a display device is provided. The display device comprises: a display panel as described in any of the above embodiments, a backlight module arranged on one side of the display panel, and a dimming chip; the dimming chip is electrically connected to the display panel and the backlight module, and the dimming chip is configured to receive a first current generated by the shading unit and a second current generated by the light leakage unit, and adjust the light output brightness of the backlight module according to the first current and the second current.

[0035] The above-mentioned display device has the same structure and beneficial technical effects as the display panels provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0037] Figure 1 is a structural diagram of a display panel according to some embodiments;

[0038] Figure 2A is another structural diagram of a display panel according to some embodiments;

[0039] Figure 2B is another structural diagram of a display panel according to some embodiments;

[0040] Figure 2C is another structural diagram of a display panel according to some embodiments;

[0041] Figure 3 is a diagram showing a connection structure of a light sensing unit of a display panel according to some embodiments;

[0042] Figure 4A is another connection structure diagram of a light sensing unit of a display panel according to some embodiments;

[0043] Figure 4B is another connection structure diagram of the light sensing unit of the display panel according to some embodiments;

[0044] Figure 5 is another connection structure diagram of a light sensing unit of a display panel according to some embodiments;

[0045] Figure 6 is another connection structure diagram of the light sensing unit of the display panel according to some embodiments;

[0046] Figure 7 is a structural diagram of a light shielding unit of a display panel according to some embodiments;

[0047] Figure 8 is a structural diagram of a light leakage unit of a display panel according to some embodiments;

[0048] Fig. 9 is a structural diagram of a light sensing unit of a display panel according to some embodiments;

[0049] Fig. 10A is a diagram of a welding structure of a photosensitive unit in a display panel according to some embodiments;

[0050] Fig. 10B is another welding structure diagram of a photosensitive unit in a display panel according to some embodiments;

[0051] Fig. 10C is another welding structure diagram of a photosensitive unit in a display panel according to some embodiments;

[0052] Fig. 10D is another welding structure diagram of a photosensitive unit in a display panel according to some embodiments;

[0053] Fig.11A is another welding structure diagram of a photosensitive unit in a display panel according to some embodiments;

[0054] Fig. 11B is another welding structure diagram of a photosensitive unit in a display panel according to some embodiments;

[0055] Fig. 11C is another welding structure diagram of a photosensitive unit in a display panel according to some embodiments;

[0056] Fig. 12A is another welding structure diagram of a photosensitive unit in a display panel according to some embodiments;

[0057] Fig. 12B is another welding structure diagram of a photosensitive unit in a display panel according to some embodiments;

[0058] Fig. 12C is another welding structure diagram of a photosensitive unit in a display panel according to some embodiments;

[0059] Fig.13A is a diagram of a welding structure of a photosensitive unit in a display panel according to some embodiments;

[0060] Fig. 13B Based on Fig.13A The cross-sectional structure diagram obtained by making a cross section along the cross-sectional line FF';

[0061] Fig. 13C Based on Fig.13A Another cross-sectional structure diagram obtained by making a cross section along the cross-sectional line FF';

[0062] Fig.14 is a structural diagram of a light shielding layer in a display panel according to some embodiments;

[0063] Fig.15 Based on Fig.14 A local enlarged structural diagram at A;

[0064] Fig.16is another structural diagram of a light shielding layer in a display panel according to some embodiments;

[0065] Fig.17 is another structural diagram of a light shielding layer in a display panel according to some embodiments;

[0066] Fig.18 is a structural diagram of a display device according to some embodiments. DETAILED DESCRIPTION

[0067] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0068] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0069] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0070] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0071] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0072] "Group A and / or Group B, including the following three combinations: A only, B only, and a combination of A and B.

[0073] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0074] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0075] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0076] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0077] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5 brackets; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5 brackets. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0078] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0079] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0080] At present, with the improvement of energy consumption standards, displays are developing towards low power consumption. In order to reduce the power consumption of displays, methods such as reducing the load inside the screen and increasing the transmittance of the display panel are often used. In some embodiments, the backlight brightness is adjusted to reduce power consumption, that is, a light sensor that can detect changes in ambient light brightness is set on the display panel. Through the detection of ambient light, the brightness of the display screen is adjusted according to the changes in ambient light brightness, thereby reducing the power consumption of the display screen. In the related art, the position of the light sensor is limited to a fixed position of the display panel, which is not conducive to the selective use of space.

[0081] Based on this, some embodiments of the present disclosure provide a display panel and a display device to achieve automatic adjustment of the brightness of the display panel according to changes in the ambient light brightness, thereby reducing the power consumption of the display panel and bringing better visual effects to users.

[0082] In this disclosure, Figure 1is a structural diagram of a display panel according to some embodiments, Figure 1 The figure only shows the area division of the display panel. Figure 2A to Figure 2C The specific layout of the light sensing unit in the display panel is shown in FIG. 1 , but the connection relationship of the light sensing unit in the display panel is not shown. In order to clearly describe the connection method of the light sensing unit, Figure 3 to Figure 6 is a diagram of a connection structure of a light sensing unit of a display panel according to some embodiments, illustrating specific connection methods corresponding to light sensing units being arranged in different areas in some embodiments; Figure 7 to Figure 9 The specific manner of setting the cutting position of the light sensing unit in the light shielding unit and the light leakage unit in some embodiments is shown; Figures 10A to 12C A welding structure diagram for setting welding positions for a light sensing unit in a display panel according to some embodiments; Figures 13A to 13C A plan view and a cross-sectional view of a light sensing unit in a display panel of some embodiments at a welding position are shown; Figure 14 to Figure 17 is a structural diagram of a light shielding layer in a display panel according to some embodiments; Fig.18 is a structural diagram of a display device 1000 according to some embodiments.

[0083] It should be noted that, for example, 1 to 10 in the drawings of the present disclosure indicates that component 1 belongs to component 10, and for example, 1 to 10 indicates that shading unit 1 belongs to light sensing unit 10, and other similar reference numerals in the drawings also follow the above description. For example, 1051 / SB in the drawings of the present disclosure indicates that the first signal line 1051 and the first source line SB can refer to the structure indicated by the reference numeral, and other similar reference numerals in the drawings also follow the above description.

[0084] like Figure 1 As described, some embodiments of the present disclosure provide a display panel 100, which includes a display area AA and a peripheral area BB surrounding the display area, wherein the peripheral area BB includes a first area B1, a second area B2, a third area B3 and a fourth area B4, the first area B1 and the second area B2 are respectively located on both sides of the display area AA along a first direction Y, the third area B3 and the fourth area B4 are respectively located on both sides of the display area AA along a second direction X, the first direction Y and the second direction X are perpendicular, and the second area B2 includes a binding area CC.

[0085] It should be noted that the display panel 100 includes a display surface and a non-display surface. The above descriptions of the display area AA and the peripheral area BB are all descriptions of the display surface of the display panel 100 , wherein the first direction Y and the second direction X are both parallel to the display surface of the display panel 100 .

[0086] like Figure 2A to Figure 2CAs shown, the display panel 100 includes a light sensing unit 10 disposed in the peripheral area BB and a plurality of binding electrodes 20 disposed in the binding area CC. The light sensing unit 10 includes a light shielding unit 1 and a light leakage unit 2, the light shielding unit 1 includes a plurality of light shielding transistors 11, the light leakage unit 2 includes a plurality of light leakage transistors 12, and the light sensing unit 10 is disposed in at least one of the first area B1, the second area B2, the third area B3 or the fourth area B4.

[0087] It can be understood that the photosensitive unit 10 can be arranged in one of the first area B1, the second area B2, the third area B3 or the fourth area B4, for example, the photosensitive unit is located in the first area B2; the photosensitive unit 10 can also be arranged in any two of the first area B1, the second area B2, the third area B3 and the fourth area B4, for example, a part of the photosensitive unit 10 is arranged in the first area B1, and the other part is arranged in the third area B3; similarly, the photosensitive unit 10 can also be arranged in any three of the first area B1, the second area B2, the third area B3 and the fourth area B4, for example, a part of the photosensitive unit 10 is arranged in the first area B1, another part is arranged in the third area B3, and a part is arranged in the fourth area B4; the photosensitive unit 10 can also be arranged in the first area B1, the second area B2, the third area B3 and the fourth area B4, for example, the photosensitive unit is divided into four parts, and the four parts are respectively arranged in the first area B1, the second area B2, the third area B3 and the fourth area B4.

[0088] For example, Figure 2A As shown, the photosensitive unit 10 is disposed in the first area B1, or as Figure 2B As shown, the photosensitive unit 10 is located in the second area B2, or, as shown Figure 2C As shown, the light shielding unit 1 and the light leakage unit 2 are located in the third area B3 and the fourth area B4 respectively. The plurality of binding electrodes 20 are configured to connect to the dimming chip, and the plurality of binding electrodes 20 include a first electrode 21 , a second electrode 22 , a third electrode 23 and a fourth electrode 24 .

[0089] The photosensitive unit 10 described above can detect changes in ambient light brightness. By setting a shading unit 1 and a light leakage unit 2, during the operation of the light leakage unit 2, the light leakage transistor 12 in the light leakage unit 2 is affected by light and will generate a large photosensitive current, while the light shading transistor 11 in the shading unit 1 is not affected by ambient light. The generated dark current can be used as a reference current. The photosensitive current and the reference current are respectively transmitted to the corresponding binding electrodes 20, and the current signal is transmitted to the dimming chip through the binding electrodes 20. The dimming chip can detect the ambient light according to the difference in the current signal, and then complete the adjustment of the brightness of the display panel according to the change in ambient light brightness.

[0090] The light sensing unit 10 can be specifically arranged in a manner according to the actual spatial layout of the display panel 100 . In some embodiments of the present disclosure, there is no limitation on the area where the light sensing unit 10 is specifically located.

[0091] It should be noted that the first electrode 21, the second electrode 22, the third electrode 23 and the fourth electrode 24 among the multiple binding electrodes 20 are all electrically connected to the dimming chip. The photosensitive unit 10 transmits different electrical signals to the binding electrodes 20 connected to the dimming chip, and transmits the electrical signals to the dimming chip through the binding electrodes 20. The dimming chip analyzes the relationship between the electrical signals and the ambient light through simulation calculation, and further realizes the adjustment of the brightness of the display panel 100.

[0092] In some embodiments, reference Figure 3 , Figure 5 and Figure 6 As shown, the control electrodes 1k of the plurality of light-shielding transistors 11 are electrically connected in sequence and electrically connected to the first electrode 21, the first electrodes 1d of the plurality of light-shielding transistors 11 are electrically connected in sequence and electrically connected to the second electrode 22, and the second electrodes 1s of the plurality of light-shielding transistors 11 are electrically connected in sequence and electrically connected to the third electrode 23; the control electrodes 2k of the plurality of leakage transistors 12 are electrically connected in sequence and electrically connected to the first electrode 21, the first electrodes 2d of the plurality of leakage transistors 12 are electrically connected in sequence and electrically connected to the second electrode 22, and the second electrodes 2s of the plurality of leakage transistors 12 are electrically connected in sequence and electrically connected to the fourth electrode 24.

[0093] It should be noted that if Figure 3 As shown, the control electrodes 1k of the multiple shading transistors 11 are all electrically connected to the gate signal line GL, the gate signal line GL is electrically connected to the first electrode 21, and the multiple shading transistors 11 receive the gate signal provided by the first electrode 21; the first electrodes 1d of the multiple shading transistors 11 are all connected to the drain signal line DL, the drain signal line DL is electrically connected to the second electrode 22, and the multiple shading transistors 11 receive the drain signal provided by the second electrode 22; the second electrodes 1s of the multiple shading transistors 11 are all electrically connected to the first source line SB, the first source line SB is electrically connected to the third electrode 23, and the multiple shading transistors 11 transmit the generated dark current to the third electrode 23 through the first source line SB.

[0094] The control electrodes 2k of the multiple leakage transistors 12 are all electrically connected to the gate signal line GL, the gate signal line GL is electrically connected to the first electrode 21, and the multiple leakage transistors 12 receive the gate signal provided by the first electrode 21; the first electrodes 2d of the multiple leakage transistors 12 are all electrically connected to the drain signal line DL, the drain signal line DL is electrically connected to the second electrode 22, and the multiple leakage transistors 12 receive the drain signal provided by the second electrode 22; the second electrodes 2s of the multiple leakage transistors 12 are all electrically connected to the second source line SW, the second source line SW is electrically connected to the fourth electrode 24, and the multiple leakage transistors 12 transmit the generated photosensitive current to the fourth electrode 24.

[0095] In the embodiment of the present disclosure, the position of the light sensing unit 10 in the display panel is flexible. The light sensing unit 10 can be set in any one of the first area B1, the second area B2, the third area B3 and the fourth area B4 in the peripheral area BB of the display panel, and has a corresponding scheme for connecting with the binding electrode 20. The arrangement position can be reasonably selected according to the spatial layout in the display panel 100, thereby improving the space utilization of the display panel 100 and enhancing the practicality.

[0096] In some embodiments, reference Figure 3 The photosensitive unit 10 also includes a virtual unit 3, which includes a plurality of virtual transistors 13, a plurality of virtual transistors 13; a plurality of light-shielding transistors 11 are arranged in the same direction, a plurality of light-leaking transistors 12 are arranged in the same direction, and at least some of the plurality of virtual transistors 13 are arranged in the same direction; at least one of the plurality of light-shielding transistors 11 and the plurality of light-leaking transistors 12 and at least some of the virtual transistors 13 are arranged in the same direction; a plurality of binding electrodes 20 are arranged at intervals along the second direction X.

[0097] It can be understood that at least some of the multiple virtual transistors 13 are arranged along the same direction, that is, some of the multiple virtual transistors 13 are arranged along the same direction, and another part of the virtual transistors 13 are arranged along another direction, or, all of the multiple virtual transistors 13 are arranged along the same direction.

[0098] The arrangement of the plurality of light-shielding transistors 11 and at least one of the plurality of light-leaking transistors 12 and at least some of the dummy transistors 13 along the same direction can be divided into the following multiple examples. Specifically, for example, the plurality of light-shielding transistors 11 and some of the dummy transistors 13 are arranged along the same direction, or the plurality of light-leaking transistors 12 and some of the dummy transistors 13 are arranged along the same direction, or the plurality of light-shielding transistors 11 and some of the dummy transistors 13 are arranged along the same direction, or the plurality of light-leaking transistors 12 and some of the dummy transistors 13 are arranged along the same direction, or the plurality of light-shielding transistors 11 and some of the light-leaking transistors 12 and some of the dummy transistors 13 are arranged along the same direction, or the plurality of light-shielding transistors 11 and some of the light-leaking transistors 12 and some of the dummy transistors 13 are arranged along the same direction.

[0099] The same direction here can be the first direction Y or the second direction X, and the multiple dummy transistors 13 can be arranged between the multiple shading transistors 11 and the multiple leakage transistors 12, or can be arranged on the side of the multiple shading transistors 11 and the multiple leakage transistors 12 away from the binding electrode 20.

[0100] Exemplarily, the spacing between two adjacent light-shielding transistors in the plurality of light-shielding transistors 11 along the arrangement direction thereof is equal, the spacing between two adjacent light-leaking transistors 12 in the plurality of light-leaking transistors 12 along the arrangement direction thereof is equal, and the spacing between two adjacent virtual transistors 13 in the plurality of virtual transistors 13 along the arrangement direction thereof is equal. Further, the spacing between any two adjacent transistors in the plurality of virtual transistors 13, the plurality of light-shielding transistors 11, and the plurality of light-leaking transistors 12 along the arrangement direction thereof is equal, so that the plurality of transistors are evenly arranged and arranged in a regular manner.

[0101] Exemplarily, the film layer structure of each transistor is consistent, and each transistor includes a gate pattern, an active layer pattern, a source pattern and a drain pattern. The patterns of the virtual transistor 13 are arranged on the same layer and have the same shape as the corresponding patterns of the light-shielding transistor 11 and / or the light-leaking transistor 12. For example, the gate pattern of the virtual transistor 13 is located on the same layer as the gate pattern of the light-shielding transistor 11, and has the same shape, thereby further ensuring that the film layer environment of multiple transistors is consistent.

[0102] In the preparation process of the display panel 100, the Rubbing process is often used. Due to the number limitation of the multiple photosensitive transistors (leakage transistors) and the multiple light-shielding transistors in the photosensitive unit 10, the multiple photosensitive transistors (leakage transistors) and the multiple light-shielding transistors 11 cannot fill an area in the peripheral area along their arrangement direction (for example, the photosensitive unit cannot fill the first area), resulting in uneven arrangement of the transistors in the photosensitive unit (leakage unit), so that the film layer environment at different positions is different, there will be a Rubbing risk, and the phenomenon of bad moiré fringes will appear. By setting a virtual unit 3 in the photosensitive unit 10, and making the arrangement of each virtual transistor 13 in the virtual unit 3 consistent with the arrangement of each light-shielding transistor 11 and the leakage transistor 12, each pattern of the virtual transistor 13 is set in the same layer and has the same shape as the corresponding patterns of the light-shielding transistor 11 and / or the leakage transistor 12, that is, the film layer environment of the multiple transistors in the photosensitive unit 10 is consistent, which can reduce the phenomenon of bad moiré fringes generated in the Rubbing process of the preparation process of the display product, thereby ensuring the uniformity of brightness and chromaticity of the display product.

[0103] The following specifically describes the spatial layout of the multiple dummy transistors 13 in the photosensitive unit 10 , the multiple light shielding transistors 11 , and the multiple light leakage transistors 12 in the display panel 100 and the specific connection methods with the binding electrodes 20 .

[0104] In some embodiments, reference Figure 3 , Figure 4A to Figure 4B The photosensitive unit 10 is located in the first area B1, a plurality of light-shielding transistors 11 are arranged along the second direction X, a plurality of light-leaking transistors 12 are arranged along the second direction X, a plurality of dummy transistors 13 are arranged along the second direction X, the photosensitive unit 10 includes a light-shielding unit 1, a light-leaking unit 2 and a dummy unit 3, the light-shielding unit 11, the dummy unit 13 and the light-leaking unit 12 are arranged along the second direction X, wherein the dummy unit 3 is arranged between the light-shielding unit 1 and the light-leaking unit 2. The control electrodes 1k of the plurality of light-shielding transistors 11, the control electrodes 3k of the plurality of dummy transistors 13, and the control electrodes 2k of the plurality of light-draining transistors 12 are electrically connected in sequence through the gate signal line GL, and the gate signal line GL is electrically connected to the first electrode 21. The first electrodes 1d of the plurality of light-shielding transistors 11 and the first electrodes 2d of the plurality of light-draining transistors 12 are electrically connected in sequence through the drain signal line DL, and the drain signal line DL is electrically connected to the second electrode 22. The second electrodes 1s of the plurality of light-shielding transistors 11 are electrically connected to the first source line SB, the first source line SB is electrically connected to the third electrode 23, the second electrodes 2s of the plurality of light-draining transistors 12 are electrically connected to the second source line SW, and the second source line SW is electrically connected to the fourth electrode 24. The second electrodes 3s and the first electrodes of the plurality of dummy transistors 13 are not connected to the second electrodes 1s and the first electrodes of the plurality of light-shielding transistors 11, and the second electrodes 2s and the first electrodes of the plurality of light-draining transistors 12, respectively.

[0105] For example, refer to Figure 4A In the figure, the second electrodes 3s of the multiple virtual transistors 13 are electrically connected through a virtual source line XS, wherein the virtual source line XS is electrically isolated from the first source line SB and the second source line SW, and the first electrodes 3d of the multiple virtual transistors 13 are not connected and are in a floating state.

[0106] For example, refer to Figure 4B In the figure, the first electrodes 3d of the plurality of dummy transistors 13 are electrically connected via a dummy drain line XD, wherein the dummy drain line XD is electrically isolated from the drain signal line DL, and the second electrodes 3s of the plurality of dummy transistors 13 are not connected and are in a floating state.

[0107] For example, refer to Figure 3 In the figure, there is no connection between the first electrodes 3d of the multiple virtual transistors 13, and the first electrodes 3d of the multiple virtual transistors 13 are electrically isolated from the first source line SB and the second source line SW; there is no connection between the second electrodes 3s of the multiple virtual transistors 13, and the second electrodes 3s of the multiple virtual transistors 13 are electrically isolated from the first source line SB and the second source line SW.

[0108] The working process of the above-mentioned light sensing unit 10 is, for example: the dimming chip outputs an electrical signal to a plurality of electrodes, the first electrode 21 transmits a gate control signal, the gate control signal is transmitted to a plurality of light-shielding transistors 11 and a plurality of light-leaking transistors 12 through a gate signal line GL, so that the plurality of light-shielding transistors 11 and a plurality of light-leaking transistors 12 are turned on, the second electrode 22 transmits a drain signal, the drain signal is transmitted to a plurality of light-shielding transistors 11 and a plurality of light-leaking transistors 12 through a drain signal line DL, wherein the plurality of light-leaking transistors 12 generate a large light-sensing current under the influence of light, the light-sensing current is transmitted to the fourth electrode 24 through the second source line SW, the plurality of light-shielding transistors 11 are not affected by light, and generate a dark current, the dark current is transmitted to the third electrode 23 through the first source line SB, and then the light-sensing current and the dark current are transmitted to the light sensing chip. The virtual transistor does not participate in the work.

[0109] In the above layout, a virtual unit 3 is simultaneously arranged in the first area B1, so that each transistor in the photosensitive unit 10 can fill the first area along the second direction X, which can ensure that the film environment of the transistor in the photosensitive unit 10 is consistent, thereby reducing the phenomenon of bad moiré fringes generated in the rubbing process (Rubbing Mura) of the display product during the preparation process, and ensuring uniform brightness and chromaticity of the display product. Exemplarily, in a display panel of a high-transmittance display mode (HADS, High Transmittance Advanced Super Dimension Switch), the direction of the rubbing process is along the short side direction of the display panel (i.e., the first direction Y). Since each transistor in the photosensitive unit 10 is arranged uniformly in the second direction X, the risk of Rubbing can be reduced. At the same time, since there is no electrical connection between the virtual transistor 13 in the virtual unit 3 and the light-shielding transistor 11 and the light-leaking transistor 12, there is no signal access in the virtual transistor 13, which will not affect the normal operation of the light-shielding transistor 11 and the light-leaking transistor 12.

[0110] In some examples, such as Figure 3 to Figure 4B As shown, the dummy unit 3 is arranged between the light shielding unit 1 and the light leakage unit 2, a plurality of light shielding transistors 11 are arranged along the second direction X, a plurality of light leakage transistors 12 are arranged along the second direction X, a plurality of dummy transistors 13 are arranged along the second direction X, the light shielding unit 11, the dummy unit 13 and the light leakage unit 12 are arranged along the second direction X, and correspondingly, the third electrode 23 and the fourth electrode 24 are respectively arranged at two ends of the plurality of binding electrodes 20 along the second direction X. In this arrangement, the plurality of light shielding transistors 11 are arranged close to the third electrode 23, and the plurality of light leakage transistors 12 are arranged close to the fourth electrode 24, which facilitates the arrangement of the first source line SB and the second source line SW. For example, the first source line SB connects the second electrodes 1s of the plurality of light shielding transistors 11, and is connected to the third electrode 23 through the third area B3, and the second source line SW connects the second electrodes 2s of the plurality of light leakage transistors 12, and is connected to the fourth electrode 24 through the fourth area B4, thereby avoiding unnecessary winding and reducing the difficulty of wiring.

[0111] Exemplarily, the second electrode 22 is close to the third area B3, and the first electrode 21 is close to the fourth area B4, so that the drain signal line DL and the gate signal line GL are respectively arranged in the third area B3 and the fourth area B4. For example, the drain signal line DL connects the first electrodes 2d of multiple light-shielding transistors 11 and multiple light-leaking transistors 12, and is connected to the second electrode 22 through the third area B3. The gate signal line GL connects the control electrodes 2k of multiple light-shielding transistors 11 and multiple light-leaking transistors 12, and is connected to the first electrode 21 through the fourth area B4, thereby avoiding unnecessary winding and reducing the difficulty of wiring.

[0112] In other embodiments, reference Figure 5, the photosensitive unit 10 is located in the second area B2, a plurality of light shielding transistors 11 are arranged along the second direction X, a plurality of light leakage transistors 12 are arranged along the second direction X, a plurality of dummy transistors 13 are arranged along the second direction X, the photosensitive unit 10 includes a light shielding unit 1, a light leakage unit 2 and a dummy unit 3, the light shielding unit 11, the dummy unit 13 and the light leakage unit 12 are arranged along the second direction X, wherein the dummy unit 3 is arranged between the light shielding unit 1 and the light leakage unit 2. A plurality of groups of fan-out wirings 40 are arranged between the display area AA and the binding area CC, and there is a spacing area Q between two adjacent groups of fan-out wirings 40 of the plurality of groups of fan-out wirings 40, the spacing area Q includes a first spacing area Q1, a second spacing area Q2 and a third spacing area Q3, the light shielding unit 1 is located in the first spacing area Q1, the light leakage unit 2 is located in the second spacing area Q2, and the dummy unit 3 is located in the third spacing area Q3; the first electrode 21 includes a first sub-electrode 21a and a second sub-electrode 21b, and the second electrode 22 includes a third sub-electrode 22a and a fourth sub-electrode 22b. The gate signal lines GL include a first gate line GL1, a second gate line GL2, and a dummy gate line XG; the drain signal lines DL include a first drain line DL1, a second drain line DL2, and a dummy drain line XD.

[0113] The control electrodes 1k of the plurality of light-shielding transistors 11 are electrically connected in sequence through the first gate line GL1, and the first gate line GL1 is electrically connected to the first sub-electrode 21a. The first electrodes 1d of the plurality of light-shielding transistors 11 are electrically connected in sequence through the first drain line DL1, and the first drain line DL1 is electrically connected to the third sub-electrode 22a. The control electrodes 2k of the plurality of leakage transistors 12 are electrically connected in sequence through the second gate line GL2, and the second gate line GL2 is electrically connected to the second sub-electrode 21b. The first electrodes 2d of the plurality of leakage transistors 12 are electrically connected in sequence through the second drain line DL1. DL2 are electrically connected in sequence, and the second drain line DL2 is electrically connected to the fourth sub-electrode 22b; the control electrodes 3k of the multiple virtual transistors 13 are electrically connected in sequence through the virtual gate line XG, and the virtual gate line XG is electrically connected to a virtual electrode 25, the second electrodes 3s of the multiple virtual transistors 13 are electrically connected in sequence through the virtual source line XS, and the virtual source line XS is electrically connected to a virtual electrode 25, and the first electrodes 3d of the multiple virtual transistors 13 are electrically connected in sequence through the virtual drain line XD, and the virtual drain line XD is electrically connected to a virtual electrode 25.

[0114] As a possible implementation manner, the first electrodes 3d of the plurality of dummy transistors 13 are not connected to each other and are in a floating state, and / or the second electrodes 3s of the plurality of dummy transistors 13 are not connected to each other and are in a floating state.

[0115] The working process of the above-mentioned photosensitive unit 10 is, for example: the dimming chip outputs an electrical signal to multiple electrodes, the first sub-electrode 21a and the second sub-electrode 21b transmit gate control signals, and the gate control signals are respectively transmitted to multiple light-shielding transistors 11 and multiple light-leaking transistors 12 through the first gate line GL1 and the second gate line GL2, so that the multiple light-shielding transistors 11 and the multiple light-leaking transistors 12 are turned on, the third sub-electrode 22a and the fourth sub-electrode 22b transmit drain signals, and the drain signals are respectively transmitted to multiple light-shielding transistors 11 and multiple light-leaking transistors 12 through the first drain line DL1 and the second drain line DL2, wherein the multiple light-leaking transistors 12 generate a large photosensitive current under the influence of light, and the photosensitive current is transmitted to the fourth electrode 24 through the second source line SW, and the multiple light-shielding transistors 11 are not affected by the light and generate dark current, which is transmitted to the third electrode 23 through the first source line SB, and then the photosensitive current and the dark current are transmitted to the photosensitive chip.

[0116] It should be noted that the virtual electrode 25 does not provide an electrical signal during the above-mentioned working process. That is to say, there is no electrical connection between the virtual transistor 13 connected to the virtual electrode 25 through the virtual gate line XG, the virtual drain line XD and the virtual source line XS, and there is no input of electrical signals. Therefore, the virtual transistor 13 does not participate in the work.

[0117] Exemplarily, the display area AA is provided with a plurality of sub-pixels arranged in an array and a plurality of data lines and a plurality of gate lines. The plurality of data lines extend, for example, along a first direction Y. A plurality of groups of fan-out routing lines 40 are used to connect the plurality of data lines and binding electrodes so that the source driver chip provides data signals to the data lines through the binding electrodes and the fan-out routing lines. Each group of fan-out routing lines 40 includes a plurality of fan-out routing lines, and the plurality of fan-out routing lines 40 narrow inwardly in a direction from the display area AA to the binding area CC, forming a fan shape.

[0118] The layout of the above-mentioned photosensitive unit 10 is to set the photosensitive unit 10 in the spacing area Q of the second area B2, and each unit in the photosensitive unit 10 is set in the gap between two adjacent sets of fan-out wiring 40, so that the wiring and device settings of the second area B2 are more compact, which can avoid the waste of space of the display panel 100, and make the space utilization rate of the display panel 100 higher; and because the virtual unit 3 is set, the film layer environment of the transistor in the photosensitive unit 10 can be guaranteed to be consistent, thereby reducing the moiré phenomenon generated in the friction process (Rubbing Mura) of the display product during the preparation process, and ensuring the uniform brightness and color of the display product. At the same time, since there is no electrical connection between the virtual transistor 13 in the virtual unit 3 and the shading transistor 11 and the leakage transistor 12, there is no signal access in the virtual transistor 13, which will not affect the normal operation of the shading transistor 11 and the leakage transistor 12.

[0119] In some examples, such as Figure 5 As shown, a plurality of light shielding transistors 11 are arranged along the second direction X, a plurality of light leakage transistors 12 are arranged along the second direction X, a plurality of dummy transistors 13 are arranged along the second direction X, the light sensing unit 10 includes a light shielding unit 1, a light leakage unit 2 and a dummy unit 3, the light shielding unit 11, the dummy unit 13 and the light leakage unit 12 are arranged along the second direction X, the dummy unit 3 is arranged between the light shielding unit 1 and the light leakage unit 2, a plurality of dummy transistors 13, a plurality of light shielding transistors 11 and a plurality of light leakage transistors 12 are arranged along the second direction X, and the light shielding unit 1, the light leakage unit 2 and the dummy unit 3 are all located in the spacing area Q between two adjacent groups of fan-out wirings 40, correspondingly, the binding electrodes 20 electrically connected to the light shielding unit 1, the light leakage unit 2 and the dummy unit 3 are respectively arranged near the first spacing area Q1, the second spacing area Q2 and the third spacing area Q3 and on both sides along the second direction X, such a configuration facilitates the connection process between the light shielding unit 1, the light leakage unit 2 and the dummy unit 3 in the light sensing unit 10 and the corresponding binding electrodes 20, avoiding unnecessary winding and reducing the wiring difficulty.

[0120] Exemplarily, the third sub-electrode 22a and the third electrode 23 are arranged near the first spacing area Q1, and the fourth sub-electrode 22b and the fourth electrode 24 are arranged near the second spacing area Q2, so that the first drain line DL1, the first gate line GL1 and the first source line SB are all arranged in the first spacing area Q1, and the second drain line DL2, the second gate line GL2 and the second source line SW are all arranged in the second spacing area Q2. For example, the first drain line DL1 is connected to the first electrodes 1d of multiple light-shielding transistors 11, and the second drain line DL2 is connected to the first electrodes 2d of multiple light-leaking transistors 12. The virtual electrode 25 is arranged near the third spacing area Q3, and the virtual gate line XG, the virtual drain line XD and the virtual source line XS are all arranged in the third spacing area Q3. In the process of connecting the above-mentioned signal line with the corresponding binding electrode 20, it is equivalent to shortening the length of the signal line, avoiding unnecessary winding, and reducing the difficulty of wiring.

[0121] In some further embodiments, reference Figure 6, the shading unit 1 is located in the third area B3, and the light leakage unit 2 is located in the fourth area B4, wherein the multiple virtual transistors 13 of the virtual unit 3 include multiple first virtual transistors 131 and multiple second virtual transistors 132; the multiple first virtual transistors 131 are located in the third area B3, and the multiple second virtual transistors 132 are located in the fourth area B4, the multiple shading transistors 11 are arranged along the first direction Y, the multiple light leakage transistors 12 are arranged along the first direction Y, the multiple first virtual transistors 131 are arranged along the first direction Y, and the multiple second virtual transistors 132 are arranged along the first direction Y; the shading unit 1 and the multiple first virtual transistors 131 are arranged along the first direction Y, and the light leakage unit 2 and the multiple second virtual transistors 132 are arranged along the first direction Y; the multiple first virtual transistors 131 are arranged relative to the multiple shading The transistor 11 is far away from the multiple binding electrodes 20, and the multiple second virtual transistors 132 are far away from the multiple binding electrodes 20 relative to the multiple leakage transistors 12; the first electrode 21 includes a first sub-electrode 21a and a second sub-electrode 21b, and the second electrode 22 includes a third sub-electrode 22a and a fourth sub-electrode 22b; the gate signal line GL includes a first gate line GL1, a second gate line GL2 and a virtual gate line XG; the drain signal line DL includes a first drain line DL1, a second drain line DL1 and a virtual drain line XD; the virtual gate line XG includes a first virtual gate line XG1 and a second virtual gate line XG2, the virtual drain line XD includes a first virtual drain line XD1 and a second virtual drain line XD2, and the virtual source line XD includes a first virtual source line XS1 and a second virtual source line XS2.

[0122] Among them, the control electrodes 1k of multiple shading transistors 11 are electrically connected in sequence through the first gate line GL1, and the first gate line GL1 is electrically connected to the first sub-electrode 21a, the first electrodes 1d of multiple shading transistors 11 are electrically connected in sequence through the first drain line DL1, and the first drain line DL1 is electrically connected to the third sub-electrode 22a; the control electrodes 2k of multiple leakage transistors 12 are all electrically connected to the second gate line GL2, and the second gate line GL2 is electrically connected to the second sub-electrode 21b, the first electrodes 2d of multiple leakage transistors 12 are all electrically connected to the second drain line DL2, and the second drain line DL2 is electrically connected to the fourth sub-electrode 22b.

[0123] In some examples, the control electrodes 4k of the plurality of first virtual transistors 131 are electrically connected in sequence through the first virtual gate line XG1, the second electrodes 4d of the plurality of first virtual transistors 131 are electrically connected in sequence through the first virtual source line XS1, and the first electrodes 4s of the plurality of first virtual transistors 131 are electrically connected in sequence through the first virtual drain line XD1; the control electrodes 5k of the plurality of second virtual transistors 132 are electrically connected in sequence through the second virtual gate line XG2, the second electrodes 5d of the plurality of second virtual transistors 132 are electrically connected in sequence through the second virtual source line XS2, and the first electrodes 5s of the plurality of second virtual transistors 132 are electrically connected in sequence through the second virtual drain line XD2. Exemplarily, the plurality of first virtual transistors 131 have no electrical relationship with the plurality of light-shielding transistors 11, and the plurality of second virtual transistors 132 have no electrical relationship with the plurality of light-leaking transistors 12. Alternatively, the first virtual drain line XD1 is electrically connected to the first drain line DL1, and the first virtual gate line XG1 is electrically connected to the first gate line GL1, that is, there is an electrical relationship between the first electrodes 4s / control electrodes of the multiple first virtual transistors 131 and the first electrodes 1d / control electrodes 1k of the multiple light-shielding transistors 11, but since the second electrode of the first virtual transistor 131 is not connected to the electrode, the first virtual transistor 131 does not participate in the work; the second virtual transistor 132 refers to the connection method of the multiple first virtual transistors 131, which will not be repeated here.

[0124] As a possible implementation, the first electrodes 4s of the plurality of first virtual transistors 131 are not connected to each other and are in a floating state, and / or the second electrodes of the plurality of first virtual transistors 13 are not connected to each other and are in a floating state. Alternatively, the first electrodes 5s of the plurality of second virtual transistors 132 are not connected to each other and are in a floating state, and / or the second electrodes 5d of the plurality of second virtual transistors 132 are not connected to each other and are in a floating state.

[0125] The working process of the above-mentioned photosensitive unit is, for example: the dimming chip outputs an electrical signal to multiple electrodes, the first sub-electrode 21a and the second sub-electrode 21b transmit gate control signals, and the gate control signals are transmitted to multiple light-shielding transistors 11 and multiple light-leaking transistors 12 through the first gate line GL1 and the second gate line GL2 respectively, so that the multiple light-shielding transistors 11 and the multiple light-leaking transistors 12 are turned on, the third sub-electrode 22a and the fourth sub-electrode 22b transmit drain signals, and the drain signals are transmitted to multiple light-shielding transistors 11 and multiple light-leaking transistors 12 through the first drain line DL1 and the second drain line DL2 respectively, wherein the multiple light-leaking transistors 12 generate a large photosensitive current under the influence of light, and the photosensitive current is transmitted to the fourth electrode 24 through the second source line SW, and the multiple light-shielding transistors 11 are not affected by the light and generate dark current, which is transmitted to the third electrode 23 through the first source line SB, and then the photosensitive current and the dark current are transmitted to the photosensitive chip.

[0126] It should be noted that, refer to Figure 6 As can be seen from the figure, the multiple first virtual transistors 131 have no electrical relationship with the multiple light-shielding transistors 11, or the two have an electrical relationship but the second pole of the first virtual transistor 131 is not connected to the electrode, the multiple second virtual transistors 132 have no electrical relationship with the multiple light-leaking transistors 12, or the two have an electrical relationship but the second pole of the second virtual transistor 132 is not connected to the electrode, and the multiple first virtual transistors 131 and the multiple second virtual transistors 132 have no input and output of electrical signals. Therefore, in the above working process, the multiple first virtual transistors 131 and the multiple second virtual transistors 132 do not participate in the work.

[0127] In the above-mentioned layout, multiple light-shielding transistors 11 are arranged along the first direction Y, multiple light-leaking transistors 12 are arranged along the first direction Y, multiple first dummy transistors 131 are arranged along the first direction Y, and multiple second dummy transistors 132 are arranged along the first direction Y. The multiple dummy transistors 13 are divided into multiple first dummy transistors 131 and multiple second dummy transistors 132. In the third area B3, the multiple first dummy transistors 131 and the light-shielding unit 1 are extended along the first direction Y, and in the fourth area B4, the multiple second dummy transistors 132 and the light-leaking unit 2 are extended along the first direction Y. This can ensure that the film layer environment of the transistors in the photosensitive unit 10 is consistent, thereby reducing the phenomenon of moiré fringes generated in the friction process (Rubbing) of the display product during the preparation process, and ensuring the uniformity of brightness and color of the display product. For example, when the display panel adopts the ADS (Advanced Super Dimension Switch) display mode, the rubbing direction of the rubbing process is along the long side direction of the display panel 100 (i.e., the second direction X). Since the transistors in the photosensitive unit 10 are arranged uniformly in the first direction Y, the risk of Rubbing can be reduced.

[0128] In some examples, such as Figure 6 As shown, the multiple first dummy transistors 131 are far away from the multiple binding electrodes 20 relative to the multiple light-shielding transistors 11, and the multiple second dummy transistors 132 are far away from the multiple binding electrodes 20 relative to the multiple light-leaking transistors 12; correspondingly, the binding electrodes 20 connected to the multiple light-shielding transistors 11 and the binding electrodes connected to the multiple light-leaking transistors 12 are respectively arranged at the two ends of the multiple binding electrodes 20 along the second direction X. This arrangement facilitates the wiring of the signal lines connecting the transistors and the corresponding binding electrodes 20, can shorten their length, avoid unnecessary winding or crossing, and reduce the wiring difficulty.

[0129] Exemplarily, the third sub-electrode 22a and the third electrode 23 are arranged close to the third area B3, and the fourth sub-electrode 22b and the fourth electrode 24 are arranged close to the fourth area B4, so that the first drain line DL1, the first gate line GL1 and the first source line SB connecting the multiple light-shielding transistors 11 are close to the corresponding binding electrodes, and the second drain line DL2, the second gate line GL2 and the second source line SW connecting the multiple light-leaking transistors 12 are close to the corresponding binding electrodes. In the process of connecting the above-mentioned signal lines with the corresponding binding electrodes 20, it is equivalent to shortening the length of the signal lines, avoiding unnecessary winding or crossing, and reducing the difficulty of wiring.

[0130] Usually, when detecting ambient light, photosensitive transistors are often used as photosensitive elements, and the number of photosensitive transistors on the display panel needs to be determined by simulating the current size and combining the actual measurement of the characteristics of the photosensitive transistors, and the current monitoring of the matching circuit is also required. Therefore, after the number of photosensitive transistors on the display panel is determined, there may be an impact of improper matching during the later debugging of the circuit. Based on this, the following embodiments of the present disclosure provide a specific solution for reasonably selecting the number of photosensitive transistors by laser cutting / fusion during the debugging stage of the light-sensitive screen circuit.

[0131] The following describes a method for changing the number of light-shielding transistors / light-draining transistors by laser cutting.

[0132] In some embodiments, reference Figure 7 On the basis that the control electrodes 1k of the multiple light-shielding transistors 11 are electrically connected to the gate signal line GL, the first electrodes 1d of the multiple light-shielding transistors 11 are electrically connected to the drain signal line DL, the second electrodes 1s of the multiple light-shielding transistors 11 are electrically connected to the first source line SB, and there is at least one first cutting position G1 on the first source line SB, and the first cutting position G1 is located between the second electrodes of any two light-shielding transistors 11.

[0133] In other embodiments, reference Figure 8 On the basis that the control electrodes 2k of the plurality of leakage transistors 12 are electrically connected to the gate signal line GL, the first electrodes 2d of the plurality of leakage transistors 12 are electrically connected to the drain signal line DL, the second electrodes 2s of the plurality of leakage transistors 12 are electrically connected to the second source line SW, and the second source line SW has at least one second cutting position G2, and the second cutting position G2 is located between the second electrodes of any two adjacent leakage transistors 12.

[0134] In some other embodiments, reference Fig. 9 On the basis that the control electrodes 1k of the plurality of light-shielding transistors 11 are electrically connected to the gate signal line GL, and the first electrodes 1d of the plurality of light-shielding transistors 11 are electrically connected to the drain signal line DL, on the basis that the control electrodes 2k of the plurality of leakage transistors 12 are electrically connected to the gate signal line GL, and the first electrodes 2d of the plurality of leakage transistors 12 are electrically connected to the drain signal line DL, the second electrodes 1s of the plurality of light-shielding transistors 11 are electrically connected to the first source line SB, and the first source line SB has at least one first cutting position G1, and the first cutting position G1 is located between the second electrodes of any two light-shielding transistors 11; the second electrodes 2s of the plurality of leakage transistors 12 are electrically connected to the second source line SW, and the second source line SW has at least one second cutting position G2, and the second cutting position G2 is located between the second electrodes of any two adjacent leakage transistors 12.

[0135] The above-mentioned first cutting position G1 and second cutting position G2 are mainly used for selecting the number of working light shielding transistors 11 and light leakage transistors 12 in the photosensitive unit 10. If it is found that the number of designed light shielding transistors 11 is too much or the number of designed light leakage transistors 12 is too much during the circuit debugging process, the number of actually working light shielding transistors 11 and light leakage transistors 12 can be changed by laser cutting the first cutting position G1 on the first source line SB connecting multiple light shielding transistors 11, or laser cutting the second cutting position G2 connecting multiple light leakage transistors 12. For example, referring to Fig. 9 As shown, the laser cuts at the first cutting position G1, that is, the first cutting position G1 is used as the critical position, and the shading transistors 11 close to the virtual transistor 13 among the multiple shading transistors 11 will not participate in the work, and the shading transistors 11 far away from the virtual transistor 13 are retained and continue to work, which is equivalent to reducing the number of shading transistors 11; and the laser cuts at the second cutting position G2, that is, the second cutting position G2 is used as the critical position, and the shading transistors 11 close to the virtual transistor 13 among the multiple leakage transistors 12 will not participate in the work, and the leakage transistors 12 far away from the virtual transistor 13 are retained and continue to work, which is equivalent to reducing the number of leakage transistors 12; by selecting laser cutting at an appropriate position, it is ensured that in the process of the dimming chip adjusting the light brightness, the number of shading transistors 11 and leakage transistors 12 in the photosensitive unit 10 is set within a reasonable range.

[0136] It should be noted that setting a first cutting position G1 on the first source line SB and setting at least one second cutting position G2 on the second source line SW is suitable for Figure 3 to Figure 6 The scheme corresponding to any of the accompanying drawings.

[0137] The following describes a method for changing the number of light-shielding transistors / light-draining transistors by laser welding.

[0138] In some embodiments, Figures 10A to 10C As shown, the photosensitive unit 10 is located in the first area B1, and the control electrodes 3k of the multiple virtual transistors 13 are electrically connected to the control electrodes 1k of the multiple light-shielding transistors 11 and the control electrodes 2k of the multiple light-leaking transistors 12, for example, they are all electrically connected to the gate signal line GL; the first electrodes 3d of the multiple virtual transistors 13 are electrically connected in sequence, and are electrically connected to the first electrodes 1d of the multiple light-shielding transistors 11 and the first electrodes 2d of the multiple light-leaking transistors 12, for example, they are all electrically connected to the drain signal line DL; the second electrodes 3s of the multiple virtual transistors 13 are all electrically connected to the virtual source line XS.

[0139] In some examples, reference Fig. 10AThere is a first welding position R1 between the first source line SD and the virtual source line XS. The first source line SD and the virtual source line XS can be electrically connected at the first welding position R1 under the action of an external force.

[0140] In other examples, refer to Fig. 10B A second welding position R2 is provided between the second source line SW and the virtual source line XS. The second source line SW and the virtual source line XS can be electrically connected at the second welding position R2 under the action of an external force.

[0141] In some other examples, reference Fig. 10C As shown, there is a first welding position R1 between the first source line SD and the virtual source line XS, and there is a second welding position R2 between the second source line SW and the virtual source line XS. In the actual debugging process, one of the first welding position R1 and the second welding position R2 is selected for welding as needed.

[0142] It should be noted that, in the above-mentioned photosensitive unit 10, there is no electrical connection between the first source line SD and the virtual source line XS, there is no electrical connection between the second source line SW and the virtual source line XS, and the virtual transistor does not participate in the work. During the circuit debugging process, it is necessary to use external force (such as laser) to enable the first source line SD and the virtual source line XS to be welded, or the second source line SW and the virtual source line XS to be welded, so that each virtual transistor 13 in the virtual unit 3 can access the electrical signal.

[0143] The above-mentioned setting of the first welding position R1 and the second welding position R2 can adjust the number of light-shielding transistors and / or light-draining transistors that are actually working. If it is found during the circuit debugging process that the number of designed light-shielding transistors is too small, or the number of designed light-draining transistors 12 is too small, the first source line SD and the virtual source line XS are welded at the first welding position R1 by laser action between the first source line SD and the virtual source line XS to achieve electrical connection. At this time, in the virtual unit 3, multiple virtual transistors 13 and multiple light-shielding transistors 11 can receive the same signal, and the virtual transistors 13 can play the role of light-shielding transistors 11, which is equivalent to converting all virtual transistors 13 into light-shielding transistors 11, thereby increasing the number of light-shielding transistors 11. Similarly, by laser action on the second source line SW and the virtual The second welding position R2 of the source line XS enables the second source line SW and the virtual source line XS to be welded at the second welding position R2 to achieve electrical connection. At this time, in the virtual unit 3, multiple virtual transistors 13 and multiple leakage transistors 12 can receive the same signal, and the virtual transistor 13 can also play the role of the leakage transistor 12, which is equivalent to converting all the virtual transistors 13 into leakage transistors 12, thereby increasing the number of leakage transistors 12. Therefore, the above-mentioned setting of the first welding position R1 and the second welding position R2 can ensure that when the dimming chip is adjusting the light brightness, the number of the shading transistors 11 and the leakage transistors 12 in the photosensitive unit 10 is controlled to be within a reasonable range.

[0144] In some embodiments, reference Fig. 10D The virtual source line XS includes at least two disconnected virtual source sub-lines XSa, and a third welding position R3 is provided between two adjacent virtual source sub-lines XSa. The two adjacent virtual source sub-lines XSa can be electrically connected at the third welding position R3 under the action of external force.

[0145] For example, refer to Fig. 10D In the figure, the virtual source line XS includes three disconnected virtual source sub-lines XSa, and there is a third welding position R3 between two adjacent virtual source sub-lines XSa. Fig. 10CThe device also includes a first welding position R1 and a second welding position R2. A plurality of virtual transistors 13 are divided into three groups according to the plurality of welding positions. Each group includes two virtual transistors. The two virtual transistors between the first welding position R1 and the third welding position R3 close to the side of the shading unit 1 are hereinafter referred to as the first group of virtual transistors, the two virtual transistors between two adjacent third welding positions R3 are the second group of virtual transistors, the two virtual transistors between the third welding position R3 close to the side of the light leakage unit 2 and the second welding position R2 are the third group of virtual transistors, the first welding position R1 is position a, the third welding position R3 close to the side of the shading unit 1 is position b, the third welding position R3 close to the side of the light leakage unit 2 is position c, and the second welding position R2 is position d.

[0146] like Fig. 10D As shown, when the first welding position R1 (position a) between the first source line SD and the virtual source line XS is welded by the laser welding process, the first group of virtual transistors and the multiple shading transistors 11 can receive the same signal, and the first group of virtual transistors can also play the role of the shading transistor 11, that is, the number of shading transistors 11 is increased; on this basis, if the dimming chip is in the process of adjusting the light brightness, the number of shading transistors 11 is still insufficient, the virtual source sub-lines XSa at both ends of the third welding position R3 (position b) close to the shading unit 1 can be electrically connected through the laser welding process. At this time, the second group of virtual transistors also receives the source signal of the first source line SB to increase the number of shading transistors 11. Similarly, the third welding position R3 (position c) close to the light leakage unit 2 is electrically connected. At this time, the third group of virtual transistors can also receive the source signal of the first source line SB, further increasing the number of shading transistors, so as to reasonably adjust the number of shading transistors.

[0147] Continue to refer to Fig. 10D, when the second welding position R2 between the second source line SW and the virtual source line XS is welded by the laser welding process (position d), the third group of virtual transistors and multiple leakage transistors 12 can receive the same signal, and the third group of virtual transistors can also play the role of leakage transistors 12, that is, the number of leakage transistors 12 is increased; on this basis, if the number of leakage transistors 12 is still insufficient in the process of adjusting the light brightness of the dimming chip, the virtual source sub-lines XSa at both ends of the third welding position R3 (position c) close to the side of the leakage unit 2 can be electrically connected through the laser welding process. At this time, the second group of virtual transistors also receives the source signal of the second source line SW to increase the number of shading transistors. Similarly, the third welding position R3 (position b) close to the side of the shading unit 1 is electrically connected. At this time, the first group of virtual transistors can also receive the source signal of the second source line SW, further increasing the number of shading transistors 11, so as to reasonably adjust the number of shading transistors 11.

[0148] In some other examples, the first welding position R1 (position a) between the first source line SD and the virtual source line XS is welded by a laser welding process, so that the first group of virtual transistors and the plurality of light-shielding transistors 11 can receive the same signal, and the first group of virtual transistors are converted into light-shielding transistors 11. At the same time, the second welding position R2 (position d) between the second source line SW and the virtual source line XS is welded by a laser welding process, so that the third group of virtual transistors and the plurality of light-leaking transistors 12 can receive the same signal, and the third group of virtual transistors are converted into light-shielding transistors 11. No welding is done at the two third welding positions R3, that is, there is no electrical connection between the virtual source sub-line XSa electrically connected to the second group of virtual transistors and other signal lines, and the second group of virtual transistors are not connected to electrical signals and still do not participate in the work.

[0149] The above only gives several examples of the first welding position R1, the second welding position R2 and the third welding position R3 during use. The number of the third welding position R3 can be more, and multiple choices can be made as needed during the actual debugging process. The above-mentioned setting of the third welding position R3 can be more reasonable according to the need to adjust the light brightness, and accurately adjust the number of shading transistors 11 and light leakage transistors 12.

[0150] In some embodiments, reference Fig.11AThe shading unit 1 is located in the third area B3, the light leakage unit 2 is located in the fourth area B4, the control electrodes 4k of the multiple first virtual transistors 131 are electrically connected to the control electrodes 1k of the multiple shading transistors 11, for example, they are all electrically connected to the first gate line GL1; the first electrodes 4s of the multiple first virtual transistors 131 are electrically connected to the first electrodes 1d of the multiple shading transistors 11, for example, they are all electrically connected to the first drain line DL1; the second electrodes 4d of the multiple first virtual transistors 131 are all electrically connected to the shading virtual source line ZXS; there is a fourth welding position R4 between the first source line SB and the shading virtual source line ZXS, and the first source line SB and the shading virtual source line ZXS can be electrically connected at the fourth welding position R4 under the action of external force.

[0151] In other embodiments, reference Fig. 11B The shading unit 1 is located in the third area B3, the light leakage unit 2 is located in the fourth area B4, the control electrodes 5k of the multiple second virtual transistors 132 are electrically connected to the control electrodes 2k of the multiple leakage transistors 12, for example, they are all electrically connected to the second gate line GL2; the first electrodes 5s of the multiple second virtual transistors 132 are electrically connected to the first electrodes 2d of the multiple leakage transistors 12, for example, they are all electrically connected to the second drain line DL2; the second electrodes 5d of the multiple second virtual transistors 132 are all electrically connected to the light leakage virtual source line LXS; there is a fifth welding position R5 between the second source line SW and the light leakage virtual source line LXS, and the second source line SW and the light leakage virtual source line LXS can be electrically connected at the fifth welding position R5 under the action of external force.

[0152] In some other embodiments, reference Fig. 11C , the shading unit 1 is located in the third area B3, the light leakage unit 2 is located in the fourth area B4, the control electrodes 4k of the plurality of first virtual transistors 131 are electrically connected to the control electrodes 1k of the plurality of light-shielding transistors 11, the first electrodes 4s of the plurality of first virtual transistors 131 are electrically connected to the first electrodes 1d of the plurality of light-shielding transistors 11; the second electrodes 4d of the plurality of first virtual transistors 131 are all electrically connected to the light-shielding virtual source line ZXS; there is a fourth welding position R4 between the first source line SB and the light-shielding virtual source line ZXS, and the first source line SB and the light-shielding virtual source line ZXS can be under the action of external force, Electrically connected at the fourth welding position R4; the control electrodes 5k of the plurality of second virtual transistors 132 are electrically connected to the control electrodes 2k of the plurality of leakage transistors 12, and the first electrodes 5s of the plurality of second virtual transistors 132 are electrically connected to the first electrodes 2d of the plurality of leakage transistors 12; the second electrodes 5d of the plurality of second virtual transistors 132 are all electrically connected to the leakage virtual source line LXS; there is a fifth welding position R5 between the second source line SW and the leakage virtual source line LXS, and the second source line SW and the leakage virtual source line LXS can be electrically connected at the fifth welding position R5 under the action of external force.

[0153] It should be noted that the fourth welding position R4 and the fifth welding position R5 are set to adjust the number of light-shielding transistors and / or light-draining transistors that are actually in operation. If, during the circuit debugging process, it is found that the number of designed light-shielding transistors is too small, or the number of designed light-draining transistors is too small, the laser is applied to the fourth welding position R4 between the first source line SD and the light-shielding virtual source line ZXS, so that the first source line SD and the light-shielding virtual source line ZXS are welded at the fourth welding position R4 to achieve electrical connection. At this time, in the virtual unit 3, multiple first virtual transistors 131 and multiple light-shielding transistors 11 can receive the same signal, and the first virtual transistors 131 can also play the role of light-shielding transistors 11, which is equivalent to converting all the first virtual transistors 131 into light-shielding transistors 11, that is, increasing the number of light-shielding transistors 11; similarly, the laser is applied to the second source line SW and the light-draining virtual source line ZXS. The fifth welding position R5 of the optical virtual source line LXS enables the second source line SW and the light leakage virtual source line LXS to be welded at the fifth welding position R5 to achieve electrical connection. At this time, in the virtual unit 3, multiple second virtual transistors 132 and multiple light leakage transistors 12 can receive the same signal, and the second virtual transistors 132 can play the role of the light leakage transistor 12, which is equivalent to converting all the second virtual transistors 132 into light leakage transistors 12, that is, increasing the number of light leakage transistors 12; therefore, the above-mentioned setting of the fourth welding position R4 and the fifth welding position R5 can also ensure that when the dimming chip is adjusting the light brightness, the number of light shielding transistors 11 and light leakage transistors 12 in the photosensitive unit 10 is controlled within a reasonable range.

[0154] In some embodiments, reference Fig. 12A The shading virtual source line ZXS includes at least two disconnected shading virtual source sub-lines ZXS1, each shading virtual source sub-line ZXS1 is electrically connected to at least one first virtual transistor 131; there is a sixth welding position R6 between two adjacent shading virtual source sub-lines ZXS1, and the two adjacent shading virtual source sub-lines ZXS1 can be electrically connected at the sixth welding position R6 under the action of external force.

[0155] For example, refer to Fig. 12A, the shading virtual source line ZXS includes two disconnected shading virtual source sub-lines ZXS1, and there is a sixth welding position R6 between two adjacent shading virtual source sub-lines ZXS1. Taking the virtual unit 3 as an example, in which two first virtual transistors 131 are included, each first virtual transistor 131 is electrically connected to a shading virtual source sub-line ZXS1. Referring to the description in the foregoing part, when the laser welding process is used to weld the first source line SB and the shading virtual source sub-line ZXS1 on the side of the shading unit 1 at the fourth welding position R4, at this time, the two first virtual transistors 131 on the side of the shading unit 1 The first virtual transistor 131 receives the signal transmitted by the first source line SB, which is equivalent to the first virtual transistor 131 being converted into a shading transistor, and the other first virtual transistor 131 does not receive the signal; on this basis, if the number of shading transistors is still insufficient, after the sixth welding position R6 between the two shading virtual source sub-lines ZXS1 is laser welded, the two first virtual transistors 131 can both receive the signal transmitted by the first source line SB, and the above-mentioned laser welding process and the setting of the corresponding welding position can achieve a more refined control of the number of shading transistors 11 to keep it within a reasonable range.

[0156] In some embodiments, reference Fig. 12B The light leakage virtual source line LXS includes at least two disconnected light leakage virtual source sub-lines LXS1, each light leakage virtual source sub-line ZXS1 is electrically connected to at least one second virtual transistor 132; there is a seventh welding position R7 between two adjacent light leakage virtual source sub-lines LXS1, and the two adjacent light leakage virtual source sub-lines LXS1 can be electrically connected at the seventh welding position R7 under the action of external force.

[0157] For example, refer to Fig. 12B, the light leakage virtual source line LXS includes two disconnected light leakage virtual source sub-lines LXS1, and there is a seventh welding position R7 between two adjacent light leakage virtual source sub-lines LXS1. Taking the virtual unit 3 including two second virtual transistors 132 as an example, each second virtual transistor 132 is electrically connected to a light leakage virtual source sub-line LXS1. Referring to the description in the foregoing part, when the laser welding process is used to weld the fifth welding position R5 between the first source line SB and the light leakage virtual source sub-line LXS1 close to the side of the light shielding unit 1, at this time, the second virtual transistor 132 of the two second virtual transistors 132 close to the side of the light leakage unit 2 is The two virtual transistors 132 receive the signal transmitted by the second source line SW, which is equivalent to the second virtual transistor 132 being converted into a leakage transistor 12, and the other second virtual transistor 132 does not receive the signal; on this basis, if the number of leakage transistors 12 is still insufficient, after the seventh welding position R7 between the two leakage virtual source sub-lines LXS1 is laser welded, the two second virtual transistors 132 can both receive the signal transmitted by the second source line SW, and the above-mentioned laser welding process and the setting of corresponding welding positions can achieve a more refined control of the number of leakage transistors 12 to keep it within a reasonable range.

[0158] In some embodiments, reference Fig. 12C The light-shielding virtual source line ZXS includes at least two disconnected light-shielding virtual source sub-lines ZXS1, each of which is electrically connected to at least one first virtual transistor 131; a sixth welding position R6 is provided between two adjacent light-shielding virtual source sub-lines ZXS1, and two adjacent light-shielding virtual source sub-lines ZXS1 can be electrically connected at the sixth welding position R6 under the action of external force; the light-leaking virtual source line LXS includes at least two disconnected light-leaking virtual source sub-lines LXS1, each of which is electrically connected to at least one second virtual transistor 132; a seventh welding position R7 is provided between two adjacent light-leaking virtual source sub-lines LXS1, and two adjacent light-leaking virtual source sub-lines LXS1 can be electrically connected at the seventh welding position R7 under the action of external force.

[0159] For example, refer to Fig. 12CThe light-shielding virtual source line ZXS includes two disconnected light-shielding virtual source sub-lines ZXS1, and a sixth welding position R6 is provided between two adjacent light-shielding virtual source sub-lines ZXS1. Taking the virtual unit 3 including two first virtual transistors 131 as an example, each first virtual transistor 131 is electrically connected to a light-shielding virtual source sub-line ZXS1; the light-leaking virtual source line LXS includes two disconnected light-leaking virtual source sub-lines LXS1, and a seventh welding position R7 is provided between two adjacent light-leaking virtual source sub-lines LXS1. Taking the virtual unit 3 including two second virtual transistors 132 as an example, each second virtual transistor 132 is electrically connected to a light-leaking virtual source sub-line LXS1; this setting method has the same beneficial effects as the aforementioned part, and can more finely regulate the number of light-shielding transistors 11 and light-leaking transistors 12 to be kept within a reasonable range, which will not be elaborated here.

[0160] The following introduces the film layer structure included in the display panel, and explains the structure of the welding position and the method of achieving welding.

[0161] In some embodiments, reference Fig.13A , Fig. 13B and Fig. 13C The display panel 100 further includes a base substrate 101, a gate layer 102, an insulating layer 103, an active layer 104, a metal layer 105, a passivation layer 106 and a connection layer 107. The gate layer 102 is arranged on one side of the base substrate 101, and the gate layer 102 includes a first connection line 1021; the insulating layer 103 is arranged on the side of the gate layer 102 away from the base substrate 101; the active layer 104 is arranged on the side of the insulating layer 103 away from the base substrate 101, and includes a plurality of active patterns 1041; the metal layer 105 is arranged on the side of the gate layer 102 away from the base substrate 101, and includes a plurality of active patterns 1041; The source layer 104 is away from the side of the base substrate 101, the metal layer 105 includes the first and second electrodes of multiple transistors T, and multiple signal lines L, the multiple signal lines L include: a first source line SB, a second source line SW, a virtual source line XS, a light-shielding virtual source line ZXS, and a light-leaking virtual source line LXS; the passivation layer 106 is arranged on the side of the metal layer 105 away from the base substrate 101; the connecting layer 107 is arranged on the side of the passivation layer 106 away from the base substrate 101; the connecting layer 107 includes a second connecting line 1071.

[0162] Among them, the two signal lines that need to be electrically connected under the action of external force are the first signal line 1051 and the second signal line 1052, the second connection line 1071 is electrically connected to the first signal line 1051 through the first via O1 penetrating the passivation layer 106, and the second connection line 1071 is electrically connected to the first connection line 1021 through the second via O2 penetrating the passivation layer 106 and the insulating layer 103; the first connection line 1021 and the second signal line 1052 at least partially overlap, and the overlapping position of the two is the welding position R; the welding position R includes the first welding position R1, the second welding position R2, the third welding position R3, the fourth welding position R4, the fifth welding position R5, the sixth welding position R6 and the seventh welding position R7.

[0163] It should be noted that the first signal line 1051 and the second signal line 1052 are both arranged in the metal layer 105, wherein the first signal line 1051 can be the first source line SB, the second source line SW or the virtual source line XS, and the second signal line 1052 can be the light-shielding virtual source line ZXS or the light-leaking virtual source line LXS; the first connecting line 1021 and the second signal line 1052 at least partially overlap, that is, the first connecting line 1021 and the second signal line 1052 at least partially overlap in the orthographic projection of the substrate 101, and the position where the orthographic projections of the two overlap is the welding position R, that is, the laser welding process can be used to electrically connect the second signal line 1052 located in the metal layer 105 with the first connecting line 1021 located in the gate layer 102, and the above Fig.13A and Fig. 13B FIG. 1 shows a structure diagram of the mutual fusion between the light shielding transistor 11 and the dummy transistor 13. For the fusion structure between other transistors, refer to Fig.13A , Fig. 13B and Fig. 13C .

[0164] For example, refer to Fig.13A , Fig. 13B and Fig. 13C , Fig.13A FIG. 1 is a structural diagram of the electrical connection between the first signal line 1051 and the second signal line 1052 at the welding position R, for example, the first welding position R1. Fig. 13B and Fig. 13C for Fig.13A Cross-sectional view at section line FF', Fig. 13B is a structural diagram before the first signal line 1051 and the second signal line 1052 are electrically connected, Fig. 13C1 is a structural diagram after the first signal line 1051 and the second signal line 1052 are electrically connected, wherein the first signal line 1051 is a first source line SB, the second signal line 1052 is a virtual source line XS, the first source line SB and the virtual source line XS are located in the same layer and extend in the same direction, a first connection line 1021 and a second connection line 1071 are arranged between the first source line SB and the virtual source line XS, the first connection line 1021 and the virtual source line XS partially overlap with the orthographic projection of the base substrate 101, the second connection line 1071 and the first source line SB partially overlap with the orthographic projection of the base substrate 101, and the second connection line 1071 located in the connection layer 107 is connected to the first signal line 1021 through a first via hole O1 penetrating the passivation layer 106. 51 is electrically connected, and the second connection line 1071 is electrically connected to the first connection line 1021 located on the gate layer 102 through the second via O2 that penetrates the passivation layer 106 and the insulating layer 103. That is to say, the second connection line 1071 can transfer the signal transmitted by the first source line SB to the first connection line 1021, and further fuse the first connection line 1021 and the virtual source line XS at the overlapping part (fusion position R) of the orthographic projection of the substrate 101, such as area G, through the action of external force, to realize the electrical connection between the first signal line 1051 and the virtual source line XS, and then realize the electrical connection between the first source line SB and the virtual source line XS, so as to ensure that the first source line SB and the virtual source line XS transmit the same electrical signal.

[0165] It should be noted that the region G is only a part of the welding position R. Inside the welding position R, the position where the first signal line 1051 and the second signal line 1052 can be electrically connected can be called the region G, that is, the specific action position under the action of external force.

[0166] In some embodiments, Fig.14 As shown, the display panel 100 includes a base substrate and a light shielding layer 108 arranged on the side of the photosensitive unit 10 away from the base substrate 101; the light shielding layer 108 is provided with a plurality of openings K arranged at intervals, and each of the plurality of openings K exposes a light leakage transistor 12.

[0167] It should be noted that, on the above-mentioned shading layer 108 above the orthographic projection of the corresponding leakage transistor 12, an opening K is set at the corresponding position of each leakage transistor 12, which can prevent other areas around the leakage transistor 12 from reflecting metal light under the irradiation of ambient light, presenting a bright edge phenomenon, and affecting the visual effect of the display panel 100. This setting method is suitable for small-sized display panels, ensuring that each leakage transistor 12 can receive sufficient ambient light, thereby improving the current generated by the leakage unit 2 to be more precise, and thereby making the signal transmitted by the dimming chip more accurate and effective.

[0168] In some embodiments, continue to refer to Fig.14 The light-draining transistor 12 includes an active layer pattern 121 , the active layer pattern 121 includes a channel region 121 a , and the orthographic projection of the channel region 121 a on the base substrate 101 is located at the middle position of the orthographic projection of the opening K on the base substrate 101 .

[0169] In some embodiments, reference Fig.15 In the third direction Z1, the distance between the boundary of the orthographic projection of the channel region 121a and the boundary of the orthographic projection of the opening K on the same side is the first distance H1, and the first distance H1 is 5 to 6 um; in the fourth direction Z2, the distance between the boundary of the orthographic projection of the channel region 121a and the boundary of the orthographic projection of the opening K on the same side is the second distance H2, and the second distance H2 is 5 to 6 um; the fourth direction Z2 is the direction from the second pole 12a of the leakage transistor 12 to the first pole 12b, and the third direction Z1 is perpendicular to the fourth direction Z2.

[0170] For example, refer to Fig.14 and Fig.15 , the orthographic projection of the channel region 121a on the substrate 101 is located in the middle of the orthographic projection of the opening K on the substrate 101, that is, the center of the orthographic projection of the channel region 121a on the substrate 101 coincides with the center of the orthographic projection of the opening K on the substrate 101. Fig.15 The orthographic projection boundaries of the channel region 121a in the third direction Z1 are the first channel boundary a1 and the second channel boundary a2, the orthographic projection boundaries of the channel region 121a in the fourth direction Z2 are the third channel boundary a3 and the fourth channel boundary a4, the orthographic projection boundaries of the opening K in the third direction Z1 are the first opening boundary b1 and the second opening boundary b2, the orthographic projection boundaries of the channel region 121a in the fourth direction Z2 are the third opening boundary b3 and the fourth opening boundary b4, the first distance H1 is the distance between the first channel boundary a1 and the first opening boundary b1, or the distance between the second channel boundary a2 and the second opening boundary b2, the second distance H2 is the distance between the third channel boundary a3 and the third opening boundary b3, or the distance between the fourth channel boundary a4 and the fourth opening boundary b4.

[0171] In some embodiments, reference Fig.16 and Fig.17 The light shielding layer 108 further includes at least one light shielding strip 1081 disposed in the opening K, and the light shielding strip 1081 at least partially overlaps with the second electrode 12 a and the first electrode 12 b of the light leakage transistor 12 .

[0172] For example, refer to Fig.16 and Fig.17 , Fig.16 and Fig.17The light shielding layer 108 shown includes two light shielding strips 1081 disposed in the opening K. Among the two light shielding strips 1081, one of the light shielding strips 1081 overlaps with the second electrode 12a of the light leakage transistor 12, and the other light shielding strip 1081 overlaps with both the second electrode 12a and the first electrode 12b of the light leakage transistor. By providing the light shielding strips 1081, at least part of the second electrode 12a and the first electrode 12b of the light leakage transistor 12 can be covered to reduce the degree of nakedness, thereby reducing the risk of reflection on the surface of the second electrode 12a and the first electrode 12b of the light leakage transistor 12 in a light environment, affecting the appearance of the display product.

[0173] In some embodiments, reference Fig.16 and Fig.17 The light shielding layer 108 includes at least two light shielding strips 1081, and the at least two light shielding strips 1081 are arranged in parallel.

[0174] For example, continue to refer to Fig.16 and Fig.17 In the figure, two shading strips 1081 are arranged in an opening K, wherein the two shading strips 1081 are arranged in parallel to each other, which can avoid the reflection phenomenon occurring in the same direction under the influence of the light environment.

[0175] Exemplarily, the two shading strips 1081 located in the same opening K are not parallel to each other, which can reduce the reflection phenomenon at a side viewing angle to a certain extent.

[0176] It should be noted that the directions of the at least two shading strips 1081 arranged in the same opening K are not limited, and the directions of the at least two shading strips 1081 in different openings K are also not limited, which can better avoid the reflection phenomenon.

[0177] In some embodiments, continue to refer to Fig.16 and Fig.17 The shading layer 108 includes at least two shading strips 1081, the width of at least two shading strips 1081 is the first width W1, and the spacing d1 between two adjacent shading strips 1081, the spacing d2 between the shading strip 1081 near the first boundary J1 of the opening K and the first boundary of the opening K, and the spacing d3 between the shading strip 1081 near the second boundary of the opening K and the second boundary J2 of the opening K are all the first spacing S.

[0178] For example, refer to Fig.16The shading layer 108 includes two shading strips 1081 which are arranged parallel to each other, and each shading strip 1081 is parallel to the first boundary J1 and the second boundary J2 of the opening K, wherein the two shading strips 1081 are arranged at equal intervals in the opening K, that is, the spacing d1 between two adjacent shading strips 1081, the spacing d2 between the shading strip 1081 close to the first boundary J1 of the opening K and the first boundary of the opening K, and the spacing d3 between the shading strip 1081 close to the second boundary of the opening K and the second boundary J2 of the opening K are all the first spacing S, that is, d1=d2=d3=S, and the two shading strips 1081 evenly divide the opening K into three parts.

[0179] For example, refer to Fig.17 The shading layer 108 includes two shading strips 1081 arranged parallel to each other, and each shading strip 1081 is not parallel to the first boundary J1 and the second boundary J2 of the opening K, wherein the two shading strips 1081 are arranged at equal intervals in the opening K, that is, the spacing d1 between two adjacent shading strips 1081, the maximum spacing d2 between the shading strip 1081 close to the first boundary J1 of the opening K and the first boundary J1 of the opening K, and the maximum spacing d3 between the shading strip 1081 close to the second boundary of the opening K and the second boundary J2 of the opening K are all the first spacing S, that is, d1=d2=d3=S, and the two shading strips 1081 divide the opening K into three parts.

[0180] In some embodiments, continue to refer to Fig.16 and Fig.17 , the first width W1 is 8um~10um, and the first spacing S is 8um~10um.

[0181] Exemplarily, the first width W1 may be set to 8um, 9um or 10um, and the first spacing S may be set to 8um, 9um or 10um, that is, W1 and S1 are set to be equal.

[0182] In some embodiments, the plurality of openings K include at least one dummy opening, and the dummy opening exposes at least one dummy transistor 13 adjacent to the light-leaking transistor 12 among the plurality of dummy transistors 13 .

[0183] For example, refer to Fig. 10B , Fig. 10C , Fig. 11B , Fig. 11C , Fig. 12B and Fig. 12CAfter the corresponding laser welding positions are welded, when the virtual transistor 13 and the leakage transistor 12 can receive the same signal, the shading layer 108 on the virtual transistor 13 does not completely shield the virtual transistor 13, but a plurality of virtual openings are provided on the shading layer 108, each of which exposes the virtual transistor 13 adjacent to the leakage transistor 12 and receiving the same signal among the plurality of virtual transistors 13, thereby ensuring that each virtual transistor 13 can receive sufficient ambient light, so that the dimming chip can be more accurate in the adjustment process.

[0184] In some embodiments, the plurality of transistors included in the photosensitive unit 10 are oxide transistors.

[0185] Exemplarily, the oxide transistor can be a P-type transistor or an N-type transistor. The oxide transistor is used because the current it generates is greater than the current generated by the amorphous silicon transistor, which is beneficial to the detection of photosensitive signals, and has a strong charge retention ability and good stability.

[0186] The transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other devices with the same characteristics. In the present embodiment, the coupling mode of the drain and source of each transistor can be interchangeable, so there is actually no difference between the drain and source of each transistor in the embodiments of the present disclosure. Here, only in order to distinguish the two poles of the transistor except the control electrode (i.e., the gate), one of the poles is called the drain and the other pole is called the source. The thin film transistor used in the embodiments of the present disclosure can be an N-type transistor or a P-type transistor. In the embodiments of the present disclosure, when an N-type thin film transistor is used, its first pole can be a drain and the second pole can be a source. The thin film transistor is an N-type transistor as an example, that is, when the signal of the control electrode is a high level, the thin film transistor is turned on. It can be imagined that when a P-type transistor is used, the timing change of the drive signal needs to be adjusted accordingly. The specific details are not repeated here, but should also be within the scope of protection of the present invention.

[0187] like Fig.18 As shown, some embodiments of the present disclosure further provide a display device 1000, including the display panel 100 provided by any of the above embodiments, and the display device 1000 includes the above display panel 100, a backlight module 200 and a dimming chip 300. The backlight module 200 is disposed on one side of the display panel 100.

[0188] For example, refer to Fig.18 The display panel 100 is stacked on the light emitting side of the backlight module 200 .

[0189] In some embodiments, reference Fig.18The dimming chip 300 is electrically connected to the display panel 100 and the backlight module 200. The dimming chip 300 is configured to receive the first current generated by the shading unit and the second current generated by the light leakage unit, and adjust the light output brightness of the backlight module 200 according to the first current and the second current.

[0190] For example, refer to Fig.18 The display device 1000 further includes a flexible circuit board 400, which is disposed on one side of the display panel 100 and the backlight module 200, wherein the flexible circuit board 400 is electrically connected to the display panel 100 and the backlight module 200. Specifically, one end of the flexible circuit board 400 is electrically connected to a plurality of binding electrodes located in the binding area, and the other end is electrically connected to the dimming chip 300, and the flexible circuit board 400 is configured to transmit the signal emitted by the dimming chip 300 to the plurality of binding electrodes.

[0191] Exemplarily, the first current is a reference current, and the second current is a light-sensing current, wherein the dimming chip can receive and compare the first current and the second current, convert the first current and the second current into an analog signal difference, and output a dimming signal to the backlight module 200 to control the light output brightness of the backlight module 200, thereby adjusting the backlight brightness as the ambient light changes, reducing power consumption while improving the display effect.

[0192] Exemplarily, the display device 1000 may be a liquid crystal display device (Liquid Crystal Display, LCD), such as an ADS (Advanced Super Dimension Switch) type liquid crystal display device. The display device provided in this embodiment may also be a TN (Twisted Nematic) type, MVA (Multi-domain Vertical Alignment) type, PVA (Patterned Vertical Alignment) type, IPS (In-Plane Switching) type, FFS (Fringe Field Switching) type or ADS type liquid crystal display device.

[0193] Exemplarily, the display panel is a liquid crystal display panel. The liquid crystal display panel may include an array substrate and a color filter substrate of a pair of boxes, a liquid crystal layer is arranged between the column substrate and the color filter substrate, the liquid crystal layer is filled with liquid crystal molecules, the array substrate includes a plurality of pixel electrodes and a driving circuit, the opposing substrate includes a common electrode, etc., the pixel electrode and the common electrode are arranged relative to each other to form a capacitor, and an electric field is formed between the pixel electrode and the common electrode under the control of the driving circuit, and the liquid crystal molecules can be deflected in the electric field. Specifically, each driving circuit corresponds to a pixel point, which is used to control the display of the pixel point (whether the pixel point emits light, and the brightness of the light); the driving circuit can control the intensity of the electric field formed between the pixel electrode and the common electrode, thereby controlling the angle at which the liquid crystal molecules between the pixel electrode and the common electrode rotate, thereby changing the transmittance of the pixel point. The peripheral area of ​​the array substrate and the color filter substrate is sealed by setting a sealing glue, and also includes a light shielding layer on the array substrate located between the array substrate and the sealing glue, wherein the light shielding layer completely covers the peripheral circuit arranged on the array substrate and located outside the display area.

[0194] Exemplarily, the material of the shading layer is preferably an opaque metal material such as molybdenum (Mo), copper (Cu) or aluminum (Al), or an opaque resin material, such as the black matrix (BM) material for making a color filter substrate CF (Color Filter, CF) or other opaque color-resisting resin materials.

[0195] Exemplarily, the display device 1000 may be any device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether textual or . More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, augmented reality (AR) devices, virtual reality (VR) devices, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0196] The embodiment of the present disclosure does not impose any special restrictions on the specific form of the above-mentioned display device 1000. The display device 1000 adopts the display panel 100 provided by the above-mentioned embodiment. Therefore, the display device 1000 provided by the present disclosure has all the beneficial effects of the display panel 100 provided by any of the above embodiments, which will not be repeated here.

[0197] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: include: a display area and a peripheral area surrounding the display area; the peripheral area includes a first area, a second area, a third area and a fourth area, the first area and the second area are respectively located on both sides of the display area along a first direction, the third area and the fourth area are respectively located on both sides of the display area along a second direction, the first direction is perpendicular to the second direction; the second area includes a binding area; The display panel comprises: A light sensing unit disposed in a peripheral area of ​​the display panel, the light sensing unit comprising a light shielding unit and a light leakage unit, the light shielding unit comprising a plurality of light shielding transistors, and the light leakage unit comprising a plurality of light leakage transistors; the light sensing unit is disposed in at least one of the first area, the second area, the third area, and the fourth area; The plurality of binding electrodes are disposed in a binding area of ​​the display panel, and the plurality of binding electrodes are configured to be connected to a dimming chip; the plurality of binding electrodes include a first electrode, a second electrode, a third electrode, and a fourth electrode; Among them, the control electrodes of the multiple light-shielding transistors are electrically connected in sequence and electrically connected to the first electrode, the first electrodes of the multiple light-shielding transistors are electrically connected in sequence and electrically connected to the second electrode, and the second electrodes of the multiple light-shielding transistors are electrically connected in sequence and electrically connected to the third electrode; the control electrodes of the multiple leakage transistors are electrically connected in sequence and electrically connected to the first electrode, the first electrodes of the multiple leakage transistors are electrically connected in sequence and electrically connected to the second electrode, and the second electrodes of the multiple leakage transistors are electrically connected in sequence and electrically connected to the fourth electrode.

2. The display panel according to claim 1, characterized in that: The light sensing unit further includes a dummy unit, the dummy unit includes a plurality of dummy transistors; the plurality of light shielding transistors are arranged in the same direction, the plurality of light leaking transistors are arranged in the same direction, and at least some of the plurality of dummy transistors are arranged in the same direction; At least one of the plurality of light-shielding transistors and the plurality of light-leaking transistors and the at least part of the dummy transistors are arranged in the same direction; The plurality of binding electrodes further include a plurality of virtual electrodes, and the plurality of binding electrodes are arranged at intervals along the second direction.

3. The display panel according to claim 2, characterized in that: The light sensing unit is located in the second area; The plurality of light-shielding transistors are arranged along the second direction, the plurality of light-leaking transistors are arranged along the second direction, and the plurality of dummy transistors are arranged along the second direction; The light shielding unit, the virtual unit and the light leakage unit are arranged along the second direction, and the virtual unit is located between the light shielding unit and the light leakage unit.

4. The display panel according to claim 3, characterized in that: A plurality of groups of fan-out routings are arranged between the display area and the binding area, and a spacing area is provided between two adjacent groups of the plurality of groups of fan-out routings, and the spacing area includes a first spacing area, a second spacing area and a third spacing area, the shading unit is located in the first spacing area, the light leakage unit is located in the second spacing area, and the virtual unit is located in the third spacing area.

5. The display panel according to claim 3 or 4, characterized in that: The first electrode includes a first sub-electrode and a second sub-electrode, and the second electrode includes a third sub-electrode and a fourth sub-electrode; The control electrodes of the multiple shading transistors are electrically connected in sequence through the first gate line, and the first gate line is electrically connected to the first sub-electrode, the first electrodes of the multiple shading transistors are electrically connected in sequence through the first drain line, and the first drain line is electrically connected to the third sub-electrode; the control electrodes of the multiple leakage transistors are electrically connected in sequence through the second gate line, and the second gate line is electrically connected to the second sub-electrode, the first electrodes of the multiple leakage transistors are electrically connected in sequence through the second drain line, and the second drain line is electrically connected to the fourth sub-electrode.

6. The display panel according to claim 5, characterized in that: The control electrodes of the multiple virtual transistors are electrically connected in sequence through virtual gate lines, and the virtual gate lines are electrically connected to a virtual electrode, the second electrodes of the multiple virtual transistors are electrically connected in sequence through virtual source lines, and the virtual source lines are electrically connected to a virtual electrode, and the first electrodes of the multiple virtual transistors are electrically connected in sequence through virtual drain lines, and the virtual drain lines are electrically connected to a virtual electrode.

7. The display panel according to claim 2, characterized in that: The light sensing unit is located in the first area; The plurality of light-shielding transistors are arranged along the second direction, the plurality of light-leaking transistors are arranged along the second direction, and the plurality of dummy transistors are arranged along the second direction; The light shielding unit, the virtual unit and the light leakage unit are arranged along the second direction, and the virtual unit is located between the light shielding unit and the light leakage unit.

8. The display panel according to claim 7, characterized in that: The control electrodes of the multiple light-shielding transistors and the control electrodes of the multiple light-leaking transistors are electrically connected in sequence through gate signal lines, and the gate signal lines are electrically connected to the first electrode, and the first electrodes of the multiple light-shielding transistors and the first electrodes of the multiple light-leaking transistors are electrically connected in sequence through drain signal lines, and the drain signal lines are electrically connected to the second electrode.

9. The display panel according to claim 7 or 8, characterized in that: The control electrodes of the plurality of dummy transistors are electrically connected in sequence; and the second electrodes of the plurality of dummy transistors are electrically connected in sequence.

10. The display panel according to claim 2, characterized in that: The light shielding unit is located in the third area, and the light leakage unit is located in the fourth area; The plurality of dummy transistors of the dummy unit include a plurality of first dummy transistors and a plurality of second dummy transistors; the plurality of first dummy transistors are located in the third area, and the plurality of second dummy transistors are located in the fourth area; The plurality of light-shielding transistors are arranged along a first direction, the plurality of light-leaking transistors are arranged along a first direction, the plurality of first dummy transistors are arranged along a first direction, and the plurality of second dummy transistors are arranged along a first direction; The light shielding unit and the plurality of first dummy transistors are arranged along the first direction, and the light leakage unit and the plurality of second dummy transistors are arranged along the first direction.

11. The display panel according to claim 10, characterized in that: The first electrode includes a first sub-electrode and a second sub-electrode, and the second electrode includes a third sub-electrode and a fourth sub-electrode; The control electrodes of the multiple shading transistors are electrically connected in sequence through the first gate line, and the first gate line is electrically connected to the first sub-electrode, the first electrodes of the multiple shading transistors are electrically connected in sequence through the first drain line, and the first drain line is electrically connected to the third sub-electrode; the control electrodes of the multiple leakage transistors are electrically connected in sequence through the second gate line, and the second gate line is electrically connected to the second sub-electrode, the first electrodes of the multiple leakage transistors are electrically connected in sequence through the second drain line, and the second drain line is electrically connected to the fourth sub-electrode.

12. The display panel according to claim 10 or 11, characterized in that: The control electrodes of the plurality of first dummy transistors are electrically connected in sequence, the second electrodes of the plurality of first dummy transistors are electrically connected in sequence, and the first electrodes of the plurality of first dummy transistors are electrically connected in sequence; The control electrodes of the plurality of second dummy transistors are electrically connected in sequence, the second electrodes of the plurality of second dummy transistors are electrically connected in sequence, and the first electrodes of the plurality of second dummy transistors are electrically connected in sequence.

13. The display panel according to claim 10, characterized in that: The plurality of first dummy transistors are far away from the plurality of binding electrodes relative to the plurality of light-shielding transistors; and the plurality of second dummy transistors are far away from the plurality of binding electrodes relative to the plurality of light-leaking transistors.

14. The display panel according to claim 1 or 2, characterized in that: The second electrodes of the plurality of light-shielding transistors are all electrically connected to the first source line, the first source line has at least one first cutting position, and the first cutting position is located between the second electrodes of any two adjacent light-shielding transistors; and / or the second electrodes of the plurality of light-leaking transistors are all electrically connected to the second source line, the second source line has at least one second cutting position, and the second cutting position is located between the second electrodes of any two adjacent light-leaking transistors.

15. The display panel according to claim 14, characterized in that: The photosensitive unit further includes a virtual unit, the virtual unit includes a plurality of virtual transistors, and the photosensitive unit is located in the first area; The control electrodes of the multiple virtual transistors are electrically connected to the control electrodes of the multiple light-shielding transistors and the control electrodes of the multiple light-leaking transistors; the first electrodes of the multiple virtual transistors are electrically connected in sequence, and are electrically connected to the first electrodes of the multiple light-shielding transistors and the first electrodes of the multiple light-leaking transistors; the second electrodes of the multiple virtual transistors are electrically connected to the virtual source lines; there is a first welding position between the first source line and the virtual source line, and the first source line and the virtual source line can be electrically connected at the first welding position under the action of external force; and / or there is a second welding position between the second source line and the virtual source line, and the second source line and the virtual source line can be electrically connected at the second welding position under the action of external force.

16. The display panel according to claim 15, characterized in that: The virtual source line includes at least two disconnected virtual source sub-lines, each virtual source sub-line is electrically connected to the source of at least one virtual transistor, and there is a third welding position between two adjacent virtual source sub-lines. The two adjacent virtual source sub-lines can be electrically connected at the third welding position under the action of external force.

17. The display panel according to claim 14, characterized in that: The light sensing unit further includes a virtual unit, the virtual unit includes a plurality of virtual transistors, the light shielding unit is located in the third area, and the light leakage unit is located in the fourth area; the plurality of virtual transistors of the virtual unit include a plurality of first virtual transistors and a plurality of second virtual transistors; the plurality of first virtual transistors are located in the third area, and the plurality of second virtual transistors are located in the fourth area; The control electrodes of the plurality of first dummy transistors are electrically connected to the control electrodes of the plurality of light-shielding transistors, and the first electrodes of the plurality of first dummy transistors are electrically connected to the first electrodes of the plurality of light-shielding transistors; The second electrodes of the plurality of first virtual transistors are all electrically connected to the light-shielding virtual source line; a fourth welding position is provided between the first source line and the light-shielding virtual source line, and the first source line and the light-shielding virtual source line can be electrically connected at the fourth welding position under the action of an external force; and / or, The control electrodes of the plurality of second dummy transistors are electrically connected to the control electrodes of the plurality of light-leaking transistors, and the first electrodes of the plurality of second dummy transistors are electrically connected to the first electrodes of the plurality of light-leaking transistors; The second electrodes of the plurality of second virtual transistors are all electrically connected to the light-leaking virtual source line; there is a fifth welding position between the second source line and the light-leaking virtual source line, and the second source line and the light-leaking virtual source line can be electrically connected at the fifth welding position under the action of external force.

18. The display panel according to claim 17, characterized in that: The light-shielding virtual source line includes at least two disconnected light-shielding virtual source sub-lines, each of which is electrically connected to at least one first virtual transistor; a sixth welding position is provided between two adjacent light-shielding virtual source sub-lines, and the two adjacent light-shielding virtual source sub-lines can be electrically connected at the sixth welding position under the action of an external force; and / or, The light-leaking virtual source line includes at least two disconnected light-leaking virtual source sub-lines, each of which is electrically connected to at least one second virtual transistor; there is a seventh welding position between two adjacent light-leaking virtual source sub-lines, and the two adjacent light-leaking virtual source sub-lines can be electrically connected at the seventh welding position under the action of external force.

19. The display panel according to any one of claims 15 to 18, characterized in that: The display panel further includes: substrate substrate; A gate layer is disposed on the base substrate; the gate layer includes a first connecting line; An insulating layer disposed on a side of the gate layer away from the base substrate; An active layer disposed on a side of the insulating layer away from the substrate; A metal layer disposed on a side of the active layer away from the base substrate, the metal layer comprising a plurality of signal lines, the plurality of signal lines comprising: a first source line, a second source line, a virtual source line, a light-shielding virtual source line, and a light-leaking virtual source line; A passivation layer disposed on a side of the metal layer away from the substrate; A connection layer disposed on a side of the passivation layer away from the substrate; the connection layer includes a second connection line; The two signal lines that need to be electrically connected under the action of an external force are a first signal line and a second signal line, the second connecting line is electrically connected to the first signal line through a first via hole penetrating the passivation layer, and the second connecting line is electrically connected to the first connecting line through a second via hole penetrating the passivation layer and the insulating layer; the first connecting line and the second signal line at least partially overlap, and the overlapping position of the two is the welding position; The welding positions include a first welding position, a second welding position, a third welding position, a fourth welding position, a fifth welding position, a sixth welding position and a seventh welding position.

20. The display panel according to claim 1 or 2, characterized in that: The display panel includes a base substrate, and also includes a light shielding layer arranged on a side of the light sensing unit away from the base substrate; The light shielding layer is provided with a plurality of openings arranged at intervals, and each of the plurality of openings exposes a light leakage transistor.

21. The display panel according to claim 20, characterized in that: The light-draining transistor includes an active layer pattern, and the active layer pattern includes a channel region; the orthographic projection of the channel region on the base substrate is located at a middle position of the orthographic projection of the opening on the base substrate.

22. The display panel according to claim 21, characterized in that: The distances between the boundary of the orthographic projection of the channel region and the boundary of the orthographic projection of the opening on the same side in the third direction are both the first distance; the distances between the boundary of the orthographic projection of the channel region and the boundary of the orthographic projection of the opening on the same side in the fourth direction are both the second distance; the fourth direction is the direction in which the second pole of the source of the light-draining transistor points to the first pole, and the third direction is perpendicular to the fourth direction.

23. The display panel according to claim 21, characterized in that: The light shielding layer further includes at least one light shielding strip disposed in the opening, and the light shielding strip at least partially overlaps with the second electrode and the first electrode of the light leakage transistor.

24. The display panel according to claim 23, wherein: The shading layer includes at least two shading strips, and the at least two shading strips are arranged in parallel.

25. The display panel according to claim 24, characterized in that: The shading layer includes at least two shading strips, the widths of the at least two shading strips are all the first width, and the spacing between two adjacent shading strips, the spacing between the shading strip near the first boundary of the opening and the first boundary of the opening, and the spacing between the shading strip near the second boundary of the opening and the second boundary of the opening are the first spacing.

26. The display panel according to claim 20, characterized in that: The plurality of openings include at least one dummy opening, and the dummy opening exposes at least one dummy transistor adjacent to the light-leaking transistor among the plurality of dummy transistors.

27. The display panel according to claim 1, characterized in that: The plurality of transistors included in the photosensitive unit are oxide transistors.

28. A display device, characterized in that: include: The display panel according to any one of claims 1 to 27; A backlight module disposed on one side of the display panel; A dimming chip is electrically connected to the display panel and the backlight module, and is configured to receive a first current generated by the shading unit and a second current generated by the light leakage unit, and adjust the light output brightness of the backlight module according to the first current and the second current.

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