Display substrate, display motherboard, display panel and display device

Abstract

The display substrate provided by the present disclosure comprises a display area, a binding area, a binding pair area, a side edge area, a first corner area and a second corner area; a substrate; a gate drive circuit; a plurality of first signal lines in the side edge area, the first corner area and the second corner area; wherein the plurality of first signal lines comprises a starting signal line and a starting signal lead line, the starting signal lead line is located on one side of the starting signal line close to the gate drive circuit, the starting signal line and the starting signal lead line both extend along a second direction and are electrically connected by a first connecting line in the second corner area; an anti-static structure is arranged on the plurality of first signal lines, the anti-static structure is located on at least one of a first position and a second position, the first position comprises the connection of the starting signal line, the starting signal lead line and the first connecting line, and the second position comprises the part of the plurality of first signal lines located on one side close to the binding pair area in the row where the first stage shift register unit is located.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically to a display substrate, a display motherboard, a display panel, and a display device. Background Technology

[0002] Currently, by using masking and partial exposure processes, a single mask pattern can be reused to expose multiple sizes of display substrate areas on the same display motherboard, thus simultaneously forming display substrates of various sizes on a single motherboard. This method can save on the development costs of mask templates. However, small-sized display substrates obtained in this way may lack anti-static units, resulting in weaker anti-static capabilities. Summary of the Invention

[0003] In view of the above problems, this disclosure provides a display substrate, a display motherboard, a display panel, and a display device.

[0004] According to a first aspect of this disclosure, a display substrate is provided, comprising:

[0005] The system comprises a display area, a binding area, a binding pair area, a side area, a first corner area, and a second corner area. The side area and the display area are arranged along a first direction, and the binding pair area, the display area, and the binding area are arranged sequentially along a second direction. The first direction and the second direction intersect. The first corner area is located between the side area and the binding pair area and at least partially surrounds the first corner of the display area. The second corner area is located between the side area and the binding area and at least partially surrounds the second corner of the display area.

[0006] Substrate;

[0007] A gate driving circuit disposed on the substrate and located in the side region, the gate driving circuit including cascaded multi-stage shift register units;

[0008] Multiple first signal lines disposed on the substrate and located in the side area, the first corner area and the second corner area;

[0009] The plurality of first signal lines are located on the side of the gate driving circuit away from the display area;

[0010] The plurality of first signal lines include a start signal line and a start signal lead. The start signal lead is located on the side of the start signal line closer to the gate drive circuit. Both the start signal line and the start signal lead extend along the second direction and are electrically connected in the second corner area by a first connecting line.

[0011] An anti-static structure is provided on the plurality of first signal lines. The anti-static structure is located on at least one of a first position and a second position. The first position includes the connection point of the start signal line, the start signal lead and the first connecting line. The second position includes the portion of the plurality of first signal lines located on the side of the first-level shift register unit near the binding pair area.

[0012] According to an embodiment of this disclosure, the antistatic structure located at the first position includes:

[0013] A first fusion structure, at the junction of the starting signal line and the first connecting line, fuses the starting signal line and the first connecting line together; and / or

[0014] The second fusion structure, at the connection point of the starting signal lead and the first connecting line, fuses the starting signal lead and the first connecting line together.

[0015] According to an embodiment of the present disclosure, the display substrate includes a first conductive layer, a second conductive layer located on the side of the first conductive layer opposite to the substrate, and a third conductive layer located on the side of the second conductive layer opposite to the second conductive layer.

[0016] The display substrate further includes a first transition structure located in the third conductive layer, the start signal line located in the first conductive layer, and the first connection line located in the second conductive layer;

[0017] The starting signal line includes a first connecting portion and a signal line body. The orthographic projection of the first connecting portion on the substrate overlaps at least partially with the orthographic projection of the first adapter structure on the substrate. In the overlapping area, the first connecting portion is electrically connected to the first adapter structure through at least one first via.

[0018] The orthographic projection of the first connecting line on the substrate at least partially overlaps with the orthographic projection of the first adapter structure on the substrate, and in the overlapping area, the first connecting line is electrically connected to the first adapter structure through at least one second via.

[0019] The orthographic projection of the first fusion structure on the substrate overlaps with the orthographic projection of the first connection portion on the substrate, the orthographic projection of the signal line body on the substrate, and the orthographic projection of the first connection line on the substrate. In the overlapping area, the first fusion structure fuses the first connection portion, the signal line body, and the first connection line together.

[0020] According to an embodiment of this disclosure, the first connecting line includes a second connecting portion and a connecting line body. The orthographic projection of the second connecting portion on the substrate at least partially overlaps with the orthographic projection of the first adapter structure on the substrate. Furthermore, in the overlapping area, the second connecting portion is electrically connected to the first adapter structure through a second via. The first fusion welding structure includes:

[0021] A first fusion joint, wherein the orthographic projection of the first fusion joint on the substrate overlaps with the orthographic projections of the first connecting portion and the second connecting portion on the substrate, and in the overlapping area, the first fusion joint fuses the first connecting portion and the second connecting portion together; and / or

[0022] The second fusion section has its orthographic projection on the substrate overlapping with the orthographic projections of the signal line body and the connection line body on the substrate. In the overlapping area, the second fusion section fuses the signal line body and the connection line body together.

[0023] According to an embodiment of the present disclosure, the orthographic projection of the first fusion portion on the substrate and the orthographic projection of the second fusion portion on the substrate are located on the same side of the orthographic projection of the second connection portion on the substrate, and the orthographic projections of the first fusion portion on the substrate and the second fusion portion on the substrate are spaced apart.

[0024] According to an embodiment of this disclosure, the display substrate further includes a second transition structure located in the third conductive layer, and the start signal lead is located in the first conductive layer;

[0025] The start signal lead includes a third connection portion and a lead body. The orthographic projection of the third connection portion on the substrate overlaps at least partially with the orthographic projection of the second adapter structure on the substrate. In the overlapping area, the third connection portion and the second adapter structure are electrically connected through at least one third via.

[0026] The orthographic projection of the first connecting line on the substrate and the orthographic projection of the second adapter structure on the substrate at least partially overlap, and in the overlapping area, the first connecting line and the second adapter structure are electrically connected through at least one fourth via.

[0027] The orthographic projection of the second fusion structure on the substrate overlaps with the orthographic projection of the second connection portion on the substrate, the orthographic projection of the lead body on the substrate, and the orthographic projection of the first connection line on the substrate. In the overlapping area, the second fusion structure fuses the second connection portion, the lead body, and the first connection line together.

[0028] According to embodiments of this disclosure, the first connecting line further includes a fourth connecting portion and a connecting line body. The orthographic projection of the fourth connecting portion on the substrate at least partially overlaps with the orthographic projection of the second transition structure on the substrate. Furthermore, in the overlapping region, the fourth connecting portion is electrically connected to the second transition structure. The second fusion structure includes:

[0029] The third fusion section 1 has its orthographic projection on the substrate overlapping with the orthographic projections of the third connecting section and the fourth connecting section on the substrate. In the overlapping area, the third fusion section 1 fuses the third connecting section and the fourth connecting section together; and / or

[0030] The fourth fusion section has its orthographic projection on the substrate overlapping with the orthographic projections of the lead body and the connecting wire body on the substrate. In the overlapping area, the fourth fusion section fuses the lead body and the connecting wire body together.

[0031] According to an embodiment of the present disclosure, the orthographic projection of the third fusion portion on the substrate and the orthographic projection of the fourth fusion portion on the substrate are located on different sides of the orthographic projection of the third connection portion on the substrate, and the orthographic projections of the third fusion portion and the fourth fusion portion on the substrate are spaced apart.

[0032] According to embodiments of this disclosure, the materials of the first fusion structure and the second fusion structure include solid fusion materials. The first fusion structure fuses the start signal line and the first connecting line together through at least one first fusion hole. The second fusion structure fuses the start signal lead and the first connecting line together through at least one second fusion hole. The diameter of at least one first fusion hole and at least one second fusion hole is less than or equal to the line width of the first connecting line.

[0033] According to embodiments of this disclosure, the orthographic projections of at least one first weld hole and at least one second weld hole on the substrate at least partially overlap with the orthographic projection of the first connecting line on the substrate.

[0034] According to embodiments of this disclosure, the materials of the first welding structure and the second welding structure include solid welding materials or liquid welding materials. The first welding structure welds the start signal line and the first connecting line together through a third welding hole, and the second welding structure welds the start signal lead and the first connecting line together through a fourth welding hole. The diameter of the third welding hole and the fourth welding hole is larger than the line width of the first connecting line.

[0035] According to an embodiment of this disclosure, the orthographic projections of the third weld hole and the fourth weld hole on the substrate are spaced apart from the orthographic projection of the first connecting line on the substrate.

[0036] According to embodiments of this disclosure, at least one of the first weld structure and the second weld structure is in contact with the surface of the first connecting line on the side opposite to the substrate.

[0037] According to embodiments of this disclosure, the display substrate further includes:

[0038] Multiple third connection lines and at least one fourth connection line are disposed on the substrate and located in the side area;

[0039] Wherein, the plurality of third connection lines extend along the second direction, the at least one fourth connection line extends along the first direction, and the plurality of third connection lines are located on the side of the gate drive circuit away from the start signal lead.

[0040] At least one level of shift register unit includes a first input terminal. The first input terminals of the first N levels of shift register units are electrically connected to the plurality of third connection lines. The first input terminals of different levels of shift register units are electrically connected to different third connection lines.

[0041] The start signal line is electrically connected to the plurality of third connection lines through the at least one fourth connection line, and N is a positive integer.

[0042] According to an embodiment of this disclosure, the antistatic structure located at the second position includes: a partition structure, wherein on a plurality of first signal lines, a portion of the partition structure located on the side near the bonding pair area and a portion of the partition structure located on the side near the bonding area are separated by the partition structure;

[0043] The starting signal lead is fused to at least one of the fourth connecting lines through a third fusion structure, and at least one of the fourth connecting lines is fused to multiple of the third connecting lines through a fourth fusion structure;

[0044] The partition structure, the third fusion structure, and the fourth fusion structure are located within a preset range.

[0045] According to embodiments of this disclosure, the display substrate further includes:

[0046] The sealing adhesive is disposed on the substrate, and the orthographic projection of the partition structure on the substrate is located in the side area, and the orthographic projection of the sealing adhesive on the substrate covers the orthographic projection of the partition structure on the substrate.

[0047] According to an embodiment of this disclosure, the display substrate further includes a plurality of invalid shift register units, wherein, in the second direction, the plurality of invalid shift register units are located on the side of the gate drive circuit closer to the bonding pair region;

[0048] The partition structure, the third fusion structure, and the fourth fusion structure are located between two adjacent invalid shift register units in the second direction.

[0049] According to a second aspect of this disclosure, a display motherboard is provided, the display motherboard including a first substrate region and a second substrate region, the first substrate region being used to fabricate the above-described display substrate;

[0050] The first substrate region and the second substrate region have different dimensions in a third direction, and the second substrate region includes a first sub-region and a second sub-region that at least partially surrounds the first sub-region.

[0051] The first substrate region includes a fourth conductive layer, and the second substrate region includes a fifth conductive layer. The fourth conductive layer and the fifth conductive layer are in the same layer and made of the same material.

[0052] The pattern of the fourth conductive layer is the same as the pattern of the portion of the fifth conductive layer located in the first sub-region.

[0053] According to a third aspect of this disclosure, a display panel is provided, comprising the display substrate described above.

[0054] According to a fourth aspect of this disclosure, a display device is provided, comprising the display panel described above. Attached Figure Description

[0055] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0056] Figure 1 A schematic diagram of a pair of scaled-down plan views of the motherboard is shown.

[0057] Figure 2 A partial plan view of a pair of display substrates in scale is schematically shown;

[0058] Figure 3 A schematic diagram of the overall plan view of a pair of display substrates in proportion is shown;

[0059] Figure 4 A schematic plan view of a display substrate according to an embodiment of the present disclosure is shown;

[0060] Figure 5 A schematic plan view illustrating the location of the antistatic structure according to an embodiment of the present disclosure is shown.

[0061] Figure 6 A plan view of a first location according to an embodiment of the present disclosure is schematically shown;

[0062] Figure 7 One of the plan views of a first fusion structure according to an embodiment of the present disclosure is shown schematically;

[0063] Figure 8 One of the plan views of a second fusion structure according to an embodiment of the present disclosure is shown schematically;

[0064] Figure 9 A schematic plan view of a first weld hole according to an embodiment of the present disclosure is shown;

[0065] Figure 10 A schematic plan view of a second weld hole according to an embodiment of the present disclosure is shown;

[0066] Figure 11 A second plan view of a first fusion structure according to an embodiment of the present disclosure is shown schematically;

[0067] Figure 12 A second plan view of a second fusion structure according to an embodiment of the present disclosure is shown schematically;

[0068] Figure 13 A schematic plan view of a third weld hole according to an embodiment of the present disclosure is shown;

[0069] Figure 14 A schematic plan view of a fourth weld hole according to an embodiment of the present disclosure is shown;

[0070] Figure 15 A schematic plan view of the first fusion structure according to an embodiment of the present disclosure is shown in Figure 3.

[0071] Figure 16 A schematic plan view of the second fusion structure according to an embodiment of the present disclosure is shown in Figure 3.

[0072] Figure 17 An equivalent circuit diagram of a shift register unit according to an embodiment of the present disclosure is shown schematically;

[0073] Figure 18 One of the schematic diagrams of a display motherboard according to an embodiment of the present disclosure is shown schematically;

[0074] Figure 19 A schematic plan view illustrating the positions of the third and fourth welding structures according to embodiments of the present disclosure is shown.

[0075] Figure 20 A schematic plan view illustrating the location of the partition structure according to an embodiment of the present disclosure is shown.

[0076] Figure 21 A schematic plan view of the sealing adhesive and partition structure according to an embodiment of the present disclosure is shown;

[0077] Figure 22 A second plan view of a display motherboard according to an embodiment of the present disclosure is shown schematically. Detailed Implementation

[0078] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0079] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0080] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0081] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0082] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0083] In this document, the terms “substantially,” “approximately,” “approximately,” “roughly,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” as used herein includes stated values ​​and indicates that a particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0084] It should be noted that in this paper, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for a specific pattern, and then using the same mask to pattern that film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or portions located in the "same layer" are made of the same material and formed by the same single patterning process. Typically, multiple elements, components, structures, and / or portions located in the "same layer" have approximately the same thickness.

[0085] Those skilled in the art will understand that, unless otherwise stated herein, the terms “height” or “thickness” refer to the dimensions along the surface of each film layer disposed perpendicular to the display substrate, i.e., the dimensions along the light-emitting direction of the display substrate, or the dimensions along the normal direction of the display device.

[0086] Figure 1 A schematic diagram shows a pair of scaled plan views of the motherboard. Figure 2 A partial plan view of a pair of display substrates in scale is schematically shown. Figure 3 A schematic diagram of the overall plan view of a pair of display substrates in scale is shown.

[0087] In a pair of proportions, a display master is provided for reference. Figure 1 The display motherboard in this comparative example includes multiple substrate regions 100, with different substrate regions 100 used to form display substrates of different sizes. For example, the multiple substrate regions 100 include a first substrate region 110 and a second substrate region 120. In a third direction, the size of the first substrate region 110 is smaller than the size of the second substrate region 120. For example, the third direction can refer to... Figure 1In the horizontal direction, that is, the width of the first substrate region 110 is smaller than the width of the second substrate region 120. Thus, after cutting along the first substrate region 110, a display substrate with a first width (hereinafter also referred to as the first display substrate) can be obtained, and after cutting along the second substrate region 120, a display substrate with a second width (hereinafter also referred to as the second display substrate) can be obtained. That is, by cutting a display motherboard, display substrates of two widths can be formed, thereby saving the development cost of the photomask.

[0088] It should be noted that the cutting steps mentioned above can refer to the coarse cutting step performed on the display motherboard. Optionally, in addition to the coarse cutting step, a fine cutting step can also be performed, for example, to remove some unnecessary components or cut some unnecessary signal lines.

[0089] In this comparative example, a single mask pattern can be reused to pattern the same film layer on the first substrate region 110 and the second substrate region 120. For example, the display motherboard includes a first film layer 130, which may include multiple signal lines. The following description uses the first film layer 130 as an example to illustrate patterning using a single mask pattern. First, conductive material and photoresist for fabricating the first film layer 130 are formed in the first substrate region 110 and the second substrate region 120. Then, the photoresist on the first substrate region 110 and the second substrate region 120 is exposed using the same mask pattern. When exposing the second substrate region 120, the complete pattern of the first mask pattern can be used for exposure. When exposing the first substrate region 110, a portion of the pattern in the first mask pattern can be blocked, so that the first substrate region 110 is exposed using a partial pattern on the first mask. Afterwards, by development, the desired photolithographic patterns can be formed on the photoresist in the first substrate region 110 and the second substrate region 120, respectively. Subsequently, based on the photolithographic patterns on the first substrate region 110 and the second substrate region 120, the conductive material is etched to form the first film layer 130 required in the first substrate region 110 and the second substrate region 120, respectively.

[0090] Under this exposure method, the first film layer 130 formed on the second substrate region 120 is a complete pattern, while the first film layer 130 formed on the first substrate region 110 is a non-complete pattern. Therefore, further processing of the first film layer 130 is required. For example, excess signal lines in the first film layer 130 can be cut or removed, and some signal lines can be overlapped to ensure that each signal line on the final display substrate can transmit electrical signals as needed.

[0091] However, the display substrate obtained through the above method may have some missing components. For example, anti-static units can be formed at the four corners of the second display substrate: the upper left, upper right (two corners on the side of the second display substrate closest to the bonding area), lower left, and lower right (two corners on the side of the second display substrate closest to the bonding area). These anti-static units can promptly release static electricity from the signal lines electrically connected to them to the ground line, thereby preventing excessive static electricity buildup on the signal lines. On the first display substrate, the anti-static units at the upper left and upper right corners (two corners on the side of the first display substrate closest to the bonding area) will be removed, resulting in the lack of anti-static protection at the upper left and upper right corners of the first display substrate. It should be noted that "left," "right," "upper," and "lower" refer to the left, right, upper, and lower positions of the display substrate (screen) as viewed by the human eye during display.

[0092] Furthermore, in the first display substrate formed in the above manner, there is a risk that some signal lines in the upper left and upper right corners may be exposed due to incomplete coverage by the encapsulation layer 150, and these exposed signal lines are highly susceptible to static electricity. For example, refer to... Figure 2 In the upper left corner of the display substrate, there are multiple signal lines 140, of which four signal lines 140 on the left side are exposed and not effectively covered by the encapsulation layer 150.

[0093] Reference Figure 3 The four exposed signal lines 140 include a start signal line 141 for providing a start signal to the gate drive circuit, and the start signal line 141 is electrically connected to the gate drive circuit via a start signal lead 142. Both the start signal line 141 and the start signal lead 142 extend along the second direction Y, and are electrically connected at the lower left and lower right corners of the first display substrate via a connecting line 160 extending along the first direction X, where the first direction X intersects the second direction Y. For example, the start signal line 141 and the start signal lead 142 are in the same layer and made of the same material, and the connecting line 160 is located in a different film layer from the start signal line 141; the three are electrically connected through corresponding connection holes. As mentioned above, the start signal line 141 is at risk of being exposed due to incomplete coverage by the encapsulation layer (hereinafter referred to as the exposure risk location LD). The start signal line 141 extends from the top to the bottom of the display substrate, resulting in a relatively long start signal line 141. Furthermore, there is an inflection point GD at the connection between the start signal line 141 and the start signal lead 142. Therefore, once the exposed start signal line 141 introduces static electricity, the introduced static electricity is likely to accumulate in large quantities at the connection between the start signal line 141 and the start signal lead 142 (i.e., the inflection point GD). This makes the inflection point GD very prone to electrostatic discharge, which in turn causes nearby signal lines, transition structures, or related components to be electrostatically damaged.

[0094] In view of this, embodiments of the present disclosure provide a display substrate, wherein the display motherboard for fabricating the display substrate may include multiple substrate regions, and different substrate regions are used to fabricate display substrates of different sizes.

[0095] The display substrate in this embodiment includes: a display area, a bonding area, a bonding pair area, a side area, a first corner area, and a second corner area. The side area and the display area are arranged along a first direction, and the bonding pair area, the display area, and the bonding area are arranged sequentially along a second direction. The first direction and the second direction intersect. The first corner area is located between the side area and the bonding pair area and at least partially surrounds the first corner of the display area. The second corner area is located between the side area and the bonding area and at least partially surrounds the second corner of the display area.

[0096] The display substrate in this embodiment further includes: a substrate, a gate driving circuit disposed on the substrate and located in the side area, and a plurality of first signal lines disposed on the substrate and located in the side area, the first corner area, and the second corner area. The gate driving circuit includes cascaded multi-stage shift register units.

[0097] Among them, multiple first signal lines are located on the side of the gate driving circuit away from the display area. These multiple first signal lines include a start signal line and a start signal lead. The start signal lead is located on the side of the start signal line closest to the gate driving circuit. Both the start signal line and the start signal lead extend along a second direction and are electrically connected in the second corner area via a first connecting line. An anti-static structure is provided on the multiple first signal lines. The anti-static structure is located at at least one of a first position and a second position. The first position includes the connection point of the start signal line, the start signal lead, and the first connecting line. The second position includes the portion of the multiple first signal lines located on the side of the row containing the first-stage shift register unit closest to the bonding pair area.

[0098] For display substrates of different sizes prepared by reusing mask patterns, even if some display substrates of certain sizes lack some anti-static units, the above-mentioned anti-static structure can improve the problem of static electricity accumulation at the connection between the start signal line (and / or start signal lead) and the first connection line, thereby reducing the risk of electrostatic breakdown at the connection between the start signal line (and / or start signal lead) and the first connection line, and improving the product yield of the display substrate under this preparation scheme.

[0099] The following is combined Figures 4 to 22 The display substrate in the embodiments of this disclosure will be described in detail.

[0100] Figure 4 A schematic plan view of a display substrate according to an embodiment of the present disclosure is shown.

[0101] See Figure 4The display substrate of this embodiment includes: a display area AA, a bonding area DP, a bonding pair area DPO, a side area CB, a first corner area GJ1, and a second corner area GJ2. The side area CB and the display area AA are arranged along a first direction X, and the bonding pair area DPO, the display area AA, and the bonding area DP are arranged sequentially along a second direction Y. The first direction X and the second direction Y intersect. The first corner area GJ1 is located between the side area CB and the bonding pair area DPO, and at least partially surrounds the first corner of the display area AA. The second corner area GJ2 is located between the side area CB and the bonding area DP, and at least partially surrounds the second corner of the display area AA. For example, the second direction Y can be... Figure 4 The vertical direction in the middle, the first direction X can be Figure 4 The horizontal direction in the equation means that the second direction Y and the first direction X are perpendicular to each other.

[0102] In embodiments of this disclosure, the display area AA can have various shapes. For example, the display area AA can be configured in various shapes such as a polygon (e.g., a rectangle) with a closed shape including straight edges, a circle or ellipse with curved edges, and a semicircle or semi-ellipse with both straight and curved edges. In embodiments of this disclosure, the display area AA is configured as an area having a quadrilateral shape including straight edges. It should be understood that this is only an exemplary embodiment of this disclosure and not a limitation thereof.

[0103] The binding area DP and the binding pair area DPO can be set on opposite sides of the display area AA. For example, the binding area DP and the binding pair area DPO can be set on the upper and lower sides of the display area AA, so that the binding pair area DPO, the display area AA and the binding area DP are arranged sequentially along the second direction Y.

[0104] The display substrate may include two side regions CB, which are disposed on opposite sides of the display area AA and located on different sides of the display area AA, such as the bonding area DP and the bonding pair area DPO. For example, the two side regions CB are located on the left and right sides of the display area AA, thereby arranging the side regions CB and the display area AA along the first direction X.

[0105] The shape of the display area AA can be rectangular, with four corners. The first corner can be the corner of the display area AA closest to the bonding pair area DPO, and the second corner can be the corner of the display area AA closest to the bonding pair area DP. That is, refer to... Figure 4The first corner can refer to the corner at the upper left or upper right of the display area AA, and the second corner can refer to the corner at the lower left or lower right of the display area AA. The first corner area GJ1 can surround the outer periphery of the first corner, and the second corner area GJ2 can surround the outer periphery of the second corner area GJ2. The display substrate can also include at least a plurality of signal lines (such as the first signal line mentioned below) located in the side area CB and bonding pads PAD located in the bonding area DP. The plurality of signal lines can extend from the side area CB into the second corner area GJ2, and then through the second corner area GJ2 into the bonding area DP to be electrically connected to the bonding pads PAD in the bonding area DP.

[0106] The display substrate may further include a substrate 200 and a plurality of pixel units P disposed on the substrate 200 and located in the display area AA. The plurality of pixel units P may be arranged in an array along the second direction Y and the first direction X. Each pixel unit P may include a plurality of sub-pixels PX. For example, pixel unit P may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. Exemplarily, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be set as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, but the embodiments disclosed herein are not limited thereto.

[0107] The display substrate also includes a plurality of gate lines GL and a plurality of data lines DL disposed on the substrate 200 and at least located in the display area AA. The gate lines GL extend along a first direction X, and the data lines DL extend along a second direction Y. For example, a sub-pixel PX is connected to one data line DL and one gate line GL, sub-pixels PX in the same row are connected to the same gate line GL, sub-pixels PX in different rows are connected to different gate lines GL, sub-pixels PX in the same column are connected to the same data line DL, and sub-pixels PX in different columns are connected to different data lines DL.

[0108] The display substrate in this embodiment further includes a gate driving circuit 210 disposed on the substrate 200 and located in the side region CB, the gate driving circuit 210 including cascaded multi-stage shift register units.

[0109] exist Figure 4 In the illustrated embodiment, the gate driving circuits 210 are located on the left and right sides of the display area AA, respectively. It should be noted that the left and right sides can refer to the left and right sides of the display substrate (screen) as viewed by the human eye during display. The display substrate also includes a driving chip (not shown in the figure), which may be located in the bonding area DP.

[0110] The driver chip includes a data driver circuit, which sequentially latches the input data according to a first clock signal and converts the latched data into analog signals, which are then input to the data lines DL of the display substrate. The gate driver circuit 210 is typically implemented by a shift register unit, which converts the second clock signal into on / off voltages and outputs them to the gate lines GL of the display substrate, respectively.

[0111] It should be noted that, although Figure 4 The diagram shows that the gate driving circuit 210 is located on the left and right sides of the display area AA. However, the embodiments of this disclosure are not limited to this, and the gate driving circuit 210 can be located at any suitable position on the display substrate.

[0112] Optionally, each shift register unit is connected to a gate line GL, and the scanning signals are output sequentially by each shift register unit to achieve line-by-line scanning of the pixel units. In some embodiments, each shift register unit may also be connected to multiple gate lines. This adapts to the development trend of high resolution and narrow bezels in display substrates.

[0113] Figure 5 A schematic plan view illustrating the location of the antistatic structure according to an embodiment of the present disclosure is shown.

[0114] See also Figure 4 and Figure 5 The display substrate in this embodiment further includes a plurality of first signal lines 220 disposed on the substrate 200 and located in the side area CB, the first corner area GJ1, and the second corner area GJ2. The plurality of first signal lines 220 are located on the side of the gate driving circuit 210 opposite to the display area AA. The plurality of first signal lines 220 include a start signal line STV and a start signal lead STVY. The start signal lead STVY is located on the side of the start signal line STV closest to the gate driving circuit 210. Both the start signal line STV and the start signal lead STVY extend along the second direction Y and are electrically connected in the second corner area GJ2 via a first connecting line 230.

[0115] In embodiments of this disclosure, both the starting signal line STV and the starting signal lead STVY extend along the second direction Y from the first corner region GJ1, through the side region CB, to the second corner region GJ2. The starting signal line STV and the starting signal lead STVY are disposed in the same layer and made of the same material, while the first connecting line 230 is located in a different film layer than the starting signal line STV and the starting signal lead STVY. For example, the first connecting line 230 is located in the second conductive layer, while the starting signal line STV and the starting signal lead STVY are located in the first conductive layer. The first connecting line 230 at least partially overlaps with the starting signal line STV, and they are electrically connected through a connecting hole at the overlapping portion. The first connecting line 230 also at least partially overlaps with the starting signal lead STVY, and they are electrically connected through a connecting hole at the overlapping portion.

[0116] The start signal line STV is located outside the start signal lead STVY. The start signal line STV is electrically connected to the bonding pad PAD in the bonding area DP through the adapter wire 240, and then electrically connected to the driver chip through the bonding pad PAD. The start signal lead STVY is electrically connected to the gate drive circuit 210, specifically to the first N-stage shift register units in the gate drive circuit 210, thereby providing a start signal to the first N-stage shift register units.

[0117] Reference Figure 5 In the embodiments of this disclosure, an anti-static structure E is provided on a plurality of first signal lines 220. The anti-static structure E is located on at least one of a first position 251 and a second position 252. The first position includes the connection point of the start signal line STV, the start signal lead STVY and the first connecting line 230. For example, at least one of the start signal lines STV and the start signal lead STVY is near the connection hole of the first connecting line 230. The second position includes the portion of the plurality of first signal lines 220 located on the side of the first-stage shift register cell row near the bonding pair area DPO. For example, on the start signal lines STV and the start signal lead STVY, above the row of the first-stage shift register cell.

[0118] In the embodiments of this disclosure, the first position 251, i.e., the position on the start signal line STV and the start signal lead STVY, is prone to static electricity accumulation. Providing an anti-static structure E at this position can directly improve the problem of static electricity accumulation. For example, the anti-static structure E may include a structure that can reduce the connection impedance at the connection point. For instance, near the connection hole between the start signal line STV (and / or the start signal lead STVY) and the first connection line 230, additional conductive material can be used to weld the start signal line STV (and / or the start signal lead STVY) and the first connection line 230. This increases the contact area between the start signal line STV (and / or the start signal lead STVY) and the first connection line 230, thereby reducing the connection impedance between the start signal line STV (and / or the start signal lead STVY) and the first connection line 230, and thus directly improving the problem of static electricity accumulation at the connection point between the start signal line STV (and / or the start signal lead STVY) and the first connection line 230.

[0119] The second position 252, namely the area on the starting signal line STV and the starting signal lead STVY near the exposed risk location, is equipped with an anti-static structure E to reduce static electricity introduced from the outside onto the starting signal line STV and the starting signal lead STVY. For example, at the second position 252, the starting signal line STV (and / or the starting signal lead STVY) is cut off, thereby isolating the portion of the starting signal line STV (and / or the starting signal lead STVY) at the exposed risk location from other parts, thus blocking the static electricity transmission path, and indirectly improving the problem of static electricity accumulation at the connection between the starting signal line STV (and / or the starting signal lead STVY) and the first connecting line 230.

[0120] In embodiments of this disclosure, the anti-static structure E can be located at the first position 251 to reduce the connection impedance between the starting signal line STV (and / or the starting signal lead STVY) and the first connecting line 230; or, the anti-static structure E can be located at the second position 252 to reduce the static electricity introduced from the outside by the starting signal line STV (and / or the starting signal lead STVY); or, the anti-static structure E can be located at both the first position 251 and the second position 252, thereby reducing both the static electricity introduced from the outside by the starting signal line STV (and / or the starting signal lead STVY) and the connection impedance between the starting signal line STV (and / or the starting signal lead STVY) and the first connecting line 230, thus achieving a better electrostatic protection effect.

[0121] In this way, for display substrates of different sizes prepared by reusing mask patterns, even if some display substrates of certain sizes lack some anti-static units, the anti-static structure E described above can improve the problem of static electricity accumulation at the connection between the start signal line STV (and / or start signal lead STVY) and the first connection line 230, thereby reducing the risk of electrostatic breakdown at the connection between the start signal line STV (and / or start signal lead STVY) and the first connection line 230, and improving the product yield of the display substrate under this preparation scheme.

[0122] The display substrate of the present disclosure embodiment will be further described below.

[0123] Figure 6 A plan view of a first location according to an embodiment of the present disclosure is shown schematically.

[0124] See also Figures 4 to 6 In some specific embodiments, the antistatic structure E located at the first position 251 includes: a first fusion structure E11 and / or a second fusion structure E12. In other words, the antistatic structure E located at the first position 251 may only include the first fusion structure E11; or, the antistatic structure E located at the first position 251 may only include the second fusion structure E12; or, the antistatic structure E located at the first position 251 may simultaneously include both the first fusion structure E11 and the second fusion structure E12. For clarity, unless otherwise specified, the following description uses the example of the antistatic structure E located at the first position 251 simultaneously including both the first fusion structure E11 and the second fusion structure E12 to illustrate the display substrate of the embodiments of this disclosure.

[0125] At the connection point of the start signal line STV and the first connecting line 230, a first fusion structure E11 fuses the start signal line STV and the first connecting line 230 together to reduce the connection impedance between the start signal line STV and the first connecting line 230. At the connection point of the start signal lead STVY and the first connecting line 230, a second fusion structure E12 fuses the start signal lead STVY and the first connecting line 230 together to reduce the connection impedance between the start signal lead STVY and the first connecting line 230.

[0126] In embodiments of this disclosure, a via can be formed at the connection point of the starting signal line STV and the first connecting line 230 using a laser. Then, a welding material is filled into the via and heated to form a first welding structure E11. The welding material is conductive, enabling it to conduct electricity between the starting signal line STV and the first connecting line 230. The first welding structure E11 further increases the conductive area of ​​the starting signal line STV and the first connecting line 230, thereby reducing the connection impedance between them.

[0127] Correspondingly, a via can be formed at the connection between the starting signal lead STVY and the first connecting line 230 using a laser. Then, a welding material is filled into the via and heated to form a second welding structure E12. The welding material is conductive, allowing it to conduct electricity between the starting signal lead STVY and the first connecting line 230. Through the first welding structure E11, the conductive area of ​​the starting signal lead STVY and the first connecting line 230 can be further increased based on their existing conductive structure, thereby reducing the connection impedance between them.

[0128] Optionally, at least one of the first fusion structure E11 and the second fusion structure E12 may be selected from a fusion material with good conductivity, which is beneficial to reduce the connection impedance between the start signal line STV and the first connection line 230 to a greater extent. For example, the fusion material may include tungsten and silver.

[0129] Optionally, the first fusion structure E11 and the second fusion structure E12 are made of the same material, and the first fusion structure E11 and the second fusion structure E12 can be formed simultaneously, thereby simplifying the manufacturing process.

[0130] In some specific embodiments, the display substrate includes a first conductive layer 261, a second conductive layer 262 located on the side of the first conductive layer 261 facing away from the substrate 200, and a third conductive layer 263 located on the side of the second conductive layer 262 facing away from the second conductive layer 262.

[0131] In embodiments of this disclosure, the first conductive layer 261 may include a gate metal layer, and the second conductive layer 262 may include source and drain electrode layers. The display substrate also includes a plurality of transistors, each transistor including a first electrode, a second electrode, and a gate, wherein one of the first electrode and the second electrode is a source, and the other is a drain. At least a portion of the transistors have their gates located in the gate metal layer, and at least a portion of the transistors have their first and second electrodes located in the source and drain electrode layers. The third conductive layer 263 may be any conductive film layer located on the side of the source and drain electrode layers away from the substrate 200, and can be specifically determined according to actual needs; embodiments of this disclosure do not limit this. For example, the display substrate of embodiments of this disclosure can be applied to a liquid crystal display panel, and the third conductive layer 263 may include a pixel electrode layer for setting pixel electrodes or a common electrode layer for setting common electrodes, etc.

[0132] The display substrate also includes a first transition structure 2631 located in the third conductive layer 263, a start signal line STV located in the first conductive layer 261, and a first connecting line 230 located in the second conductive layer 262. The start signal line STV includes a first connecting portion L1 and a signal line body S1. It should be noted that a portion of the signal line body S1 is covered by the first connecting line 230 (specifically, the second connecting portion L2, which will be mentioned below). Figure 6 The main body of the signal line S1 is not shown. The orthographic projection of the first connecting portion L1 on the substrate 200 at least partially overlaps with the orthographic projection of the first adapter structure 2631 on the substrate 200, and in the overlapping area, the first connecting portion L1 is electrically connected to the first adapter structure 2631 through at least one first via V1. The orthographic projection of the first connecting line 230 on the substrate 200 at least partially overlaps with the orthographic projection of the first adapter structure 2631 on the substrate 200, and in the overlapping area, the first connecting line 230 is electrically connected to the first adapter structure 2631 through at least one second via V2. The orthographic projection of the first fusion structure E11 on the substrate 200 overlaps with the orthographic projections of the first connection portion L1, the signal line body S1, and the first connecting line 230 on the substrate 200. In the overlapping area, the first fusion structure E11 fuses the first connection portion L1, the signal line body S1, and the first connecting line 230 together.

[0133] In this embodiment, insulating layers are provided between the first conductive layer 261 and the third conductive layer 263, and between the first conductive layer 261 and the second conductive layer 262. A first via V1 penetrates the insulating layer between the first conductive layer 261 and the third conductive layer 263, exposing a first connection portion L1. The first via V1 is filled with a conductive material. One end of the conductive material in the first via V1 is connected to the first transition structure 2631, and the other end is connected to the first connection portion L1, thereby enabling the first transition structure 2631 to be electrically connected to the first connection portion L1 through the conductive material in the first via V1. Optionally, the conductive material in the first via V1 and the first transition structure 2631 are formed as an integral structure. The second via V2 penetrates the insulating layer between the second conductive layer 262 and the third conductive layer 263, exposing the first connecting line 230. The second via V2 is filled with conductive material. One end of the conductive material in the second via V2 is connected to the first transition structure 2631, and the other end is connected to the first connecting line 230, thereby enabling the first transition structure 2631 to be electrically connected to the first connecting line 230 through the conductive material in the second via V2. Optionally, the conductive material in the second via V2 and the first transition structure 2631 are formed as an integral structure.

[0134] Optionally, the first connecting portion L1 is electrically connected to the first transition structure 2631 through a plurality of first vias V1, the plurality of first vias V1 being arranged in an array along the first direction X and the second direction Y. For example, referring to Figure 6 The first connecting part L1 is electrically connected to the first transition structure 2631 through six first vias V1, which are arranged in three rows and two columns along the first direction X and the second direction Y. The first connecting line 230 is electrically connected to the first transition structure 2631 through multiple second vias V2, which are arranged in an array along the first direction X and the second direction Y. For example, refer to Figure 6 The first connecting line 230 is electrically connected to the first adapter structure 2631 through six second vias V2, and the six second vias V2 are arranged in three rows and two columns along the first direction X and the second direction Y.

[0135] Optionally, the orthographic projection of the first fusion structure E11 on the substrate 200 overlaps with the edge of the orthographic projection of the first connecting portion L1 on the substrate 200. The orthographic projection of the first fusion structure E11 on the substrate 200 is spaced apart from the orthographic projections of the first via V1 and the second via V2 on the substrate 200. This allows sufficient fusion space to be reserved for the first fusion structure E11, reducing the impact of the first fusion structure E11 on the existing structure.

[0136] In some specific embodiments, the first connecting line 230 includes a second connecting portion L2 and a connecting line body S2. The orthographic projection of the second connecting portion L2 on the substrate 200 overlaps at least partially with the orthographic projection of the first adapter structure 2631 on the substrate 200. In the overlapping area, the second connecting portion L2 is electrically connected to the first adapter structure 2631 through a second via V2.

[0137] Optionally, the orthographic projection of the second connection portion L2 on the substrate 200 at least partially overlaps with the orthographic projection of the signal line body S1 on the substrate 200. The orthographic projections of the second connection portion L2 on the substrate 200 and the first connection portion L1 on the substrate 200 can be arranged along the second direction Y. The orthographic projections of the plurality of first vias V1 on the substrate 200 are located within the orthographic projections of the first connection portion L1 on the substrate 200, and the orthographic projections of the plurality of second vias V2 on the substrate 200 are located within the orthographic projections of the second connection portion L2 on the substrate 200.

[0138] Optionally, a plurality of first vias V1 and a plurality of second vias V2 are arranged in an array along a first direction X and a second direction Y, for example, referring to Figure 6 The six first vias V1 and the six second vias V2 are arranged in six rows and two columns along the first direction X and the second direction Y.

[0139] The first fusion structure E11 includes a first fusion portion E111 and / or a second fusion portion E112. The orthographic projection of the first fusion portion E111 on the substrate 200 overlaps with the orthographic projections of the first connecting portion L1 and the second connecting portion L2 on the substrate 200. In the overlapping region, the first fusion portion E111 fuses the first connecting portion L1 and the second connecting portion L2 together. The orthographic projection of the second fusion portion E112 on the substrate 200 overlaps with the orthographic projections of the signal line body S1 and the connecting line body S2 on the substrate 200. In the overlapping region, the second fusion portion E112 fuses the signal line body S1 and the connecting line body S2 together.

[0140] In the embodiments of this disclosure, the first fusion structure E11 may include only the first fusion portion E111, or the first fusion structure E11 may include only the second fusion portion E112, or the first fusion structure E11 may include both the first fusion portion E111 and the second fusion portion E112. For clarity, unless otherwise specified, the embodiments of this disclosure will be described below using the example of the first fusion structure E11 simultaneously including the first fusion portion E111 and the second fusion portion E112.

[0141] In embodiments of this disclosure, the orthographic projections of the first weld portion E111 and the second weld portion E112 on the substrate 200 may be located on the same side or different sides of the orthographic projection of the second connecting portion L2 on the substrate 200. For example, the shape of the second connecting portion L2 may include a rectangle, and the orthographic projections of the first weld portion E111 and the second weld portion E112 on the substrate 200 may be located on opposite sides of the orthographic projection of the second connecting portion L2 on the substrate 200. For instance, in the first direction X, one of the orthographic projections of the first weld portion E111 and the second weld portion E112 on the substrate 200 may be located on the side of the orthographic projection of the second connecting portion L2 on the substrate 200 that is away from the display area AA, while the other may be located on the side of the orthographic projection of the second connecting portion L2 on the substrate 200 that is close to the display area AA. Alternatively, the orthographic projections of the first weld portion E111 and the second weld portion E112 on the substrate 200 can be located on adjacent sides of the orthographic projection of the second connecting portion L2 on the substrate 200. For example, one of the orthographic projections of the first weld portion E111 and the second weld portion E112 on the substrate 200 may be located on the side of the orthographic projection of the second connecting portion L2 on the substrate 200 closer to the bonding pair area DPO, and the other may be located on the side of the orthographic projection of the second connecting portion L2 on the substrate 200 closer to the display area AA. The specific details can be determined according to actual needs, and the embodiments disclosed herein will not be listed one by one.

[0142] In some specific embodiments, the orthographic projection of the first fusion portion E111 on the substrate 200 and the orthographic projection of the second fusion portion E112 on the substrate 200 are located on the same side of the orthographic projection of the second connecting portion L2 on the substrate 200, and the orthographic projections of the first fusion portion E111 and the second fusion portion E112 on the substrate 200 are spaced apart.

[0143] For example, in the first direction X, the connecting line body S2 is connected to the second connecting portion L2 on the side near the display area AA, and the orthographic projections of the first welding portion E111 and the second welding portion E112 on the substrate 200 are both located on the side of the orthographic projection of the second connecting portion L2 on the substrate 200 near the display area AA. (Refer to...) Figure 6The first fusion joint E111 and the second fusion joint E112 are both located on the right side of the second connecting part L2. Specifically, the first fusion joint E111 is located at the upper right corner of the second connecting part L2, and the second fusion joint E112 is located directly below the first fusion joint E111. This ensures effective fusion of the first fusion joint E111 and the second fusion joint E112, while also maintaining sufficient spacing between them and other signal lines to prevent short circuits.

[0144] Optionally, the shape of the second connecting portion L2 may include a rectangle, and the rectangular corners of the orthographic projection of the first welding portion E111 on the substrate 200 and the orthographic projection of the second connecting portion L2 on the substrate 200 overlap.

[0145] In some specific embodiments, the display substrate further includes a second transition structure 2632 located in the third conductive layer 263, and the start signal lead STVY is located in the first conductive layer 261.

[0146] The start signal lead STVY includes a third connecting part L3 and a lead body S3. It should be noted that a portion of the lead body S3 is covered by the first connecting line 230 (specifically, the fourth connecting part L4, which will be mentioned below). Figure 6 The lead body S3 is not shown in the image. The orthographic projection of the third connection portion L3 on the substrate 200 at least partially overlaps with the orthographic projection of the second transition structure 2632 on the substrate 200, and in the overlapping area, the third connection portion L3 and the second transition structure 2632 are electrically connected through at least one third via V3. The orthographic projection of the first connection line 230 on the substrate 200 at least partially overlaps with the orthographic projection of the second transition structure 2632 on the substrate 200, and in the overlapping area, the first connection line 230 and the second transition structure 2632 are electrically connected through at least one fourth via V4. The orthographic projection of the second fusion structure E12 on the substrate 200 overlaps with the orthographic projection of the second connecting portion L2 on the substrate 200, the orthographic projection of the lead body S3 on the substrate 200, and the orthographic projection of the first connecting line 230 on the substrate 200. In the overlapping area, the second fusion structure E12 fuses the second connecting portion L2, the lead body S3, and the first connecting line 230 together.

[0147] In this embodiment, a third via V3 penetrates the insulating layer between the first conductive layer 261 and the third conductive layer 263, exposing a third connection portion L3. The third via V3 is filled with a conductive material. One end of the conductive material in the third via V3 is connected to the second transition structure 2632, and the other end is connected to the third connection portion L3, thereby enabling the second transition structure 2632 to be electrically connected to the third connection portion L3 through the conductive material in the third via V3. Optionally, the conductive material in the third via V3 and the second transition structure 2632 are formed as an integral structure. A fourth via V4 penetrates the insulating layer between the second conductive layer 262 and the third conductive layer 263, exposing a first connecting line 230. The fourth via V4 is filled with a conductive material. One end of the conductive material in the fourth via V4 is connected to the second transition structure 2632, and the other end is connected to the first connecting line 230, thereby enabling the second transition structure 2632 to be electrically connected to the first connecting line 230 through the conductive material in the fourth via V4. Optionally, the conductive material in the fourth via V4 is integrated with the second transition structure 2632.

[0148] Optionally, the third connecting portion L3 is electrically connected to the second transition structure 2632 through a plurality of third vias V3, the plurality of third vias V3 being arranged in an array along the first direction X and the second direction Y. For example, referring to Figure 6 The third connecting part L3 is electrically connected to the second transition structure 2632 through four third vias V3, which are arranged in two rows and two columns along the first direction X and the second direction Y. The first connecting line 230 is electrically connected to the second transition structure 2632 through multiple fourth vias V4, which are arranged in an array along the first direction X and the second direction Y. For example, refer to Figure 6 The first connecting line 230 is electrically connected to the second adapter structure 2632 through four fourth vias V4, and the four fourth vias V4 are arranged in two rows and two columns along the first direction X and the second direction Y.

[0149] Optionally, the orthographic projection of the second fusion structure E12 on the substrate 200 overlaps with the edge of the orthographic projection of the third connecting portion L3 on the substrate 200. The orthographic projection of the second fusion structure E12 on the substrate 200 is spaced apart from the orthographic projections of the first via V1 and the second via V2 on the substrate 200. This allows sufficient fusion space to be reserved for the second fusion structure E12, reducing the impact of the second fusion structure E12 on the existing structure.

[0150] In some specific embodiments, the first connecting line 230 further includes a fourth connecting portion L4 and a connecting line body S2. The orthographic projection of the fourth connecting portion L4 on the substrate 200 at least partially overlaps with the orthographic projection of the second transition structure 2632 on the substrate 200. In the overlapping area, the fourth connecting portion L4 is electrically connected to the second transition structure 2632.

[0151] Optionally, the orthographic projection of the fourth connection portion L4 on the substrate 200 at least partially overlaps with the orthographic projection of the lead body S3 on the substrate 200. The orthographic projections of the third connection portion L3 and the fourth connection portion L4 on the substrate 200 can be arranged along the second direction Y. The orthographic projections of the plurality of third vias V3 on the substrate 200 are located within the orthographic projections of the third connection portion L3 on the substrate 200, and the orthographic projections of the plurality of fourth vias V4 on the substrate 200 are located within the orthographic projections of the fourth connection portion L4 on the substrate 200.

[0152] Optionally, a plurality of third vias V3 and a plurality of fourth vias V4 are arranged in an array along the first direction X and the second direction Y, for example, referring to Figure 6 The four third vias V3 and the four fourth vias V4 are arranged in four rows and two columns along the first direction X and the second direction Y.

[0153] The second welding structure E12 includes a third welding portion E121 and / or a fourth welding portion E122. The orthographic projection of the third welding portion E121 on the substrate 200 overlaps with the orthographic projections of the third connecting portion L3 and the fourth connecting portion L4 on the substrate 200, and in the overlapping area, the third welding portion E121 welds the third connecting portion L3 and the fourth connecting portion L4 together. The orthographic projection of the fourth welding portion E122 on the substrate 200 overlaps with the orthographic projections of the lead body S3 and the connecting wire body S2 on the substrate 200, and in the overlapping area, the fourth welding portion E122 welds the lead body S3 and the connecting wire body S2 together.

[0154] In the embodiments of this disclosure, the second fusion structure E12 may include only the third fusion portion E121, or the second fusion structure E12 may include only the fourth fusion portion E122, or the second fusion structure E12 may include both the third fusion portion E121 and the fourth fusion portion E122. For clarity, unless otherwise specified, the embodiments of this disclosure will be described below using the example of the second fusion structure E12 simultaneously including both the third fusion portion E121 and the fourth fusion portion E122.

[0155] In embodiments of this disclosure, the orthographic projections of the third weld portion E121 and the fourth weld portion E122 on the substrate 200 may be located on the same side or different sides of the orthographic projection of the fourth connecting portion L4 on the substrate 200. Exemplarily, the shape of the fourth connecting portion L4 may include a rectangle, and the orthographic projections of the third weld portion E121 and the fourth weld portion E122 on the substrate 200 may be located on opposite sides of the orthographic projection of the fourth connecting portion L4 on the substrate 200. For example, in the first direction X, one of the orthographic projections of the third weld portion E121 and the fourth weld portion E122 on the substrate 200 may be located on the side of the orthographic projection of the fourth connecting portion L4 on the substrate 200 away from the bonding pair region DPO, while the other may be located on the side of the orthographic projection of the fourth connecting portion L4 on the substrate 200 closer to the bonding pair region DPO. Alternatively, the orthographic projections of the third weld portion E121 and the fourth weld portion E122 on the substrate 200 may be located on the same side of the orthographic projection of the fourth connecting portion L4 on the substrate 200. For example, the orthographic projections of the third weld portion E121 and the fourth weld portion E122 on the substrate 200 may both be located on the side of the orthographic projection of the fourth connecting portion L4 on the substrate 200 that is closer to the display area AA.

[0156] In some specific embodiments, the orthographic projection of the third fusion portion E121 on the substrate 200 and the orthographic projection of the fourth fusion portion E122 on the substrate 200 are located on different sides of the orthographic projection of the third connecting portion L3 on the substrate 200, and the orthographic projections of the third fusion portion E121 and the fourth fusion portion E122 on the substrate 200 are spaced apart.

[0157] In embodiments of this disclosure, the orthographic projections of the third fusion portion E121 and the fourth fusion portion E122 on the substrate 200 can be located on adjacent sides of the orthographic projection of the fourth connecting portion L4 on the substrate 200. For example, the orthographic projection of the third fusion portion E121 on the substrate 200 is located on the side of the orthographic projection of the fourth connecting portion L4 on the substrate 200 closer to the display area AA, and the orthographic projections of the fourth fusion portion E122 on the substrate 200 are both located on the side of the orthographic projection of the fourth connecting portion L4 on the substrate 200 closer to the bonding area DP. (Refer to...) Figure 6The third fusion splice E121 is located to the right of the fourth connector L4, and the main body of the connecting wire S2 is connected to the lower part of the fourth connector L4. The fourth fusion splice E122 is located below the fourth connector L4. This ensures effective fusion of the third and fourth fusion splices E121 and E122, while also maintaining sufficient spacing between them and other signal lines to prevent short circuits.

[0158] Optionally, the shape of the fourth welding portion E122 may include a rectangle, and the rectangular corners of the orthographic projection of the third welding portion E121 on the substrate 200 and the orthographic projection of the fourth connecting portion L4 on the substrate 200 overlap.

[0159] Figure 7 One of the plan views of a first fusion structure according to an embodiment of the present disclosure is schematically shown. Figure 8 One of the plan views of a second fusion structure according to an embodiment of the present disclosure is shown schematically. Figure 9 A schematic plan view of a first weld hole according to an embodiment of the present disclosure is shown. Figure 10 A schematic plan view of a second weld hole according to an embodiment of the present disclosure is shown. Wherein, Figure 7 (and Figure 8 The image shows the surface of the start signal line (and start signal lead) facing away from the substrate 200. Figure 9 (and Figure 10 The image shows the surface of the start signal line (and start signal lead) near the substrate 200.

[0160] Combined with reference Figures 7 to 10 In some specific embodiments, the materials of the first fusion structure E11 and the second fusion structure E12 include solid fusion materials. The first fusion structure E11 fuses the start signal line STV and the first connecting line 230 together through at least one first fusion hole VR1. The second fusion structure E12 fuses the start signal lead STVY and the first connecting line 230 together through at least one second fusion hole VR2. The diameter of at least one first fusion hole VR1 and at least one second fusion hole VR2 is less than or equal to the line width of the first connecting line 230.

[0161] In this embodiment, the first fusion structure E11 and the second fusion structure E12 are made of the same material, both of which can include metal powder. For example, the materials of both the first fusion structure E11 and the second fusion structure E12 include tungsten powder. The first fusion hole and the second fusion hole can be formed by a first laser. For example, the wavelength of the first laser can be between 900 nm and 1200 nm, such as 1064 nm. The aperture of the first fusion hole and the second fusion hole formed by this laser is small, for example, the aperture of the first fusion hole and the second fusion hole is less than or equal to 10 μm.

[0162] In the embodiments of this disclosure, the first fusion structure E11 fuses the starting signal line STV and the first connecting line 230 together through a plurality of first fusion holes VR1. Specifically, the first connecting portion L1 and the second connecting portion L2 are arranged along the second direction Y, and the connecting line body S2 and the second connecting portion L2 are arranged along the first direction X. In the second direction Y, a first fusion hole VR1 is formed at the junction of the first connecting portion L1 and the second connecting portion L2, and in the first direction X, another first fusion hole VR1 is formed at the junction of the connecting line body S2 and the second connecting portion L2. A first laser can drill holes from the back side of the display substrate to form the first fusion hole VR1 and the second fusion hole VR2. For example, the first fusion hole VR1 formed at the junction of the first connecting portion L1 and the second connecting portion L2 penetrates the first connecting portion L1 and exposes a portion of the second connecting portion L2, and the first fusion hole VR1 formed at the junction of the connecting line body S2 and the second connecting portion L2 penetrates the signal line body S1 and exposes a portion of the connecting line body S2.

[0163] Next, tungsten powder is filled into the two first fusion holes VR1 to connect the first connecting part L1 and the second connecting part L2, as well as the signal line body S1 and the connecting line body S2. Then, the tungsten powder in the two first fusion holes VR1 is heated to fuse them, thereby forming the first fusion part E111 and the second fusion part E112. Since the diameter of the first fusion hole VR1 is less than or equal to 10 μm, the space occupied by the formed first fusion part E111 and the second fusion part E112 is also small; for example, the diameter of either the first fusion part E111 or the second fusion part E112 is less than or equal to 10 μm.

[0164] In the embodiments of this disclosure, the second fusion structure E12 fuses the start signal lead STVY and the first connecting line 230 together through a plurality of second fusion holes VR2. Specifically, the third connecting portion L3 and the fourth connecting portion L4 are arranged along the second direction Y. A second fusion hole VR2 is formed at the junction of the third connecting portion L3 and the fourth connecting portion L4 in the second direction Y, and the second fusion hole VR2 penetrates the third connecting portion L3, exposing a portion of the fourth connecting portion L4. Similarly, the connecting line body S2 and the fourth connecting portion L4 are arranged along the second direction Y. A second fusion hole VR2 is formed at the junction of the connecting line body S2 and the fourth connecting portion L4 in the second direction Y, and the second fusion hole VR2 penetrates the lead body S3, exposing a portion of the connecting line body S2.

[0165] Next, tungsten powder is filled into the two second welding holes VR2 to connect the third connecting part L3 and the fourth connecting part L4, as well as the lead body S3 and the connecting body S2. Then, the tungsten powder in the two second welding holes VR2 is heated to weld, thereby forming the third welding part E121 and the fourth welding part E122. Since the diameter of the second welding holes VR2 is less than or equal to 10 μm, the space occupied by the formed third welding part E121 and the fourth welding part E122 is also small; for example, the diameter of either the third welding part E121 or the fourth welding part E122 is less than or equal to 10 μm.

[0166] In some specific embodiments, the orthographic projections of at least one first weld hole VR1 and at least one second weld hole VR2 on the substrate 200 at least partially overlap with the orthographic projection of the first connecting line 230 on the substrate 200.

[0167] In the embodiments of this disclosure, the formed first weld hole VR1 can penetrate the first connecting portion L1 and the signal line body S1, exposing the surface of the first connecting line 230 near the substrate 200. For example, the two first weld holes VR1 respectively expose the surface of the second connecting portion L2 near the substrate 200 and the surface of the connecting line body S2 near the substrate 200. The formed second weld hole VR2 can penetrate the third connecting portion L3 and the lead body S3, exposing the surface of the first connecting line 230 near the substrate 200. For example, the two second weld holes VR2 respectively expose the surface of the fourth connecting portion L4 near the substrate 200 and the surface of the connecting line body S2 near the substrate 200.

[0168] Figure 11 A second plan view of a first fusion structure according to an embodiment of the present disclosure is schematically shown. Figure 12A second plan view of a second fusion structure according to an embodiment of the present disclosure is shown schematically. Figure 13 A schematic plan view of a third weld hole according to an embodiment of the present disclosure is shown. Figure 14 A schematic plan view of a fourth weld hole according to an embodiment of the present disclosure is shown. Figure 15 A third plan view schematically illustrates a first fusion structure according to an embodiment of the present disclosure. Figure 16 A third plan view schematically illustrates a second fusion structure according to an embodiment of the present disclosure. Wherein, Figures 11 to 16 The start signal line (or start signal lead) shown is the surface of the start signal line (or start signal lead) facing away from the substrate 200.

[0169] Combined with reference Figures 11 to 16 In some specific embodiments, the materials of the first fusion structure E11 and the second fusion structure E12 include solid fusion materials or liquid fusion materials. The first fusion structure E11 fuses the start signal line STV and the first connecting line 230 together through the third fusion hole VR3. The second fusion structure E12 fuses the start signal lead STVY and the first connecting line 230 together through the fourth fusion hole VR4. The diameter of the third fusion hole VR3 and the fourth fusion hole VR4 is larger than the line width of the first connecting line 230.

[0170] In other implementation examples, the diameters of the third weld hole VR3 and the fourth weld hole VR4 may not be greater than the line width of the first connecting line 230, but their diameters are greater than the diameters of the first weld hole VR1 and the second weld hole VR2.

[0171] In this embodiment, the first fusion structure E11 and the second fusion structure E12 are made of the same material. Optionally, both materials may include solid fusion materials, for example, both the first fusion structure E11 and the second fusion structure E12 may include tungsten powder. Optionally, both the first fusion structure E11 and the second fusion structure E12 may include liquid fusion materials, for example, both the first fusion structure E11 and the second fusion structure E12 may include silver solution, for example, silver-containing printing ink (INK).

[0172] The first weld hole VR1 and the second weld hole VR2 can be formed by a second laser, which may include a pulsed laser, such as a picosecond laser or a femtosecond laser. The wavelength of the second laser can be between 400 nm and 600 nm, for example, 532 nm. The first weld hole VR1 and the second weld hole VR2 formed by this laser have a relatively large aperture, for example, the aperture of the first weld hole VR1 and the second weld hole VR2 is greater than or equal to 10 μm.

[0173] Unlike the previous embodiments, since the second laser can form a first weld hole VR1 and a second weld hole VR2 with a larger aperture, the materials for the first weld structure E11 and the second weld structure E12 can be either solid weld materials or liquid weld materials. This is because the larger aperture allows the liquid weld material to be fully heated, thereby enabling the liquid weld material to reach the expected degree of solidification and achieve welding.

[0174] The following section first describes the preparation process of solid welding materials for the first welding structure E11 and the second welding structure E12 in this embodiment.

[0175] In the embodiments of this disclosure, the first fusion structure E11 fuses the start signal line STV and the first connecting line 230 together through a plurality of third fusion holes VR3. Specifically, the first connecting portion L1 and the second connecting portion L2 are arranged along the second direction Y, and the connecting line body S2 and the second connecting portion L2 are arranged along the first direction X. In the second direction Y, a third fusion hole VR3 is formed at the junction of the first connecting portion L1 and the second connecting portion L2, and in the first direction X, another third fusion hole VR3 is formed at the junction of the connecting line body S2 and the second connecting portion L2.

[0176] Unlike the previous embodiments, the second laser can selectively peel off a film layer from the display substrate without damaging other film layers. For example, it can selectively peel off the insulating layer between the first connecting portion L1 and the second connecting portion L2 without damaging the first connecting portion L1 and the second connecting portion L2 (or the connecting line body S2). Therefore, in this embodiment, the third weld hole VR3 formed at the junction of the first connecting portion L1 and the second connecting portion L2 can expose only the surface on one side of the first connecting portion L1 (e.g., the surface facing away from the substrate 200), rather than penetrating through the first connecting portion L1. Optionally, the third weld hole VR3 formed at the junction of the first connecting portion L1 and the second connecting portion L2 can be disposed adjacent to the second connecting portion L2.

[0177] Accordingly, the third weld hole VR3 formed at the junction of the connector body S2 and the second connector L2 exposes only the surface of the signal line body S1 (e.g., the surface facing away from the substrate 200), rather than penetrating the signal line body S1. Optionally, the third weld hole VR3 formed at the junction of the connector body S2 and the second connector L2 is disposed adjacent to the connector body S2.

[0178] In some specific embodiments, the first weld structure E11 contacts the surface of the first connecting line 230 facing away from the substrate 200. For example, after forming two third weld holes VR3, tungsten powder is filled into the two third weld holes VR3. The tungsten powder covers the surface of the first connecting portion L1 facing away from the substrate 200 and the surface of the second connecting portion L2 facing away from the substrate 200, thereby making the first connecting portion L1 and the second connecting portion L2 conductive. Additionally, the tungsten powder covers the surface of the first connecting portion L1 facing away from the substrate 200 and the surface of the connecting line body S2 facing away from the substrate 200, thereby making the signal line body S1 and the connecting line body S2 conductive. Then, the tungsten powder in the two third weld holes VR3 is heated to perform welding, thereby forming the first weld portion E111 and the second weld portion E112. Since the aperture of the first weld hole VR1 is greater than or equal to 10μm, the space occupied by the first weld portion E111 and the second weld portion E112 is larger. Compared with the previous embodiment, the connection area of ​​the first weld portion E111 and the second weld portion E112 in this embodiment is larger, which can further reduce the connection impedance and thus has a better effect on improving electrostatic accumulation.

[0179] In the embodiments of this disclosure, the second fusion structure E12 fuses the start signal lead STVY and the first connecting line 230 together through a plurality of fourth fusion holes VR4. Specifically, the third connecting portion L3 and the fourth connecting portion L4 are arranged along the second direction Y, and the connecting line body S2 and the fourth connecting portion L4 are arranged along the second direction Y. In the second direction Y, a fourth fusion hole VR4 is formed at the junction of the third connecting portion L3 and the fourth connecting portion L4, and another fourth fusion hole VR4 is formed at the junction of the connecting line body S2 and the fourth connecting portion L4 in the second direction Y.

[0180] Unlike the previous embodiments, the second laser can selectively peel off a film layer from the display substrate without damaging other film layers. For example, it can selectively peel off the insulating layer between the third connection portion L3 and the fourth connection portion L4 without damaging the third connection portion L3 and the fourth connection portion L4 (or the connecting line body S2). Therefore, in this embodiment, the second weld hole VR2 formed at the junction of the third connection portion L3 and the fourth connection portion L4 can expose only one side surface of the third connection portion L3 (e.g., the side surface facing away from the substrate 200), rather than penetrating through the third connection portion L3. Optionally, the fourth weld hole VR4 formed at the junction of the third connection portion L3 and the fourth connection portion L4 can be disposed adjacent to the fourth connection portion L4.

[0181] Accordingly, the fourth weld hole VR4 formed at the junction of the connecting wire body S2 and the fourth connecting portion L4 exposes only one side surface of the lead wire body S3 (e.g., the side surface of the lead wire body S3 and / or the side surface facing away from the substrate 200), rather than penetrating through the lead wire body S3. Optionally, the second weld hole VR2 formed at the junction of the connecting wire body S2 and the fourth connecting portion L4 is disposed adjacent to the connecting wire body S2.

[0182] In some specific embodiments, the second weld structure E12 contacts the surface of the first connecting line 230 facing away from the substrate 200. For example, after forming two fourth weld holes VR4, tungsten powder is filled into the two fourth weld holes VR4. The tungsten powder covers the surface of the third connecting portion L3 facing away from the substrate 200 and the surface of the fourth connecting portion L4 facing away from the substrate 200, thereby connecting the third connecting portion L3 and the fourth connecting portion L4. Additionally, tungsten powder covers the side surface (and / or the surface facing away from the substrate 200) of the lead body S3 and the surface of the connecting body S2 facing away from the substrate 200, thereby connecting the lead body S3 and the connecting body S2. Then, the tungsten powder in the two fourth weld holes VR4 is heated to perform welding, thereby forming the third weld portion E121 and the fourth weld portion E122. Since the aperture of the fourth weld hole VR4 is greater than or equal to 10μm, the space occupied by the formed third weld portion E121 and fourth weld portion E122 is larger. Compared with the previous embodiment, the connection area of ​​the third weld portion E121 and the fourth weld portion E122 in this embodiment is larger, which can further reduce the connection impedance and thus has a better effect on improving electrostatic accumulation.

[0183] In some specific embodiments, each of the first fusion structure E11 and the second fusion structure E12 is in contact with the surface of the first connecting line 230 on the side opposite to the substrate 200.

[0184] The following describes the preparation process of the first welding structure E11 and the second welding structure E12 in this embodiment using liquid welding materials.

[0185] In the embodiments of this disclosure, the first fusion structure E11 fuses the start signal line STV and the first connecting line 230 together through a plurality of third fusion holes VR3. Specifically, the first connecting portion L1 and the second connecting portion L2 are arranged along the second direction Y, and the connecting line body S2 and the second connecting portion L2 are arranged along the first direction X. In the second direction Y, a third fusion hole VR3 is formed at the junction of the first connecting portion L1 and the second connecting portion L2, and in the first direction X, another third fusion hole VR3 is formed at the junction of the connecting line body S2 and the second connecting portion L2.

[0186] The second laser can selectively peel off a film layer from the display substrate without damaging other film layers. For example, it can selectively peel off the insulating layer between the first connecting portion L1 and the second connecting portion L2 without damaging the first connecting portion L1 and the second connecting portion L2 (or the connecting line body S2). Therefore, in this embodiment, the third weld hole VR3 formed at the junction of the first connecting portion L1 and the second connecting portion L2 can expose only the surface of the first connecting portion L1 facing away from the substrate 200. Optionally, the third weld hole VR3 formed at the junction of the first connecting portion L1 and the second connecting portion L2 can be disposed adjacent to the second connecting portion L2.

[0187] Accordingly, the third weld hole VR3 formed at the junction of the connector body S2 and the second connection portion L2 exposes only the surface of the signal line body S1 facing away from the substrate 200. Optionally, the third weld hole VR3 formed at the junction of the connector body S2 and the second connection portion L2 is disposed adjacent to the connector body S2.

[0188] Next, silver solution is filled into the two first fusion holes VR1. The silver solution covers the surface of the first connection portion L1 facing away from the substrate 200 and the surface of the second connection portion L2 facing away from the substrate 200, thereby making the first connection portion L1 and the second connection portion L2 conductive. Similarly, silver solution covers the surface of the signal line body S1 facing away from the substrate 200 and the surface of the connection line body S2 facing away from the substrate 200, thereby making the signal line body S1 and the connection line body S2 conductive. Then, the silver solution in the two third fusion holes VR3 is heated to perform fusion, thereby forming the third fusion portion E121 and the fourth fusion portion E122. The heating temperature can be from 150°C to 250°C, for example, 200°C, and the heating time can be from 4s to 12s, for example, 8s. Compared to the previous embodiment, excess silver solution can be removed by laser, thereby preventing the final formed first fusion portion E111 and second fusion portion E112 from short-circuiting with other signal lines.

[0189] In the embodiments of this disclosure, the second fusion structure E12 fuses the start signal lead STVY and the first connecting line 230 together through a plurality of fourth fusion holes VR4. Specifically, the third connecting portion L3 and the fourth connecting portion L4 are arranged along the second direction Y, and the connecting line body S2 and the fourth connecting portion L4 are arranged along the second direction Y. In the second direction Y, a fourth fusion hole VR4 is formed at the junction of the third connecting portion L3 and the fourth connecting portion L4, and another fourth fusion hole VR4 is formed at the junction of the connecting line body S2 and the fourth connecting portion L4 in the second direction Y.

[0190] The second laser can selectively peel off a film layer from the display substrate without damaging other film layers. For example, it can selectively peel off the insulating layer between the third connection portion L3 and the fourth connection portion L4 without damaging the third connection portion L3 and the fourth connection portion L4 (or the connecting line body S2). Therefore, in this embodiment, the fourth weld hole VR4 formed at the junction of the third connection portion L3 and the fourth connection portion L4 can expose only the surface of the third connection portion L3 facing away from the substrate 200. Optionally, the fourth weld hole VR4 formed at the junction of the third connection portion L3 and the fourth connection portion L4 can be disposed adjacent to the fourth connection portion L4.

[0191] In other words, in the embodiments disclosed herein, the orthographic projections of the third weld hole VR3 and the fourth weld hole VR4 on the substrate 200 are spaced apart from the orthographic projection of the first connecting line 230 on the substrate 200.

[0192] Accordingly, the fourth weld hole VR4 formed at the junction of the connecting wire body S2 and the fourth connecting portion L4 exposes only the side surface of the lead body S3 (e.g., the side surface of the lead body S3 and / or the surface facing away from the substrate 200). Optionally, the fourth weld hole VR4 formed at the junction of the connecting wire body S2 and the fourth connecting portion L4 is disposed adjacent to the connecting wire body S2.

[0193] Next, silver solution is filled into the two fourth fusion holes VR4. The silver solution covers the surface of the third connection L3 facing away from the substrate 200 and the surface of the fourth connection L4 facing away from the substrate 200, thereby making the third connection L3 and the fourth connection L4 conductive. Additionally, silver solution covers the side surface (and / or the surface facing away from the substrate 200) of the lead body S3 and the surface of the connecting line body S2 facing away from the substrate 200, thereby making the lead body S3 and the connecting line body S2 conductive. Then, the silver solution in the two fourth fusion holes VR4 is heated to perform fusion, thereby forming the third fusion portion E121 and the fourth fusion portion E122. Compared to the previous embodiment, excess silver solution can be removed by laser, thereby preventing the final formed third fusion portion E121 and fourth fusion portion E122 from short-circuiting with other signal lines.

[0194] With the antistatic structure E at the first position 251, the antistatic effect can be improved from 14-15KV before the improvement (i.e., without any antistatic structure E in the embodiments of this disclosure) to 25-29KV.

[0195] The antistatic structure E at the second position 252 in the embodiments of this disclosure will be described below.

[0196] Figure 17 An equivalent circuit diagram of a shift register unit according to an embodiment of the present disclosure is shown schematically. Figure 18 A schematic diagram of one of the display motherboards according to an embodiment of the present disclosure is shown. Figure 19 A schematic plan view illustrating the positions of the third and fourth welding structures according to embodiments of the present disclosure is shown.

[0197] Let's combine the following... Figure 17 First, the circuit of the shift register unit GOA involved in the embodiments of this disclosure will be introduced.

[0198] The shift register unit GOA in this embodiment includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and a capacitor C.

[0199] The gate of the first transistor M1 is connected to the first input terminal SR, the first terminal of the first transistor M1 is connected to the pull-up point PU, and the second terminal of the first transistor M1 is connected to the first voltage terminal VGL.

[0200] The gate of the second transistor M2 is connected to the data input terminal INPUT, the first terminal of the second transistor M2 is connected to the data input terminal INPUT, and the second terminal of the second transistor M2 is connected to the pull-up point PU.

[0201] The gate of the third transistor M3 is connected to the pull-up point reset terminal RST PU, the first terminal of the third transistor M3 is connected to the pull-up point PU, and the second terminal of the third transistor M3 is connected to the first voltage terminal VGL.

[0202] The gate of the sixteenth transistor M16 is connected to the pull-up point PU, the first terminal of the sixteenth transistor M16 is connected to the clock signal terminal CLK, and the second terminal of the sixteenth transistor M16 is connected to the first output terminal OUTPUT.

[0203] The gate of the fourth transistor M4 is connected to the first pull-down point PD1, the first terminal of the fourth transistor M4 is connected to the first terminal of the third transistor M3, and the second terminal of the fourth transistor M4 is connected to the second voltage terminal VGL.

[0204] The gate of the fifth transistor M5 is connected to the second pull-down point PD2, the first terminal of the fifth transistor M5 is connected to the first terminal of the fourth transistor M4, and the second terminal of the fifth transistor M5 is connected to the second voltage terminal VGL.

[0205] The gate of the sixth transistor M6 is connected to the third voltage terminal VDDO, the first terminal of the sixth transistor M6 is connected to the third voltage terminal VDDO, and the second terminal of the sixth transistor M6 is connected to the third pull-down point PD CN1.

[0206] The gate of the seventh transistor M7 is connected to the pull-up point PU, the first terminal of the seventh transistor M7 is connected to the second terminal of the sixth transistor M6, and the second terminal of the seventh transistor M7 is connected to the second voltage terminal VGL.

[0207] The gate of the eighth transistor M8 is connected to the second terminal of the sixth transistor M6, the first terminal of the eighth transistor M8 is connected to the third voltage terminal VDDO, and the second terminal of the eighth transistor M8 is connected to the first pull-down point PD1.

[0208] The gate of the ninth transistor M9 is connected to the pull-up point PU, the first terminal of the ninth transistor M9 is connected to the second terminal of the eighth transistor M8, and the second terminal of the ninth transistor M9 is connected to the second voltage terminal VGL.

[0209] The gate of the tenth transistor M10 is connected to the fourth voltage terminal VDDE, the first terminal of the tenth transistor M10 is connected to the fourth voltage terminal VDDE, and the second terminal of the tenth transistor M10 is connected to the fourth pull-down point PD CN2.

[0210] The gate of the eleventh transistor M11 is connected to the pull-up point PU, the first terminal of the eleventh transistor M11 is connected to the second terminal of the tenth transistor M10, and the second terminal of the eleventh transistor M11 is connected to the second voltage terminal VGL.

[0211] The gate of the twelfth transistor M12 is connected to the second terminal of the tenth transistor M10, the first terminal of the twelfth transistor M12 is connected to the fourth voltage terminal VDDE, and the second terminal of the twelfth transistor M12 is connected to the second pull-down point PD2.

[0212] The gate of the thirteenth transistor M13 is connected to the pull-up point PU, the first terminal of the thirteenth transistor M13 is connected to the second terminal of the twelfth transistor M12, and the second terminal of the thirteenth transistor M13 is connected to the second voltage terminal VGL.

[0213] The gate of the seventeenth transistor M17 is connected to the reset voltage terminal RESET, the first terminal of the seventeenth transistor M17 is connected to the first output terminal OUTPUT, and the second terminal of the seventeenth transistor M17 is connected to the second voltage terminal VGL.

[0214] The gate of the fifteenth transistor M15 is connected to the first pull-down point PD1, the first terminal of the fifteenth transistor M15 is connected to the first terminal of the seventeenth transistor M17, and the second terminal of the fifteenth transistor M15 is connected to the second voltage terminal VGL.

[0215] The gate of the fourteenth transistor M14 is connected to the second pull-down point PD2, the first terminal of the fourteenth transistor M14 is connected to the first terminal of the fifteenth transistor M15, and the second terminal of the fourteenth transistor M14 is connected to the second voltage terminal VGL.

[0216] The first end of capacitor C is connected to the pull-up point PU, and the second end of capacitor C is connected to the first output terminal OUTPUT.

[0217] In the embodiments of this disclosure, any transistor in the shift register unit GOA can be an N-type transistor or a P-type transistor, which can be selected according to the actual situation; the first terminal of the transistor is the source or drain, and the second terminal of the transistor is the drain or source corresponding to the first terminal.

[0218] Reference Figure 18 The display motherboard includes multiple first substrate regions 300 arranged along a third and a fourth direction, and start signal lines and start signal leads on the display motherboard extend along the fourth direction. For a portion of the first substrate region 300, after cutting along the third direction (e.g., a roughing step and / or a finishing step), a portion of the signal lines will be cut off, see reference. Figure 19 The cutting line QL is shown in the diagram.

[0219] To ensure that the start input terminal of the first N-stage shift register unit GOA in the gate drive circuit 210 can receive the start signal normally, in the embodiments of this disclosure, the start input terminal of the first N-stage shift register unit GOA needs to be re-fused with the SVT signal line and the start signal lead STVY.

[0220] Reference Figure 19 Specifically, the display substrate further includes: a plurality of third connection lines 310 and at least one fourth connection line 320 disposed on the substrate 200 and located in the side region CB. The plurality of third connection lines 310 extend along the second direction Y, and the at least one fourth connection line 320 extends along the first direction X. The plurality of third connection lines 310 are located on the side of the gate drive circuit 210 opposite to the start signal lead STVY. At least one level of shift register unit GOA includes a first input terminal SR. The first input terminals SR of the first N levels of shift register units GOA are electrically connected to the plurality of third connection lines 310, and the first input terminals SR of different levels of shift register units GOA are electrically connected to different third connection lines 310. The start signal lead STVY is electrically connected to the plurality of third connection lines 310 through at least one fourth connection line 320. N is a natural number.

[0221] The first N-stage shift register unit GOA can refer to the first three-stage shift register unit GOA. The fourth connection line 320 can be in the same layer and made of the same material as the first connection line 230. For example, the fourth connection line 320 is located in the second conductive layer 262. The first input terminal SR of the first three-stage shift register unit GOA can be electrically connected to the start signal lead STVY through the bridging of the fourth connection line 320, thereby transmitting the start signal on the start signal lead STVY to the first input terminal SR of the first three-stage shift register unit GOA.

[0222] It should be noted that in the embodiments of this disclosure, the shift register units GOA in the gate driving circuit 210 all refer to effective shift register units GOA, that is, the shift register units GOA in the gate driving circuit 210 can output scanning signals sequentially according to the cascade relationship when the display substrate is working.

[0223] Figure 20 A schematic plan view illustrating the location of the partition structure according to an embodiment of the present disclosure is shown.

[0224] Combined with reference Figure 19 and Figure 20 In some specific embodiments, the display substrate further includes a ground signal line GND, a common voltage signal line VCOM, multiple clock signal lines CLKL, and a first voltage signal line VGLL. At least one of the multiple clock signal lines CLKL is electrically connected to the clock signal terminal CLK in the shift register unit GOA, and the first voltage signal line VGLL is electrically connected to the second voltage terminal VGL in the shift register unit GOA. In the first direction X, the start signal line STV is located between the common voltage signal line VCOM and the clock signal lines CLKL.

[0225] In some specific embodiments, the antistatic structure E located at the second position 252 includes: a partition structure E21, on which portions of the partition structure E21 near the bonding pair area DPO and near the bonding pair area DP are separated by the partition structure E21. The starting signal lead STVY is fused to at least one fourth connecting line 320 via a third fusion structure R1, and at least one fourth connecting line 320 is fused to multiple third connecting lines 310 via a fourth fusion structure R2. The partition structure E21, the third fusion structure R1, and the fourth fusion structure R2 are located within a preset range, which is less than or equal to the range defined by the laser operation window.

[0226] In the embodiments of this disclosure, the preparation methods of the third fusion structure R1 and the fourth fusion structure R2 can be the same as those of the first fusion structure E11 and the second fusion structure E12. Therefore, the morphology of the third fusion structure R1 and the fourth fusion structure R2 can be determined with reference to the first fusion structure E11 and the second fusion structure E12. Hence, the embodiments of this disclosure will not be described again here.

[0227] The laser operation window is configured such that the portion within the laser operation window can be formed through a single-step laser cutting (or welding) process. For example, when cutting excess signal lines, a partition structure E21 can be formed simultaneously at the second position 252. In this way, compared to the welding structure in the aforementioned embodiment, the partition structure E21 does not require additional process steps, thus simplifying the fabrication process.

[0228] Figure 21 A schematic plan view of the sealing adhesive and partition structure according to an embodiment of the present disclosure is shown.

[0229] Reference Figure 21 In some specific embodiments, the display substrate further includes a sealing adhesive F disposed on the substrate 200. The orthographic projection of the partition structure E21 on the substrate 200 is located in the side area CB, and the orthographic projection of the sealing adhesive F on the substrate 200 covers the orthographic projection of the partition structure E21 on the substrate 200. This ensures that the partition structure E21 is covered by the sealing adhesive F, and that the partition structure E21 is not exposed due to fluctuations in the sealing adhesive F coating process. In this way, static electricity introduced by the start signal line STV exposed by the sealing adhesive F can be blocked, thereby better improving the problem of static electricity accumulation at the connection between the start signal line STV and the start signal lead STVY.

[0230] For example, the sealing adhesive F includes two first portions extending along a first direction X, two second portions extending along a second direction Y, and four corner portions located between the first and second portions. The two first portions, the two second portions, and the four corner portions can form a closed structure that surrounds the outer periphery of the display area AA. The two first portions are located in the bonding area DP and the bonding pair area DPO, respectively, and the two second portions are located in the side area CB. Optionally, in the second direction Y, the distance between the second portions and the bonding pair area DPO can be set to 2800 μm to 3700 μm, the distance between the third welding structure R1 and the fourth welding structure R2 and the bonding pair area DPO can be set to 5400 μm, and the distance between the partition structure E21 and the bonding pair area DPO can be set to 3700 to 5400 μm.

[0231] In some specific embodiments, the display substrate further includes a plurality of invalid shift registers DGOA, which are located on the side of the gate drive circuit 210 near the bonding pair region DPO in the second direction Y. The isolation structure E21, the third fusion structure R1, and the fourth fusion structure R2 are located between two adjacent invalid shift registers DGOA in the second direction Y.

[0232] For example, refer to Figure 20 Above the first-stage shift register unit GOA, two more shift register units are disposed. The relevant signal lines of these shift register units are cut off. Therefore, when the display substrate is working, these shift register units do not output scan signals to the display area AA. Therefore, in the embodiments of this disclosure, these shift register units are referred to as invalid shift register units DGOA. In the embodiments of this disclosure, the isolation structure E21, the third fusion structure R1, and the fourth fusion structure R2 are disposed between the two invalid shift register units DGOA, thereby ensuring that the first-stage shift register unit GOA can be electrically connected to the corresponding signal lines, and also ensuring that the isolation structure E21, the third fusion structure R1, and the fourth fusion structure R2 do not affect the existing structure.

[0233] It should be noted that the above description takes the start signal line STV, start signal lead STVY, and anti-static structure E located on one side of the display area AA as an example. In some embodiments, the start signal line STV, start signal lead STVY, and anti-static structure E can be provided on both opposite sides of the display area AA. The start signal line STV, start signal lead STVY, and anti-static structure E on opposite sides of the display area AA can be roughly the same, so the embodiments disclosed herein will not be described in detail.

[0234] By using the antistatic structure E at the second position 252, the antistatic effect can be improved from 14-15KV before the improvement (i.e., without any antistatic structure E in the embodiments of this disclosure) to 19-25KV.

[0235] In some specific embodiments, an antistatic structure E can be provided at both the first position 251 and the second position 252. In this embodiment, the antistatic effect can be improved from 14-15KV before improvement (i.e., without any antistatic structure E in the embodiments of this disclosure) to 23-29KV.

[0236] Figure 22 A second plan view of a display motherboard according to an embodiment of the present disclosure is shown schematically.

[0237] Reference Figure 22At least some embodiments of this disclosure also provide a display motherboard, which includes a first substrate region 300 and a second substrate region 400, wherein the first substrate region 300 is used to prepare the above-described display substrate.

[0238] The first substrate region 300 and the second substrate region 400 have different dimensions in a third direction; for example, the third direction is the same as the first direction X described above. The second substrate region 400 includes a first sub-region 410 and a second sub-region 420 that at least partially surrounds the first sub-region 410. The first sub-region 410 includes a fourth conductive layer 510, and the first substrate region 300 includes a fifth conductive layer 520. The fourth conductive layer 510 and the fifth conductive layer 520 are co-layered and made of the same material. The pattern of the fourth conductive layer 510 is the same as the pattern of the portion of the fifth conductive layer 520 located in the first sub-region 410.

[0239] In embodiments of this disclosure, the first substrate region 300 and the second substrate region 400 have different dimensions in a third direction; therefore, these two regions can be used to fabricate display substrates of different sizes. Optionally, the first substrate region 300 and the second substrate region 400 have the same dimensions in a fourth direction, and the third and fourth directions intersect. Exemplarily, the third line can refer to the horizontal direction in the figure, and the fourth direction can refer to the vertical direction in the figure; that is, the third and fourth directions are perpendicular to each other.

[0240] The fourth conductive layer 510 and the fifth conductive layer 520 can be fabricated based on the same mask pattern. However, the fifth conductive layer 520 is fabricated based on the complete mask pattern, while the fourth conductive layer 510 is fabricated based on a pattern obtained by partially obscuring the mask pattern. In this way, the same mask pattern can be reused to expose the first substrate region 300 and the second substrate region 400. That is, two display substrates of different sizes can be fabricated using a single mask pattern, thereby saving on the development cost of the mask.

[0241] At least some embodiments of this disclosure also provide a display panel, which includes the display substrate as described above, having a display area and a bonding area, a bonding pair area and a side area, and related structures therein. For example, the display panel may be a liquid crystal display panel.

[0242] At least some embodiments of this disclosure also provide a display device, which may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0243] It should be understood that the display device according to the embodiments of this disclosure has all the features and advantages of the above-described display substrate and display panel PAN, which can be referred to in detail above and will not be repeated here.

Claims

1. A display substrate, wherein, include: The system comprises a display area, a binding area, a binding pair area, a side area, a first corner area, and a second corner area. The side area and the display area are arranged along a first direction, and the binding pair area, the display area, and the binding area are arranged sequentially along a second direction. The first direction and the second direction intersect. The first corner area is located between the side area and the binding pair area and at least partially surrounds the first corner of the display area. The second corner area is located between the side area and the binding area and at least partially surrounds the second corner of the display area. Substrate; A gate driving circuit disposed on the substrate and located in the side region, the gate driving circuit including cascaded multi-stage shift register units; Multiple first signal lines disposed on the substrate and located in the side area, the first corner area and the second corner area; The plurality of first signal lines are located on the side of the gate driving circuit away from the display area; The plurality of first signal lines include a start signal line and a start signal lead. The start signal lead is located on the side of the start signal line closer to the gate drive circuit. Both the start signal line and the start signal lead extend along the second direction and are electrically connected in the second corner area by a first connecting line. An anti-static structure is provided on the plurality of first signal lines. The anti-static structure is located on at least one of a first position and a second position. The first position includes the connection point of the start signal line, the start signal lead and the first connecting line. The second position includes the portion of the plurality of first signal lines located on the side of the first-level shift register unit near the binding pair area.

2. The display substrate according to claim 1, wherein, The antistatic structure located at the first position includes: A first fusion structure, at the junction of the starting signal line and the first connecting line, fuses the starting signal line and the first connecting line together; and / or The second fusion structure, at the connection point of the starting signal lead and the first connecting line, fuses the starting signal lead and the first connecting line together.

3. The display substrate according to claim 2, wherein, The display substrate includes a first conductive layer, a second conductive layer located on the side of the first conductive layer opposite to the substrate, and a third conductive layer located on the side of the second conductive layer opposite to the second conductive layer. The display substrate further includes a first transition structure located in the third conductive layer, the start signal line located in the first conductive layer, and the first connection line located in the second conductive layer; The starting signal line includes a first connecting portion and a signal line body. The orthographic projection of the first connecting portion on the substrate overlaps at least partially with the orthographic projection of the first adapter structure on the substrate. In the overlapping area, the first connecting portion is electrically connected to the first adapter structure through at least one first via. The orthographic projection of the first connecting line on the substrate at least partially overlaps with the orthographic projection of the first adapter structure on the substrate, and in the overlapping area, the first connecting line is electrically connected to the first adapter structure through at least one second via. The orthographic projection of the first fusion structure on the substrate overlaps with the orthographic projection of the first connection portion on the substrate, the orthographic projection of the signal line body on the substrate, and the orthographic projection of the first connection line on the substrate. In the overlapping area, the first fusion structure fuses the first connection portion, the signal line body, and the first connection line together.

4. The display substrate according to claim 3, wherein, The first connecting line includes a second connecting portion and a connecting line body. The orthographic projection of the second connecting portion on the substrate at least partially overlaps with the orthographic projection of the first adapter structure on the substrate. In the overlapping area, the second connecting portion is electrically connected to the first adapter structure through a second via. The first fusion structure includes: A first fusion joint, wherein the orthographic projection of the first fusion joint on the substrate overlaps with the orthographic projections of the first connecting portion and the second connecting portion on the substrate, and in the overlapping area, the first fusion joint fuses the first connecting portion and the second connecting portion together; and / or The second fusion section has its orthographic projection on the substrate overlapping with the orthographic projections of the signal line body and the connection line body on the substrate. In the overlapping area, the second fusion section fuses the signal line body and the connection line body together.

5. The display substrate according to claim 4, wherein, The orthographic projections of the first fusion portion and the second fusion portion on the substrate are located on the same side of the orthographic projection of the second connection portion on the substrate, and the orthographic projections of the first fusion portion and the second fusion portion on the substrate are spaced apart.

6. The display substrate according to claim 3, wherein, The display substrate further includes a second transition structure located in the third conductive layer, and the start signal lead is located in the first conductive layer; The start signal lead includes a third connection portion and a lead body. The orthographic projection of the third connection portion on the substrate overlaps at least partially with the orthographic projection of the second adapter structure on the substrate. In the overlapping area, the third connection portion and the second adapter structure are electrically connected through at least one third via. The orthographic projection of the first connecting line on the substrate and the orthographic projection of the second adapter structure on the substrate at least partially overlap, and in the overlapping area, the first connecting line and the second adapter structure are electrically connected through at least one fourth via; the first connecting line includes a second connecting portion and a connecting line body; The orthographic projection of the second fusion structure on the substrate overlaps with the orthographic projection of the second connection portion on the substrate, the orthographic projection of the lead body on the substrate, and the orthographic projection of the first connection line on the substrate. In the overlapping area, the second fusion structure fuses the second connection portion, the lead body, and the first connection line together.

7. The display substrate according to claim 6, wherein, The first connecting line further includes a fourth connecting portion and a connecting line body. The orthographic projection of the fourth connecting portion on the substrate at least partially overlaps with the orthographic projection of the second transition structure on the substrate. Furthermore, in the overlapping area, the fourth connecting portion is electrically connected to the second transition structure. The second fusion structure includes: The third fusion joint has its orthographic projection on the substrate overlapping with the orthographic projections of the third connecting part and the fourth connecting part on the substrate, and in the overlapping area, the third fusion joint fuses the third connecting part and the fourth connecting part together; and / or The fourth fusion section has its orthographic projection on the substrate overlapping with the orthographic projections of the lead body and the connecting wire body on the substrate. In the overlapping area, the fourth fusion section fuses the lead body and the connecting wire body together.

8. The display substrate according to claim 7, wherein, The orthographic projections of the third fusion portion and the fourth fusion portion on the substrate are located on different sides of the orthographic projection of the third connection portion on the substrate, and the orthographic projections of the third fusion portion and the fourth fusion portion on the substrate are spaced apart.

9. The display substrate according to claim 2, wherein, The materials of the first fusion structure and the second fusion structure include solid fusion materials. The first fusion structure fuses the start signal line and the first connecting line together through at least one first fusion hole. The second fusion structure fuses the start signal lead and the first connecting line together through at least one second fusion hole. The diameter of at least one first fusion hole and at least one second fusion hole is less than or equal to the line width of the first connecting line.

10. The display substrate according to claim 9, wherein, The orthographic projections of at least one of the first weld holes and at least one of the second weld holes on the substrate at least partially overlap with the orthographic projection of the first connecting line on the substrate.

11. The display substrate according to claim 2, wherein, The materials of the first welding structure and the second welding structure include solid welding materials or liquid welding materials. The first welding structure welds the start signal line and the first connecting line together through a third welding hole. The second welding structure welds the start signal lead and the first connecting line together through a fourth welding hole. The diameter of the third welding hole and the fourth welding hole is larger than the line width of the first connecting line.

12. The display substrate according to claim 11, wherein, The orthographic projections of the third and fourth weld holes on the substrate are spaced apart from the orthographic projection of the first connecting line on the substrate.

13. The display substrate according to claim 11, wherein, At least one of the first fusion structure and the second fusion structure is in contact with the surface of the first connecting line on the side opposite to the substrate.

14. The display substrate according to claim 1, wherein, The display substrate further includes: Multiple third connection lines and at least one fourth connection line are disposed on the substrate and located in the side area; Wherein, the plurality of third connection lines extend along the second direction, the at least one fourth connection line extends along the first direction, and the plurality of third connection lines are located on the side of the gate drive circuit away from the start signal lead. At least one level of shift register unit includes a first input terminal. The first input terminals of the first N levels of shift register units are electrically connected to the plurality of third connection lines. The first input terminals of different levels of shift register units are electrically connected to different third connection lines. The start signal line is electrically connected to the plurality of third connection lines through the at least one fourth connection line, and N is a positive integer.

15. The display substrate according to claim 14, wherein, The antistatic structure located at the second position includes: a partition structure, wherein on the plurality of first signal lines, the portion of the partition structure located on the side of the bonding pair area and the portion of the partition structure located on the side of the bonding pair area are separated by the partition structure; The starting signal lead is fused to at least one of the fourth connecting lines through a third fusion structure, and at least one of the fourth connecting lines is fused to multiple of the third connecting lines through a fourth fusion structure; The partition structure, the third fusion structure, and the fourth fusion structure are located within a preset range.

16. The display substrate according to claim 15, wherein, The display substrate further includes: The sealing adhesive is disposed on the substrate, and the orthographic projection of the partition structure on the substrate is located in the side area, and the orthographic projection of the sealing adhesive on the substrate covers the orthographic projection of the partition structure on the substrate.

17. The display substrate according to claim 15, wherein, The display substrate further includes a plurality of invalid shift register units, wherein, in the second direction, the plurality of invalid shift register units are located on the side of the gate drive circuit closer to the bonding pair region; The partition structure, the third fusion structure, and the fourth fusion structure are located between two adjacent invalid shift register units in the second direction.

18. A display motherboard, the display motherboard comprising a first substrate region and a second substrate region, the first substrate region being used to fabricate a display substrate as described in any one of claims 1 to 17; The first substrate region and the second substrate region have different dimensions in a third direction, and the second substrate region includes a first sub-region and a second sub-region that at least partially surrounds the first sub-region. The first substrate region includes a fourth conductive layer, and the second substrate region includes a fifth conductive layer. The fourth conductive layer and the fifth conductive layer are in the same layer and made of the same material. in, The pattern of the fourth conductive layer is the same as the pattern of the portion of the fifth conductive layer located in the first sub-region.

19. A display panel, wherein, Includes the display substrate as described in any one of claims 1 to 17.

20. A display device, wherein, Includes the display panel as described in claim 19.

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