Method for manufacturing display panel, display panel and display device

Abstract

The application belongs to the technical field of display, and particularly relates to a preparation method of a display panel, the display panel and a display device. The method comprises the following steps: providing an array substrate, and coating a first alignment film on the array substrate; coating a layer of photoinitiator on the first alignment film, and at least part of the photoinitiator is located in the via hole; performing deactivation treatment on the photoinitiator located outside the via hole; performing alignment treatment on the first alignment film; providing a liquid crystal layer and a color film substrate; and performing cell processing on the color film substrate, the array substrate and the liquid crystal layer. The liquid crystal layer comprises liquid crystal molecules and a reaction piece. The reaction piece can generate a second alignment film with the photoinitiator in the via hole under the action of light. The second alignment film can align the liquid crystal molecules in the via hole. The application can realize the alignment of the liquid crystal molecules in the via hole, thereby reducing the problem of trace mura when pressing.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to a method for preparing a display panel, the display panel itself, and a display device. Background Technology

[0002] With the development of display technology, liquid crystal display (LCD) panels have become increasingly popular among consumers due to their low cost and mature technology.

[0003] Liquid crystal display panels typically use a rubbing alignment process to define the initial orientation of liquid crystal molecules. Because the vias are relatively deep, the alignment film within the vias is not easily rubbed by the rubbing device during the subsequent alignment process. This results in the alignment film within the vias having no binding force on the liquid crystal molecules, causing the liquid crystal molecules to flow out when the LCD panel is pressed, resulting in scratches and trace mura. Summary of the Invention

[0004] The purpose of this application is to provide a method for manufacturing a display panel, a display panel, and a display device, which can achieve the alignment of liquid crystal molecules within the vias, thereby reducing the problem of trace mura when pressed.

[0005] The first aspect of this application provides a method for manufacturing a display panel, comprising the following steps:

[0006] An array substrate is provided, and a first alignment film is coated on the array substrate; the array substrate includes a substrate and a transistor, a first insulating layer and a pixel electrode disposed on the substrate, the transistor includes a first electrode and a second electrode disposed at intervals, the pixel electrode is disposed on the side of the first insulating layer away from the substrate, the first insulating layer is provided with a via, the via exposes a portion of the first electrode, the pixel electrode is connected to the first electrode through the via, and the first alignment film covers the pixel electrode;

[0007] A photoinitiator is coated on the first alignment film, with at least a portion of the photoinitiator located within the vias;

[0008] The photoinitiator located outside the via is deactivated.

[0009] The first alignment film is subjected to alignment treatment;

[0010] A liquid crystal layer and a color filter substrate are provided. The color filter substrate, the array substrate, and the liquid crystal layer are assembled into a cell. The liquid crystal layer is sealed between the color filter substrate and the array substrate. The liquid crystal layer includes liquid crystal molecules and reactive elements. The liquid crystal molecules located outside the via can be aligned under the action of a first alignment film. The reactive elements can generate a second alignment film with a photoinitiator in the via under illumination. The second alignment film can align the liquid crystal molecules in the via.

[0011] In one exemplary embodiment of this application, a method for preparing a photoinitiator located outside the via by deactivation treatment includes:

[0012] The substrate is subjected to light irradiation on the side away from the pixel electrode.

[0013] In one exemplary embodiment of this application, before performing alignment treatment on the first alignment film, the preparation method further includes:

[0014] The array substrate is heated to sublimate the deactivated photoinitiator.

[0015] In one exemplary embodiment of this application, the method for preparing the array substrate by heating includes:

[0016] The array substrate is then baked.

[0017] In one exemplary embodiment of this application, a method for preparing a second alignment film by which the reactant reacts with a photoinitiator within the via under illumination includes:

[0018] The substrate is treated with ultraviolet light on the side away from the pixel electrode to move the reactant toward the via.

[0019] The reactant combines with the photoinitiator to form the second alignment film.

[0020] In one exemplary embodiment of this application, the method for preparing the first alignment film by alignment treatment includes:

[0021] The first alignment film is rubbed and aligned.

[0022] A second aspect of this application provides a display panel prepared using any of the above-described preparation methods, the display panel comprising:

[0023] An array substrate includes a substrate and a transistor, a first insulating layer, and a pixel electrode disposed on the substrate. The transistor includes a gate, a semiconductor layer, a first electrode, and a second electrode. The semiconductor layer is disposed on the side of the gate away from the substrate. A gate insulating layer is disposed between the gate and the semiconductor layer. The first electrode and the second electrode are respectively connected to the two ends of the semiconductor layer. A via is provided on the first insulating layer, and a portion of the first electrode is exposed through the via. The pixel electrode is connected to the first electrode through the via. A photoinitiator is disposed in the via.

[0024] A first alignment film is disposed on the side of the first insulating layer away from the substrate and covers the pixel electrode;

[0025] The reaction element is disposed on the side of the first alignment film away from the substrate, and the reaction element is disposed within the via.

[0026] Color filter substrate; and

[0027] A liquid crystal layer is disposed between the array substrate and the color filter substrate. The liquid crystal layer includes liquid crystal molecules and a reactive element. The reactive element can generate a second alignment film with the photoinitiator under illumination. The second alignment film can align the liquid crystal molecules inside the via and the liquid crystal molecules outside the via can be aligned under the action of the first alignment film.

[0028] In another exemplary embodiment of this application, the pixel electrode covers the inner wall of the via.

[0029] In another exemplary embodiment of this application, the orthogonal projection of the photoinitiator on the substrate is located within the orthogonal projection of the first electrode on the substrate, and the orthogonal projection of the photoinitiator on the substrate is located within the orthogonal projection of the gate on the substrate.

[0030] A third aspect of this application provides a display device, the display device including a backlight module and a display panel as described in any of the above claims, the display panel being disposed on the light-emitting side of the backlight module.

[0031] The method for manufacturing the display panel, the display panel, and the display device described in this application have at least the following beneficial effects:

[0032] This application proposes a method to generate a second alignment film by using the reactants in the liquid crystal layer and the photoinitiator in the via under illumination. The second alignment film is used to align the liquid crystal molecules in the via, thereby forming an alignment force on the disordered liquid crystal in the via. When subjected to external pressure, the liquid crystal in the via will not move to the display area, thus preventing the liquid crystal in the display area from becoming disordered and reducing or avoiding the problem of trace mura.

[0033] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0036] Figure 1 A schematic flowchart of the manufacturing method of the display panel provided in Embodiment 1 of this application is shown;

[0037] Figure 2 This paper shows a schematic diagram of the structure of the reaction device combined with the photoinitiator provided in Embodiment 1, Embodiment 2 or Embodiment 3 of this application;

[0038] Figure 3 A schematic diagram of the fabrication method of the array substrate provided in Embodiment 1 of this application is shown;

[0039] Figure 4 This paper shows a schematic diagram of the array substrate provided in Embodiment 1, Embodiment 2, or Embodiment 3 of this application;

[0040] Figure 5 This illustration shows a schematic diagram of the structure of the first alignment film fabricated on the array substrate according to Embodiment 1, Embodiment 2 or Embodiment 3 of this application;

[0041] Figure 6 This illustration shows a schematic diagram of a structure provided in Embodiment 1, Embodiment 2 or Embodiment 3 of this application, showing a layer of photoinitiator coated on a first alignment film;

[0042] Figure 7 This paper shows a schematic flowchart of a method for removing photoinitiator from the outside of a via according to Embodiment 1 of this application;

[0043] Figure 8 This application illustrates the use of ultraviolet light to treat photoinitiators according to Embodiment 1, Embodiment 2, or Embodiment 3.

[0044] Figure 9 This illustration shows a schematic diagram of a structure in which a photoinitiator is provided within a via according to Embodiment 1, Embodiment 2, or Embodiment 3 of this application;

[0045] Figure 10 This illustrates a schematic diagram of the structure for triboelectric alignment of the first alignment film provided in Embodiment 1, Embodiment 2, or Embodiment 3 of this application;

[0046] Figure 11 This illustration shows a schematic diagram of the reaction element provided in Embodiment 1, Embodiment 2, or Embodiment 3 of this application without being combined with a photoinitiator;

[0047] Figure 12 A schematic diagram of the process of combining a reactive element with a photoinitiator under illumination, as provided in Embodiment 1 of this application, is shown.

[0048] Figure 13 This illustration shows a schematic diagram of the structure of the reaction element combined with the photoinitiator under light irradiation, provided in Embodiment 1, Embodiment 2, or Embodiment 3 of this application.

[0049] Figure 14 This paper shows a schematic diagram of the structure of the display panel provided in Embodiment 3 of this application, which is located on the light-emitting side of the backlight module.

[0050] Explanation of reference numerals in the attached figures:

[0051] 10. Display device; 100. Display panel; 110. Array substrate; 111. Substrate; 112. Transistor; 1120. Gate; 1121. Semiconductor layer; 1122. First electrode; 1123. Second electrode; 113. First insulating layer; 114. Pixel electrode; 115. Gate insulating layer; 120. Color filter substrate; 121. Black matrix; 122. Substrate; 123. Color resist layer; 1230. Color resist unit; 130. Liquid crystal layer; 131. Liquid crystal molecule; 132. Reactor; 140. First alignment film; 150. Photoinitiator; 160. Via; 170. Support pillar; 200. Backlight module. Detailed Implementation

[0052] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0053] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0054] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0055] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0056] Example 1

[0057] Embodiment 1 of this application provides a method for manufacturing a display panel 100. This display panel 100 can be a liquid crystal display (LCD) panel, which includes an array substrate 110, a color filter substrate 120, and a liquid crystal layer 130 located between the array substrate 110 and the color filter substrate 120.

[0058] Please see Figure 1 and Figure 2 As shown, the manufacturing method of this display panel 100 includes the following steps:

[0059] Step S100: Provide an array substrate 110 and coat a first alignment film 140 on the array substrate 110;

[0060] Step S200: A photoinitiator 150 is coated on the first alignment film 140, and at least a portion of the photoinitiator 150 is located within the via 160;

[0061] Step S300: Deactivate the photoinitiator 150 located outside the via 160;

[0062] Step S400: The first alignment film 140 is subjected to alignment treatment;

[0063] In step S500, a liquid crystal layer 130 and a color filter substrate 120 are provided. The color filter substrate 120, the array substrate 110, and the liquid crystal layer 130 are assembled into a cell. The liquid crystal layer 130 is sealed between the color filter substrate 120 and the array substrate 110. The liquid crystal layer 130 includes liquid crystal molecules 131 and reactive elements 132. The liquid crystal molecules 131 located outside the via 160 can be aligned under the action of the first alignment film 140. The reactive elements 132 can generate a second alignment film with the photoinitiator 150 in the via 160 under the action of light. The second alignment film can align the liquid crystal molecules 131 in the via 160.

[0064] In step S100, please refer to Figure 2 As shown, the array substrate 110 includes a substrate 111 and transistors 112, a first insulating layer 113 and pixel electrodes 114 disposed on the substrate 111. The transistor 112 includes a gate 1120, a semiconductor layer 1121, a first electrode 1122, and a second electrode 1123. The gate 1120 is disposed on the side of the semiconductor layer 1121 close to the substrate 111, and a gate insulating layer 115 is provided between the gate 1120 and the semiconductor layer 1121. The first electrode 1122 and the second electrode 1123 are respectively connected to opposite ends of the semiconductor layer 1121, and the first electrode 1122 and the second electrode 1123 are spaced apart from each other. A first insulating layer 113 is disposed on the side of the gate insulating layer 115 away from the substrate 111, and the first insulating layer 113 covers the first electrode 1122, the semiconductor layer 1121, and the second electrode 1123. A via 160 is provided on the first insulating layer 113, and the via 160 exposes a portion of the first electrode 1122. The pixel electrode 114 is electrically connected to the exposed portion of the first electrode 1122 through the via 160.

[0065] Please see below. Figure 3 and Figure 4 As shown, the fabrication method of this array substrate 110 includes the following steps:

[0066] In step S110, a first metal layer is formed on the substrate 111, and the first metal layer is patterned to form a gate 1120 and a scan line, wherein the scan line is connected to the gate 1120.

[0067] This step S110 includes:

[0068] A first metal layer is deposited on a substrate 111 using physical vapor deposition (PVD).

[0069] The first metal layer is patterned using the first photomask process to obtain the gate 1120 and the scan lines.

[0070] The substrate 111 can be made of glass, quartz or other suitable materials; the material of the first metal layer includes molybdenum (Mo), copper (Cu), etc.

[0071] Furthermore, this first photomask process includes photoresist coating, exposure, development, wet etching, and photoresist stripping. Multiple gates 1120 are formed on the substrate 111 using this first photomask process, with adjacent gates 1120 spaced apart from each other.

[0072] In step S120, a gate insulating layer 115 and a semiconductor layer 1121 are sequentially formed on the substrate 111, with the gate insulating layer 115 covering the gate 1120 and the scan line.

[0073] The gate insulating layer 115 is made of one or more of silicon oxide (SiOx) and silicon nitride (SiNx); the semiconductor layer 1121 is made of one or more of amorphous silicon, polycrystalline silicon, and metal oxide.

[0074] In addition, both the gate insulating layer 115 and the semiconductor layer 1121 are deposited using chemical vapor deposition (CVD).

[0075] In step S130, a second metal layer is deposited on the gate insulating layer 115 and the semiconductor layer 1121, and the second metal layer is patterned to form a first electrode 1122, a second electrode 1123 and a data line that are spaced apart from each other.

[0076] It should be noted that the method used to deposit the second metal layer is physical vapor deposition (PVD).

[0077] In addition, the patterning process for the second metal layer includes photoresist coating, exposure, development, wet etching, and photoresist stripping.

[0078] Materials for the second metal layer include molybdenum (Mo) and copper (Cu).

[0079] It is worth mentioning that the first electrode 1122 can be either the source or the drain, and the second electrode 1123 can be either the source or the drain.

[0080] For example, the first electrode 1122 is the drain electrode and the second electrode 1123 is the source electrode. The two electrodes are spaced apart on the gate insulating layer 115. One end of the first electrode 1122 and one end of the second electrode 1123 are respectively connected to the opposite sides of the semiconductor layer 1121.

[0081] In step S140, a first insulating layer 113 is formed on the gate insulating layer 115 and the semiconductor layer 1121, and the first insulating layer 113 is patterned to obtain a via 160.

[0082] The first insulating layer 113 covers the first electrode 1122, the second electrode 1123, and the data line. The via 160 exposes at least a portion of the first electrode 1122 so that the subsequent pixel electrode 114 can be connected to the first electrode 1122 through the via 160.

[0083] In step S150, a pixel electrode 114 is formed on the first insulating layer 113, and the pixel electrode 114 is connected to the first electrode 1122 through a via 160.

[0084] The pixel electrode 114 can be made of indium tin oxide (ITO) or indium tin zinc oxide (ITZO). The pixel electrode 114 can be in block or strip shape.

[0085] Furthermore, to prevent the photoinitiator 150 and the first alignment film 140, as described below, from damaging the first electrode 1122, the pixel electrode 114 completely covers the exposed portion of the first electrode 1122. To ensure protection, the pixel electrode 114 is connected to the inner wall of the via 160, that is, the pixel electrode 114 is attached to the inner wall of the via 160.

[0086] In step S100, see Figure 5 As shown, a first alignment film 140 is coated on the first insulating layer 113.

[0087] The first alignment film 140 is prepared after the pixel electrode 114 is prepared, and it can cover the pixel electrode 114.

[0088] In step S200, see Figure 6 As shown, the photoinitiator 150 is located on the side of the first alignment film 140 away from the substrate 111, so as to facilitate the subsequent formation of the second alignment film in the via 160.

[0089] In this embodiment, the via 160 is filled with a layer of photoinitiator 150, which can cover the pixel electrode 114 within the via 160.

[0090] In step S300, see Figure 7As shown, the photoinitiator 150 located outside the via 160 is deactivated to ensure that the liquid crystal molecules 131 located outside the via 160 are only aligned by the first alignment film 140, and that the photoinitiator 150 located outside the via 160 does not react with the reactant 132 described below to form a second alignment film, thus ensuring the alignment of the liquid crystal molecules 131 outside the via 160. The photoinitiator 150 located inside the via 160 is not deactivated, allowing it to form a second alignment film with the reactant 132 described below. This allows the liquid crystal molecules 131 within the via 160 to align under the action of the second alignment film, thus constraining the liquid crystal molecules 131 within the via 160. When the display panel 100 is pressed, the liquid crystal molecules 131 within the via 160 will not move towards the display area, thus preventing the occurrence of trace mura.

[0091] Among them, see Figure 7 As shown, the preparation method for deactivating the photoinitiator 150 located outside the via 160 includes:

[0092] In step S310, light irradiation is performed on the side of the substrate 111 away from the pixel electrode 114.

[0093] like Figure 8 As shown, the back side of the substrate 111 is exposed using ultraviolet light (UV) to deactivate the photoinitiator 150 outside the via 160, preventing it from reacting with the reactant 132 described below to form a second alignment film.

[0094] Because the ultraviolet light irradiates from the side of the substrate 111 away from the pixel electrode 114, and because the metal traces are opaque, and the orthographic projection of the photoinitiator 150 in the via 160 onto the substrate 111 lies within the orthographic projection of the first electrode 1122 onto the substrate 111, the first electrode 1122 will block the photoinitiator 150 in the via 160 when the ultraviolet light irradiates from the side of the substrate 111 away from the pixel electrode 114. This prevents the photoinitiator 150 from being deactivated by the ultraviolet light, ensuring that the photoinitiator 150 in the via 160 can form a second alignment film with the reactant 132 in the liquid crystal layer 130, aligning the liquid crystal molecules 131 in the via 160. When subjected to external pressure, the liquid crystal molecules 131 in the via 160 will not move into the display area, causing disordered liquid crystal arrangement in the display area, thus reducing or avoiding the problem of tracemura.

[0095] In step S300, after deactivating the photoinitiator 150 outside the via 160, the process further includes:

[0096] Step S320: The array substrate 110 is heated to sublimate the inactive photoinitiator 150, thereby removing the photoinitiator 150 from the side of the first alignment film 140 away from the substrate 111. This ensures the alignment of the first alignment film 140 with the liquid crystal molecules 131 outside the via 160. See [link to previous step]. Figure 9 As shown.

[0097] It is understood that heating the array substrate 110 may include heating, baking or other heating methods.

[0098] In addition, the photoinitiator 150 on the side of the first alignment film 140 away from the substrate 111 is removed to prevent the photoinitiator 150 on the outside of the via 160 from being incompletely deactivated and reacting with the reactant 132 in the liquid crystal layer 130 to form a second alignment film, which would affect the alignment of the liquid crystal molecules 131 on the outside of the via 160.

[0099] In this embodiment, the array substrate 110 is baked to sublimate the deactivated photoinitiator 150, thereby completely removing the photoinitiator 150 from the first alignment film 140 away from the substrate 111.

[0100] It is worth mentioning that, due to the small size of the via 160, the first alignment film 140 inside the via 160 cannot be subjected to the friction alignment effect during the traditional friction alignment process. As a result, the first alignment film 140 of the via 160 cannot be aligned, which leads to the disordered arrangement of the liquid crystal molecules 131 inside the via 160. When the display panel 100 is pressed, the liquid crystal molecules 131 inside the via 160 will move towards the display area, resulting in the problem of trace mura.

[0101] In step S400, as Figure 10 As shown, when the first alignment film 140 is rubbed aligned, the photoinitiator 150 and the first alignment film 140 in the via 160 will not be rubbed aligned, and thus will not affect the subsequent formation of the second alignment film by the photoinitiator 150 and the reactant 132.

[0102] After the first alignment film 140 is rubbed aligned, the first alignment film 140 can provide alignment force for the liquid crystal molecules 131 outside the via 160.

[0103] In step S500, as Figure 11 As shown, the reactant 132 in the liquid crystal layer 130 can be made of hexyl methacrylate (HMA monomers) ions, which are mixed with liquid crystal molecules 131 between the array substrate 110 and the color filter substrate 120.

[0104] When the second alignment film is generated, the reactant 132 in the liquid crystal layer 130 can generate the second alignment film with the photoinitiator 150 in the via 160 under the action of light. This second alignment film can align the liquid crystal molecules 131 in the via 160.

[0105] Please see Figure 12 and Figure 13 As shown, the preparation method for generating the second alignment film includes:

[0106] In step S510, the substrate 111 is irradiated with ultraviolet light on the side away from the pixel electrode 114 so that the reactant 132 moves toward the via 160.

[0107] In step S520, the reactant 132 combines with the photoinitiator 150 to form a second alignment film.

[0108] In step S510, not only can the light irradiation process be performed on the side of the substrate 111 away from the pixel electrode 114, but also the ultraviolet exposure process can be performed on the side of the color filter substrate 120 away from the array substrate 110. The black matrix 121 on the color filter substrate 120 is used to block the photoinitiator 150 in the via 160, so as to prevent the photoinitiator 150 in the via 160 from losing its activity, ensuring that a second alignment film is formed with the reactant 132, thereby ensuring the alignment effect of the liquid crystal molecules 131 in the via 160.

[0109] During ultraviolet exposure, the reactant 132 in the liquid crystal layer 130 gradually moves into the via 160 and combines with the photoinitiator 150 in the via 160 to form a second alignment film that binds the liquid crystal molecules 131 in the via 160.

[0110] Understandably, since the photoinitiator 150 on the outside of the via 160 has lost its activity due to exposure to ultraviolet (UV) light, the reactant 132 can only combine with the photoinitiator 150 inside the via 160.

[0111] This application utilizes the photoinitiator 150 in the via 160 to combine with the reactant 132 in the liquid crystal layer 130 to generate a second alignment film that binds the liquid crystal molecules 131. This binds the liquid crystal molecules 131 in the via 160, preventing them from moving into the display area when pressed by external force, thus avoiding or reducing the occurrence of trace mura.

[0112] Example 2

[0113] Embodiment 2 of this application provides a display panel 100 prepared using the preparation method in Embodiment 1. This display panel 100 can be a liquid crystal display (LCD) panel 100.

[0114] like Figure 2 As shown, this display panel 100 includes a color filter substrate 120, a liquid crystal layer 130, a support pillar 170, an array substrate 110, and a first alignment film 140 disposed on the array substrate 110. The array substrate 110 and the color filter substrate 120 are arranged in a cell. The liquid crystal layer 130 and the support pillar 170 are disposed between the array substrate 110 and the color filter substrate 120. The support pillar 170 is disposed on the side of the color filter substrate 120 and extends towards the side of the array substrate 110. The array substrate 110 includes a substrate 111 and a gate 1120, a gate insulating layer 115, a semiconductor layer 1121, a first electrode 1122, a second electrode 1123, a first insulating layer 113, and a pixel electrode 114 disposed on the substrate 111. The gate 1120 is disposed on the substrate 111, and the gate insulating layer 115 is disposed between the gate 1120 and the semiconductor layer 1121. The first electrode 1122 and the second electrode 1123 overlap at both ends of the semiconductor layer 1121. The first insulating layer 113 is disposed on the side of the gate insulating layer 115 away from the substrate 111, and the first insulating layer 113 covers the first electrode 1122, the second electrode 1123, and the semiconductor layer 1121.

[0115] It should be noted that, as Figure 2 As shown, the liquid crystal layer 130 includes liquid crystal molecules 131 and reactive elements 132; this liquid crystal layer 130 contains a plurality of liquid crystal molecules 131 spaced apart and a plurality of reactive elements 132, and the reactive elements 132 may be hexyl methacrylate (HMA monomers).

[0116] In addition, such as Figure 2 As shown, the array substrate 110 is provided with a via 160. The via 160 is provided on the first insulating layer 113. The via 160 exposes a portion of the first electrode 1122 so that the pixel electrode 114 is connected to the first electrode 1122 located in the via 160, thereby enabling the pixel electrode 114 to receive electrical signals and drive the liquid crystal molecules 131 in the liquid crystal layer 130 to deflect.

[0117] Because the first alignment film 140 cannot be rubbed during tribological alignment, the first alignment film 140 inside the via 160 cannot be aligned, thus failing to exert a binding force on the liquid crystal molecules 131 inside the via 160. Therefore, in order to ensure that the liquid crystal molecules 131 inside the via 160 have a binding force, the display panel 100 also includes a photoinitiator 150. The photoinitiator 150 is disposed inside the via 160, covering the pixel electrode 114 inside the via 160, and the orthogonal projection of the photoinitiator 150 on the substrate 111 is located within the orthogonal projection of the gate 1120 on the substrate 111, so that the photoinitiator 150 inside the via 160 will not lose its activity under subsequent ultraviolet irradiation.

[0118] It is understandable that, such as Figure 2 As shown, a black matrix 121 is provided on the color filter substrate 120. This black matrix 121 corresponds to the transistor 112 of the array substrate 110, and its orthogonal projection on the substrate 111 covers the orthogonal projection of the transistor 112 on the substrate 111. Therefore, the black matrix 121 on the color filter substrate 120 can also block the photoinitiator 150 in the via 160. Thus, ultraviolet light can be applied from either the array substrate 110 side or the color filter substrate 120 side without causing the photoinitiator 150 to lose its activity. It can react with the reactant 132 to form a second alignment film, which aligns the liquid crystal molecules 131 in the via 160.

[0119] like Figure 2 As shown, the color filter substrate 120 also includes a substrate 122, a color resist layer 123 disposed on the substrate 122, and a common electrode. The color resist layer 123 includes a plurality of color resist units 1230 arranged in an array. The colors of adjacent color resist units 1230 are different, and adjacent color resist units 1230 are provided with the aforementioned black matrix 121 to avoid color cross-contamination. The common electrode is disposed on the side of the color resist layer 123 away from the substrate 122. This common electrode can work together with the pixel electrode 114 on the array substrate 110 side to control the deflection angle of the liquid crystal molecules 131.

[0120] It is worth mentioning that, such as Figure 2 As shown, in order to avoid damage to the first electrode 1122 during the preparation of the first alignment film 140 and the photoinitiator 150, the pixel electrode 114 completely covers the inner wall of the via 160, that is, the inner wall of the via 160 is provided with the pixel electrode 114.

[0121] The photoinitiator 150 within the via 160 covers the first alignment film 140 so that it can combine with the reactant 132 in the liquid crystal layer 130.

[0122] When ultraviolet light is used for exposure, the reactant 132 in the liquid crystal layer 130 moves toward the via 160. The reactant 132 combines with the photoinitiator 150 in the via 160 to form a second alignment film, thereby forming an alignment force on the disordered liquid crystal molecules 131 in the via 160. This prevents the liquid crystal molecules 131 in the via 160 from moving into the display area when the display panel 100 is pressed by an external force, thus avoiding or reducing the occurrence of trace mura.

[0123] Example 3

[0124] This third embodiment provides a display device 10, please refer to... Figure 14 As shown, it includes the display panel 100 described in Embodiment 2, and may also be provided with a backlight module 200, wherein the display panel 100 is located on the light-emitting side of the backlight module 200.

[0125] According to the embodiments of this application, the specific type of the display device 10 is not particularly limited. Any type of display device 10 commonly used in the art can be used, such as liquid crystal displays, mobile devices such as mobile phones and laptops, wearable devices such as watches, VR devices, etc. Those skilled in the art can make appropriate selections according to the specific purpose of the display device, which will not be elaborated here.

[0126] It should be noted that, in addition to the display panel 100, the display device 10 also includes other necessary components and parts. Taking a monitor as an example, it may also include a housing, a main circuit board, a power cord, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device 10, which will not be elaborated here.

[0127] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0128] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A method for manufacturing a display panel, characterized by, The method comprises the following steps: providing an array substrate and coating a first alignment film on the array substrate; the array substrate comprises a substrate, a transistor, a first insulating layer and a pixel electrode, the transistor comprises a first electrode and a second electrode which are spaced apart from each other, the pixel electrode is arranged on the side of the first insulating layer away from the substrate, a via hole is arranged on the first insulating layer, the via hole exposes part of the first electrode, the pixel electrode is connected to the first electrode through the via hole, and the first alignment film covers the pixel electrode; coating a layer of photoinitiator on the first alignment film, at least part of the photoinitiator is located in the via hole; deactivating the photoinitiator located outside the via hole; performing a temperature rising process on the array substrate to sublimate the deactivated photoinitiator; performing an alignment process on the first alignment film; providing a liquid crystal layer and a color filter substrate, performing a cell processing on the color filter substrate, the array substrate and the liquid crystal layer, the liquid crystal layer is sealed between the color filter substrate and the array substrate, the liquid crystal layer comprises liquid crystal molecules and a reaction component, the liquid crystal molecules located outside the via hole can be aligned under the action of the first alignment film, and the reaction component can generate a second alignment film with the photoinitiator in the via hole under the action of light, and the second alignment film can align the liquid crystal molecules in the via hole.

2. The method of manufacturing a display panel according to claim 1, wherein The method for deactivating the photoinitiator located outside the via hole comprises the following steps: performing light treatment on the side of the substrate away from the pixel electrode.

3. The method of manufacturing a display panel according to claim 1, wherein The method for performing a temperature rising process on the array substrate comprises the following steps: performing a baking process on the array substrate.

4. The method of claim 1, wherein the method further comprises: The method for generating a second alignment film with the photoinitiator in the via hole under the action of light by the reaction component comprises the following steps: performing light treatment on the side of the substrate away from the pixel electrode by using ultraviolet rays, so that the reaction component moves towards the via hole; the reaction component combines with the photoinitiator to form the second alignment film.

5. The method of manufacturing a display panel according to claim 1, wherein The method for performing an alignment process on the first alignment film comprises the following steps: performing a rubbing alignment process on the first alignment film.

6. The method of producing a display panel according to any one of claims 1 to 5, wherein The display panel prepared by the display panel preparation method comprises: an array substrate, the array substrate comprises a substrate, a transistor, a first insulating layer and a pixel electrode, the transistor comprises a gate, a semiconductor layer, a first electrode and a second electrode, the semiconductor layer is arranged on the side of the gate away from the substrate, a gate insulating layer is arranged between the gate and the semiconductor layer, the first electrode and the second electrode are respectively overlapped on both ends of the semiconductor layer, a via hole is arranged on the first insulating layer, the via hole exposes part of the first electrode, the pixel electrode is connected to the first electrode through the via hole, and a photoinitiator is arranged in the via hole; a first alignment film, the first alignment film is arranged on the side of the first insulating layer away from the substrate and covers the pixel electrode; a reaction component, the reaction component is arranged on the side of the first alignment film away from the substrate, and the reaction component is arranged in the via hole. A color film substrate; and A liquid crystal layer disposed between the array substrate and the color film substrate, the liquid crystal layer comprising liquid crystal molecules and a reaction member, the reaction member being capable of generating a second alignment film with the photoinitiator under the action of light, the second alignment film being capable of aligning the liquid crystal molecules in the via, and the liquid crystal molecules outside the via being capable of being aligned under the action of the first alignment film.

7. The method of manufacturing a display panel according to claim 6, wherein, The pixel electrode covers the inner wall of the via.

8. The method of manufacturing a display panel according to claim 6, wherein, The orthographic projection of the photoinitiator on the substrate substrate is located within the orthographic projection of the first electrode on the substrate substrate, and the orthographic projection of the photoinitiator on the substrate substrate is located within the orthographic projection of the gate electrode on the substrate substrate.

9. A display device, characterized by comprising: The display device comprises a backlight module and a display panel prepared by the preparation method of any one of claims 1 to 8, and the display panel is disposed on the light-emitting side of the backlight module.

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