Array substrate and manufacturing method thereof, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a manufacturing method of the array substrate, a display panel and a display device. The array substrate comprises a substrate body, a plurality of grid lines, a plurality of data lines and at least one auxiliary line. The substrate is provided with a display area and a peripheral area, and the peripheral area surrounds the display area. At least one of the plurality of grid lines and the plurality of data lines is a target signal line, each target signal line is connected with at least one auxiliary line, the connected auxiliary line and target signal line are in different layers and have the same extension direction, and orthographic projections of the connected auxiliary line and target signal line on the surface of the substrate at least partially coincide; the auxiliary lines and the target signal lines which are connected are connected through a plurality of via holes, and the plurality of via holes are arranged at intervals in the length direction of the target signal lines. According to the embodiment of the invention, poor display caused by the fact that the signal line is too thin and broken can be improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, a display panel and a display device. Background Art

[0002] Liquid crystal display panel is a common display panel, which has the advantages of low manufacturing cost and simple manufacturing process, and occupies a large market share in the field of display technology.

[0003] In the related art, the liquid crystal display panel includes an array substrate and a color filter substrate connected relatively to each other, and a liquid crystal layer located between the array substrate and the color filter substrate. The array substrate includes a base substrate, a plurality of data lines and a plurality of gate lines. The base substrate has a display area and a peripheral area, and the peripheral area surrounds the display area. The plurality of gate lines and the plurality of data lines intersect and define a plurality of pixel areas in the display area.

[0004] As the resolution of liquid crystal display panels increases, the signal lines in the display area of ​​the array substrate become thinner and thinner. Too thin signal lines are prone to breakage during the manufacturing process, resulting in poor display of the liquid crystal display panel. Summary of the invention

[0005] The present disclosure provides an array substrate and a manufacturing method thereof, a display panel and a display device, which can improve the display defects caused by the disconnection of signal lines due to being too thin.

[0006] On the one hand, an array substrate is provided, the array substrate comprising a base substrate, a plurality of gate lines, a plurality of data lines and at least one auxiliary line. The base substrate has a display area and a peripheral area, and the peripheral area surrounds the display area. The plurality of gate lines and the plurality of data lines intersect and define a plurality of pixel areas in the display area. At least one of the plurality of gate lines and the plurality of data lines is a target signal line, each of the target signal lines is connected to at least one auxiliary line, the connected auxiliary lines and the target signal lines are in different layers and extend in the same direction, the connected auxiliary lines and the target signal lines have at least partially overlapped orthographic projections on the surface of the base substrate, the connected auxiliary lines and the target signal lines are connected through a plurality of vias, and the plurality of vias are arranged at intervals along the length direction of the target signal lines.

[0007] Optionally, the array substrate further comprises a gate drive circuit and a plurality of pixel units, each of the pixel units is located in one of the pixel regions, the pixel unit comprises a first thin film transistor and a first electrode, the first electrode is located on a side of the first thin film transistor away from the substrate, and the first electrode is connected to a first electrode of the first thin film transistor. The gate drive circuit is located in the peripheral region, the gate drive circuit is connected to the plurality of gate lines, and the gate drive circuit comprises a plurality of second thin film transistors. The active layer of the second thin film transistor is in a different layer from the active layer of the first thin film transistor, and the gate of the second thin film transistor is in a different layer from the gate of the first thin film transistor. The target signal line is a data line, and the auxiliary line connected to the target signal line comprises at least one of the following: a first auxiliary line, in the same layer as the active layer of the second thin film transistor; a second auxiliary line, in the same layer as the gate of the second thin film transistor; and a third auxiliary line, in the same layer as the first electrode.

[0008] Optionally, the first thin film transistor includes a first active layer, a first gate and a first source and drain electrode stacked in sequence along a direction away from the base substrate; the second thin film transistor includes a second active layer, a second gate and a second source and drain electrode stacked in sequence along a direction away from the base substrate, and in a direction perpendicular to the supporting surface of the base substrate, the second active layer and the second gate are located between the first active layer and the array substrate; the first source and drain electrode and the second source and drain electrode are in the same layer and are located on the side of the second gate away from the array substrate.

[0009] Optionally, the auxiliary line includes at least one of the first auxiliary line and the second auxiliary line; and a via hole between the target signal line and the auxiliary line passes through the first active layer.

[0010] Optionally, the first thin film transistor includes a first source and drain electrode, a first active layer and a first gate electrode stacked in sequence along a direction away from the base substrate; the second thin film transistor includes a second active layer, a second gate electrode and a second source and drain electrode stacked in sequence along a direction away from the base substrate; the first source and drain electrode and the second source and drain electrode are in the same layer.

[0011] Optionally, the first active layer and the first source and drain are in contact with a surface of the same insulating layer; the auxiliary line includes the third auxiliary line, and the third auxiliary line is in contact with the first active layer and the first source in the first source and drain at the same time.

[0012] Optionally, the array substrate further includes a plurality of pixel units, each of the pixel units being located in one of the pixel regions, the pixel unit including a first thin film transistor and a first electrode, the first electrode being located on a side of the first thin film transistor away from the base substrate, the first thin film transistor including a first source and a drain, the first electrode being connected to the first source and a drain; the target signal line is a data line, and the auxiliary line is in the same layer as the first electrode.

[0013] Optionally, a line width of the target signal line is smaller than or equal to a line width of the auxiliary line.

[0014] Optionally, the pixel unit also includes a pixel electrode, and the first electrode is the pixel electrode; or, the pixel unit also includes a first transfer electrode and a pixel electrode, and in a direction perpendicular to the supporting surface of the substrate, the first transfer electrode is located between the first thin film transistor and the pixel electrode, the first transfer electrode connects the first thin film transistor and the pixel electrode, and the first electrode is the pixel electrode or the first transfer electrode.

[0015] Optionally, the array substrate further includes a second switching electrode, which is located between the first switching electrode and the pixel electrode in a direction perpendicular to the bearing surface of the base substrate, and the first switching electrode connects the first switching electrode and the pixel electrode.

[0016] Optionally, the first gate comprises a first sub-gate layer and a second sub-gate layer stacked in sequence. The first sub-gate layer is made of a transparent conductive material, and the second sub-gate layer is made of a metal material.

[0017] Optionally, the first thin film transistor is a metal oxide transistor, and the second thin film transistor is a low temperature polysilicon transistor.

[0018] On the other hand, a method for manufacturing an array substrate is provided, the method comprising: providing a base substrate. Manufacturing a plurality of gate lines, a plurality of data lines and at least one auxiliary line on the base substrate to obtain the array substrate. The base substrate has a display area and a peripheral area, the peripheral area surrounds the display area, the plurality of gate lines and the plurality of data lines intersect and define a plurality of pixel areas in the display area. At least one of the plurality of gate lines and the plurality of data lines is a target signal line, each of the target signal lines is connected to at least one auxiliary line, the connected auxiliary lines and the target signal lines are in different layers and extend in the same direction, the connected auxiliary lines and the target signal lines at least partially overlap in their orthographic projections on the surface of the base substrate, the connected auxiliary lines and the target signal lines are connected through a plurality of vias, and the plurality of vias are arranged at intervals along the length direction of the target signal lines.

[0019] On the other hand, a display panel is provided. The display panel includes a color filter substrate and any one of the aforementioned array substrates facing each other, and a liquid crystal layer located between the array substrate and the color filter substrate.

[0020] On the other hand, a display device is provided. The display device includes a backlight module and the aforementioned display panel. The backlight module provides a light source for the display panel.

[0021] The beneficial effects of the technical solution provided by the present disclosure include at least:

[0022] By making auxiliary lines and connecting the target signal lines to the auxiliary lines, the electrical signals that the target signal lines need to transmit can be transmitted through the auxiliary lines when the target signal lines are broken, thereby improving the display defects caused by the target signal lines. In addition, the target signal lines and the corresponding auxiliary lines are connected through a plurality of vias arranged at intervals along the length direction of the target signal lines, so that as long as the target signal lines and the auxiliary signal lines are not disconnected at the same time between the two vias, the signals can be transmitted normally, and the possibility of the target signal lines and the auxiliary signal lines being disconnected at the same time between the two vias is very small, thus further ensuring the display defects caused by the signal line disconnection. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 is a schematic diagram of a planar structure of an array substrate provided by an embodiment of the present disclosure;

[0025] Figure 2 is a partial enlarged structural schematic diagram of a display area of ​​an array substrate provided by an embodiment of the present disclosure;

[0026] Figure 3 is a schematic diagram of a hierarchical structure of an array substrate provided by an embodiment of the present disclosure;

[0027] Figure 4 is a schematic diagram of a hierarchical structure of another array substrate provided by an embodiment of the present disclosure;

[0028] Figure 5 is a schematic diagram of a hierarchical structure of another array substrate provided by an embodiment of the present disclosure;

[0029] Figure 6is a schematic diagram of a hierarchical structure of another array substrate provided by an embodiment of the present disclosure;

[0030] Figure 7 is a schematic diagram of a hierarchical structure of another array substrate provided by an embodiment of the present disclosure;

[0031] Figure 8 is a schematic diagram of a hierarchical structure of another array substrate provided by an embodiment of the present disclosure;

[0032] Fig. 9 is a schematic diagram of a hierarchical structure of another array substrate provided by an embodiment of the present disclosure;

[0033] Fig.10 is a schematic flow chart of another method for manufacturing an array substrate provided in an embodiment of the present disclosure;

[0034] Figures 11 to 19 is a schematic diagram of a manufacturing process of an array substrate provided by an embodiment of the present disclosure;

[0035] Figure 20 to Figure 26 is a schematic diagram of another manufacturing process of an array substrate provided by an embodiment of the present disclosure;

[0036] Fig. 27 The present disclosure is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment.

[0037] Legend:

[0038] 100, array substrate 200, color filter substrate 300, liquid crystal layer

[0039] 1. Base substrate 2. Signal line 3. Auxiliary line 4. Via hole

[0040] 101. Display area 102. Peripheral area

[0041] 21. Data line 22. Gate line

[0042] 3a, first auxiliary line 3b, second auxiliary line 3c, third auxiliary line

[0043] 41. First via hole 42. Second via hole

[0044] 5. First TFT 51, first source and drain electrode 52, first active layer 53, first gate electrode

[0045] 61, pixel electrode 62, first switching electrode 63, second switching electrode

[0046] 7. second TFT 71, second source and drain electrode 72, second active layer 73, second gate electrode

[0047] 531, first sub-gate layer 532, second sub-gate layer

[0048] 8. Buffer layer 9. Second gate insulating layer 10. First insulating layer

[0049] 11. first gate insulating layer 12. second insulating layer 13. third insulating layer

[0050] 14, first planarization layer 15, second planarization layer 16, dielectric layer 17, common electrode

[0051] 18. Light shielding structure 19. First spacer 20. Second spacer

[0052] 21, second substrate 22, color block 23, black matrix 24, third planarization layer DETAILED DESCRIPTION

[0053] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0054] The terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure, and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one" or "one" do not indicate quantitative restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing in front of "include" or "comprise" cover the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects.

[0055] Figure 1 FIG. 1 is a schematic diagram of a planar structure of an array substrate provided by an embodiment of the present disclosure. Figure 1 As shown, the array substrate 100 includes a base substrate 1, a plurality of data lines 21 and a plurality of gate lines 22. The base substrate 1 has a display area 101 and a peripheral area 102. The display area 101 is used to display images. The peripheral area 102 surrounds the display area and is used to arrange peripheral wiring, etc. The plurality of gate lines 22 and the plurality of data lines 21 intersect and define a plurality of pixel areas in the display area 101.

[0056] As the resolution of liquid crystal display panels increases, the signal lines (i.e., data lines 21 or gate lines 22) in the display area of ​​the array substrate become thinner and thinner. Too thin signal lines are prone to breakage during the manufacturing process, and the signal lines cannot transmit signals normally after being broken, resulting in poor display of the liquid crystal display panel.

[0057] To this end, the embodiment of the present disclosure sets auxiliary lines that are in different layers and extend in the same direction as the signal lines, and connects the auxiliary lines to the signal lines through multiple vias. In this way, the signal in the disconnected signal line can be transmitted through the auxiliary lines, thereby reducing or even eliminating display defects caused by disconnected signal lines.

[0058] Optionally, the signal line provided with the auxiliary line (i.e., the target signal line hereinafter) may be a data line or a gate line, or the signal line provided with the auxiliary line may include a data line and a gate line. Since the data line 21 is usually arranged more densely and has a smaller line width, the possibility of disconnection is greater, therefore, the target signal line will be taken as the data line 21 as an example for explanation below.

[0059] Figure 2 FIG. 1 is a schematic diagram of a partially enlarged structure of a display area of ​​an array substrate provided by an embodiment of the present disclosure. Figure 1 and Figure 2 As shown, the target signal line is a data line 21, each data line 21 is connected to at least one auxiliary line 3, the auxiliary line 3 and the connected target signal line 20 are in different layers and extend in the same direction. The orthographic projections of the auxiliary line 3 and the connected data line 21 on the surface of the substrate 1 at least partially overlap, and the auxiliary line 3 and the connected data line 21 are connected through a plurality of vias 4, and the plurality of vias 4 are arranged at intervals along the length direction of the data line 21.

[0060] In the embodiments of the present disclosure, the same layer means formed by the same patterning process, or in contact with the same surface of the same film layer, or located on the same side of the same film layer, etc. Different layers mean formed by different patterning processes, or in contact with surfaces of different film layers, or located on different sides of the same film layer, etc.

[0061] When the data line 21 is disconnected due to being too thin, the electrical signal that needs to be transmitted in the data line 21 can be transmitted through the auxiliary line 3 connected to the data line 21, thereby improving the poor display caused by the disconnection of the data line 21. The design of the auxiliary line 3 can also increase the cross-sectional area of ​​current transmission and reduce the overall resistance of the data line 21. In addition, the data line 21 and the corresponding auxiliary line are connected through a plurality of vias arranged at intervals along the length direction of the data line 21. In this way, as long as the data line 21 and the auxiliary signal line are not disconnected at the same time between the two vias, the signal can be transmitted normally, and the possibility of the data line 21 and the auxiliary line being disconnected at the same time between the two vias is very small, thus further ensuring the poor display caused by the disconnection of the data line 21.

[0062] It should be noted that Figure 2 In the embodiment, the data line 21 extends along the y direction, and the gate line 22 extends along the x direction, and the x direction is perpendicular to the y direction. In other embodiments, the extending directions of the data line 21 and the gate line 22 may not be perpendicular, but may be at an angle other than 90 degrees.

[0063] Optionally, the x direction may be a column direction, and the y direction may be a row direction; or, the x direction may be a row direction, and the y direction may be a column direction.

[0064] In some examples, each data line 21 is correspondingly connected to at least one auxiliary line 3 ; or, a portion of the data lines 21 are correspondingly connected to the auxiliary lines 3 , and another portion of the data lines 21 are not connected to the auxiliary lines 3 .

[0065] The hierarchical position of auxiliary line 3 is described in detail below.

[0066] Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of an array substrate provided by an embodiment of the present disclosure. Figure 3 As shown, the array substrate 100 further includes a plurality of pixel units, each of which is located in a pixel area, that is, the pixel unit is located in the display area 101. Each pixel unit includes a first TFT (Thin Film Transistor) 5 and a first electrode. The first electrode is located on a side of the first TFT 5 away from the base substrate 1, and the first electrode is connected to the first electrode of the first TFT 5. Optionally, the first electrode is the source or drain of the first TFT.

[0067] Optionally, the array substrate 100 further includes a GOA (Gate Driven on Array, array substrate row drive), which is also called a gate drive circuit. The GOA is located on one side of the base substrate 1 and in the peripheral area 102, and the GOA is connected to a plurality of gate lines 22. The GOA includes a plurality of second TFTs 7. The active layer (second active layer 72) of the second TFT 7 is in a different layer from the active layer (first active layer 52) of the first TFT, and the gate (second gate 73) of the second TFT is in a different layer from the gate (first gate 53) of the first TFT.

[0068] For an array substrate with GOA, the auxiliary line 3 connected to each data line 21 includes at least one of the following: a first auxiliary line, which is in the same layer as the active layer of the second TFT; a second auxiliary line, which is in the same layer as the gate electrode of the second TFT; and a third auxiliary line, which is in the same layer as the first electrode. The first electrode may be any of the pixel electrode 61, the first switching electrode 62, and the second switching electrode 63 described below.

[0069] The material of the first auxiliary line is the same as that of the active layer of the second TFT7, both of which are semiconductor materials. After the active layer of the second TFT7 is formed, the part not blocked by the gate of the second TFT7 will have conductivity under the action of the subsequent doping process, so that the first auxiliary line has conductivity; the material of the second auxiliary line is the same as that of the gate of the second TFT, and has conductivity; the material of the third auxiliary line is the same as that of the first electrode, and has conductivity. Setting the auxiliary line 3 and these existing structures of the array substrate 100 in the same layer can save processes, and these existing structures have conductivity, which meets the conductivity requirements of the auxiliary line 3. In practical applications, these solutions can be combined with each other to meet different product requirements.

[0070] Combine the following Figures 3 to 9 The hierarchical position of the auxiliary line 3 is exemplified.

[0071] like Figure 3 As shown, the first TFT5 includes a first active layer 52, a first gate 53 and a first source and drain electrode 51 stacked in sequence in a direction away from the base substrate 1. The second TFT7 includes a second active layer 72, a second gate 73 and a second source and drain electrode 71 stacked in sequence in a direction away from the base substrate 1.

[0072] In a direction perpendicular to the bearing surface of the substrate 1, the second active layer 72 and the second gate 73 are located between the first active layer 52 and the substrate 1. The first source and drain electrode 51 and the second source and drain electrode 71 are in the same layer and are located on the side of the second gate 73 away from the substrate 1. The data line 21 is in the same layer as the first source and drain electrode 51. Since the data line 21 is in the same layer as the first source and drain electrode 51, the gate line 22 is in the same layer as the first gate 53, and a plurality of gate lines 22 intersect with a plurality of data lines 21, when the layer where the first source and drain electrode 51 is located is located on the side of the layer where the first gate 53 is located away from the substrate 1, the data line 21 will cross the gate line 22 at the intersection of the data line 21 and the gate line 22, and the data line 21 is more likely to be broken at the crossing point. Therefore, it is more necessary to use the auxiliary line 3 to ensure the normal transmission of the signal.

[0073] The term “in sequence” in the present disclosure is only a limitation on the relative relationship of the listed structures, and does not mean that the listed structures must be in direct contact. For example, “the first TFT 5 includes a first active layer 52, a first gate electrode 53, and a first source and drain electrode 51 stacked in sequence in a direction away from the base substrate 1”. The first active layer 52, the first gate electrode 53, and the first source and drain electrode 51 are not necessarily in direct contact, and other structures may be arranged between any two structures.

[0074] For example, Figure 3 As shown, the auxiliary line 3 includes a first auxiliary line 3a and a second auxiliary line 3b. Any via 4 between the data line 21, the first auxiliary line 3a and the second auxiliary line 3b is connected to the data line 21, the first auxiliary line 3a and the second auxiliary line 3b at the same time. That is, the via 4 passes through all the insulating layers between the data line 21 and the first auxiliary line 3a.

[0075] For example, Figure 3 As shown, the array substrate 100 further includes a buffer layer 8, a second gate insulating layer 9, a first insulating layer 10, a first gate insulating layer 11, a second insulating layer 12 and a third insulating layer 13. The buffer layer 8, the second active layer 72, the second gate insulating layer 9, the second gate layer (i.e., the layer where the second gate 73 is located), the first insulating layer 10, the first active layer 52, the first gate insulating layer 11, the first gate layer (i.e., the layer where the first gate 53 is located), the second insulating layer 12, the source-drain electrode layer (i.e., the layer where the first source-drain electrode 51 and the second source-drain electrode 71 are located) and the third insulating layer 13 are sequentially stacked on the surface of the array substrate 1. The via 4 penetrates the second gate insulating layer 9, the first insulating layer 10, the first gate insulating layer 11 and the second insulating layer 12.

[0076] Since the second auxiliary line 3b and the second gate 73 are in the same layer, and the manufacturing material of the second gate 73 generally includes a metal material, and the etching rate of the metal material is relatively slow, which affects the etching rate of the via 4. Therefore, the orthographic projection of the via 4 on the surface of the base substrate 1 can be connected to the orthographic projection of the connected second auxiliary line 3b on the surface of the array substrate 1 but not overlapped, that is, the via is located on one side of the second auxiliary line 3b and is connected to the second auxiliary line 3b, so that the second auxiliary line 3b does not need to be etched, thereby improving the manufacturing efficiency of the array substrate.

[0077] Optionally, the via 4 passes through the first active layer 52, so that the via 4 can simultaneously connect the data line 21, the first active layer 52 and the auxiliary line 3. The via 4 directly passes through the first active layer 52 to save space, and can reduce the total number of vias in the array substrate 100, reducing the risk of light leakage.

[0078] In this embodiment, since the first active layer 52 is connected to the first source and drain electrode 51 through the via hole 4, a via hole 4 needs to be arranged in each pixel area, that is, each pixel unit corresponds to a via hole 4 to provide a data signal to each pixel unit.

[0079] It should be noted that, in another possible implementation, the data line 21 is connected to the auxiliary line 3 by a first via, and the first source and drain electrode 51 is connected to the first active layer 52 by a second via, and the orthographic projections of the first via and the second via on the surface of the substrate 1 do not overlap. In this implementation, a via 4 may be arranged in one pixel unit in each group of pixel units, and each group of pixel units includes one pixel unit or includes at least two adjacent pixel units. The number of pixel units in each two groups of pixel units may be the same or different, that is, the vias 4 may be arranged in an array or may not be arranged in an array.

[0080] Alternatively, if Figure 3 As shown, the array substrate 100 also includes a first transfer electrode 62 and a pixel electrode 61. In a direction perpendicular to the bearing surface of the base substrate 1, the first transfer electrode 61 is located between the first TFT5 and the pixel electrode 61, and the first transfer electrode 62 connects the first TFT5 and the pixel electrode 61. If there is no first transfer electrode 62, a deeper hole needs to be opened to connect the first TFT5 and the pixel electrode 61. Due to the deeper hole, the problem of missing connection of the pixel electrode 61 may occur; and because the hole is deeper and the place is less flat, after the display panel is subsequently formed, the thickness of the liquid crystal layer here is different from that of the liquid crystal layer at other places, and the liquid crystal disorder here may cause dark state light leakage. After adding the first transfer electrode 61, the via hole connecting the pixel electrode 61 can be shallower, reducing the possibility of missing the pixel electrode 61 and improving the problem of liquid crystal disorder.

[0081] Optionally, the array substrate 100 further includes a second transfer electrode 63, and in a direction perpendicular to the bearing surface of the base substrate 1, the second transfer electrode 63 is located between the first transfer electrode 62 and the pixel electrode 61, and the first transfer electrode 62 is connected to the pixel electrode 61 through the second transfer electrode 63. If there is no second transfer electrode 63, a deeper hole needs to be opened to connect the pixel electrode 61 and the first transfer electrode 62. Due to the deeper hole, the first transfer electrode 62 may be missing. The problem of connection; and because the hole is deeper and the place is less flat, after the display panel is subsequently formed, the thickness of the liquid crystal layer here is different from that of the liquid crystal layer at other places, and the liquid crystal disorder here may cause dark state light leakage. After adding the second transfer electrode 63, the via hole connecting the first transfer electrode 62 can be made shallower, reducing the possibility of missing the first transfer electrode 62, while improving the problem of liquid crystal disorder.

[0082] Alternatively, if Figure 3 As shown, a portion of the area on the first active layer 52 is processed by conductorization to form a drain area, and the first transfer electrode 62 is connected to the drain area. Since the first transfer electrode 62 is located below the pixel electrode 61, that is, the first transfer electrode 62 is located in the opening area of ​​the pixel, the portion of the first TFT 5 connected to the first transfer electrode 62 is also located in the opening area of ​​the pixel. In order to reduce the shielding of light by the shading structure, in this embodiment, the drain is not separately made on the first source and drain layer, but a portion of the area on the first active layer 52 is processed by conductorization to form a drain area.

[0083] The array substrate 100 further includes a first planarization layer 14 and a second planarization layer 15 stacked sequentially on the surface of the third insulating layer 13 away from the base substrate 1. The first switching electrode 62 is connected to the drain region through a through hole penetrating the first gate insulating layer 11, the second insulating layer 12 and the third insulating layer 13. The second switching electrode 63 is connected to the first switching electrode 62 through a through hole penetrating the first planarization layer 14. The second planarization layer 15 includes a plurality of filling blocks, each of which is located in a through hole of the first planarization layer 14, and is used to fill the through hole. The orthographic projection of the filling block on the surface of the base substrate 1 is located within the orthographic projection of the pixel electrode 61 on the surface of the base substrate 1.

[0084] Figure 4 FIG. 1 is a schematic diagram of a hierarchical structure of another array substrate provided in an embodiment of the present disclosure. Figure 3 Compared with the embodiment shown, Figure 4 The difference of the embodiment shown is that Figure 4 In the illustrated embodiment, the auxiliary line 3 only includes the first auxiliary line; and Figure 4 The exemplary embodiment shown has a first switching electrode 62 but does not have a second switching electrode 63 .

[0085] Figure 5FIG. 1 is a schematic diagram of a hierarchical structure of another array substrate provided in an embodiment of the present disclosure. Figure 3 Compared with the embodiment shown, Figure 5 The difference of the embodiment shown is that Figure 5 The exemplary embodiment shown has a first switching electrode 62 but does not have a second switching electrode 63 .

[0086] Figure 6 FIG. 1 is a schematic diagram of a hierarchical structure of another array substrate provided in an embodiment of the present disclosure. Figure 3 Compared with the embodiment shown, Figure 6 The difference of the embodiment shown is that Figure 6 In the illustrated embodiment, the auxiliary lines 3 only include the first auxiliary lines.

[0087] Figure 7 FIG. 1 is a schematic diagram of a hierarchical structure of another array substrate provided in an embodiment of the present disclosure. Figure 3 Compared with the embodiment shown, Figure 7 The difference of the embodiment shown is that Figure 7 In the illustrated embodiment, the first source-drain electrode 51 includes a first drain electrode, and the first transfer electrode 62 is connected to the first drain electrode in the first source-drain electrode 51 .

[0088] Figure 8 It is a schematic diagram of the hierarchical structure of another array substrate provided in an embodiment of the present disclosure. Figure 8 The hierarchical positions of the various film layers of the first TFT in Figures 3 to 7 The embodiments shown are different. Figure 8 As shown, the first TFT5 includes a first source-drain electrode 51, a first active layer 52, and a first gate electrode 53 stacked in sequence along a direction away from the base substrate 1. The second TFT7 includes a second active layer 72, a second gate electrode 73, and a second source-drain electrode 71 stacked in sequence along a direction away from the base substrate 1. The first source-drain electrode 51 and the second source-drain electrode 71 are in the same layer.

[0089] For example, Figure 8 As shown, the auxiliary line 3 includes a first auxiliary line 3a and a third auxiliary line 3c. The first auxiliary line 3a is in the same layer as the second active layer 72, and the third auxiliary line 3c is in the same layer as the first switching electrode 62. That is, the layer where the first auxiliary line 3a is located and the layer where the third auxiliary line 3c is located are respectively located on both sides of the layer where the data line 21 is located. Therefore, the data line 21 is connected to the first auxiliary line 3a through the first via 41, and the data line 21 is connected to the third auxiliary line 3c through the second via 42.

[0090] The orthographic projections of the first via hole 41 and the second via hole 42 in the same pixel region on the surface of the base substrate 1 at least partially overlap. The first via hole 41 and the second via hole 42 are arranged in the same vertical direction as much as possible, which can reduce the number of via holes as a whole, thereby reducing the risk of light leakage.

[0091] For example, Figure 8 As shown, the first active layer 52 and the first source-drain electrode 71 are in contact with the surface of the same insulating layer. The third auxiliary line 3c is in contact with the first active layer 52 and the first source electrode in the first source-drain electrode 51 at the same time. Because the bottom surface of the first active layer 52 close to the substrate substrate 1 is poorer in surface treatment effect than the top surface far from the substrate substrate 1, if the data line 21 or the first source-drain electrode 51 is only in contact with the bottom surface of the first active layer 52, problems such as poor contact and reduced on-current of the TFT are likely to occur. The third auxiliary line 1c is in contact with the first active layer 52 and the first source electrode in the first source-drain electrode 51 at the same time, so as to ensure the electrical connection between the first active layer 52 and the first source-drain electrode 51.

[0092] Fig. 9 FIG. 1 is a schematic diagram of a hierarchical structure of another array substrate provided in an embodiment of the present disclosure. Figure 8 Compared with the embodiment shown, Fig. 9 The difference of the illustrated embodiment is that the auxiliary line 3 only includes the third auxiliary line but does not include the first auxiliary line.

[0093] Exemplarily, for an array substrate 100 without GOA, the auxiliary lines 3 may be in the same layer as the first electrodes, or may be in a separate layer.

[0094] For example, see again Figure 2 , the line width d of the signal line 2 is less than or equal to the line width D of the auxiliary line 3. The signal line 2 is thin and may be broken, while the auxiliary line 3 is wide and not easy to be broken, which can further ensure the transmission process of the electrical signal on the signal line 2.

[0095] In some examples, the line width d of the signal line 2 is less than 2 μm, and the line width D of the auxiliary line 3 is also less than 2 μm. The signal line 2 and the auxiliary line 3 can be formed by ultra-narrow process to make the signal line 2 and the auxiliary line 3 as thin as possible, so as to improve the pixel aperture ratio in high PPI (Pixels Per Inch, number of pixels per inch) products.

[0096] In the disclosed embodiment, the first electrode is a pixel electrode 61 or a first transfer electrode 62; in a direction perpendicular to the bearing surface of the base substrate 1, the first transfer electrode 61 is located between the first TFT 5 and the pixel electrode 61, and the first transfer electrode 62 connects the first TFT 5 and the pixel electrode 61. The third auxiliary line can be arranged in the same layer as the first transfer electrode 61 or the pixel electrode 61, and the auxiliary line 3 is arranged in the same layer as the existing conductive structure of the array substrate 100 to save process steps.

[0097] Exemplarily, the first TFT is a metal oxide transistor, and the second TFT is an LTPS (Low Temperature Poly-Silicon) transistor. For example, the second active layer 72 is made of low temperature polysilicon material, and the first active layer 52 is made of IGZO (Indium Gallium Zinc Oxide) or other oxide semiconductor materials. Alternatively, both the first TFT and the second TFT are LTPS transistors.

[0098] See again Figures 3 to 9 , the array substrate 100 further includes a dielectric layer 16 and a common electrode 17. The dielectric layer covers the pixel electrode 61. The common electrode 17 is located on the surface of the dielectric layer 16 away from the base substrate 1. The pixel electrode 61 and the common electrode 17 are used to form an electric field to control the deflection of the liquid crystal.

[0099] Optionally, the array substrate 100 further includes a light shielding structure 18 and a first PS (Photo Spacer) 19. The light shielding structure 18 and the first PS 19 are sequentially stacked on the surface of the dielectric layer 16 away from the base substrate 1. The light shielding structure 18 and the common electrode 17 are in the same layer.

[0100] In the disclosed embodiment, the base substrate 1 can be any transparent substrate, such as a glass substrate, a quartz substrate, a plastic substrate, other transparent hard substrates or other transparent flexible substrates, which can be a single layer or a multilayer structure. Taking the multilayer structure as an example, the base substrate 1 includes a first PI (polyimide) layer, a first protective layer, a second PI (polyimide) layer, and a second protective layer stacked from bottom to top. The two protective layers are used to protect the PI layer to prevent subsequent processes from damaging the PI layer. The second protective layer is also covered with a buffer layer, which can block water oxygen and block alkaline ions.

[0101] Exemplarily, the second gate insulating layer 9 and the first gate insulating layer 11 may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0102] Exemplarily, the second gate 73 can be made of a metal material, such as one or more of molybdenum, copper, and aluminum. Because the second TFT is an LTPS transistor, a high-temperature process is required after the second gate is made, and the high-temperature process includes hydrogenation and rapid annealing processes. Compared with other metal materials, molybdenum materials have a larger resistance but are resistant to high temperatures. Therefore, in this embodiment, the second gate 73 is formed of molybdenum.

[0103] Exemplarily, the first gate 53 includes a first sub-gate layer 531 and a second sub-gate layer 532 stacked in sequence. The first sub-gate layer 531 is made of a transparent conductive material, such as ITO (Indium tin oxide); the second sub-gate layer 532 is made of a metal material, such as titanium, aluminum, and titanium materials stacked alternately in sequence. The width of ITO limits the channel length, but if only ITO is used, the resistance is relatively large; under this premise, making a metal material can reduce the resistance, and the metal material can be made as small as possible to increase the aperture ratio. Here, there is no high-temperature process after making the second sub-gate layer 532, so the second sub-gate layer 532 can be made of a titanium-aluminum-titanium laminated material, which has a low resistance and is not resistant to high temperatures.

[0104] Exemplarily, the first insulating layer 10 , the second insulating layer 12 and the third insulating layer 13 are formed of silicon oxide or silicon nitride, silicon oxynitride or the like.

[0105] Exemplarily, the first planarization layer 14 and the second planarization layer 15 are made of an organic insulating material, such as resin.

[0106] Exemplarily, the first switching electrode 62 , the second switching electrode 63 and the common electrode 17 are made of a transparent conductive material, such as ITO, IZO (Indium zinc oxide) and the like.

[0107] Exemplarily, the light shielding structure 18 may be made of a light-proof metal material, such as molybdenum, aluminum, titanium, copper, etc.

[0108] Exemplarily, the first spacer 19 is made of an inorganic material, such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0109] It should be noted that the above is an illustrative explanation using the example of auxiliary lines being produced on the same layer as the existing film layer of the array substrate. In other embodiments, the auxiliary lines may also include a fourth type of auxiliary lines, which are on a different layer from the existing film layer structure of the array substrate 100 and are a separate layer.

[0110] In the disclosed embodiment, the target signal line is the gate line 22, and the auxiliary line 3 connected to the target signal line includes at least one of the following: a fifth auxiliary line, which is in the same layer as the active layer 72 of the second TFT; a sixth auxiliary line, which is in the same layer as the gate 73 of the second TFT; and a seventh auxiliary line, which is in a different layer from the existing film layer structure of the array substrate 100 and is a separate layer.

[0111] Fig.10 FIG. 1 is a flow chart of a method for manufacturing an array substrate provided by an embodiment of the present disclosure. Fig.10 As shown, the method includes the following steps.

[0112] In step S1, a substrate is provided;

[0113] In step S2, a plurality of data lines, a plurality of gate lines and at least one auxiliary line are manufactured on a base substrate.

[0114] The base substrate has a display area and a peripheral area, the peripheral area surrounds the display area, the plurality of signal lines include a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the plurality of data lines intersect and define a plurality of pixel areas in the display area.

[0115] At least one of the multiple gate lines and the multiple data lines is a target signal line, each target signal line is connected to at least one auxiliary line, the connected auxiliary lines and the target signal lines are in different layers and extend in the same direction, the orthographic projections of the connected auxiliary lines and the target signal lines on the surface of the substrate at least partially overlap, the connected auxiliary lines and the target signal lines are connected through multiple vias, and the multiple vias are arranged at intervals along the length direction of the target signal lines.

[0116] Figures 11 to 19 is a schematic diagram of a manufacturing process of an array substrate provided by an embodiment of the present disclosure, which can be manufactured as follows Figure 6 The array substrate shown in FIG. The manufacturing process includes the following steps:

[0117] The first step, such as Fig.11 As shown, first, a buffer layer 2 is formed on the base substrate 1, for example, by deposition. Then, a second active layer pattern is formed on the buffer layer 2, and the second active layer pattern includes a second active layer 72 and auxiliary lines 3.

[0118] For example, an initial second active layer may be deposited on the buffer layer 2, a photoresist structure may be obtained through processes such as photoresist coating, exposure, and development, and the initial second active layer may be etched using the photoresist structure as a mask to form a second active layer pattern.

[0119] The second step is, Fig.12As shown, a second gate insulating layer 9 and an initial second gate layer are sequentially deposited on the second active layer pattern, and the second gate insulating layer 9 covers the second active layer pattern. A photoresist structure is obtained on the initial second gate layer by photoresist coating, exposure, development and other processes, and the initial second gate layer is etched using the photoresist structure as a mask to form a second gate layer pattern, the second gate layer pattern including a second gate 73, and a first insulating layer 10 is deposited on the second gate pattern.

[0120] The third step is Fig.13 As shown, an initial first active layer is deposited in the display area 101 , a photoresist structure is obtained through processes such as photoresist coating, exposure, and development, and the initial first active layer is etched using the photoresist structure as a mask to form a first active layer pattern, and the first active layer pattern includes a first active layer 52 .

[0121] The fourth step is Fig.14 As shown, a first gate insulating layer 11 and an initial first gate layer are deposited on the first active layer 52, a photoresist structure is obtained on the initial first gate layer by processes such as photoresist coating, exposure, and development, and the initial first gate layer is etched using the photoresist structure as a mask to form a first gate layer pattern, and the first gate layer pattern includes a first gate 53. The first gate 53 includes a first sub-gate layer 531 and a second sub-gate layer 531.

[0122] Step 5: Fig.15 As shown, a second insulating layer 12 is deposited on the first gate layer pattern, and via holes are etched in both the peripheral area 102 and the display area 101 to the layer where the second active layer 72 is located.

[0123] Step 6: Fig.16 As shown, in the via holes etched into the second active layer 72 in the peripheral area 102 and the display area 101, a series of processes such as deposition, photoresist coating, exposure, etching, and stripping are used to form a source-drain electrode layer, which includes a first source-drain electrode 51 and a second source-drain electrode 71. The data line 21 is connected to the source electrode in the first source-drain electrode 51.

[0124] Step 7: Fig.17 As shown, a third insulating layer 13 is deposited on the source and drain layer, a via is etched to the layer where the first active layer 52 is located, and in the via etched to the layer where the first active layer 52 is located, a series of processes such as deposition, photoresist coating, exposure, etching, and stripping are used to form a first transfer electrode layer, and the first transfer electrode layer includes a first transfer electrode 62, and the first transfer electrode 62 is connected to the first active layer 52 through the via.

[0125] Step 8: Fig.18As shown, a first planarization layer 14 is deposited and a via hole is etched to the first transfer electrode layer, and a series of processes such as deposition, photoresist coating, exposure, etching, and stripping are used to form a second transfer electrode layer, and the second transfer electrode layer includes a second transfer electrode 63. A portion of the second transfer electrode 63 is located in the via hole, and another portion is located on the surface of the first planarization layer 14 away from the base substrate 1.

[0126] Step 9: Fig.19 As shown, a second planarization layer 15 is deposited in the via hole formed in the eighth step to fill the via hole formed in the eighth step and eliminate the step difference.

[0127] Step 10: Figure 6 As shown, a series of processes such as deposition, photoresist coating, exposure, etching, and stripping are sequentially used on the second planarization layer 15, the second transfer electrode layer, and the first planarization layer 14 to form a pixel electrode layer, a dielectric layer 16, a common electrode layer, a light shielding structure 18, and a first spacer 19. Among them, the pixel electrode layer includes a pixel electrode 61, and the common electrode layer includes a common electrode 17.

[0128] Optionally, when forming the second gate layer in the second step, in addition to forming the second gate 73, a second gate layer pattern may be formed in the area corresponding to the data line 21, that is, a second auxiliary line is formed, so as to obtain Figure 3 Here, corresponding means that the orthographic projection of the data line 21 on the bearing surface of the base substrate 1 and the orthographic projection of the second auxiliary line on the bearing surface of the base substrate 1 at least partially overlap.

[0129] Optionally, in the seventh step, after forming the third insulating layer 13 on the source and drain layer, the first planarization layer 14 is formed, and a via hole is etched on the first planarization layer 14 until it penetrates the third insulating layer 13 to the first active layer 52, and a first transfer electrode layer and a second planarization layer 15 are formed in the via hole, and the first transfer electrode layer includes a first transfer electrode 62. Figure 6 The process of the array substrate shown in FIG. 1 is the same, and a pixel electrode layer, a dielectric layer 16, a common electrode layer, a light shielding structure 18 and a first spacer 19 are sequentially formed on the second planarization layer 15, the first transfer electrode layer and the first planarization layer 14. The pixel electrode layer includes a pixel electrode 61, and the common electrode layer includes a common electrode 17. Figure 4 The array substrate is shown.

[0130] Optionally, in forming Figure 4 In the process of forming the array substrate shown in FIG. 1 , when forming the second gate layer in the second step, in addition to forming the second gate 73, a second gate layer pattern is formed in the area corresponding to the data line 21, that is, a second auxiliary line is formed, and the second gate layer pattern is formed in the area corresponding to the data line 21. Figure 5 The array substrate shown.

[0131] Figure 20 to Figure 26 is a schematic diagram of a manufacturing process of an array substrate provided by an embodiment of the present disclosure, which can be manufactured as follows Fig. 9 The array substrate shown in FIG. The manufacturing process includes the following steps:

[0132] The first step, such as Fig. 20 As shown, a base substrate 1 is provided and a buffer layer 2 is deposited on the base substrate 1, an initial second active layer is deposited on the buffer layer, a photoresist structure is obtained by photoresist coating, exposure, development and other processes, and the initial second active layer is etched using the photoresist structure as a mask to form a second active layer pattern, the second active layer pattern includes a second active layer 72 and auxiliary lines 3. A series of processes such as deposition, photoresist coating, exposure, etching, and stripping are sequentially used on the second active layer pattern to form a second gate insulating layer 11, a second gate layer, and a first insulating layer 10. Among them, the second gate layer includes a second gate 73.

[0133] The second step is, Fig.21 As shown, via holes are formed by etching the first insulating layer 10 and the second gate insulating layer 9 to expose the second active layer 72 .

[0134] The third step is Fig. 22 As shown, a series of processes such as deposition, photoresist coating, exposure, etching, and stripping are used to form a source-drain layer in the peripheral area 102 and the display area 101. The source-drain layer includes a first source-drain 51 and a second source-drain 71. The data line 21 is connected to the source electrode in the first source-drain 51.

[0135] The fourth step is Fig.23 As shown, a series of processes such as deposition, photoresist coating, exposure, etching, and stripping are used to form a first active layer pattern in the display area 101 to obtain the first active layer 52 .

[0136] Step 5: Fig.24 As shown, a first gate insulating layer 11 is deposited on the first active layer 52, and a first gate layer is formed by a series of processes such as deposition, photoresist coating, exposure, etching, and stripping, wherein the first gate layer includes a first gate, and the first gate is composed of two sub-layers.

[0137] Step 6: Fig.25 As shown, a second insulating layer 12 is deposited and formed, and strip grooves are etched in the data lines 21 of the display area 101 and the source region in the first source and drain electrodes 51 to the first active layer 52 , and via holes are etched in the drain region in the first source and drain electrodes 51 to the first active layer 52 .

[0138] Step 7: Fig.26As shown, in the sixth step, a series of processes such as deposition, photoresist coating, exposure, etching, and stripping are used to form a first transfer electrode layer in the strip grooves and vias. The first transfer electrode layer includes a first transfer electrode 62 and an auxiliary line 3 (third auxiliary line 3c).

[0139] Step 8: Fig. 9 As shown, a first planarization layer 14 is formed in sequence and a via hole is etched to the first transfer electrode layer, a second transfer electrode layer is formed in the via hole, the second transfer electrode layer includes a second transfer electrode 63, and a second planarization layer 15 is formed in the via hole to fill the via hole and eliminate the step difference. A pixel electrode layer, a dielectric layer 16, a common electrode layer, a light shielding structure 18 and a first spacer 19 are formed in sequence. Among them, the pixel electrode layer includes a pixel electrode 61, and the common electrode layer includes a common electrode 17.

[0140] Optionally, when forming the second active layer pattern in the first step, the second active layer pattern is also formed at the position corresponding to the data line 21 in the display area 101, thereby obtaining the auxiliary line 3 (first auxiliary line 3a). When forming via holes in the first insulating layer 10 and the second gate insulating layer 9 in the second step, via holes are also formed at the position corresponding to the data line 21 in the display area 101 until the auxiliary line 3 is exposed, so that the data line 21 can be connected to the auxiliary line 3 through the via holes when it is formed. Figure 8 The array substrate shown.

[0141] The present disclosure further provides a display panel, which includes a color filter substrate 200 and any of the aforementioned array substrates 100 , which are opposite to each other, and a liquid crystal layer 300 located between the array substrate 100 and the color filter substrate 200 .

[0142] The display panel has the same effect as the aforementioned array substrate, which will not be described in detail here.

[0143] Fig. 27 FIG. 1 is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present disclosure. Fig. 27 As shown, the color filter substrate 200 includes a stacked second substrate 21, a color filter layer and a third planarization layer 24, and the third planarization layer 24 is located on the side of the second substrate 21 close to the liquid crystal layer 300. The color filter layer includes a plurality of color blocks 22 distributed in an array and a black matrix 23 located between the plurality of color blocks 22. The array substrate 100 also includes a plurality of first spacers 19, and the color filter substrate 200 also includes a plurality of second spacers 20. The plurality of first spacers 19 and the plurality of second spacers 20 form a plurality of support columns relative to each other. The color filter substrate 200 and the array substrate 100 are relative to each other, and the first spacers 19 and the second spacers 20 form support columns, which facilitate the formation of a receiving cavity between the color filter substrate 200 and the array substrate 100, so as to facilitate the filling of the liquid crystal layer 300 material in the receiving cavity.

[0144] The present disclosure also provides a display device, which includes a backlight module and the aforementioned display panel, wherein the backlight module is used to provide a light source for the display panel.

[0145] Exemplarily, the display device further includes a power supply circuit, and the power supply circuit is used to supply power to the display panel.

[0146] Illustratively, the display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0147] The display device may be a VR (Virtual Reality) display device or a common two-dimensional display device, etc.

[0148] The display device has the same effect as the above-mentioned display panel, which will not be described in detail here.

[0149] The above are only optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. An array substrate, characterized in that: The array substrate comprises a base substrate, a plurality of gate lines, a plurality of data lines and at least one auxiliary line; The base substrate has a display area and a peripheral area, and the peripheral area surrounds the display area; The plurality of gate lines and the plurality of data lines intersect and define a plurality of pixel areas in the display area; At least one of the multiple gate lines and the multiple data lines is a target signal line, each of the target signal lines is connected to at least one auxiliary line, the connected auxiliary lines and the target signal lines are in different layers and have the same extension direction, the connected auxiliary lines and the target signal lines have at least partially overlapping orthographic projections on the surface of the substrate, the connected auxiliary lines and the target signal lines are connected through a plurality of vias, and the plurality of vias are arranged at intervals along the length direction of the target signal lines.

2. The array substrate according to claim 1, characterized in that: The array substrate further comprises a gate driving circuit and a plurality of pixel units, each of the pixel units is located in one of the pixel regions, the pixel unit comprises a first thin film transistor and a first electrode, the first electrode is located at a side of the first thin film transistor away from the base substrate, and the first electrode is connected to a first electrode of the first thin film transistor; The gate driving circuit is located in the peripheral area, the gate driving circuit is connected to the plurality of gate lines, and the gate driving circuit includes a plurality of second thin film transistors; The active layer of the second thin film transistor is in a different layer from the active layer of the first thin film transistor, and the gate of the second thin film transistor is in a different layer from the gate of the first thin film transistor; The target signal line is a data line, and the auxiliary line connected to the target signal line includes at least one of the following: a first auxiliary line, which is in the same layer as the active layer of the second thin film transistor; a second auxiliary line, which is in the same layer as the gate electrode of the second thin film transistor; The third auxiliary line is in the same layer as the first electrode.

3. The array substrate according to claim 2, characterized in that: The first thin film transistor includes a first active layer, a first gate electrode and a first source and drain electrode stacked in sequence in a direction away from the base substrate; The second thin film transistor comprises a second active layer, a second gate electrode and a second source and drain electrode stacked in sequence in a direction away from the base substrate, and in a direction perpendicular to the carrying surface of the base substrate, the second active layer and the second gate electrode are located between the first active layer and the array substrate; The first source and drain are in the same layer as the second source and drain, and are located on a side of the second gate away from the array substrate.

4. The array substrate according to claim 3, characterized in that: The auxiliary line includes at least one of the first auxiliary line and the second auxiliary line; A via hole between the target signal line and the auxiliary line penetrates the first active layer.

5. The array substrate according to claim 2, characterized in that: The first thin film transistor comprises a first source and drain electrode, a first active layer and a first gate electrode which are sequentially stacked in a direction away from the base substrate; The second thin film transistor comprises a second active layer, a second gate electrode and a second source and drain electrode stacked in sequence in a direction away from the base substrate; The first source and drain are in the same layer as the second source and drain.

6. The array substrate according to claim 5, characterized in that: The first active layer and the first source and drain are in contact with a surface of the same insulating layer; The auxiliary line includes the third auxiliary line, and the third auxiliary line is in contact with the first active layer and the first source electrode in the first source and drain electrodes at the same time.

7. The array substrate according to claim 1, characterized in that: The array substrate further comprises a plurality of pixel units, each of the pixel units is located in one of the pixel regions, the pixel unit comprises a first thin film transistor and a first electrode, the first electrode is located at a side of the first thin film transistor away from the base substrate, the first thin film transistor comprises a first source and drain, and the first electrode is connected to the first source and drain; The target signal line is a data line, and the auxiliary line is in the same layer as the first electrode.

8. The array substrate according to any one of claims 1 to 7, characterized in that: The line width of the target signal line is smaller than or equal to the line width of the auxiliary line.

9. The array substrate according to claim 2, characterized in that: The pixel unit further includes a pixel electrode, and the first electrode is the pixel electrode; or, The pixel unit also includes a first transfer electrode and a pixel electrode. In a direction perpendicular to the supporting surface of the substrate, the first transfer electrode is located between the first thin film transistor and the pixel electrode. The first transfer electrode connects the first thin film transistor and the pixel electrode. The first electrode is the pixel electrode or the first transfer electrode.

10. The array substrate according to claim 9, characterized in that: The array substrate further includes: a second transfer electrode, which is located between the first transfer electrode and the pixel electrode in a direction perpendicular to the supporting surface of the base substrate, and the first transfer electrode connects the first transfer electrode and the pixel electrode.

11. The array substrate according to any one of claims 3 to 6, characterized in that: The first gate comprises a first sub-gate layer and a second sub-gate layer stacked in sequence; The first sub-gate layer is made of a transparent conductive material, and the second sub-gate layer is made of a metal material.

12. The array substrate according to any one of claims 2 to 6, claim 9 and claim 10, characterized in that: The first thin film transistor is a metal oxide transistor, and the second thin film transistor is a low temperature polysilicon transistor.

13. A method for manufacturing an array substrate, characterized in that: The method comprises: providing a substrate base plate; Fabricating a plurality of gate lines, a plurality of data lines and at least one auxiliary line on the base substrate to obtain the array substrate; Wherein, the base substrate has a display area and a peripheral area, the peripheral area surrounds the display area, the plurality of gate lines and the plurality of data lines intersect and define a plurality of pixel areas in the display area; At least one of the multiple gate lines and the multiple data lines is a target signal line, each of the target signal lines is connected to at least one auxiliary line, the connected auxiliary lines and the target signal lines are in different layers and have the same extension direction, the connected auxiliary lines and the target signal lines have at least partially overlapping orthographic projections on the surface of the substrate, the connected auxiliary lines and the target signal lines are connected through a plurality of vias, and the plurality of vias are arranged at intervals along the length direction of the target signal lines.

14. A display panel, characterized in that: The display panel includes a color filter substrate and an array substrate as claimed in any one of claims 1 to 12 that are opposite to each other, and a liquid crystal layer located between the array substrate and the color filter substrate.

15. A display device, characterized in that: The display device comprises a backlight module and the display panel as claimed in claim 14, wherein the backlight module provides a light source for the display panel.

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