A data transmission system and method based on HSB bus

Abstract

This invention belongs to the field of data transmission technology, specifically relating to a data transmission system and method based on an HSB bus. The system includes an HSB bus and a central control PLC and multiple distributed PLCs connected to the HSB bus. Each of the central control PLC and distributed PLCs contains a CPU and an FPGA, with the FPGA including a shared data RAM. The CPU executes control logic, programs, and interacts with external devices, manages the main control tasks of the board, and processes input / output signals. The FPGA is used for data transmission and real-time control on the bus. The shared data RAM stores the board's own data and data received when communicating with other boards via the HSB bus. The CPU reads and writes to the shared data RAM through a memory mapping mechanism, thereby realizing data exchange and collaboration between the CPU and the FPGA.

Description

Technical Field

[0001] This invention belongs to the field of data transmission technology, specifically relating to a data transmission system and method based on HSB (High-Speed ​​Bus). Background Technology

[0002] In the field of industrial control, refer to Figure 1 A typical industrial control device consists of a central control PLC (Programmable Logic Controller), multiple distributed PLCs, and a PWR board (Power Amplifier Board). The central control PLC focuses on data acquisition and decision-making logic, while the distributed PLCs focus on executing specific control tasks. The PWR board provides a stable power supply to the entire device. This distributed computing task allocation allows each PLC to work independently, improving the system's parallel processing capabilities.

[0003] IEC 61131-3 is a PLC programming standard developed by the International Electrotechnical Commission (IEC). It provides various programming languages, among which Function Block Diagram (FBD) is a graphical programming method. The FBD language represents control logic graphically, enabling engineers to intuitively design and implement control logic by dragging and dropping function blocks and connecting inputs and outputs.

[0004] Taking a cooling system control scenario based on a temperature sensor as an example, refer to... Figure 2 The system is constructed using one central control PLC and two distributed PLCs. The central control PLC is responsible for temperature monitoring and decision-making logic. It connects to temperature sensors to collect temperature data in real time and determines whether to start or stop the cooling system based on the set temperature threshold. The distributed PLCs are responsible for receiving start or stop commands from the central control PLC, executing the corresponding operations, and feeding back the cooling system's status, such as running, stopped, or faulty, to the central control PLC for monitoring and management.

[0005] Reference Figure 3 As can be seen from the function block diagrams of the central control PLC and the distributed PLC, data needs to be exchanged between the central control PLC and the distributed PLC in each cycle. Therefore, designing an effective data interaction method between PLCs is particularly important to ensure the efficiency and real-time performance of the entire industrial control device.

[0006] In existing technologies, CAN bus, Ethernet, and RS-485 can be used to enable data exchange between PLCs. However, each of these solutions has some significant drawbacks. The standard data rate of CAN bus is 125 kbps to 1 Mbps, and bandwidth becomes a bottleneck when large amounts of data need to be transmitted or multiple nodes communicate simultaneously. Ethernet communication requires the configuration of network devices such as switches, routers, and firewalls, resulting in a complex system architecture. Under high traffic or heavy network load, packet collisions and losses frequently occur, potentially leading to communication interruptions or control command delays. RS-485 typically operates at speeds between 9600 bps and 115200 bps, and the number of nodes it supports simultaneously is limited by bus load and wiring electrical characteristics, resulting in poor scalability.

[0007] To address these issues, the HSB bus was designed to provide a more efficient and stable data interaction solution to meet the real-time and reliability requirements of industrial control systems, while also offering advantages such as high speed and good scalability. Summary of the Invention

[0008] To overcome the problems in the prior art, this invention proposes a data transmission system and method based on the HSB bus.

[0009] The technical solution of the present invention to solve the above-mentioned technical problems is as follows:

[0010] In a first aspect, the present invention provides a data transmission system based on an HSB bus, including an HSB bus and a central control PLC and multiple distributed PLCs connected to the HSB bus; each of the central control PLC and distributed PLCs is equipped with a CPU and an FPGA, and the FPGA includes a shared data RAM; the shared data RAM is used to store the board's own data and the data received when communicating with other boards through the HSB bus; the CPU reads and writes the shared data RAM through a memory mapping mechanism, thereby realizing data exchange and cooperation between the CPU and the FPGA.

[0011] Furthermore, the HSB bus uses the LVDS bus mode for transmission, and its lines include: clock CLK line, control signal CTRL line, and data bus; among them, the clock CLK line is used to provide a synchronous clock signal to ensure that all boards send and receive data at the same time, the control signal CTRL line is used to control the access permissions of the bus and the start or end of data transmission, and the data bus is used to transmit data.

[0012] Furthermore, when the system starts up or is reconfigured, the central control PLC is responsible for sending configuration requests and aggregating the data volume of each distributed PLC to calculate the total data transmission volume and allocate node information; the distributed PLC is responsible for responding to the configuration request of the central control PLC, reporting its own data volume, and processing the data nodes it occupies on its FPGA according to the received node information.

[0013] Furthermore, the FPGA is equipped with a transmitting module and a receiving module;

[0014] The transmitting module is used to send data to the bus in a predetermined format according to the relevant registers configured by the CPU when an FPGA timer interrupt occurs.

[0015] The receiving module is used to receive data from the bus in real time. Based on the register configuration and the condition of the board, it parses the received data and stores it in the corresponding location of the shared data RAM according to the control information in the data frame.

[0016] Furthermore, the data frame format includes a start address, byte length, data content, checksum, and end marker.

[0017] Furthermore, the receiving module is also used to verify the data frame to ensure the correctness of the data. If the verification code is incorrect, it indicates that an error has occurred in the data transmission process, and a request is made to retransmit the data frame.

[0018] Secondly, the present invention also provides a data transmission method based on the HSB bus, comprising the following steps:

[0019] Step 100: When data transmission begins, the sending module of one board sends the data frames within the board to the bus in a predetermined format according to the pre-configured information.

[0020] After the data is sent, the sending module enters a waiting state, waiting for feedback from the receiving module;

[0021] Step 200: The receiving modules of other boards monitor the data on the bus. When data transmission is detected, they start receiving data. The receiving modules write the received data to the corresponding location in the RAM according to the content of the data.

[0022] The receiving module calculates the checksum of the received data and compares it with the received checksum. If the checksums match, it continues to receive subsequent data or prepares to send data for this board.

[0023] If there is a discrepancy, a retransmission request is sent to the bus; upon receiving the retransmission signal, the transmitting module will retransmit the previous data.

[0024] Step 300: When all boards have completed one data transmission and reception cycle and no checksum error is detected, the data exchange of one HSB cycle is complete;

[0025] Each board will determine whether the entire transmission process is complete based on the total number of nodes.

[0026] Furthermore, if the number of retransmissions exceeds a set value, the transmission will be stopped and the CPU will be notified.

[0027] Furthermore, before the data transmission operation begins, the following steps are included:

[0028] A central control PLC and multiple distributed PLCs are connected to the HSB bus, where each PLC is considered a board. Both the central control PLC and the distributed PLCs are equipped with a CPU and an FPGA. The FPGA includes a shared data RAM, and the shared data RAM of each board is configured, with a partition reserved for the data content of each board. During initialization, the central control PLC configures the interrupt operation parameters to the FPGA and sets the interrupt mode.

[0029] Furthermore, before the data transmission begins, data preparation and node division are also included: the data size occupied by each board is determined in advance, that is, the central control PLC and the distributed PLC have known their respective data areas in the shared data RAM in advance when the system starts.

[0030] Compared with the prior art, the present invention has the following technical effects:

[0031] In this invention, each board connected to the bus has a shared data RAM. When one board sends data, the other boards act as receivers to receive data from the bus. The FPGA on the receiving board stores the received data into the corresponding location in its shared data RAM according to the information in the data frame. Following a pre-assigned starting address transmission order, all boards sequentially send their own data while simultaneously receiving data from other boards. Within one HSB interrupt cycle, all boards exchange data, ensuring that their data RAMs contain the same data content, thus achieving data sharing, exchange, and synchronization. Attached Figure Description

[0032] To more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of a typical industrial control device;

[0034] Figure 2 The control flowchart is an example of a cooling system control scenario based on a temperature sensor.

[0035] Figure 3 Function block diagrams for central control PLC and distributed PLC;

[0036] Figure 4 This is a schematic diagram of interrupt mode 0 of the present invention;

[0037] Figure 5 This is a schematic diagram of interruption mode 1 of the present invention;

[0038] Figure 6 This is a schematic diagram of RAM memory allocation in this invention;

[0039] Figure 7 This is a schematic diagram of the memory allocation of each board component in this invention;

[0040] Figure 8 This is a schematic diagram of the state machine of the transmitting module of the present invention;

[0041] Figure 9 This is a schematic diagram of the state machine of the receiving module of the present invention;

[0042] Figure 10 This is a schematic diagram of the process of the present invention. Detailed Implementation

[0043] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the specific implementation methods, structures, features, and effects of the technical solutions proposed according to the present invention are described in detail below with reference to the accompanying drawings and preferred embodiments. Specific features, structures, or characteristics in one or more embodiments may be combined in any suitable form. Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0044] In one embodiment of the present invention, a data transmission system based on an HSB bus is provided. The system includes an HSB bus and boards connected to the HSB bus. Both the central control PLC and the distributed PLC are equipped with a CPU and an FPGA. The FPGA includes a shared data RAM. The shared data RAM is used to store the board's own data and the data received when communicating with other boards through the HSB bus. The CPU reads and writes the shared data RAM through a memory mapping mechanism, thereby realizing data exchange and cooperation between the CPU and the FPGA.

[0045] In this invention, each board connected to the bus has a shared data RAM. When one board sends data, the other boards act as receivers to receive data from the bus. The FPGA on the receiving board stores the received data into the corresponding location in its shared data RAM according to the information in the data frame. Following a pre-assigned starting address transmission order, all boards sequentially send their own data while simultaneously receiving data from other boards. Within one HSB interrupt cycle, all boards exchange data, ensuring that their data RAMs contain the same data content, thus achieving data sharing, exchange, and synchronization.

[0046] In this embodiment, the HSB bus uses LVDS (Low Voltage Differential Signaling) bus mode, which includes six lines: one clock line (CLK), one control signal line (CTRL), and four data lines (DATA0-3). The clock line (CLK) provides a synchronization clock signal, ensuring all boards send and receive data at the same time. The control signal line (CTRL) controls bus access permissions and the start / end of data transmission. The data lines (DATA0-3) include four parallel data lines for transmitting 4-bit data. This bus design supports multiple boards sending and receiving data frames in a time-division multiplexing manner to achieve data sharing, exchange, and synchronization.

[0047] In this embodiment, both the central control PLC and the distributed PLC are equipped with a CPU and an FPGA. The CPU is the core processing unit of the board, responsible for executing control logic, programs, and interaction with external devices. It manages the main control tasks of the board and processes input / output signals. The FPGA is responsible for high-speed data transmission and real-time control on the bus. It ensures fast data transmission and processing through hardware acceleration, especially in applications with parallel tasks and high real-time requirements. The shared data RAM is stored in the FPGA, but the CPU can directly read and write to the shared data RAM through a memory mapping mechanism, thereby realizing data exchange and cooperation between the CPU and the FPGA.

[0048] Reference Figure 6 and Figure 7The shared data RAM is used to store the board's own data and data received when communicating with other boards via the HSB bus. Each board has its own independent shared data RAM, but all boards logically share the same data RAM, meaning they contain the same data content. This can be understood as each board connected to the bus having its own 4096-byte RAM. The shared data RAM is partitioned according to the board's configuration, reserving space for the data content of different boards. For example, bytes 0-64 store the data of the first board, bytes 65-127 store the data of the second board, and so on.

[0049] In addition to the shared data RAM that stores shared data, an FPGA also includes a separate register RAM, namely the configuration register. This hardware register controls and configures the internal functions of the FPGA. The CPU configures the FPGA hardware functions by writing data to this register RAM. Essentially, this process involves the CPU transferring data to the FPGA's register RAM through write operations, thereby controlling the FPGA's behavior or configuring its operating mode.

[0050] In a specific embodiment, the concept of nodes is introduced to control the data length of a single transmission. The data for each board is divided into multiple nodes, and each node contains a specific range of data bytes. Each node contains a maximum of 64 bytes of data, and each node contains only the data for one board. For example, PLC1 has two nodes with a starting node number of 0; node 0 contains bytes 0-63, and node 1 contains bytes 64. PLC2 has one node with a starting node number of 2; node 2 contains bytes 65-127. The node starting number is used to identify the order of each node, thus facilitating data organization and transmission. For example, the central control PLC with a starting address of 0 is configured to be the first board to send data.

[0051] Since all boards use the same clock signal CLK for synchronization, they can send and receive data at the same time. This timing synchronization mechanism ensures the correct transmission and reception of data on the bus.

[0052] In this embodiment, the board includes a central control PLC and a distributed PLC.

[0053] The central control PLC is the core control unit of the system. It is used to send start and interrupt signals to ensure synchronization and coordination between all boards. It is also responsible for the overall configuration and management of the system, including configuring the start address of each board and setting data transmission rules.

[0054] Specifically, the CPU of the central control PLC is used to start the entire system and send configuration requests during system startup or reconfiguration. It also aggregates the data volume of each distributed PLC, calculates the total data transmission volume, and allocates node information (including starting node number, starting address, byte length, and total number of nodes). Furthermore, it sends start and interrupt signals to ensure synchronization and coordination between all boards. It is also responsible for the overall configuration and management of the system, including configuring starting addresses for each board and setting data transmission rules. Finally, it executes control logic, programs, and interactions with external devices, processes input / output signals, and makes decisions and controls based on real-time data provided by the FPGA.

[0055] As another component in the system, the distributed PLC executes corresponding data transmission and processing tasks based on the configuration and management information of the central control PLC. It receives or sends data according to a preset transmission order to respond to instructions from the central control PLC or to communicate with other components.

[0056] Specifically, the CPU of the distributed PLC responds to the configuration request of the central control PLC, reports its own data volume, and processes the occupied data nodes on the FPGA of the distributed PLC according to the received node information; it receives data from other boards through the FPGA of the distributed PLC and stores this data in the shared data RAM; at the same time, it is also used to process this data and execute corresponding data transmission and processing tasks; it is used to communicate with the central control PLC and other distributed PLCs, receiving or sending data according to a preset sending order, in order to respond to the instructions of the central control PLC or to communicate with other boards.

[0057] The FPGA connected to the central control PLC is temporarily referred to as the main FPGA. Compared with other FPGAs, it has the additional function of controlling the entire bus transmission.

[0058] In a specific embodiment, an interrupt mode is set in the CPU of the central control PLC. The interrupt mode includes interrupt mode 0 and interrupt mode 1. Interrupt mode 0 is used to ensure real-time response and is suitable for latency-sensitive applications. Interrupt mode 1 reduces the CPU load by fixing the delay and is suitable for periodic data processing tasks.

[0059] The FPGA has a register that identifies the interrupt mode to be used. During initialization, the CPU of the central control PLC configures the interrupt mode to the aforementioned register in the FPGA. When the value is 0, interrupt mode 0 is used; when the value is 1, interrupt mode 1 is used.

[0060] Specifically, refer to Figure 4 and Figure 5 Two interrupt modes:

[0061] Interrupt mode 0 provides real-time response capabilities, ensuring that the PLC (central control PLC and distributed PLC) can process data from the FPGA in a timely manner. It is suitable for latency-sensitive applications such as real-time control or monitoring systems. Once the FPGA completes data exchange, it can trigger an interrupt to notify the PLC, thereby ensuring timely data transmission and processing.

[0062] Interrupt mode 1 is suitable for scenarios with relatively stable data processing, reducing the CPU's interrupt handling burden and making it suitable for tasks requiring periodic data acquisition. The fixed delay allows for better time management and is suitable for scheduling periodic tasks. The fixed interrupt delay for the PLC is provided.

[0063] Each time an HSB interrupt occurs on the FPGA, a complete data exchange is initiated, and the entire process is completed by the FPGA. During initialization, the CPU of the central control PLC configures the interrupt operation parameters, such as the interval between interrupts and the HSB cycle, for the FPGA. After completing a data exchange, the FPGA generates an interrupt according to the configured interrupt mode. Upon receiving this interrupt, the CPU of the central control PLC performs corresponding read / write operations and other tasks.

[0064] In this embodiment, the FPGA is equipped with a transmitting module and a receiving module.

[0065] The transmitting module is used to send data to the bus in a predetermined format according to the relevant registers configured by the CPU when an FPGA timer interrupt occurs. Data transmission begins in a pre-assigned order. The FPGA with node number one sends a data frame to the bus, and FPGAs on other boards listen for control signals and data on the bus. The data frame format includes a start flag, data length, data content, checksum, and end flag.

[0066] Referring to Table 1, the format of the entire data frame transmission is as follows:

[0067] 2B (starting address) + 2B (byte length) + data + CRC (2 bytes).

[0068] Table 1. Format of data frame transmission

[0069]

[0070] The receiving module's task is to receive data from the bus in real time. Based on the relevant register configurations and the characteristics of its board, it parses the received data and stores it in the corresponding location in the shared data RAM according to the control information in the data frame. Simultaneously, the FPGA verifies the data to ensure its correctness. Since the data frame contains a checksum, it is used to monitor for errors that may occur during data transmission. If other FPGAs on different boards detect a checksum mismatch, it indicates an error has occurred during data transmission. In this case, appropriate error handling measures can be taken, such as requesting a retransmission of the data frame. For example, if the checksum is a CRC checksum, no action is taken if the CRC values ​​match; otherwise, a 0x55aa signal is sent to the bus. The FPGA with node number one, upon receiving this signal, retransmits the data sequentially, up to a maximum of two times.

[0071] Once data transmission for one node is complete and there are no retransmission signals on the bus, the FPGA with node two sends data to the bus, repeating this process until the FPGA with the last node finishes sending data to the bus. It's important to note that if a board fails to complete data transmission or reception within the predetermined time, other boards can assume that the board has malfunctioned or experienced a timeout error and take appropriate measures, such as skipping the data transmission and reception of that board.

[0072] If the receiving module on the board detects that the received data is the last node value sent by the previous board, and no other board has sent a retransmission signal after receiving this node value, then the receiving module will notify the sending module to start the sending function of this board.

[0073] Within an HSB interrupt cycle—the period during which all boards complete one data transmission and reception cycle—the data RAM of all boards is updated to contain the same data. This allows each board to access the latest data, achieving data sharing, exchange, and synchronization.

[0074] In a specific embodiment, the sending module is divided into three state machines, such as... Figure 8 As shown in the state machine diagram.

[0075] T01 indicates CPU configuration startup + board startup signal transmission; T11 indicates data transmission completed; T21 indicates fixed waiting time completed.

[0076] The empty state refers to the state at power-on, during reset, or before transmission is initiated. When the board is powered on or reset, the FPGA's transmission module is in the empty state by default; this is the initial state of the transmission module. In the initial state, the FPGA continuously monitors three signals: The first signal is the start transmission signal, which only exists on the central control PLC. The CPU of the central control PLC sends a start command to the FPGA. Only when the CPU allows the FPGA to start the transmission task can the FPGA transmit data according to the rules mentioned earlier. The second signal is the interrupt signal, which only exists on the central control PLC. The FPGA only starts once each time it starts data interaction after monitoring this signal, especially the central control PLC with a configuration start address of 0, because the central control PLC with a configuration start address of 0 is the first board to transmit data. The third signal monitors the data transmitted on the bus and whether it is the board's turn to start next time. If it is, then it starts transmitting data in the next transmission; if not, it continues to be in the receiving state.

[0077] The data transmission status includes the starting address, length, and data. When the FPGA detects the relevant start transmission signal and jumps to the data transmission status, it will first transmit the starting address according to the data format described earlier. The starting address for the first transmission of all boards is the starting address configured by the CPU (CPU of the central PLC and distributed PLC). For example, board 1's starting address is 0 because the RAM's starting address is 0. The FPGA will calculate the total number of nodes to be transmitted based on the starting address configured by the CPU and the data length register. For example, if the starting address is configured as 0 and the data length is configured as 258 bytes, the FPGA will calculate that two nodes need to be transmitted. The first node transmits data with a length of 256 bytes, and the second node transmits data with a length of 2 bytes. When board 1 is in this status for the first time, the FPGA transmits data with a starting address of 0 and a byte length of 256 + 2, i.e., ... The first transmission in this state starts at address 256 and has a length of 2+2 bytes (2 bytes + 2 CRC values), followed by data and CRC.

[0078] The waiting state is used to wait for a response from the receiving board, and it waits for a fixed 8 CLK cycles. If the data 0x55aa55aa is received in this state, it indicates a transmission error, and the system jumps to an empty state to retransmit the previously received data. If the received data is not 0x55aa55aa, it indicates a correct transmission, and the system jumps to an empty state to continue subsequent transmissions.

[0079] The receiving module has three states, and the specific state machine is as follows: Figure 9As shown, T02 indicates that the control enable signal is high, T12 indicates that data reception is complete, and T22 indicates that the fixed waiting time is complete.

[0080] When the receiving module is powered on or in a reset state, it jumps to the idle state. In this state, the FPGA constantly monitors the changes in the control signals on the bus. If the control signal goes high, it indicates that data has been sent to the bus, and the receiving module's state machine will then jump to the receive comparison state.

[0081] The receive comparison state indicates that the current state is either the data receiving state or the CRC comparison state. In the receive state, the FPGA receives data transmitted from the data bus and, based on the content of the data, determines the address to which the data should be written, the length of the data, and other control signal content in the transmitted data message. At the same time, it calculates the CRC check based on the received data. After receiving the data, it compares the received CRC data with its own calculated CRC data. If they match, the matching flag is set high; if they do not match, the matching flag is pulled low, and then the process jumps to the feedback state.

[0082] The feedback status consists of 8 CLK cycles. The first two cycles are designated as idle cycles, meaning all boards do nothing. In cycles 3-6, if a board receives incorrect data, it will send 0x55aa55aa to the bus. Boards that previously sent data will then retransmit their data upon receiving this feedback. In the last two cycles, all boards do nothing. Instead, they receive feedback information from the bus and are told whether they are ready to receive new data, or it's their turn to send data.

[0083] Based on the same inventive concept, embodiments of the present invention also provide an HSB bus-based data transmission method for implementing the aforementioned HSB bus-based data transmission system. The solution provided by this system is similar to the implementation described in the above method; therefore, the specific limitations in one or more system embodiments provided below can be found in the above-described limitations regarding the HSB bus-based data transmission system, and will not be repeated here.

[0084] In one embodiment, refer to Figure 10 This paper provides a data transmission method based on the HSB bus, which includes the following steps:

[0085] Step 100: When data transmission begins, the board's sending module sends the data frames within the board to the bus according to the pre-configured information and a predetermined format.

[0086] After the data is sent, the sending module enters a waiting state, waiting for feedback from the receiving module;

[0087] Step 200: The receiving modules of other boards monitor the data on the bus. When data transmission is detected, they start receiving data. The receiving modules write the received data to the corresponding location in the RAM according to the content of the data.

[0088] The receiving module calculates the CRC of the received data and compares it with the received CRC. If the CRCs match, it continues to receive subsequent data or prepares to send data from this board. If they do not match, it sends a 0x55aa signal to the bus to request retransmission.

[0089] After receiving a retransmission signal, the sending module will retransmit the previous data; if the number of retransmissions exceeds the set value, such as 2 times, the transmission will stop and the CPU will be notified.

[0090] Step 300: When all boards have completed one data transmission and reception cycle and no CRC error is detected, the data exchange of one HSB cycle is completed; each board will determine whether the entire transmission process is complete based on the total number of nodes.

[0091] Before the data transmission begins, the process includes: connecting multiple boards to the HSB bus, setting up an FPGA and shared data RAM on each board, configuring the shared data RAM of each board, and reserving partitions for the data content of each board; during initialization, the central control PLC configures the interrupt operation parameters to the FPGA and sets the interrupt mode; the FPGA performs initialization settings according to the received configuration parameters and prepares to enter the data transmission state.

[0092] Before the data transmission begins, data preparation and node partitioning are also included: a visual configuration tool is set up, and when configuring PLC functions using the tool, the data size occupied by each board is pre-divided. The central PLC and distributed PLC are aware of the area partitioning when the system starts.

[0093] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A data transmission system based on an HSB bus, characterized in that, Suitable for industrial control applications, the system includes an HSB bus and a central control PLC connected to the HSB bus, as well as multiple distributed PLCs, where each PLC is considered as a board. Both the central control PLC and the distributed PLC are equipped with a CPU and an FPGA. The FPGA includes a shared data RAM, which stores the board's own data and data received when communicating with other boards via the HSB bus. The shared data RAM reserves partitions for the data content of different boards according to the board's configuration. The data of each board is divided into multiple nodes, and each node contains a preset range of data bytes. The node start number is used to identify the order of each node, facilitating data organization and transmission. The CPU reads and writes to the shared data RAM through a memory mapping mechanism, thereby realizing data exchange and cooperation between the CPU and the FPGA. The FPGA is equipped with a transmitting module and a receiving module; The transmitting module includes: an empty state, which is the state when powered on, reset, or before starting to transmit; the empty state monitors three signals, including the start transmitting signal, the interrupt signal, and the data transmitted on the bus, and monitors whether it is the turn of this board to start next; the transmit data state is used to transmit data according to the data frame format; the wait state is used to wait for the response from the receiving board, which is fixed at 8 CLK cycles. The receiving module includes: an idle state for monitoring changes in control signals on the bus; a receive comparison state for receiving data transmitted from the data bus, judging the received data, and performing CRC verification based on the received data; and a feedback state for sending a retransmission request when a verification error occurs. The HSB bus uses the LVDS bus method and includes a clock CLK line, a control signal CTRL line, and a data bus. During the HSB interrupt cycle, all boards exchange data with each other, so that the data RAM in the boards has the same data content.

2. The data transmission system based on the HSB bus according to claim 1, characterized in that, The clock CLK line is used to provide a synchronous clock signal, ensuring that all boards send and receive data at the same time. The control signal CTRL line is used to control bus access permissions and the start or end of data transmission. The data bus is used to transmit data.

3. The data transmission system based on the HSB bus according to claim 1, characterized in that, The FPGA also includes a configuration register, through which the CPU configures the FPGA.

4. A data transmission system based on an HSB bus according to claim 1, characterized in that, The central control PLC is used to send a configuration request and summarize the data volume of each distributed PLC when the system starts up or is reconfigured, so as to calculate the total data transmission volume and allocate node information; the distributed PLC is used to respond to the configuration request of the central control PLC, report its own data volume, and process the data nodes it occupies on its FPGA according to the received node information.

5. A data transmission system based on an HSB bus according to claim 4, characterized in that, The sending module is used to send data to the bus in a predetermined format when an FPGA timer interrupt occurs. The receiving module is used to receive data from the bus in real time. Based on the pre-configuration and the condition of the board, it parses the received data and stores it in the corresponding location of the shared data RAM according to the control information in the data frame.

6. A data transmission system based on an HSB bus according to claim 5, characterized in that, The data frame format includes a start address, byte length, data content, checksum, and end marker.

7. A data transmission system based on an HSB bus according to claim 6, characterized in that, The receiving module is also used to verify the data frame to ensure the correctness of the data; if the verification code is incorrect, it indicates that an error has occurred in the data transmission process, and a request is made to retransmit the data frame.

8. A data transmission method based on an HSB bus, used in a data transmission system based on an HSB bus as described in any one of claims 1-7, characterized in that, Includes the following steps: Step 100: When data transmission begins, the sending module of one board sends the data frames within the board to the bus in a predetermined format according to the pre-configured information. After the data is sent, the sending module enters a waiting state, waiting for feedback from the receiving module; Step 200: The receiving modules of other boards monitor the data on the bus, and when data transmission is detected, they start receiving data; The receiving module writes the received data into the corresponding location in the RAM according to the data content. The receiving module calculates the checksum of the received data and compares it with the received checksum. If the checksums match, it continues to receive subsequent data or prepares to send data for this board. If there is a discrepancy, a retransmission request is sent to the bus. After receiving a retransmission signal, the sending module will retransmit the previous data; Step 300: When all boards have completed one data transmission and reception cycle and no checksum error is detected, the data exchange of one HSB cycle is complete; Each board will determine whether the entire transmission process is complete based on the total number of nodes.

9. A data transmission method based on an HSB bus according to claim 8, characterized in that, Before the data transmission begins, the following steps are included: A central control PLC and multiple distributed PLCs are connected to the HSB bus, where each PLC is considered a board. Both the central control PLC and the distributed PLCs are equipped with a CPU and an FPGA. The FPGA includes a shared data RAM, with a reserved partition for the data content of each board. The central control PLC is configured with an interrupt mode.

10. A data transmission method based on an HSB bus according to claim 9, characterized in that, Before the data transmission begins, data preparation and node division are also included: the data size occupied by each board is determined in advance, that is, the central control PLC and the distributed PLC have known their respective data areas in the shared data RAM in advance when the system starts.

Images