Signal transmitter based on universal serial bus protocol and handshake method thereof

Abstract

The invention discloses a signal transmitter based on a universal serial bus protocol and a handshake method thereof, and relates to the technical field of signal transmission. The signal transmitter comprises a driving circuit, a control circuit and a clamping circuit. The driving circuit adjusts the level of a signal pad according to a data signal in a handshake stage so as to carry out speed negotiation with an electronic device. The control circuit generates a clamping signal according to an operation mode signal and a transmission effective signal in a universal serial bus protocol. A clamp circuit is activated in the handshake phase in accordance with the clamp signal to limit the level of the signal pad.

Description

Technical Field

[0001] The present application relates to the technical field of signal transmission, and in particular to a signal transmitter based on a universal serial bus protocol and a handshake method thereof. Background Art

[0002] Universal serial bus is commonly used in various electronic devices to transfer data to each other. Before data transmission, the host device and the device device will handshake based on the USB protocol to confirm the transfer speed that both parties can support. In existing electronic devices, due to the influence of process variation, the resistance value of resistors and / or transistors may change, causing the level on the signal pad or pin to become too high during the handshake phase, causing abnormal speed negotiation. Summary of the invention

[0003] One of the purposes of the present application is to provide a signal transmitter and a handshake method thereof that can provide voltage protection during a handshake phase, so as to improve the deficiencies of the prior art.

[0004] In some embodiments, the signal transmitter includes a driving circuit, a control circuit, and a clamping circuit. The driving circuit adjusts the level of a signal pad according to a data signal in a handshake phase to negotiate speed with an electronic device. The control circuit generates a clamping signal according to an operation mode signal and a transmission valid signal in a universal serial bus protocol. The clamping circuit is activated according to the clamping signal in the handshake phase to limit the level of the signal pad.

[0005] In some embodiments, a handshake method performed by a signal transmitter includes the following operations: in a handshake phase, adjusting the level of a signal pad according to a data signal to negotiate speed with an electronic device; generating a clamp signal according to an operation mode signal in a universal serial bus protocol and a transmission valid signal; and activating a clamp circuit in the signal transmitter in the handshake phase according to the clamp signal to limit the level of the signal pad through the clamp circuit.

[0006] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a signal transmitter according to some embodiments of the present application;

[0008] Figure 2 According to some embodiments of the present application Figure 1 A schematic diagram of the control circuit in FIG.

[0009] Figure 3According to some embodiments of the present application Figure 1 A schematic diagram of the operation timing of the clamp signal, the operation mode signal and the line status between the signal transmitter and the electronic device; and

[0010] Figure 4 An operation flow chart of a handshake method is drawn according to some embodiments of the present application.

[0011] 100: signal transmitter;

[0012] 101: Electronic devices;

[0013] 110: driving circuit;

[0014] 120: control circuit;

[0015] 130: clamping circuit;

[0016] 210: Logic gates;

[0017] 220: Inverter;

[0018] 400: handshake method;

[0019] AVDD1, AVDD2: power supply voltage;

[0020] HSCJ: clamp signal;

[0021] DN, DP: data signal;

[0022] MN1~MN3, MP1: transistor;

[0023] OpMode[1:0]: operation mode signal;

[0024] OpMode(1): first bit;

[0025] OpMode(0): second bit;

[0026] P1: signal pad;

[0027] RDN: pull-down resistor;

[0028] RT1, RT2: terminal resistance;

[0029] RUP: pull-up resistor;

[0030] S1: signal;

[0031] S410, S420, S430: operation;

[0032] TxValid: Transmits a valid signal. DETAILED DESCRIPTION

[0033] All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries, including any use examples of the words discussed herein in the content of this application are only examples and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0034] As used herein, "coupled" or "connected" may refer to two or more elements making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or may refer to two or more elements operating or acting on each other. As used herein, the term "circuit" may refer to a device composed of at least one transistor and / or at least one active and passive element connected in a certain manner to process signals.

[0035] Figure 1 A schematic diagram of a signal transmitter 100 is drawn according to some embodiments of the present application. In some embodiments, the signal transmitter 100 can be applied to a host device using a universal serial bus (USB) protocol, but the present application is not limited thereto.

[0036] The signal transmitter 100 includes a driving circuit 110, a control circuit 120, a clamping circuit 130, a terminal resistor RT1, and a pull-down resistor RDN. The driving circuit 110 adjusts the level of the signal pad P1 according to the data signal DP and the data signal DN in the handshake phase to negotiate the speed with the electronic device 101. For example, in the handshake phase, the driving circuit 110 may send a chirp (or pulse; chirp) signal according to the data signal DP and the data signal DN to communicate with the electronic device 101. In some embodiments, the electronic device 101 may be a device end using a USB protocol. In some embodiments, the driving circuit 110 may be, but not limited to, a voltage mode driving circuit. For example, the driving circuit 110 may include a transistor MN1 and a transistor MN2. The first end (e.g., the drain) of the transistor MN1 receives the power supply voltage AVDD1, the second end (e.g., the source) of the transistor MN1 is coupled to the signal pad P1 through the terminal resistor RT1, and the control end (e.g., the gate) of the transistor MN1 receives the data signal DP. The first end of transistor MN2 is coupled to the second end of transistor MN1, the second end of transistor MN2 is coupled to ground, and the control end of transistor MN2 receives data signal DN. The first end of pull-down resistor RDN is coupled to terminal resistor RT1 and signal pad P1, and the second end of pull-down resistor RDN is coupled to ground.

[0037] The control circuit 120 generates the clamp signal HSCJ according to the operation mode signal OpMode[1:0] and the transmission valid signal TxValid in the USB protocol. In some embodiments, the aforementioned USB protocol may be a USB 2.0 protocol. In some embodiments, the operation mode signal OpMode[1:0] is a two-bit signal, which is used to indicate the operation that the device should perform. In some embodiments, the transmission valid signal TxValid is used to indicate whether the device is transmitting valid data. In some embodiments, the signal transmitter 100 also includes a USB controller, which can generate the aforementioned operation mode signal OpMode[1:0] and the transmission valid signal TxValid based on the USB protocol. For example, when the first and second bits of the operation mode signal OpMode[1:0] are both logic values ​​0 (i.e., the operation mode signal OpMode[1:0] is 00), it means that the signal transmitter 100 is in the normal operation stage. When the first bit of the operation mode signal OpMode[1:0] is logic value 1 and its second bit is logic value 0 (i.e., the operation mode signal OpMode[1:0] is 10), it means that the signal transmitter 100 is in the handshake stage. During the handshake phase, the electronic device 101 may start to send a chirp signal (e.g. Figure 3 The signal transmitter 100 may send out a chirp signal (e.g., a chirp KJ signal) to inquire whether the signal transmitter 100 supports the signal transmission in the high speed mode. If the signal transmitter 100 supports the signal transmission in the high speed mode, the signal transmitter 100 may send out an alternating chirp signal (e.g., a chirp KJ signal) according to the data signal DP and the data signal DN, so that the electronic device 101 and the signal transmitter 100 may switch to the high speed mode; or, if the signal transmitter 100 does not support the high speed mode, the electronic device 101 and the signal transmitter 100 may maintain the data transmission in the full speed mode. The above operation process in the handshake phase is equivalent to the aforementioned speed negotiation.

[0038] The clamp circuit 130 is activated in the handshake phase according to the clamp signal HSCJ to limit the level of the signal pad P1. In the handshake phase, when the signal pad P1 is used to transmit the chirp J signal, the data signal DP is at a high level (e.g., a logic value of 1) and the data signal DN is at a low level (e.g., a logic value of 0), so that the transistor MN1 is turned on. At the same time, the interface circuit connected to the signal pad P1 in the electronic device 101 transmits the power supply voltage AVDD2 through the pull-up resistor RUP, wherein the level of the power supply voltage AVDD2 is higher than the level of the power supply voltage AVDD1. For example, the power supply voltage AVDD2 may be approximately 3.3 volts, and the power supply voltage AVDD1 may be approximately 0.8 volts. Under this condition, since the electronic device 101 does not connect its characteristic impedance (i.e., the terminal resistor RT2, which may be approximately, but not limited to, 45 ohms) to the signal pad P1 (hence drawn with a dotted line), the level of the signal pad P1 becomes higher, thereby causing the on-resistance of the transistor MN1 to become higher. On the other hand, since the pull-up resistor RUP and the transistor MN1 in the electronic device 101 divide the power supply voltage AVDD1 and the power supply voltage AVDD2, the level of the signal pad P1 is further increased. Due to the influence of actual process variation, the on-resistance of the transistor MN1 and the resistance of the pull-up resistor RUP will also change, making the level of the signal pad P1 susceptible to the above-mentioned variation. In order to prevent the level of the signal pad P1 from being too high during the handshake phase and causing the speed negotiation to fail, the clamp circuit 130 can be activated during the handshake phase according to the clamp signal HSCJ to reduce the level of the signal pad P1, thereby limiting the level of the signal pad P1 to the voltage range defined in the USB protocol.

[0039] In some embodiments, the clamp circuit 130 includes a transistor MP1 and a transistor MN3. The first end (e.g., source) of the transistor MP1 is coupled to the second end of the transistor MN1 and is coupled to the signal pad P1 through the terminal resistor RT1, the second end (e.g., drain) of the transistor MP1 is coupled to the first end of the transistor MN3, and the control end (e.g., gate) of the transistor MP1 receives the clamp signal HSCJ. The second end of the transistor MN3 is coupled to the ground, and the control end of the transistor MN3 is coupled to the first end of the transistor MN3. In other words, the transistor MN3 is a diode-connected transistor to operate as a diode and is coupled between the transistor MP1 and the ground. The transistor MP1 can be turned on according to the clamp signal HSCJ to couple the signal pad P1 to the ground through the transistor MN3. The above-mentioned configuration of the clamp circuit 130 is for example only, and various configurations of the clamp circuit 130 that can achieve the same limiting potential are all within the scope of the present application.

[0040] Figure 2 According to some embodiments of the present application, Figure 1Schematic diagram of the control circuit 120 in . In some embodiments, the control circuit 120 may include a logic gate 210 and an inverter 220. In some embodiments, the logic gate 210 may be, but is not limited to, a NAND gate. The logic gate 210 generates a clamp signal HSCJ based on the first bit (labeled as OpMode(1)) in the operation mode signal OpMode[1:0], the signal S1, and the transmit valid signal TxValid. The inverter 220 generates the signal S1 based on the second bit (labeled as OpMode(0)) in the operation mode signal OpMode[1:0]. The above-mentioned setting method of the control circuit 120 is used as an example. Various setting methods of the control circuit 120 that can perform clamp control in the handshake phase based on the relevant control signals in the USB specification are all within the scope of this application.

[0041] Figure 3 According to some embodiments of the present application, Figure 1 FIG. 1 is a schematic diagram of the operation timing of the clamp signal HSCJ, the operation mode signal OpMode[1:0], and the line state between the signal transmitter 100 and the electronic device 101. Figure 3 As shown, in the initial time period, the operation mode signal OpMode[1:0] is 00 (ie, the first bit OpMode(1) and the second bit OpMode(0) are both logic 0), and the transmission valid signal TxValid has a logic value of 1. Under this condition, the signal transmitter 100 is in a normal operation stage.

[0042] Next, the operation mode signal OpMode[1:0] is switched to 10 (i.e., the first bit OpMode(1) is a logic value of 1, and the second bit OpMode(0) is a logic value of 0). Under this condition, the signal transmitter 100 is in the handshake phase and starts speed negotiation. Accordingly, the line state of the signal transmitter 100 is switched to single-ended ground (Single-Ended Zero, SE0), for example, the data signal DP is a low level (e.g., a logic value of 0) and the data signal DN is a high level (e.g., a logic value of 1), so that the transistor MN 2 is turned on and grounded, thereby pulling down the level of the signal pad P1. When the electronic device 101 detects this state, the electronic device 101 starts to send a chirp K signal. In response to the chirp-K signal, the signal transmitter 100 can reset the line state to single-ended ground (SE0) again, and the driving circuit 110 can start to send a chirp-KJ signal based on the data signal DP and the data signal DN. At the same time, the transmission valid signal TxValid switches from a low level to a high level to indicate that the signal transmitter 100 is sending a valid data signal. Under this condition, the signal transmitter 100 can notify the electronic device 101 through the above-mentioned chirp-KJ signal during the handshake phase that the high-speed mode can be used for data transmission to complete the speed negotiation.

[0043] It can be seen from the above waveform that when entering the handshake stage, the operation mode signal OpMode[1:0] is switched to 10; further, when the signal transmitter 100 sends a chirp signal (i.e., the aforementioned chirp-KJ signal) in the handshake stage, the transmission valid signal TxValid is switched to a high level corresponding to a logic value of 1. Under this condition, the control circuit 120 can generate a clamp signal HSCJ with a logic value of 0 to turn on the Figure 1 The transistor MP1 of the driving circuit 110 is activated to activate the clamp circuit 130 to limit the level of the signal pad P1. In other words, when the operation mode signal OpMode[1:0] has a predetermined state (i.e., the aforementioned 10) and the transmission valid signal TxValid is a predetermined logic value (such as a logic value 1), the clamp circuit 130 can be activated accordingly to limit the level of the signal pad P1. Similarly, the clamp circuit 130 is activated when the driving circuit 110 sends a chirp signal during the handshake phase. On the other hand, when the operation mode signal OpMode[1:0] does not have the predetermined state or the transmission valid signal TxValid is not the predetermined logic value, the clamp circuit 130 is not activated to avoid affecting the normal operation of the driving circuit 110.

[0044] It should be understood that the signal transmitter 100 may also include a circuit portion for processing another signal pad, for example, Figure 1The signal pad P1 corresponds to the pin D+ in the USB interface, and the other signal pad corresponds to the pin D- in the USB interface. Figure 1 The circuit configuration shown is the same, so it will not be repeated here.

[0045] Figure 4 The following is a flowchart of an operation of a handshake method 400 according to some embodiments of the present application. In some embodiments, the handshake method 400 may be, but is not limited to, Figure 1 The signal transmitter 100 is executed. In operation S410, in a handshake phase, the level of a signal pad is adjusted according to a data signal to negotiate a speed with an electronic device. In operation S420, a clamp signal is generated according to an operation mode signal and a transmission valid signal in a universal serial bus protocol. In operation S430, a clamp circuit in the signal transmitter is activated in the handshake phase according to the clamp signal to limit the level of the signal pad through the clamp circuit.

[0046] The description of the multiple operations of the handshake method 400 can refer to the aforementioned multiple embodiments, so it will not be repeated here. The above multiple operations are only examples and are not limited to being performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present application, the various operations under the handshake method 400 can be appropriately increased, replaced, omitted or performed in a different order. Alternatively, one or more operations under the handshake method 400 can be performed simultaneously or partially simultaneously.

[0047] In summary, the signal transmitter and handshake method provided in some embodiments of the present application provide voltage protection in the handshake stage to prevent the signal pad level from being erroneously too high in the handshake stage, thereby improving the correctness of the negotiation verification in the handshake stage.

[0048] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Technicians in this technical field may change the technical features of the present application based on the explicit or implicit contents of the present application. All these changes may fall within the scope of patent protection sought by the present application. The scope of patent protection of the present application shall be based on the scope of the patent application of this specification.

Claims

1. A signal transmitter, characterized in that: include: a driving circuit that adjusts a level of a signal pad according to a data signal in a handshake phase to perform speed negotiation with an electronic device; A control circuit generates a clamp signal according to an operation mode signal and a transmission valid signal in a universal serial bus protocol; as well as A clamp circuit is activated according to the clamp signal in the handshake phase to limit the level of the signal pad.

2. The signal transmitter according to claim 1, characterized in that: The control circuit comprises: a logic gate, generating the clamp signal according to a first bit of the operation mode signal, a first signal and the transmit valid signal; and An inverter generates the first signal according to a second bit of the operation mode signal.

3. The signal transmitter according to claim 2, characterized in that: The logic gate is a NAND gate.

4. The signal transmitter according to claim 1, characterized in that: When the operation mode signal has a predetermined state and the transmit valid signal has a predetermined logic value, the clamp circuit is activated to limit the level of the signal pad.

5. The signal transmitter according to claim 4, characterized in that: When the operation mode signal does not have the predetermined state or the emission valid signal does not have the predetermined logic value, the clamp circuit is not activated.

6. The signal transmitter according to claim 1, characterized in that: The clamp circuit is activated when the driving circuit sends a chirp signal in the handshake phase to limit the level of the signal pad.

7. The signal transmitter according to claim 1, characterized in that: The clamping circuit comprises: a first transistor coupled to the signal pad and turned on according to the clamp signal; and A second transistor is coupled between the first transistor and ground and operates as a diode.

8. A handshake method, characterized in that: Executed by a signal transmitter, the handshake method includes: In a handshake phase, adjusting a level of a signal pad according to a data signal to perform speed negotiation with an electronic device; generating a clamp signal according to an operation mode signal and a transmission valid signal in a universal serial bus protocol; and A clamp circuit in the signal transmitter is activated in the handshake phase according to the clamp signal, so as to limit the level of the signal pad through the clamp circuit.

9. The handshake method according to claim 8, characterized in that: Generating the clamp signal according to the operation mode signal and the transmit valid signal in the universal serial bus protocol comprises: generating the clamp signal according to a first bit of the operation mode signal, a first signal and the transmission valid signal through a NAND gate in the signal transmitter; and The first signal is generated according to a second bit of the operation mode signal by an inverter in the signal transmitter.

10. The handshake method according to claim 8, characterized in that: Activating a clamp circuit in the signal transmitter in the handshake phase according to the clamp signal to limit the level of the signal pad through the clamp circuit includes: Turning on a first transistor in the clamp circuit according to the clamp signal, wherein the first transistor is coupled to the signal pad; and The first transistor is coupled to ground via a second transistor in the clamp circuit, wherein the second transistor operates as a diode.

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