Clock data recovery device and method

Abstract

The present application discloses a clock data recovery device, wherein a differential conversion module converts a serial signal into a single-bit signal, a delay module processes the single-bit signal to obtain a delayed data signal, a sampling module samples and obtains target sampling data, a transition edge detection module performs an XOR operation on the target sampling data to obtain current data transition phase information, a storage module stores a mapping relationship between the sampling phase and an ideal data transition phase sequence, a phase adjustment module determines an ideal data transition phase sequence corresponding to the current sampling phase, adjusts the current data transition phase information, searches for a sampling phase offset result in a phase adjustment table based on the adjusted data transition phase information, adjusts the current sampling phase based on the search result, obtains an optimal sampling phase, and a data clock recovery module performs data and clock recovery on the target sampling data based on the optimal sampling phase, thereby being able to quickly lock the clock to be recovered and improving the efficiency of clock locking.

Description

Technical Field

[0001] The present application relates to the technical field of clock data recovery, and in particular to a clock data recovery device and method. Background Art

[0002] In high-speed serial data communication, in order to save overhead, only data signals are generally transmitted without transmitting clock signals synchronized with the data signals. The clock is embedded in the data at the transmitting end, and the clock data recovery circuit is used at the receiving end to extract the clock from the received data. The clock data recovery circuit includes a phase detector, a loop filter, and a voltage-controlled oscillator. It receives serial data, obtains a clock equivalent to the data rate according to the frequency multiplication of the low-speed reference clock connected, selects the appropriate data sampling phase according to the phase detector, and fine-tunes the clock to obtain the clock locked with the data, thereby recovering the correct clock and data. This function is generally placed inside the FPGA chip in the form of a hard-core IP, corresponding to a dedicated SerDes interface and the circuit design is complex, so high-end chips are selected to implement the functional design, which will lead to higher product costs, and complex circuit design leads to increased chip power consumption. In addition, due to the high data transmission rate in the serial bus, the design of the clock data recovery circuit is complex, resulting in a longer time to lock the clock. Summary of the invention

[0003] The purpose of the present application is to provide a clock data recovery device, which can quickly lock the clock to be recovered, improve the efficiency of clock locking, and reduce the time of locking the clock.

[0004] In a first aspect, the present application provides a clock data recovery device, the device comprising:

[0005] A differential conversion module, used for converting the serial signal to be recovered into a single-bit signal;

[0006] The delay module is used to perform multi-stage delay processing on the single-bit signal to obtain multi-channel delayed data signals;

[0007] A sampling module is used to sample each delayed data signal to obtain a set of sampling data with eight different sampling phases, and to splice the obtained multiple sets of sampling data to obtain target sampling data;

[0008] A transition edge detection module is used to perform an XOR operation on the target sampled data and obtain the current data transition phase information based on the result of the XOR operation;

[0009] A storage module, used for storing a mapping relationship between a sampling phase and an ideal data transition phase sequence;

[0010] A phase adjustment module, used to determine in the storage module an ideal data jump phase sequence corresponding to the current sampling phase of the local clock, perform bit position adjustment on the current data jump phase information according to the ideal data jump phase sequence to obtain adjusted data jump phase information, search for a sampling phase offset result in a phase adjustment table based on the adjusted data jump phase information, and cyclically adjust the current sampling phase based on the sampling phase offset result to obtain an optimal sampling phase of the local clock, wherein the mapping relationship between the data jump phase information and the sampling phase offset information is stored in the phase adjustment table;

[0011] The data clock recovery module performs data recovery on the target sampled data based on the optimal sampling phase to obtain a recovered data signal, and determines a recovered clock signal based on the recovered data signal.

[0012] Furthermore, the delay module includes eight cascaded delay units, each delay unit has the same input-to-output delay time, the eight delay units are a first delay unit, a second delay unit, a third delay unit, a fourth delay unit, a fifth delay unit, a sixth delay unit, a seventh delay unit and an eighth delay unit, a single-bit signal is input into the eight delay units in sequence, and each delay unit outputs a corresponding delayed data signal to obtain eight delayed data signals, wherein the eight delayed data signals have the same data content but different data delays, and the data delays of the eight delayed data signals increase in sequence with the delay time as a step size, with one eighth of a data cycle of the serial signal to be recovered as the delay time.

[0013] Further, the sampling module includes eight sampling units, and the eight sampling units are a first sampling unit, a second sampling unit, a third sampling unit, a fourth sampling unit, a fifth sampling unit, a sixth sampling unit, a seventh sampling unit and an eighth sampling unit, wherein the first sampling unit is connected to the first delay unit, the second sampling unit is connected to the second delay unit, the third sampling unit is connected to the third delay unit, the fourth sampling unit is connected to the fourth delay unit, the fifth sampling unit is connected to the fifth delay unit, the sixth sampling unit is connected to the sixth delay unit, the seventh sampling unit is connected to the seventh delay unit, and the eighth sampling unit is connected to the eighth delay unit, and the sampling phase of the first sampling unit is set to correspond to the first sampling phase, the sampling phase of the second sampling unit is set to correspond to the second sampling phase, the sampling phase of the third sampling unit is set to correspond to the third sampling phase, the sampling phase of the fourth sampling unit is set to correspond to the fourth sampling phase, the sampling phase of the fifth sampling unit is set to correspond to the fifth sampling phase, the sampling phase of the sixth sampling unit is set to correspond to the sixth sampling phase, the sampling phase of the seventh sampling unit is set to correspond to the seventh sampling phase, and the sampling phase of the eighth sampling unit is set to correspond to the eighth sampling phase, wherein,

[0014] Based on each sampling clock, eight delayed data signals input by eight sampling units are sampled respectively to obtain a set of eight-bit sampling data with eight different sampling phases;

[0015] Based on a continuous eight-beat sampling clock, eight continuous eight-way delayed data signals are sampled to obtain eight groups of eight-bit sampling data, and the eight groups of eight-bit sampling data are spliced ​​to obtain 64 bits of target sampling data, wherein the eight eight-way delayed data signals are obtained based on eight single-bit signals of the continuous input delay module.

[0016] Furthermore, the transition edge detection module is specifically used for:

[0017] Perform an XOR operation on each bit in the target sampled data and the adjacent bit to obtain 64 bits of first data transition information;

[0018] The 64-bit first data jump information is divided into eight groups with eight bits of data as a group to obtain eight groups of second data jump information, and an XOR operation is performed on each identical bit in the eight groups of second data jump information to obtain eight bits of current data jump phase information, wherein the bit order of the eight bits of current data jump phase information is bit7~bit0 from the highest bit to the lowest bit.

[0019] Further, the first sampling phase is represented by 0, the second sampling phase is represented by 1, the third sampling phase is represented by 2, the fourth sampling phase is represented by 3, the fifth sampling phase is represented by 4, the sixth sampling phase is represented by 5, the seventh sampling phase is represented by 6, and the eighth sampling phase is represented by 7;

[0020] The storage module is specifically used for:

[0021] If the sampling phase is 0, the corresponding ideal data transition phase sequence is 4 3 2 1 0 7 6 5;

[0022] If the sampling phase is 1, the corresponding ideal data transition phase sequence is 5 4 3 2 1 0 7 6;

[0023] If the sampling phase is 2, the corresponding ideal data transition phase sequence is 6 5 4 3 2 1 0 7;

[0024] If the sampling phase is 3, the corresponding ideal data transition phase sequence is 7 6 5 4 3 2 1 0;

[0025] If the sampling phase is 4, the corresponding ideal data transition phase sequence is 7 6 5 4 3 2 1 0;

[0026] If the sampling phase is 5, the corresponding ideal data transition phase sequence is 1 0 7 6 5 4 3 2;

[0027] If the sampling phase is 6, the corresponding ideal data transition phase sequence is 2 1 0 7 6 5 4 3;

[0028] If the sampling phase is 7, the corresponding ideal data transition phase sequence is 3 2 1 0 7 6 5 4.

[0029] Furthermore, the phase adjustment module is specifically used for:

[0030] Based on the current sampling phase of the local clock, an ideal data jump phase sequence corresponding to the current sampling phase is determined in the storage module, and based on the correspondence between the bit position and the sampling phase, the current data jump phase information is adjusted in bit position sequence according to the ideal data jump phase sequence, and an adjusted eight-bit data jump phase value is obtained based on the adjusted bit position sequence, wherein the correspondence between the bit position and the sampling phase is: bit position 7 corresponds to sampling phase 7, bit position 6 corresponds to sampling phase 6, bit position 5 corresponds to sampling phase 5, bit position 4 corresponds to sampling phase 4, bit position 3 corresponds to sampling phase 3, bit position 2 corresponds to sampling phase 2, bit position 1 corresponds to sampling phase 1, and bit position 0 corresponds to sampling phase 0.

[0031] Furthermore, the phase adjustment module is specifically used for:

[0032] Search the phase adjustment table for data transition phase information that is consistent with the adjusted eight-bit data transition phase value, and determine the sampling phase offset information corresponding to the data transition phase information. If the sampling phase offset information indicates that the sampling phase is unchanged, the current sampling phase is the optimal sampling phase. If the sampling phase offset information indicates that the sampling phase is plus one or minus one, perform a sampling phase adjustment operation, wherein the sampling phase adjustment operation is:

[0033] If the sampling phase offset information is the sampling phase plus / minus one, the current sampling phase is increased / minus one, and based on the sampling phase after addition / subtraction, the corresponding ideal data jump phase sequence is determined in the storage module, and based on the correspondence between the bit position and the sampling phase, the current data jump phase information is adjusted according to the ideal data jump phase sequence. Based on the adjusted bit position sequence, an adjusted eight-bit data jump phase value is obtained, and the data jump phase information consistent with the adjusted eight-bit data jump phase value is searched in the phase adjustment table, and the sampling phase offset information corresponding to the data jump phase information is determined. If the sampling phase offset information is that the sampling phase is unchanged, the sampling phase after addition / subtraction is the optimal sampling phase. Otherwise, the sampling phase adjustment operation is repeated until the obtained sampling phase offset information is that the sampling phase is unchanged, and the sampling phase after this adjustment is the optimal sampling phase.

[0034] Furthermore, the data clock recovery module is specifically used for:

[0035] For each group of eight-bit sampled data in the target sampled data, determine the bit value corresponding to the optimal sampling phase as the recovered bit data, and output the determined eight-bit data based on each working clock to obtain the recovered eight-bit data;

[0036] The recovered eight-bit data is counted and accumulated, and when the accumulated data reaches 10 bits, a clock is generated, which is the recovered clock signal.

[0037] In a second aspect, the present application provides a clock data recovery method, the method comprising:

[0038] Converting the serial signal to be recovered into a single-bit signal;

[0039] Perform multi-stage delay processing on the single-bit signal to obtain multi-channel delayed data signals;

[0040] Perform signal sampling on each delayed data signal to obtain a set of sampling data with eight different sampling phases, and splice the obtained multiple sets of sampling data to obtain target sampling data;

[0041] Perform an XOR operation on the target sampled data, and obtain current data jump phase information based on the result of the XOR operation;

[0042] Pre-store a mapping relationship between a sampling phase and an ideal data jump phase sequence, based on a current sampling phase of a local clock and an ideal data jump phase sequence corresponding to the current sampling phase, adjust the bit position of the current data jump phase information according to the ideal data jump phase sequence to obtain adjusted data jump phase information, search a sampling phase offset result in a phase adjustment table based on the adjusted data jump phase information, and cyclically adjust the current sampling phase based on the sampling phase offset result to obtain an optimal sampling phase of the local clock, wherein the mapping relationship between the data jump phase information and the sampling phase offset information is stored in the phase adjustment table;

[0043] Based on the optimal sampling phase, data recovery is performed on the target sampled data to obtain a recovered data signal, and a recovered clock signal is determined based on the recovered data signal.

[0044] In a third aspect, the present application provides a communication device, comprising the clock data recovery apparatus as described above.

[0045] The present application determines the ideal data jump phase sequence according to the current data jump phase information and the current sampling phase, thereby searching the corresponding sampling phase offset result through the phase adjustment table, and cyclically adjusting the sampling phase so that the sampling phase gradually approaches the data center to obtain the optimal sampling phase of the local clock, thereby being able to quickly recover the serial data and clock signals, and can reduce the time requirement for the analog circuit clock locking phase locking, can quickly converge the clock locking time, and improve the efficiency of the clock locking. It can be used in application scenarios that have requirements for locking time and require fast switching interfaces, and is no longer limited to high-speed interface circuits, reducing the chip operating power consumption and reducing the cost of chip design and manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A first system block diagram of a clock data recovery device provided in an embodiment of the present application;

[0047] Figure 2 A second system block diagram of the clock data recovery device provided in an embodiment of the present application;

[0048] Figure 3 A third system block diagram of the clock data recovery device provided in an embodiment of the present application;

[0049] Figure 4 A schematic diagram of a data sampling signal provided in an embodiment of the present application;

[0050] Figure 5 A flowchart of a clock data recovery method provided in an embodiment of the present application;

[0051] Figure 6A system block diagram of a communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] The present application will be described in detail below in conjunction with the specific implementation modes shown in the accompanying drawings, but these implementation modes do not limit the present application. Structural, methodological, or functional changes made by ordinary technicians in the field based on these implementation modes are included in the protection scope of the present application.

[0053] like Figure 1As shown, a clock data recovery device provided by an embodiment of the present application includes a differential conversion module 11, a delay module 12, a sampling module 13, a transition edge detection module 14, a storage module 15, a phase adjustment module 16 and a data clock recovery module 17. The differential conversion module 11 converts the serial signal to be recovered into a single-bit signal inside the chip. The delay module 12 performs multi-stage delay processing on the single-bit signal to obtain multiple delayed data signals. For each delayed data signal, the sampling module 13 performs signal sampling to obtain a group of sampled data with eight different sampling phases, and splices the obtained multiple groups of sampled data to obtain target sampled data, wherein the clock frequency corresponding to the sampling module 13 is the clock frequency corresponding to the serial signal to be recovered. The transition edge detection module 14 performs an exclusive OR operation on the target sampled data, and obtains the current data transition phase information based on the result of the exclusive OR operation. The storage module 15 stores the mapping relationship between the sampling phase and the ideal data transition phase sequence. The phase adjustment module 16 determines the ideal data jump phase sequence corresponding to the current sampling phase of the local clock in the storage module 15, adjusts the bit position of the current data jump phase information according to the ideal data jump phase sequence, obtains the adjusted data jump phase information, searches the sampling phase offset result in the phase adjustment table based on the adjusted data jump phase information, and cyclically adjusts the current sampling phase based on the sampling phase offset result to obtain the optimal sampling phase of the local clock, wherein the mapping relationship between the data jump phase information and the sampling phase offset information is stored in the phase adjustment table. The data clock recovery module 17 performs data recovery on the target sampling data based on the optimal sampling phase to obtain the recovered data signal, and determines the recovered clock signal based on the recovered data signal. In this implementation, the serial port signal to be recovered is converted into a single-ended data signal, a uniform delay is inserted into the single-ended data signal on the data line, and the delayed data signal is sampled to obtain multiple phase sampling data of the data, that is, the current data jump phase information is obtained, and based on the current data jump phase information and the current sampling phase, the jump phase arrangement pattern located in the middle of the data that theoretically corresponds to the sampling phase is determined, that is, the ideal data jump phase sequence is determined, so that the corresponding sampling phase offset result is found through the phase adjustment table, and the sampling phase is cyclically adjusted so that the sampling phase gradually approaches the data center to obtain the best sampling phase of the local clock, that is, the sampling point data close to the middle of the data is obtained, and then the serial data and clock signal can be recovered. This implementation can reduce the time requirement for the phase locking of the analog circuit clock, can quickly converge the clock locking time, and can be used in application scenarios that have requirements for locking time and require fast switching interfaces.

[0054] In some embodiments, the differential conversion module 11 adopts an LVDS conversion module, and the external input serial signal to be recovered is converted into a single-bit signal inside the chip through the LVDS conversion module. The hardware entity of the present application can be an application specific integrated circuit (ASIC) chip. The LVDS conversion module can be integrated inside the ASIC chip, which converts the external LVDS differential signal into a data signal that can be used inside the chip. The differential signal consists of two complementary signals, one is positive (+) and the other is negative (-). The LVDS conversion module compares the voltage difference on the two signal lines and generates a single-ended logic level corresponding to the differential signal, that is, converting the differential signal into a single-bit signal. The traditional SerDes interface uses the IP core of the FPGA, which needs to be purchased, resulting in excessive cost of the FPGA chip. Based on this implementation, the function of data clock recovery is realized by using the ordinary LVDS interface of the ASIC chip, which reduces the chip working power consumption, is no longer limited to the high-speed interface circuit, reduces the outsourcing cost of the SerDes IP, and reduces the cost of chip design and manufacturing.

[0055] In some embodiments, the delay module 12 performs eight-way delay processing on the single-bit signal to obtain eight-way delayed data signals. Each logic gate inside the ASIC chip has a specific delay, usually in picoseconds (ps). The delay refers to the time required for the input signal to change to the output signal to stabilize. The delay circuit can be designed by referring to the delay parameters of the logic gate in the chip manual. The logic circuit and / or combinational logic circuit inside the ASIC chip is used to build a delay circuit to realize the data delay function.

[0056] In some embodiments, Figure 2 As shown, the delay module 12 includes eight cascaded delay units, each delay unit has the same input-to-output delay time, the eight delay units are a first delay unit 121, a second delay unit 122, a third delay unit 123, a fourth delay unit 124, a fifth delay unit 125, a sixth delay unit 126, a seventh delay unit 127 and an eighth delay unit 128, a single-bit signal is sequentially input into the eight delay units, and each delay unit outputs a corresponding delayed data signal to obtain eight delayed data signals, wherein the eight delayed data signals have the same data content but different data delays, and the data delays of the eight delayed data signals increase sequentially with the delay time as a step size, with one eighth of a data cycle of the serial signal to be recovered as the delay time.

[0057] Exemplarily, a serial signal to be recovered at a rate of 1.25G is taken as an example for explanation. One data cycle of the serial signal is 800ps, which is 100ps after being equally divided into eight. The 100ps is used as the delay time from the input to the output of the delay unit. The serial signal to be recovered at a rate of 1.25G is converted into a single-bit signal by the differential conversion module 11. The single-bit signal passes through eight delay units connected in series in sequence, that is, the first delay unit 121 to the eighth delay unit 128 in sequence, and the delay time of each delay unit is 100ps. The single-bit signal is input into the first delay unit 121, and the single-bit signal is delayed by 100ps, that is, the first delayed data signal output by the first delay unit 121 is a signal delayed by 100ps, and the first delayed data signal is input into the second delay unit 122, and the second delay unit 122 is also delayed by 100ps, so the second delay unit 122 outputs the second delay unit 122. The delayed data signal is a signal that has been delayed by 200ps. The second delayed data signal that has been delayed by 200ps is then output to the third delay unit 123. By analogy, eight delayed data signals are obtained. The first delayed data signal is delayed by 100ps based on the single-bit signal, the second delayed data signal is delayed by 200ps based on the single-bit signal, and the third delayed data signal is delayed by 300ps based on the single-bit signal. By analogy, the delays of the eight delayed data signals are different, because only delay processing is performed, and the data content is consistent, that is, it is consistent with the content of the input single-bit signal. In this implementation, the single-bit signal is uniformly delayed and inserted to obtain a data signal with uniformly distributed delays, thereby providing support for the subsequent acquisition of data signals with multiple sampling phases.

[0058] In some embodiments, for each delayed data signal, the sampling module 13 performs signal sampling to obtain a set of sampled data with eight different phases, and the eight sets of sampled data are spliced ​​to obtain target sampled data, wherein the frequency of the sampling clock corresponding to the sampling module 13 is the clock frequency corresponding to the serial signal to be recovered. For the first data signal, the data signal will be sampled at eight different sampling positions, and there will be a phase difference between the sampled data signals, so that eight sampled data signals with different phases can be obtained. Similarly, the 2nd to 8th data signals are sampled to obtain eight sets of sampled data signals, and these eight sets of sampled data are spliced ​​to obtain the target sampled data.

[0059] In some embodiments, Figure 3As shown, the sampling module 13 includes eight sampling units, which are a first sampling unit 131, a second sampling unit 132, a third sampling unit 133, a fourth sampling unit 134, a fifth sampling unit 135, a sixth sampling unit 136, a seventh sampling unit 137 and an eighth sampling unit 138, wherein the first sampling unit 131 is connected to the first delay unit 121, the second sampling unit 132 is connected to the second delay unit 122, the third sampling unit 133 is connected to the third delay unit 123, the fourth sampling unit 134 is connected to the fourth delay unit 124, the fifth sampling unit 135 is connected to the fifth delay unit 125, the sixth sampling unit 136 is connected to the sixth delay unit 126, the seventh sampling unit 137 is connected to the seventh delay unit 127, and the eighth sampling unit 138 is connected to the eighth delay unit 128, and the clock frequency corresponding to the sampling module 13 is the clock frequency corresponding to the serial signal to be recovered. Based on each sampling clock, the eight delayed data signals input by the eight sampling units are sampled respectively to obtain a set of eight-bit sampling data with eight different sampling phases. Based on eight consecutive sampling clocks, eight consecutive eight-way delayed data signals are sampled to obtain eight groups of eight-bit sampling data, and the eight groups of eight-bit sampling data are spliced ​​to obtain 64 bits of target sampling data, wherein the eight eight-way delayed data signals are obtained based on the eight single-bit signals continuously input to the delay module 12. Based on this implementation, the delayed data signal is sampled by the sampling module 13 to obtain sampling data with different phases. In this implementation, an 8-fold rate data sampling circuit is used, and for the delayed data signal, each single-bit data is sampled as data with 8 different sampling phases, which increases the anti-interference ability of the circuit and can cover a wide range of working conditions.

[0060] In some embodiments, the sampling phase of the first sampling unit 131 is set to correspond to the first sampling phase, the sampling phase of the second sampling unit 132 is set to correspond to the second sampling phase, the sampling phase of the third sampling unit 133 is set to correspond to the third sampling phase, the sampling phase of the fourth sampling unit 134 is set to correspond to the fourth sampling phase, the sampling phase of the fifth sampling unit 135 is set to correspond to the fifth sampling phase, the sampling phase of the sixth sampling unit 136 is set to correspond to the sixth sampling phase, the sampling phase of the seventh sampling unit 137 is set to correspond to the seventh sampling phase, and the sampling phase of the eighth sampling unit 138 is set to correspond to the eighth sampling phase. Exemplarily, when the first sampling clock arrives, the first sampling unit 131 samples the input first delayed data signal, and the sampling position is the first sampling phase of the sampling clock, and obtains the first bit sampling data, that is, the first bit sampling data is based on the data sampled at the first sampling phase, and the second sampling unit 132 samples the input second delayed data signal, and the sampling position is the second sampling phase of the sampling clock, and obtains the second bit sampling data, that is, the second bit sampling data is based on the data sampled at the second sampling phase, and so on, to obtain eight bits of data corresponding to the first sampling phase to the eighth sampling phase. Therefore, based on this implementation, the acquired current data jump phase information is associated with the sampling phase to provide a basis for subsequent sampling phase adjustment.

[0061] For example, taking the serial signal to be recovered at a rate of 1.25G as an example, the sampling module 13 uses a 1.25Ghz local clock to perform data sampling, samples the eight data signals, and obtains the following: Figure 4The data signal sampling schematic diagram shown. Specifically, the differential conversion module 11 converts the first serial signal to be recovered into the first single-bit signal inside the chip, and delays the first single-bit signal through the delay module 12 to obtain eight delayed data signals. When the first sampling clock arrives, the first sampling unit 131 samples the input first delayed data signal to obtain the first bit sampling data, and the second sampling unit 132 samples the input second delayed data signal to obtain the second bit sampling data, and so on. Since the delays of the data signals input to each sampling unit are different, a first group of eight-bit sampling data with eight different phases is obtained. The differential conversion module 11 converts the second serial signal to be recovered into the second single-bit signal, and delays the second single-bit signal through the delay module 12 to obtain eight delayed data signals. When the second sampling clock arrives, it is processed in the same manner as above, so as to obtain a second group of eight-bit sampling data with eight different phases. Similarly, eight consecutive single-bit signals are sampled for eight consecutive sampling clocks to obtain eight groups of eight-bit sampling data, which are then spliced ​​to obtain 64-bit target sampling data. Since the rate of the serial signal to be recovered is generally high, such as the 1.25G mentioned above, in the subsequent clock recovery process, the chip cannot always use a high-frequency clock signal due to the limitation of the chip's working clock, such as a working clock frequency of 156.25Mhz. Therefore, multiple groups of sampling data are spliced ​​into a 64-bit data bus, that is, the sampling data is divided into eight, and the 64-bit data bus is converted into a divided system clock, that is, data processing is performed at the system clock 156.25Mhz, and subsequent data processing uses the system's working clock.

[0062] In some embodiments, the transition edge detection module 14 performs an XOR operation on each bit in the target sampled data and the adjacent bit, respectively, to obtain 64 bits of first data transition information, divides the 64 bits of first data transition information into eight groups with eight bits of data as a group, obtains eight groups of second data transition information, performs an XOR operation on each identical bit in the eight groups of second data transition information, obtains eight bits of current data transition phase information, and the bit sequence of the eight bits of current data transition phase information is bit7 to bit0 from the highest bit to the lowest bit. For example, the first bit in the 64 bits of target sampled data is XORed with the second bit, the second bit is XORed with the third bit, and so on, until the last bit is XORed with the first bit in the next target sampled data, to obtain 64 bits of first data transition information, and the value of each bit of the 64 bits of first data transition information indicates whether a transition occurs between the corresponding bit and the adjacent bit. The 64-bit first data transition information is divided into eight groups with eight bits as a group, and eight groups of second data transition information are obtained, and each group of data transition information is eight bits of data. The eight groups of second data transition information are subjected to an XOR operation, that is, the first bit of each group of second data transition information is subjected to an XOR operation, and the second bit is subjected to an XOR operation, and so on, until each eighth bit is subjected to an XOR operation, thereby obtaining an eight-bit current data transition phase information, and the same bit of the eight groups of second data transition information is subjected to an XOR operation, which is similar to the logical statistical addition operation of the data on the same bit, to obtain eight bits of data transition phase information after the statistical addition operation. In this embodiment, by performing an XOR operation on the 64-bit target sampled data to perform a data change phase check on the sampled data, information on the change of the data transition edge position can be obtained, so that the data transition edge position can be subsequently analyzed and calculated.

[0063] For the selection of the sampling phase of the clock, the ideal sampling position is to select the middle one among the eight sampling phases, that is, the transition edge is farthest from the sampling phase, and the middle one of the continuous identical data is selected. In some embodiments, the storage module 15 stores the mapping relationship between the sampling phase and the ideal data transition phase sequence. The sampling phase refers to the sampling position of the clock. The first sampling phase is represented by 0, the second sampling phase is represented by 1, the third sampling phase is represented by 2, the fourth sampling phase is represented by 3, the fifth sampling phase is represented by 4, the sixth sampling phase is represented by 5, the seventh sampling phase is represented by 6, and the eighth sampling phase is represented by 7. If the sampling phase is 0, the corresponding ideal data transition phase sequence is 4 32 1 0 7 6 5. If the sampling phase is 1, the corresponding ideal data transition phase sequence is 5 4 3 2 1 0 7 6; if the sampling phase is 2, the corresponding ideal data transition phase sequence is 6 5 4 3 2 1 0 7; if the sampling phase is 3, the corresponding ideal data transition phase sequence is 7 6 5 4 3 2 1 0; if the sampling phase is 4, the corresponding ideal data transition phase sequence is 7 6 5 4 32 1 0; if the sampling phase is 5, the corresponding ideal data transition phase sequence is 1 0 7 6 5 4 3 2; if the sampling phase is 6, the corresponding ideal data transition phase sequence is 2 1 0 7 6 5 4 3; if the sampling phase is 7, the corresponding ideal data transition phase sequence is 3 2 1 0 7 6 5 4. Based on the above different sampling phases, the corresponding ideal data transition phases are arranged differently, that is, the ideal sampling position is the middle one among the eight sampling phases.

[0064] The phase adjustment module 16 determines the ideal data jump phase sequence corresponding to the current sampling phase in the storage module 15 based on the current sampling phase of the local clock, adjusts the bit position of the current data jump phase information according to the ideal data jump phase sequence, obtains the adjusted data jump phase information, searches the sampling phase offset result in the phase adjustment table based on the adjusted data jump phase information, and cyclically adjusts the current sampling phase based on the sampling phase offset result to obtain the optimal sampling phase, wherein the mapping relationship between the data jump phase information and the sampling phase offset information is stored in the phase adjustment table. It can be understood that the current sampling phase is the initial sampling phase or the optimal sampling phase confirmed when the previous data clock is recovered, and the initial sampling phase is a sampling phase set at the initialization of the system. In this implementation, based on the current sampling phase and the current data jump phase information, an ideal data jump phase sequence is determined, the bit order of the data jump phase information is adjusted based on the sequence, and the sampling phase offset result is searched in the phase adjustment table based on the adjusted data jump phase information, that is, it is determined whether the sampling phase is in the ideal sampling position, and then the sampling phase is cyclically moved to obtain the optimal sampling phase. Even if the sampling phase gradually approaches the data center, the clock locking time can be quickly converged, reducing the time requirement for the analog circuit clock locking phase.

[0065] In some embodiments, the phase adjustment module 16 determines the ideal data jump phase sequence corresponding to the current sampling phase in the storage module 15 based on the current sampling phase of the local clock, and based on the correspondence between the bit position and the sampling phase, adjusts the current data jump phase information according to the ideal data jump phase sequence in the bit position sequence, and obtains the adjusted eight-bit data jump phase value based on the adjusted bit position sequence, wherein the correspondence between the bit position and the sampling phase is: bit position 7 corresponds to sampling phase 7, bit position 6 corresponds to sampling phase 6, bit position 5 corresponds to sampling phase 5, bit position 4 corresponds to sampling phase 4, bit position 3 corresponds to sampling phase 3, bit position 2 corresponds to sampling phase 2, bit position 1 corresponds to sampling phase 1, and bit position 0 corresponds to sampling phase 0. Exemplarily, for example, the current sampling phase is 1, and the corresponding ideal data jump phase order is 5 4 3 2 1 0 7 6. Based on this order, the bit position of the current data jump phase information is adjusted, that is, the current data jump phase information is originally in the order of bit 7-bit 0, and is adjusted to a bit order of 5 4 3 2 1 0 7 6. The adjusted bit data value is determined based on the value of each bit.

[0066] In some embodiments, the phase adjustment module 16 searches the phase adjustment table for data transition phase information that is consistent with the adjusted eight-bit data transition phase value, and determines the sampling phase offset information corresponding to the data transition phase information. If the sampling phase offset information indicates that the sampling phase is unchanged, the current sampling phase is the optimal sampling phase. If the sampling phase offset information indicates that the sampling phase is increased by one or decreased by one, a sampling phase adjustment operation is performed. The sampling phase adjustment operation is:

[0067] If the sampling phase offset information is the sampling phase plus / minus one, the current sampling phase is increased / minus one, and based on the sampling phase after addition / subtraction, the corresponding ideal data jump phase sequence is determined in the storage module 15, and based on the correspondence between the bit position and the sampling phase, the current data jump phase information is adjusted according to the ideal data jump phase sequence. Based on the adjusted bit position sequence, an adjusted eight-bit data jump phase value is obtained, and the data jump phase information consistent with the adjusted eight-bit data jump phase value is searched in the phase adjustment table, and the sampling phase offset information corresponding to the data jump phase information is determined. If the sampling phase offset information is that the sampling phase is unchanged, the sampling phase after addition / subtraction is the optimal sampling phase. Otherwise, the sampling phase adjustment operation is repeated until the obtained sampling phase offset information is that the sampling phase is unchanged, and the sampling phase after this adjustment is the optimal sampling phase. In this implementation, the ideal data jump phase sequence is determined based on the current sampling phase, that is, the jump phase arrangement in the middle of the data that the sampling phase theoretically corresponds to, and the current data jump phase information is adjusted in bit order to obtain the adjusted data jump phase value, which can then be queried in the phase adjustment table to adjust the current sampling phase and move the sampling phase, that is, add or subtract one from the current sampling phase, so that the sampling phase gradually approaches the data center to achieve the best sampling phase. This implementation adopts a table lookup method to implement the sampling phase approximation selection algorithm, the table entry content is completely solidified, and all jump edge states are fully covered, which can quickly converge the clock lock time.

[0068] In a specific embodiment of the present application, the phase adjustment table is shown in the following table:

[0069]

[0070]

[0071]

[0072]

[0073]

[0074]

[0075]

[0076]

[0077] The following is a specific example to explain the sampling phase adjustment in this implementation mode. Assume that the current sampling phase is 0, and the current data transition phase information is 10000001, that is, bit7 to bit0 are 10000001 in sequence. The current sampling phase is 0, and the corresponding ideal data jump phase sequence is 4 3 2 1 0 7 6 5. According to the correspondence between the bit position and the sampling phase, that is, the bit position of the current data jump phase information is 4 3 2 1 0 7 6 5. Based on the values ​​corresponding to each bit, the eight-bit data jump phase value after the current data jump phase information is adjusted is 00001100. According to 00001100, the above phase adjustment table is queried. 00001100 corresponds to the sampling phase plus one, that is, the phase after adding one is 1. The ideal data jump phase sequence corresponding to the sampling phase of 1 is 5 4 3 2 1 0 7 6. Therefore, the eight-bit data jump phase value after the current data jump phase information is adjusted is 00000110. According to 00000110, the above phase adjustment table is queried. The sampling phase corresponding to 00000110 is plus one, that is, the phase after adding one is 2. The ideal data jump phase sequence corresponding to the sampling phase of 2 is 6 5 4 3 2 1 0 7, so the eight-bit data transition phase value after the current data transition phase information is adjusted is 00000011. According to 00000011, the above phase adjustment table is queried, and the sampling phase corresponding to 00000011 is increased by one, that is, the phase after addition is 3, and the ideal data transition phase sequence corresponding to the sampling phase 3 is 7 6 5 4 3 2 1 0. Therefore, the eight-bit data transition phase value after the current data transition phase information is adjusted is 10000001. According to 10000001, the above phase adjustment table is queried, and the sampling corresponding to 0000001 remains unchanged. At this time, the sampling phase 3 is the best sampling phase.

[0078] In some embodiments, the data clock recovery module 17 determines the bit value corresponding to the optimal sampling phase as the recovered bit data for each group of eight-bit sampling data in the target sampling data, and outputs the determined eight-bit data based on each working clock to obtain the recovered eight-bit data; the recovered eight-bit data is counted and accumulated, and a clock is generated when it is accumulated to 10 bits of data, and the clock is the recovered clock signal. As can be seen from the above, the 64-bit target sampling data is eight groups of eight-bit sampling data, each group of eight-bit sampling data is obtained through delay and sampling based on a single-bit signal, and the data content of the group of eight-bit sampling data is the same. Based on the optimal sampling phase obtained above, the bit value corresponding to the optimal sampling phase is determined, and the bit value is the sampling point data closest to the middle of the data, so that the eight-bit data can be recovered. The recovered eight-bit data is counted and accumulated, and a clock is generated when it is accumulated to 10 bits of data, and a recovery clock synchronized with the data can be recovered. The recovery clock is 125Mzh, and the recovery clock can be used as a standard clock after clock division, shaping and filtering.

[0079] In some embodiments, since the local clock and serial data are not synchronized, there is a frequency offset between the two. If the last sampling phase is 7, the optimal sampling phase determined this time is 0. When the sampling phase jumps from 7 to 0, it means that the data has a positive frequency offset relative to the local sampling clock. One clock beat needs to output 9 bits of sampling data to compensate for the clock data frequency offset to restore normal data. When the sampling phase jumps from 0 to 7, it means that the data has a negative frequency offset relative to the local sampling clock. One clock beat needs to output 7 bits of sampling data to compensate for the clock data frequency offset.

[0080] Based on the same inventive concept, an embodiment of the present application also provides a clock data recovery method. The implementation solution for solving the problem provided by the method is similar to the implementation solution recorded in the above-mentioned device. Therefore, the specific limitations in one or more clock data recovery method embodiments provided below can be referred to the limitations on the clock data recovery device above, and will not be repeated here.

[0081] Please refer to Figure 5 The present application provides a clock data recovery method, the method comprising the steps of:

[0082] S501, converting the serial signal to be recovered into a single-bit signal;

[0083] S502, performing multi-stage delay processing on the single-bit signal to obtain multi-channel delayed data signals;

[0084] S503, sampling each delayed data signal to obtain a set of sampling data with eight different sampling phases, and splicing the obtained multiple sets of sampling data to obtain target sampling data;

[0085] S504, performing an XOR operation on the target sampled data, and obtaining current data jump phase information based on the result of the XOR operation;

[0086] S505, pre-store a mapping relationship between a sampling phase and an ideal data jump phase sequence, based on the current sampling phase of the local clock and the ideal data jump phase sequence corresponding to the current sampling phase, adjust the bit position of the current data jump phase information according to the ideal data jump phase sequence to obtain adjusted data jump phase information, search a sampling phase offset result in a phase adjustment table based on the adjusted data jump phase information, and cyclically adjust the current sampling phase based on the sampling phase offset result to obtain an optimal sampling phase of the local clock, wherein the mapping relationship between the data jump phase information and the sampling phase offset information is stored in the phase adjustment table;

[0087] S506 . Perform data recovery on the target sampled data based on the optimal sampling phase to obtain a recovered data signal, and determine a recovered clock signal based on the recovered data signal.

[0088] This implementation can reduce the time requirement for clock locking and phase locking of analog circuits, can quickly converge the clock locking time, and can be used in application scenarios that have requirements for locking time and require fast switching interfaces.

[0089] Optionally, performing multi-stage delay processing on the single-bit signal to obtain multi-channel delayed data signals includes:

[0090] A single-bit signal is input into eight delay units in sequence, and each delay unit outputs a corresponding delayed data signal to obtain eight delayed data signals, wherein the eight delayed data signals have the same data content but different data delays, and the data delays of the eight delayed data signals increase in sequence with the delay time as a step, and one eighth of a data cycle of the serial signal to be restored is used as the delay time.

[0091] Optionally, signal sampling is performed for each delayed data signal to obtain a set of sampled data with eight different sampling phases, and the obtained multiple sets of sampled data are spliced ​​to obtain target sampled data, including:

[0092] Based on each sampling clock, eight delayed data signals input by eight sampling units are sampled respectively to obtain a set of eight-bit sampling data with eight different sampling phases;

[0093] Based on a continuous eight-beat sampling clock, eight continuous eight-way delayed data signals are sampled to obtain eight groups of eight-bit sampling data, and the eight groups of eight-bit sampling data are spliced ​​to obtain 64 bits of target sampling data, wherein the eight eight-way delayed data signals are obtained based on the eight single-bit signals of the continuous input sampling module 13.

[0094] Optionally, performing an XOR operation on the target sampled data, and obtaining current data jump phase information based on a result of the XOR operation, includes:

[0095] Perform an XOR operation on each bit in the target sampled data and the adjacent bit to obtain 64 bits of first data transition information;

[0096] The 64-bit first data jump information is divided into eight groups with eight bits of data as a group to obtain eight groups of second data jump information, and an XOR operation is performed on each identical bit in the eight groups of second data jump information to obtain eight bits of current data jump phase information, wherein the bit order of the eight bits of current data jump phase information is bit7~bit0 from the highest bit to the lowest bit.

[0097] Optionally, pre-storing a mapping relationship between a sampling phase and an ideal data transition phase sequence includes:

[0098] Set the first sampling phase to 0, the second sampling phase to 1, the third sampling phase to 2, the fourth sampling phase to 3, the fifth sampling phase to 4, the sixth sampling phase to 5, the seventh sampling phase to 6, and the eighth sampling phase to 7. If the sampling phase is 0;

[0099] If the sampling phase is 0, the corresponding ideal data transition phase sequence is 4 3 2 1 0 7 6 5;

[0100] If the sampling phase is 1, the corresponding ideal data transition phase sequence is 5 4 3 2 1 0 7 6;

[0101] If the sampling phase is 2, the corresponding ideal data transition phase sequence is 6 5 4 3 2 1 0 7;

[0102] If the sampling phase is 3, the corresponding ideal data transition phase sequence is 7 6 5 4 3 2 1 0;

[0103] If the sampling phase is 4, the corresponding ideal data transition phase sequence is 7 6 5 4 3 2 1 0;

[0104] If the sampling phase is 5, the corresponding ideal data transition phase sequence is 1 0 7 6 5 4 3 2;

[0105] If the sampling phase is 6, the corresponding ideal data transition phase sequence is 2 1 0 7 6 5 4 3;

[0106] If the sampling phase is 7, the corresponding ideal data transition phase sequence is 3 2 1 0 7 6 5 4.

[0107] Optionally, based on the current sampling phase of the local clock and based on the ideal data transition phase sequence corresponding to the current sampling phase, the current data transition phase information is bit-position adjusted according to the ideal data transition phase sequence to obtain the adjusted data transition phase information, including:

[0108] Based on the current sampling phase of the local clock, determine the ideal data jump phase sequence corresponding to the current sampling phase, based on the correspondence between the bit position and the sampling phase, adjust the current data jump phase information according to the ideal data jump phase sequence The bit position sequence is adjusted, and based on the adjusted bit position sequence, an adjusted eight-bit data jump phase value is obtained, wherein the correspondence between the bit position and the sampling phase is: bit position 7 corresponds to sampling phase 7, bit position 6 corresponds to sampling phase 6, bit position 5 corresponds to sampling phase 5, bit position 4 corresponds to sampling phase 4, bit position 3 corresponds to sampling phase 3, bit position 2 corresponds to sampling phase 2, bit position 1 corresponds to sampling phase 1, and bit position 0 corresponds to sampling phase 0.

[0109] Optionally, searching a sampling phase offset result in a phase adjustment table based on the adjusted data jump phase information, and cyclically adjusting a current sampling phase based on the sampling phase offset result to obtain an optimal sampling phase of a local clock, including:

[0110] Search the phase adjustment table for data transition phase information that is consistent with the adjusted eight-bit data transition phase value, and determine the sampling phase offset information corresponding to the data transition phase information. If the sampling phase offset information indicates that the sampling phase is unchanged, the current sampling phase is the optimal sampling phase. If the sampling phase offset information indicates that the sampling phase is plus one or minus one, perform a sampling phase adjustment operation, wherein the sampling phase adjustment operation is:

[0111] If the sampling phase offset information is the sampling phase plus / minus one, the current sampling phase is increased / minus one, and based on the sampling phase after addition / subtraction, the corresponding ideal data jump phase sequence is determined; based on the correspondence between the bit position and the sampling phase, the current data jump phase information is adjusted in bit position sequence according to the ideal data jump phase sequence, and an adjusted eight-bit data jump phase value is obtained based on the adjusted bit position sequence, and the data jump phase information consistent with the adjusted eight-bit data jump phase value is searched in the phase adjustment table, and the sampling phase offset information corresponding to the data jump phase information is determined; if the sampling phase offset information is that the sampling phase is unchanged, the sampling phase after addition / subtraction is the optimal sampling phase; otherwise, the sampling phase adjustment operation is repeated until the obtained sampling phase offset information is that the sampling phase is unchanged, and the sampling phase after this adjustment is the optimal sampling phase.

[0112] Optionally, based on the optimal sampling phase, performing data recovery on the target sampled data to obtain a recovered data signal, and determining a recovered clock signal based on the recovered data signal, including:

[0113] For each group of eight-bit sampled data in the target sampled data, determine the bit value corresponding to the optimal sampling phase as the recovered bit data, and output the determined eight-bit data based on each working clock to obtain the recovered eight-bit data;

[0114] The recovered eight-bit data is counted and accumulated, and when the accumulated data reaches 10 bits, a clock is generated, which is the recovered clock signal.

[0115] The embodiment of the present application further provides a communication device, which includes the above-mentioned clock data recovery device. For example, the network device includes Figure 1 The clock data recovery device shown in the figure. The communication device can be any communication device used for service forwarding in a communication network.

[0116] As an example, see Figure 6 , which shows a schematic diagram of the structure of a communication device provided by an embodiment of the present application. The network device includes a clock data recovery device 601, a communication interface 602, a processor 603, a memory 604 and a bus 605. The processor 603, the memory 604, the communication interface 602 and the clock data recovery device 601 are connected to each other through the bus 605. Among them, Figure 6 The connection method between the processor 603, memory 604, communication interface 602 and clock data recovery device 601 shown is merely exemplary. During implementation, the processor 603, memory 604, communication interface 602 and clock data recovery device 601 may also be connected to each other in communication with each other using other connection methods besides the bus 605.

[0117] The memory 604 may be used to store computer programs, which may include instructions and data. In an embodiment of the present application, the memory 604 may be various types of storage media, such as random access memory, static random access memory, non-volatile, DDR, etc. The memory 604 may include a hard disk and / or a memory.

[0118] The processor 603 may be a general-purpose processor, which may be a processor that performs specific steps and / or operations by reading and executing a computer program stored in a memory (e.g., memory 604), and the general-purpose processor is used to process the data output by the clock data recovery device 601. The general-purpose processor may be, for example, but not limited to, a central processing unit (CPU). In addition, the processor 603 may also be a dedicated processor, which may be a processor specially designed to perform specific steps and / or operations, and the dedicated processor may be, for example, but not limited to, an ASIC and an FPGA, etc. In addition, the processor 603 may also be a combination of multiple processors, such as a multi-core processor.

[0119] The communication interface 602 may include an input / output (I / O) interface, a physical interface, and a logical interface, etc., which are used to interconnect devices within the network device, and an interface for interconnecting the network device with other devices (such as a network device). The physical interface may be a Gigabit Ethernet interface (GE), which may be used to interconnect the network device with other devices, and the logical interface is an interface within the network device, which may be used to interconnect devices within the network device. It is easy to understand that the communication interface 602 may be used for the network device to communicate with other devices, for example, the communication interface 702 is used for sending and receiving messages between the network device and other devices. The bus 605 may be any type of communication bus, such as a system bus, for interconnecting the processor 603, the memory 604, the communication interface 602, and the clock data recovery device 601.

[0120] The structure of the clock data recovery device 601 can refer to Figure 1The illustrated embodiments are not described here. The interconnection between any device among the processor 603, the memory 604 and the communication interface 602 and the clock data recovery device 601 may specifically refer to the interconnection between any device and the device in the clock data recovery device 601. In some embodiments, the above-mentioned processor 603, the memory 604 and the communication interface 602 may all be integrated on the clock data recovery device 601, or the above-mentioned processor 603, the memory 604 and the communication interface 602 may be respectively arranged on chips independent of each other, or may be at least partially or completely arranged on the same chip. Whether each device is independently arranged on different chips or integrated on one or more chips often depends on the needs of product design. This application does not limit the specific implementation form of the above-mentioned devices.

[0121] The embodiments disclosed in the present application also provide a computer-readable storage medium, in which instructions are stored. When the computer-readable storage medium is run on a computer, the computer is enabled to execute the clock data recovery method described in any one of the above embodiments.

[0122] Although the preferred embodiments of the present application have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the application as disclosed in the accompanying claims.

Claims

1. A clock data recovery device, characterized in that: The device comprises: A differential conversion module, used for converting the serial signal to be recovered into a single-bit signal; A delay module, used for performing multi-stage delay processing on the single-bit signal to obtain multi-channel delayed data signals; A sampling module is used to sample each delayed data signal to obtain a set of sampling data with eight different sampling phases, and to splice the obtained multiple sets of sampling data to obtain target sampling data; A transition edge detection module, used for performing an XOR operation on the target sampled data, and obtaining current data transition phase information based on the result of the XOR operation; A storage module, used for storing a mapping relationship between a sampling phase and an ideal data transition phase sequence; A phase adjustment module, used to determine in the storage module an ideal data jump phase sequence corresponding to the current sampling phase of the local clock, perform bit position adjustment on the current data jump phase information according to the ideal data jump phase sequence to obtain adjusted data jump phase information, search for a sampling phase offset result in a phase adjustment table based on the adjusted data jump phase information, and cyclically adjust the current sampling phase based on the sampling phase offset result to obtain an optimal sampling phase of the local clock, wherein the phase adjustment table stores a mapping relationship between the data jump phase information and the sampling phase offset information; A data clock recovery module, which performs data recovery on the target sampled data based on the optimal sampling phase to obtain a recovered data signal, and determines a recovered clock signal based on the recovered data signal; Wherein, the phase adjustment module is specifically used for: Based on the current sampling phase of the local clock, an ideal data jump phase sequence corresponding to the current sampling phase is determined in the storage module, and based on the correspondence between the bit position and the sampling phase, the current data jump phase information is adjusted in bit position sequence according to the ideal data jump phase sequence, and an adjusted eight-bit data jump phase value is obtained based on the adjusted bit position sequence, wherein the correspondence between the bit position and the sampling phase is: bit position 7 corresponds to sampling phase 7, bit position 6 corresponds to sampling phase 6, bit position 5 corresponds to sampling phase 5, bit position 4 corresponds to sampling phase 4, bit position 3 corresponds to sampling phase 3, bit position 2 corresponds to sampling phase 2, bit position 1 corresponds to sampling phase 1, and bit position 0 corresponds to sampling phase 0; Search the phase adjustment table for data transition phase information that is consistent with the adjusted eight-bit data transition phase value, and determine the sampling phase offset information corresponding to the data transition phase information. If the sampling phase offset information indicates that the sampling phase is unchanged, the current sampling phase is the optimal sampling phase. If the sampling phase offset information indicates that the sampling phase is plus one or minus one, perform a sampling phase adjustment operation, wherein the sampling phase adjustment operation is: If the sampling phase offset information is the sampling phase plus / minus one, the current sampling phase is increased / minus one, and based on the sampling phase after addition / subtraction, the corresponding ideal data jump phase sequence is determined in the storage module, and based on the correspondence between the bit position and the sampling phase, the current data jump phase information is adjusted according to the ideal data jump phase sequence. Based on the adjusted bit position sequence, an adjusted eight-bit data jump phase value is obtained, and the data jump phase information consistent with the adjusted eight-bit data jump phase value is searched in the phase adjustment table, and the sampling phase offset information corresponding to the data jump phase information is determined. If the sampling phase offset information is that the sampling phase is unchanged, the sampling phase after addition / subtraction is the optimal sampling phase. Otherwise, the sampling phase adjustment operation is repeatedly performed until the obtained sampling phase offset information is that the sampling phase is unchanged, and the sampling phase after this adjustment is the optimal sampling phase.

2. The clock data recovery device according to claim 1, characterized in that: The delay module includes eight cascaded delay units, each delay unit has the same input-to-output delay time, the eight delay units are a first delay unit, a second delay unit, a third delay unit, a fourth delay unit, a fifth delay unit, a sixth delay unit, a seventh delay unit and an eighth delay unit, a single-bit signal is sequentially input into the eight delay units, and each delay unit outputs a corresponding delayed data signal to obtain eight delayed data signals, wherein the eight delayed data signals have the same data content but different data delays, and the data delays of the eight delayed data signals are sequentially increased with the delay time as a step length, and one eighth of a data cycle of the serial signal to be recovered is used as the delay time.

3. The clock data recovery device according to claim 2, characterized in that: The sampling module includes eight sampling units, which are a first sampling unit, a second sampling unit, a third sampling unit, a fourth sampling unit, a fifth sampling unit, a sixth sampling unit, a seventh sampling unit and an eighth sampling unit, wherein the first sampling unit is connected to the first delay unit, the second sampling unit is connected to the second delay unit, the third sampling unit is connected to the third delay unit, the fourth sampling unit is connected to the fourth delay unit, the fifth sampling unit is connected to the fifth delay unit, the sixth sampling unit is connected to the sixth delay unit, the seventh sampling unit is connected to the seventh delay unit, and the The eight sampling units are connected to the eighth delay unit, and the sampling phase of the first sampling unit is set to correspond to the first sampling phase, the sampling phase of the second sampling unit is set to correspond to the second sampling phase, the sampling phase of the third sampling unit is set to correspond to the third sampling phase, the sampling phase of the fourth sampling unit is set to correspond to the fourth sampling phase, the sampling phase of the fifth sampling unit is set to correspond to the fifth sampling phase, the sampling phase of the sixth sampling unit is set to correspond to the sixth sampling phase, the sampling phase of the seventh sampling unit is set to correspond to the seventh sampling phase, and the sampling phase of the eighth sampling unit is set to correspond to the eighth sampling phase, wherein, Based on each sampling clock, eight delayed data signals input by eight sampling units are sampled respectively to obtain a set of eight-bit sampling data with eight different sampling phases; Based on a continuous eight-beat sampling clock, eight continuous eight-way delayed data signals are sampled to obtain eight groups of eight-bit sampling data, and the eight groups of eight-bit sampling data are spliced ​​to obtain 64-bit target sampling data, wherein the eight eight-way delayed data signals are obtained based on eight single-bit signals continuously input into the delay module.

4. The clock data recovery device according to claim 3, characterized in that: The transition edge detection module is specifically used for: Perform an XOR operation on each bit in the target sampled data and the adjacent bit to obtain 64 bits of first data transition information; The 64-bit first data jump information is divided into eight groups with eight bits of data as a group to obtain eight groups of second data jump information, and an XOR operation is performed on each identical bit in the eight groups of second data jump information to obtain eight bits of current data jump phase information, wherein the bit order of the eight bits of current data jump phase information is bit7~bit0 from the highest bit to the lowest bit.

5. The clock data recovery device according to claim 4, characterized in that: Set the first sampling phase to 0, the second sampling phase to 1, the third sampling phase to 2, the fourth sampling phase to 3, the fifth sampling phase to 4, the sixth sampling phase to 5, the seventh sampling phase to 6, and the eighth sampling phase to 7; The storage module is specifically used for: If the sampling phase is 0, the corresponding ideal data transition phase sequence is 4 3 2 1 0 7 6 5; If the sampling phase is 1, the corresponding ideal data transition phase sequence is 5 4 3 2 1 0 7 6; If the sampling phase is 2, the corresponding ideal data transition phase sequence is 6 5 4 3 2 1 0 7; If the sampling phase is 3, the corresponding ideal data transition phase sequence is 7 6 5 4 3 2 1 0; If the sampling phase is 4, the corresponding ideal data transition phase sequence is 7 6 5 4 3 2 1 0; If the sampling phase is 5, the corresponding ideal data transition phase sequence is 1 0 7 6 5 4 3 2; If the sampling phase is 6, the corresponding ideal data transition phase sequence is 2 1 0 7 6 5 4 3; If the sampling phase is 7, the corresponding ideal data transition phase sequence is 3 2 1 0 7 6 5 4.

6. The clock data recovery device according to claim 1, characterized in that: The data clock recovery module is specifically used for: For each group of eight-bit sampled data in the target sampled data, determine the bit value corresponding to the optimal sampling phase as the recovered bit data, and output the determined eight-bit data based on each working clock to obtain the recovered eight-bit data; The recovered eight-bit data is counted and accumulated, and when the accumulated data reaches 10 bits, a clock is generated, and the clock is the recovered clock signal.

7. A clock data recovery method, characterized in that: The method comprises: Converting the serial signal to be recovered into a single-bit signal; Performing multi-stage delay processing on the single-bit signal to obtain multi-channel delayed data signals; Perform signal sampling on each delayed data signal to obtain a set of sampling data with eight different sampling phases, and splice the obtained multiple sets of sampling data to obtain target sampling data; Performing an XOR operation on the target sampled data, and acquiring current data jump phase information based on a result of the XOR operation; Pre-store a mapping relationship between a sampling phase and an ideal data jump phase sequence, based on a current sampling phase of a local clock and an ideal data jump phase sequence corresponding to the current sampling phase, adjust the bit position of the current data jump phase information according to the ideal data jump phase sequence to obtain adjusted data jump phase information, search a sampling phase offset result in a phase adjustment table based on the adjusted data jump phase information, and cyclically adjust the current sampling phase based on the sampling phase offset result to obtain an optimal sampling phase of the local clock, wherein the mapping relationship between the data jump phase information and the sampling phase offset information is stored in the phase adjustment table; Based on the optimal sampling phase, performing data recovery on the target sampled data to obtain a recovered data signal, and determining a recovered clock signal based on the recovered data signal; in, Based on the current sampling phase of the local clock, determine the ideal data jump phase sequence corresponding to the current sampling phase, based on the correspondence between the bit position and the sampling phase, adjust the current data jump phase information according to the ideal data jump phase sequence. Based on the adjusted bit position sequence, obtain an adjusted eight-bit data jump phase value, wherein the correspondence between the bit position and the sampling phase is: bit position 7 corresponds to sampling phase 7, bit position 6 corresponds to sampling phase 6, bit position 5 corresponds to sampling phase 5, bit position 4 corresponds to sampling phase 4, bit position 3 corresponds to sampling phase 3, bit position 2 corresponds to sampling phase 2, bit position 1 corresponds to sampling phase 1, and bit position 0 corresponds to sampling phase 0; Search the phase adjustment table for data transition phase information that is consistent with the adjusted eight-bit data transition phase value, and determine the sampling phase offset information corresponding to the data transition phase information. If the sampling phase offset information indicates that the sampling phase is unchanged, the current sampling phase is the optimal sampling phase. If the sampling phase offset information indicates that the sampling phase is plus one or minus one, perform a sampling phase adjustment operation, wherein the sampling phase adjustment operation is: If the sampling phase offset information is the sampling phase plus / minus one, the current sampling phase is increased / minus one, and based on the sampling phase after addition / subtraction, the corresponding ideal data jump phase sequence is determined in the storage module, and based on the correspondence between the bit position and the sampling phase, the current data jump phase information is adjusted according to the ideal data jump phase sequence. Based on the adjusted bit position sequence, an adjusted eight-bit data jump phase value is obtained, and the data jump phase information consistent with the adjusted eight-bit data jump phase value is searched in the phase adjustment table, and the sampling phase offset information corresponding to the data jump phase information is determined. If the sampling phase offset information is that the sampling phase is unchanged, the sampling phase after addition / subtraction is the optimal sampling phase. Otherwise, the sampling phase adjustment operation is repeated until the obtained sampling phase offset information is that the sampling phase is unchanged, and the sampling phase after this adjustment is the optimal sampling phase.

8. A communication device, characterized in that: It comprises a clock data recovery device as described in any one of claims 1-6.

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