A method for realizing dual-mode interconnection of chips

Abstract

This invention belongs to the field of chip communication technology and specifically discloses a method for achieving dual-mode chip interconnection. This method proposes interconnecting chips and servers by sharing a common interface logic. This not only saves chip interface circuit area and reduces chip communication power consumption, but also simplifies the chip communication system architecture and improves system stability.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip communication, and in particular relates to a method for realizing dual-mode interconnection of chips. Background Art

[0002] The rapid development of artificial intelligence (AI), particularly large-scale AI models, has led to an explosive growth in demand for computing power. Large models typically have billions or even hundreds of billions of parameters. Due to the enormous computational complexity of these models, a single computing unit often cannot meet training requirements. Therefore, distributed training technology has become widely used, distributing model training tasks across multiple computing units or servers for parallel computation.

[0003] Distributed training is a method that breaks down machine learning or deep learning model training tasks into multiple subtasks and performs them in parallel across multiple computing devices. This technique fully utilizes the computing resources of multiple computers, improving training speed and reducing computational costs. In distributed training, high-speed network connections are required between computing units or servers to transmit data and synchronize gradient information. Therefore, interconnection technology between computing units or servers is crucial for improving training speed and reducing computational costs.

[0004] Currently, different interconnect components and high-speed network technologies are commonly used to achieve interconnection between computing units or between servers. However, since the current technologies require additional switches and adapters, they not only increase the complexity and cost of the system, but also lead to higher latency and usage costs. Summary of the Invention

[0005] In order to solve at least one of the problems mentioned in the above background technology, the present invention proposes a method for realizing dual-mode interconnection of chips.

[0006] A method for realizing dual-mode interconnection of chips, comprising the steps of:

[0007] Step S1, arranging interface logic on the chip substrate, specifically, arranging interface logic on the four end sides of the chip substrate: top, bottom, left, and right;

[0008] The interface logic specifically includes a sending link module, a chip interconnection module, a chip access module, a receiving link module, and a communication network port. The sending link module is used to select a link when the chip sends data; the chip interconnection module is used for direct communication between chips; the chip access module is used for communication between chips through a switch; the receiving link module is used to select a link when the chip receives data; and the communication network port is used to establish a connection between the chip and the outside world.

[0009] Step S2, setting the working mode of the interface logic, and completing the circuit connection of the interface logic according to the set working mode;

[0010] Specifically, there are two working modes: one is the chip interconnection mode in which chips are directly interconnected with each other; the other is the server interconnection mode in which chips are interconnected with each other through switches;

[0011] The specific circuit connection method of the interface logic is:

[0012] One end of the transmit link module is connected to the chip, and the other end is connected to the chip interconnection module and the chip access module respectively;

[0013] The other end of the chip interconnection module and the chip access module is connected to one end of the receiving link module;

[0014] The other end of the receiving link module is connected to one end of the communication network port;

[0015] The other end of the communication network port is connected to the outside;

[0016] Currently, different interconnection components and high-speed network technologies are generally used to achieve interconnection between computing units or between servers. However, since the current technologies require additional switches and adapters, they not only increase the complexity and cost of the system, but also lead to higher latency and usage costs. The present invention proposes to achieve interconnection between chips and between servers by sharing a set of interface logic. This not only saves the area of ​​the chip interface circuit and reduces the power consumption of chip communication, but also simplifies the system structure of chip communication and improves the stability of the system structure.

[0017] Step S3: The chip substrates on which the interface logic is arranged are interconnected according to the set working mode, wherein:

[0018] If it is the chip interconnection mode, when the chip sends data, the sending link module sends the data to the chip interconnection module; when the chip receives data, the receiving link module sends the data to the chip interconnection module.

[0019] If it is the server interconnection mode, when the chip sends data, the sending link module sends the data to the chip access module; when the chip receives data, the receiving link module sends the data to the chip access module.

[0020] The present invention proposes a method for realizing dual-mode interconnection of chips, which has the following advantages compared with the existing technology:

[0021] Beneficial effects:

[0022] The present invention proposes to realize the interconnection between chips and between servers by sharing a set of interface logic, which not only saves the area of ​​the chip interface circuit and reduces the power consumption of chip communication, but also simplifies the system structure of chip communication and improves the stability of the system structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic flow diagram of the present invention;

[0024] Figure 2 is a schematic diagram of the layout of the interface logic in an embodiment of the present invention;

[0025] Figure 3 is a circuit connection diagram of the interface logic in an embodiment of the present invention;

[0026] Figure 4 is a schematic diagram of a chip interconnection mode in an embodiment of the present invention;

[0027] Figure 5 Schematic diagram of a server interconnection mode in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose and features of the present invention more obvious and easy to understand, the present technical solution is described in detail below through embodiments and in conjunction with the accompanying drawings.

[0029] like Figure 1 As shown, a method for realizing dual-mode interconnection of chips includes the following steps:

[0030] Step S1: Arrange interface logic on a chip substrate.

[0031] The interface logic includes a sending link module, a chip interconnection module, a chip access module, a receiving link module and a communication network port. Among them, the sending link module is used for link selection when the chip sends data; the chip interconnection module is used for direct communication between chips; the chip access module is used for communication between chips through a switch; the receiving link module is used for link selection when the chip receives data; and the communication network port is used to establish a connection between the chip and the outside world.

[0032] like Figure 2 As shown, interface logic is arranged on the four end sides of the chip substrate: top, bottom, left, and right.

[0033] Optionally, multiple interface logics can be arranged on each end side.

[0034] Step S2, setting the working mode of the interface logic, and completing the circuit connection of the interface logic according to the set working mode. Specifically, the set working modes include two types, one is the chip interconnection mode in which chips are directly interconnected with each other; the other is the server interconnection mode in which chips are interconnected with each other through a switch.

[0035] In actual applications, the interface logic includes the protocol layer, adaptation layer, physical layer and other related circuits required for chip interconnection, and the two working modes use the same adaptation layer and physical layer circuits.

[0036] Optionally, it can be configured that different control signals correspond to different operating modes in the interface logic.

[0037] In actual implementation, the external components include other chips and switches.

[0038] like Figure 3 As shown, the specific circuit connection method of the interface logic is:

[0039] One end of the transmit link module is connected to the chip, and the other end is connected to the chip interconnection module and the chip access module respectively;

[0040] The other end of the chip interconnection module and the chip access module is connected to one end of the receiving link module;

[0041] The other end of the receiving link module is connected to one end of the communication network port;

[0042] The other end of the communication network port is connected to the outside.

[0043] Step S3: The chip substrates on which the interface logic is arranged are interconnected according to the set working mode.

[0044] The interconnection is carried out according to the server interconnection mode and chip interconnection mode.

[0045] If it is the chip interconnection mode, when the chip sends data, the sending link module sends the data to the chip interconnection module; when the chip receives data, the receiving link module sends the data to the chip interconnection module.

[0046] like Figure 4 As shown, in actual implementation, in the chip interconnection mode, each chip can be connected in series or in parallel through interface logic.

[0047] If it is the server interconnection mode, when the chip sends data, the sending link module sends the data to the chip access module; when the chip receives data, the receiving link module sends the data to the chip access module.

[0048] like Figure 5 As shown, in the actual implementation process, in the server interconnection mode, the chips in the server can be interconnected through the switch, thereby realizing the interconnection between servers.

[0049] So far, according to the method disclosed in the present invention, the working process of the present invention has been implemented once.

[0050] It should be noted that the serial numbers of the above-mentioned embodiments of the present invention are for descriptive purposes only and do not represent the advantages or disadvantages of the embodiments. In addition, the terms "including", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "including a ..." does not exclude the presence of other identical elements in the process, device, article or method comprising the element.

[0051] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0052] The above are only preferred embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for realizing dual-mode interconnection of chips, characterized in that: The method comprises the following steps: step S1, arranging interface logic on a chip substrate; step S2, setting an operating mode of the interface logic and completing circuit connection of the interface logic according to the set operating mode; step S3, interconnecting the chip substrates on which the interface logic is arranged according to the set operating mode; The interface logic described in step S1 specifically includes a sending link module, a chip interconnection module, a chip access module, a receiving link module, and a communication network port; wherein the sending link module is used for link selection when the chip sends data; the chip interconnection module is used for direct communication between chips; the chip access module is used for communication between chips through a switch; the receiving link module is used for link selection when the chip receives data; and the communication network port is used to establish a connection between the chip and the outside world; The interconnection described in step S3 is performed according to the set working mode. If it is the chip interconnection mode, when the chip sends data, the sending link module sends the data to the chip interconnection module; when the chip receives data, the receiving link module sends the data to the chip interconnection module; if it is the server interconnection mode, when the chip sends data, the sending link module sends the data to the chip access module; when the chip receives data, the receiving link module sends the data to the chip access module.

2. The method for realizing dual-mode interconnection of chips according to claim 1, characterized in that: The working mode set in step S2 specifically includes two working modes: one is a chip interconnection mode in which chips are directly interconnected with each other; the other is a server interconnection mode in which chips are interconnected with each other through a switch.

3. The method for realizing dual-mode interconnection of chips according to claim 1, characterized in that: The circuit connection of the interface logic described in step S2 is specifically connected as follows: one end of the sending link module is connected to the chip, and the other end is connected to the chip interconnection module and the chip access module respectively; the other ends of the chip interconnection module and the chip access module are connected to one end of the receiving link module; the other end of the receiving link module is connected to one end of the communication network port; and the other end of the communication network port is connected to the outside.

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