Method for testing an electronic control device with a simulator
By optimizing the adder selection and decomposition strategy in matrix vector multiplication, using high-sum-availability matrix elements and multiple use of residual matrix, the problem of complexity and high cost of matrix vector multiplication calculation in simulator test is solved, and the more Fast and efficient calculations.
Patent Information
- Application Number
- CN202410856546.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-06-29
- Filing Date
- 2024-06-28
- Publication Date
- 2024-12-31
AI Technical Summary
In simulator tests, matrix vector multiplication calculation is complex and expensive, especially in semiconductor power electronic systems with fast switching, and the prior art is difficult to meet the high requirements of real-time simulation.
By determining the matrix element with the highest sum availability as the adder in the sequence in matrix vector multiplication, decomposing the matrix element into the sum of the two adders to form a sequence, and using the residual matrix and auxiliary matrix optimization calculations multiple times, Reduce repeated calculations and improve calculation efficiency.
The calculation speed of matrix vector multiplication is significantly improved, and the calculation cost is reduced, making it possible to run the environment model in real time on the simulator, especially in the programmable logic module to achieve more efficient resource utilization.
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Figure CN119227311A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a computer-implemented method for testing an electronic control device using a simulator, wherein the simulator numerically calculates a mathematical environment model on a computing unit, wherein the environment model at least partially simulates the environment of the control device, wherein the control device and the simulator are coupled to each other and interact via corresponding I / O interfaces, wherein matrix-vector multiplication is performed on the simulator in the case of the numerical calculation of the environment model, wherein a matrix and a vector are multiplied to form a result vector, wherein the matrix-vector multiplication is decomposed into a sequence of sums of two addends, wherein each addend is the product of two factors, wherein one factor is an element of the matrix and the other factor is an element of the vector. Background Art
[0002] The computer-implemented method mentioned here originates from the field of hardware-in-the-loop simulation (HIL simulation), in which the environment of a control device is partially or completely simulated. This makes it possible to test and test the control device safely in a simulated environment and not in the real physical process in which the control device is to be used later. A typical example is a control device for an electric drive, for example from the automotive sector, whose environment, i.e. the electric drive and, if necessary, other environmental components (e.g. the chassis of the vehicle), is simulated using a simulator. To this end, the control device is connected via its I / O interfaces to corresponding I / O interfaces of the simulator, so that the corresponding signals (power signals of the semiconductor bridge, sensor signals, etc.) can be exchanged as in real use of the control device. In the case of the control device for an electric drive described as an example, the simulator then also includes suitable power electronics modules in order to simulate the corresponding electrical loads for the control device.
[0003] The control unit can exist in different forms: as a development control unit, which is also different from the final hardware implementation, as a final series production control unit, but also as a virtual control unit, which is then a software simulation. In the latter case, the simulator is connected to the control unit via corresponding I / O interfaces, even if these interfaces are implemented only via data technology.
[0004] Testing a control unit involves running it in conjunction with a simulator, as this allows for determining whether the control unit and the control implemented therein achieve the expected performance. A comparison is then made between the expected target performance and the actual performance experienced in the simulation. To achieve this, not only must the mathematical environment model be numerically calculated as accurately as possible, but it must also be calculated in real time during the real-time simulation: the calculation of the system behavior within a time interval of one second of simulation time must be completed within one second of physical real time at the latest. The simulation of power electronics systems with fast-switching semiconductors is particularly demanding, as these systems often have large characteristic values and, therefore, high time rates of change in state variables, even compared to mechanical systems. Efforts are made to improve the numerical processing of the simulation to meet the real-time requirements and / or to employ specialized hardware to enable fast calculations, such as programmable logic modules, often in the form of FPGAs (field programmable gate arrays).
[0005] The numerical calculation of systems of differential equations in practice always leads to matrix calculations, often in the form of matrix-vector multiplications. It is directly clear that after achieving a time discretization - which is accompanied by numerical methods - one considers, for example, the state space description of the system (see, for example, document WO 2020 / 099659A1). Summary of the Invention
[0006] In particular, when using FPGAs, it is often necessary to operate with element-wise adders, which means that only two addends can be added to form a sum. In matrix-vector multiplication, sums with a large number of addends often occur, corresponding at most to the number of row elements in a row of the involved matrices. Therefore, the sum must be decomposed into partial sums, i.e., a sequence of sums of the two addends mentioned. The present invention aims to further improve this type of matrix-vector multiplication.
[0007] The aforementioned object is achieved in the method for testing an electronic control unit using a simulator by means of the features of the characterizing portion of independent claim 1, namely, by determining in a sequence determination step a summation whose addends are associated with the matrix element of the highest row in the matrix as the next summation in the sequence, wherein the matrix element of the highest row is selected as the one with the highest sum availability. It is advantageous to prioritize the matrix element of the highest possible row, since the highest number of two additions can be performed in the highest row until the row total is finally calculated. Furthermore, it is advantageous to start with an element of this row that has the highest possible sum availability, i.e., one element with which a pair of addends can be formed in principle and another element with which a pair of addends can be formed that also occurs in another row of the matrix. Both contribute to the sum availability of the matrix elements. Sum availability is thus also a measure of the reusability of a pair of addends in the calculation of matrix-vector products.
[0008] Furthermore, the sequence determination step is repeated several times using a residual matrix instead of the matrix until the residual matrix no longer has any matrix elements that are not equal to zero, wherein the residual matrix is generated from the matrix by setting all matrix elements of the matrix that participate in the summation scheduled in the sequence to zero. The residual matrix thus contains all matrix elements of the matrix for which no summation is yet planned.
[0009] Finally, the summation is performed in the planned sequence, wherein the product is performed in the sequence to calculate the addends as required for performing the summation. The product between the matrix elements of the matrix and the vector elements of the vector follows the plan of the summation, and if a product is required for the summation, then the product is calculated.
[0010] In the final summation step, the sum resulting from the preceding summations is calculated in each row of the result vector by successive pairwise additions.
[0011] In a further extension of the method, it is provided that the matrix is checked according to the matrix elements with the same numerical value in the columns of the matrix, because the products with the same numerical value can be calculated on these matrix positions with the same matrix elements in the columns. The corresponding products of the numerical value of one of the matrix elements with the same numerical value and the numerical value of the corresponding vector elements of the vector are calculated only once. Then the calculation results of the products on other matrix positions with the same numerical value are only called and not recalculated. Thus the computational cost of computing the matrix-vector product is reduced in a targeted manner. Preferably, when the matrix elements and the corresponding vector elements have different signs, only the sign bit of the pre-calculated product by numerical value is set, thereby also reducing computational cost.
[0012] In order to further reduce the computational cost, in a preferred embodiment of the method, it is provided that the matrix is checked based on multiple identical matrix elements in two different rows and the same column of the matrix, because this corresponds to the same sum or partial sum in the result vector, wherein such a sum or partial sum is only calculated once, and only the calculation results with the same sum or partial sum in other rows are called and not recalculated to calculate the result vector. Because in the sequence determination step, matrix positions with high sum availability are preferably processed in the summation, the same multiple calculations are identified in the same way as at the beginning of the method and the residual matrix is also quickly thinned out. It should also be noted that the sum is numerically identical, because in this case, the sum only needs to be calculated once. Sign conversion can be simply achieved by the corresponding setting of the sign bit.
[0013] Initially, sum availability was explained in general. There are various possibilities for specifically implementing the numerical calculation of sum availability metrics. In a preferred embodiment of the method, it has been demonstrated that the sum availability of a matrix element of a matrix is evaluated as 1 for element values not equal to 0 if another element of the matrix in the same row of the matrix has an element value not equal to 0 and therefore, in principle, participates in the summation in its row. Accordingly, the sum availability increases by 1 for each conceivable addend pair in a row of the matrix that has the same value in another row of the matrix.
[0014] In the case where there are multiple identically occupied top rows of a matrix, in a further development of the method, a total sum availability is determined for each of these rows of the matrix in a sequence determination step, which corresponds to the sum of the sum availability of the matrix elements of the corresponding row, and the row with the highest total sum availability is then selected.
[0015] In case there are multiple rows in the matrix with the same highest occupancy and with the same total and availability, in a preferred embodiment one of the following variants is implemented: one of these multiple rows is selected randomly or by selecting the row with the smallest row number or by selecting the row with the largest row number.
[0016] As mentioned above, in matrix-vector multiplication, to calculate the elements of the result vector, sums with significantly more than two addends can be calculated, depending on the size of the matrix and the size of the vector. If the matrix has n columns, there are a maximum of n addends. The aforementioned steps must then be repeated repeatedly until all additions are mapped to element-wise additions of only two addends in each row.
[0017] For the reasons stated above, a further development of the method is characterized in that, in the final summation step, an auxiliary matrix is formed having a number of rows corresponding to the number of rows of the matrix and a number of columns corresponding to the number of summations in the already determined sequence of summations; the summation of the already determined sequence of summations is entered in each column, i.e., in the row for which the summation (b) provides the value in the result vector; the sequence determination step is carried out using the auxiliary matrix; and the sequence determination step is repeated several times using the auxiliary residual matrix instead of the auxiliary matrix until the auxiliary residual matrix no longer has any matrix elements that are not equal to zero. The auxiliary residual matrix is generated from the auxiliary matrix by setting all matrix elements in the auxiliary matrix that participate in the summations arranged in the sequence to zero. The summation is then carried out in the now expanded planned sequence. In each row of the result vector, the sum generated in the previously expanded summation is calculated by successive pairwise additions.
[0018] The method steps shown are preferably repeated analogously multiple times until the required number of summations for the matrix-vector multiplication has been completely decomposed into a sequence of summations of two addends.
[0019] If the computing unit of the simulator is a programmable logic module, then in another embodiment of the method it is provided that within the scope of the environment model, when calculating matrix-vector multiplications, a determined sequence for the summation is used as the basis, and the environment model is transferred to the hardware description for the programmable logic module, wherein the programmable logic module is configured as a computing unit of the simulator in the hardware description.
[0020] The method described enables optimized matrix-vector multiplication, significantly increasing the speed of environment model calculation. This makes it possible to run environment models on a simulator, particularly in real time, that were previously impossible. The method makes optimal use of hardware resources, particularly when programmable logic modules are used as computing units in the simulator.
[0021] The objects indicated above are also solved by a computer program comprising instructions which, when executed in a simulator or in a simulation environment, cause the simulator or the simulation environment to carry out the above-described method. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In detail, there are now numerous possibilities for designing and further developing the method according to the invention. For this purpose, reference is made firstly to the dependent claims following the independent claim and secondly to the following description of exemplary embodiments in conjunction with the drawings. The drawings show:
[0023] Figure 1 Schematically illustrating a computer-implemented method for testing a control device with a simulator;
[0024] Figure 2 A method for testing a control device is schematically shown according to an example using a sequence determination step whose criteria are highest row occupancy and highest sum availability, and illustrating the use of a residual matrix;
[0025] Figure 3 Shown in accordance with Figure 2 A further embodiment of the method using a residual matrix;
[0026] Figure 4 Shown in accordance with Figure 2 and 3 An embodiment of the method using an auxiliary matrix and an auxiliary residual matrix; and
[0027] Figure 5 Shown according to Figures 2 to 4 The sequence of summations found in computes the matrix-vector product. DETAILED DESCRIPTION
[0028] exist Figures 1 to 5 , a computer-implemented method 1 for testing an electronic control unit 2 with a simulator 3 is shown in various aspects.
[0029] Figure 1 The following diagram shows a typical device-based structure for testing a control device 2 within the scope of a so-called hardware-in-the-loop simulation. In this case, the control device 2 is a real development control device. A simulator 3 has multiple computing units, some of which are implemented as field-programmable gate arrays (FPGAs). A mathematical environment model 4 is numerically calculated on one of the FPGA computing units, wherein the environment model 4 simulates the environment of the control device 2. In the specific case, the control device 2 is a control device 2 for a three-phase electric drive and has a corresponding power supply (not shown in detail) so that it can supply the required power. A component of the control device 2 is also a power electronic half-bridge assembly, which includes fast-switchable semiconductor switches. The simulator 3 has corresponding power electronic load modules, which can be used to electrically load the control device 2 accordingly. In generator operation, the simulated load can also feed energy into the control device 2. The control device 2 and the simulator 3 are physically coupled to each other via corresponding I / O interfaces 5 and 6 and can interact via these interfaces. By inserting modules 7, the simulator 3 can be adapted to the hardware requirements of the environment model 4 and to the desired test situation.
[0030] By applying a numerical solution, a matrix-vector multiplication must be performed on the simulator 3 in the case of the numerically calculated environment model 4. In the case of the matrix-vector multiplication, the matrix M is multiplied by the vector v to form the result vector r. Figure 2Such a matrix-vector multiplication is shown in the top row of FIGURE 1 according to a specific example. It is assumed that the matrix elements ki are not equal to 0 and the vector elements vi are also not equal to 0. Figure 2 The right-hand term in the top row of clearly shows that sums with multiple addends occur in matrix-vector multiplication, which represents a mathematically correct implementation of matrix-vector multiplication, regardless of the peculiarities of the hardware architecture or the implementation possibilities in software.
[0031] The use of an FPGA as a computation unit of the simulator 3 requires that the matrix-vector multiplication must be decomposed into a sequence of sums of two addends, where each addend is the product of two factors, where one factor is an element ki of the matrix M and the other factor is an element vj of the vector v
[0032] According to Figures 2 to 5 The embodiment shown in clarifies method 1, by which matrix-vector multiplications can be performed in a time-optimized manner, so that, for example, a large-scale environment model 4 can also be calculated on the simulator 3 - in particular under real-time conditions, which was previously not possible without applying method 1 - assuming the same hardware configuration.
[0033] Method 1 described below is based on identifying identical products and identical sums consisting of two identical addends in the overall matrix M, identifying and prioritizing the frequency with which matrix elements participate in repeated addends, and thus avoiding multiple calculations.
[0034] exist Figure 2 What can be seen first in the middle row is that in the sequence determination step 8 such a summation is determined as the next summation in the sequence, whose addend is related to the matrix element ki occupying the highest row in the matrix M, wherein the following matrix element ki occupying the highest row is selected which has the highest sum availability P.
[0035] The occupancy of a row of the matrix M is expressed in the vector s. The given value directly indicates how many positions in a row of the matrix M are occupied with a value other than zero. Accordingly, the corresponding number of possible sums is also provided (one less sum for positions other than those not equal to zero).
[0036] For example, the terminology and availability P need to be clarified. Figure 2The middle row of shows a matrix P that specifies the sum availability of each corresponding element of matrix M. Having the highest possible sum availability for an element ki of matrix M at position Mij in matrix M means, on the one hand, that in the row Mi of element Mij, there are other elements Mij of matrix M that are not equal to zero, with which, in principle, addend pairs can be formed, and, on the other hand, with which addend pairs that also occur in another row of matrix M can be formed. Both contribute to the sum availability Pij of matrix element Mij. Sum availability Pij is thus also a measure of the reusability of matrix element Mij as a component of an addend pair in the calculation of a matrix-vector product.
[0037] There are several possibilities for numerically implementing this evaluation metric. A particularly simple possibility, which has been used here, is to evaluate the sum availability Pij of an element Mij of the matrix M to 1 for an element value not equal to 0, if another element Mij of the matrix (M) in the same row Mi of the matrix M has an element value not equal to 0 and therefore this element Mij is generally included in the summation in its row. Furthermore, the sum availability Pij is increased by 1 for each possible addend pair in the row Mi of the matrix M that occurs with the same value in another row of the matrix M.
[0038] If, for example, the sum availability P11 of matrix element M11 is evaluated according to this approach, it must first be determined that two elements in row M1 of matrix M are not equal to zero, which results in the sum availability P11 of matrix element M11 having the value 1. Furthermore, it must be determined that the addend pair in row M1 of matrix M—which consists of matrix elements M11 and M12 (with the values -k1 and -k2)—recurs identically in row 2 in columns 1 and 2 of matrix M, except for the opposite signs of matrix elements M21 and M22. This also results in the sum availability P11 of matrix element M11 increasing by the value 1. The sum availability P11 of matrix element M11 then has the value 2.
[0039] For example, the sum availability P21 of the matrix element M21 should also be determined. In the second row of the matrix M, in which the matrix element P21 is also present, there are also two other matrix elements that are not equal to zero, that is, with the values k2 and k4. This leads to the sum availability P21 value of the matrix element M21 being 1. In addition, a sum can be formed with the matrix element M23 (with the value k4). This sum has a counterpart in the row M3 of the matrix M with the opposite sign. In addition, there is the sum of the matrix elements M21 and M22, which has a counterpart in the first row M1, that is, with the matrix elements -k1 and -k2. These two corresponding addend pairs each lead to the sum availability P21 value of the matrix element M21 being 1. The sum availability P21 of the matrix element M21 is therefore 3. Following this principle, it can be implemented in Figure 2The other sum availability Pij of other matrix elements Mij in the matrix M.
[0040] In accordance with Figure 2 In the exemplary embodiment, the rows M2 and M3 of the matrix M are identically occupied, i.e., each has 3 elements (see the occupancy s in rows 2 and 3). In this case, the question arises as to from which row Mi of the matrix M the matrix elements Mij in the matrix M should be considered for the sum. In the exemplary embodiment shown, it is applicable that in the sequence determination step 8, when there are multiple identically occupied highest rows Mi of the matrix M, a total sum availability qi is determined for each of the rows Mi of the matrix M, see vector q, which is equal to the sum of the sum availability Pi of the matrix elements Mi of the corresponding row Mi. The row Mi with the highest total sum availability qi is then selected. In the illustrated case, row 2 has the highest total sum availability 7 (i.e., the sum of all sum availability in row 2 is 3+2+2=7). Therefore, the sum of the participating matrix positions M21 and M22 is then calculated.
[0041] At the same time, two further measures are taken: In the calculation of products and sums, attention is paid to whether numerically identical products or sums occur again in the matrix or in the calculation of matrix-vector products. These products or sums are pre-recorded and subsequently called up and used at the corresponding locations, but are not recalculated.
[0042] In detail, this means that in method 1, the matrix M is checked for the numerically identical matrix elements ki in its columns Mj, since numerically identical products can be calculated at these matrix positions with the numerically identical matrix elements ki in the columns Mj; the corresponding product of the numerical value of one of the numerically identical matrix elements ki with the numerical value of the corresponding vector element vj of the vector v is calculated only once, and the results of the calculation of the products at the other matrix positions with the numerically identical matrix elements are only called up and not recalculated, in particular, in the case of different signs of the matrix element ki and the corresponding vector element vj, the sign bit of the precalculated numerical product is set accordingly. This applies, for example, to the position M31 with the value -k1. The product k1*v1 can be used a total of three times, also at the positions M11 and M21, where it is associated with the same sum.
[0043] Regarding sums, the aforementioned principle in method 1 means that the matrix M is examined for multiple identical matrix elements Mij in two different rows Mi and the same column Mj, as this corresponds to identical sums or partial sums in the result vector r. Such sums or partial sums are calculated only once, and only the calculation results with identical sums or partial sums in other rows are used to calculate the result vector r and are not recalculated. In rows 1 and 2 of the matrix M, there is a sum with the same value, namely k1*v1+k2*v2. This sum is calculated only once and only called up a second time. Furthermore, in the case of completely opposite signs, only the sign bit of the result value is inverted.
[0044] The principles of "prioritizing items with high sum availability" and "using products and sums with the same value multiple times" lead to a first series of summations with two addends. The required product depends on the sum. The sums k1*v1+k2*v2 and -(k1*v1+k2*v2) presuppose the calculation of the products k1*v1 and k2*v2.
[0045] exist Figure 2 As can be seen in row 3 of , matrix M is converted into the adjusted residual matrix M'. This sequence determination step 8 is repeated several times, using the residual matrix M' instead of matrix M, until the residual matrix M' no longer has any matrix elements that are not equal to zero. The residual matrix M' is generated from the matrix M by setting all matrix elements Mij in the matrix M that participate in the summation b scheduled in the sequence to zero. The scheduled summations and the multiple product operations are then recorded in the vector b, leaving only the uncalculated positions of the matrix M in the residual matrix M'.
[0046] exist Figure 3 This is shown in the top row. For the residual matrix M' or for each element M'ij of the residual matrix M' that is Figure 2 The residual matrix M' in the third row of the same - to obtain and availability, see the matrix P ( Figure 3 The elements of the sum are M32 and M33 with the values k3 and -k4, respectively, wherein the product k4*v3 can also be used in position M23 and is accordingly pre-recorded and only called up but not calculated. The result of this first sequence determination step 8 is the decomposition of the sum into the sums b1 and b2.
[0047] In method 1, summations b1, 2 are performed in a planned sequence, wherein products are performed in the sequence to calculate the addends required for performing the summation; the product calculation then follows the sum calculation. In the final summation step 9, the sum resulting from the previous summation is calculated in each row of the result vector r by successive pairwise additions.
[0048] In this exemplary embodiment, the question arises as to how the remaining sums should be treated, since only sums b1 and b2 exist so far, but these also need to be added to the result vector r. If the formation of element-wise sums with only two addends is absolutely mandatory, then the additions associated with these addends are also planned in an optimized manner. This is done in Figure 4 Shown in.
[0049] In the final summation step 9, an auxiliary matrix M'' is formed, which has a number of rows corresponding to the number of rows of the matrix M and has a number corresponding to the summation bi (i.e. Figure 3 b1, b2) in the already determined sequence. In each column, the sum of the already determined sequence of sums is recorded, that is, in the row for which the sum provides the value in the result vector r. The sequence determination step 8 is implemented using the auxiliary matrix M'; and the sequence determination step 8 is repeated several times with the auxiliary residual matrix M'' replacing the auxiliary matrix M' until the auxiliary residual matrix M'' no longer has any matrix elements that are not equal to zero. Matrix P - in which the sum availability of the elements of the auxiliary matrix M'' is recorded ( Figure 4 ) - only has entries with the value 1, since, although a summation is still performed in one row, there is no longer an identical summation (in terms of value) in the other rows of the auxiliary matrix M". Since the evaluations P, s and q are identical for rows 2 and 3 of the auxiliary matrix M", the lowest row number is taken into account for the next summation (k1*v1+k2*v2)+k4*v3. Furthermore, it is taken into account that there are positions with identical values at positions M"11 and M"21.
[0050] The auxiliary residual matrix M'' is generated from the auxiliary matrix M'' by setting to zero all the following matrix elements M'ij in the auxiliary matrix M'' that participate in Figure 4 The summation b1 arranged in sequence, see Figure 4 The elements of the auxiliary matrix M'' are also evaluated with respect to their and availability (in Figure 4 ), which yields the matrix P in row 2 of Figure 4 The other summation b2 in the auxiliary matrix M'' is then completely adjusted, see Figure 4 Finally, in the sequence of the now expanded plan Figure 4 The summation b1, b2 (appended to Figure 3 and calculating in each row of the result vector r the sum produced in the previous extended summation by successive pairwise additions.
[0051] In the case of larger matrices, it may naturally be necessary to repeat the process by analogically repeating the aforementioned method steps multiple times until the required number of summations for the matrix-vector multiplication is completely decomposed into a sequence of summations of two addends.
[0052] The result of method 1 is that the following sequence of summations is planned and implemented with the product caused by the summation:
[0053] k1*v1、k2*v2 promote k1*v1+k2*v2
[0054] k3*v2, k4*v3 contribute to k3*v2+(-k4*v3)
[0055] (k1*v1+k2*v2)+k4*v3
[0056] (k3*v2-k4*v3)+(-k1*v1)
[0057] The result is in Figure 5 The calculation is reduced to four multiplications and four additions. This allows the calculation to be performed as quickly as possible based on the available FPGA resources.
[0058] Reference Signs List
[0059] 1 Computer-implemented method
[0060] 2 Electronic control unit
[0061] 3 Simulator
[0062] 4 Mathematical environment model
[0063] 5Simulator I / O interface
[0064] 6. I / O interface of control device
[0065] 7 Insert modules
[0066] 8 Sequence determination steps
[0067] 9 Final summation step
[0068] M matrix
[0069] v vector
[0070] r result vector
[0071] Elements of the ki matrix
[0072] Elements of the vj vector
[0073] bSum
[0074] P and availability matrix
[0075] s vector of row occupancy rates
[0076] q is the vector of total and availability
[0077] M' residual matrix
[0078] M” auxiliary matrix
[0079] M'' auxiliary residual matrix
Claims
1. A computer-implemented method (1) for testing an electronic control device (2) using a simulator (3), wherein: The simulator (3) numerically calculates a mathematical environment model (4) on a computing unit, the environment model (4) at least partially simulating the environment of the control device (2), the control device (2) and the simulator (3) being coupled to each other and interacting via corresponding I / O interfaces (5, 6), and performing a matrix-vector multiplication on the simulator (3) when the environment model (4) is numerically calculated, in which a matrix (M) and a vector (v) are multiplied to form a result vector (r), wherein the matrix-vector multiplication is decomposed into a sequence of sums (b) of two addends, each addend being the product of two factors, one factor being an element (ki) of the matrix (M) and the other factor being an element (vj) of the vector (v), It is characterized in that In the sequence determination step (8), a summation (b) is determined as the next summation in the sequence, the addends of which are related to the matrix elements (ki) in the highest occupied row (s) of the matrix (M), wherein the matrix element (ki) in the highest occupied row (s) is selected with the highest sum availability (P); Repeating the sequence determination step (8) several times with the residual matrix (M') replacing the matrix (M) until the residual matrix (M') no longer has any matrix elements that are not equal to zero, wherein the residual matrix (M') is generated from the matrix (M) by setting all matrix elements (Mij) in the matrix (M) that participate in the summation (b) arranged in the sequence to zero; performing summation (b) in the planned sequence, wherein products are performed in the sequence to calculate addends as are required to perform summation (b); and In the final summation step (9), the sum resulting from the preceding summation (b) is calculated in each row of the result vector (r) by successive pairwise additions.
2. The method (1) according to claim 1, characterized in that: The matrix (M) is checked based on the matrix elements (ki) with the same values in the columns (Mj) of the matrix (M), since products with the same values can be calculated at these matrix positions with the same matrix elements (ki) in the columns (Mj); the corresponding product of the value of one of the matrix elements (ki) with the same values and the value of the corresponding vector element (vj) of the vector (v) is calculated only once and the calculation result of the product at the other matrix positions with the same values is only called up and not recalculated, in particular, the sign bit of the precalculated product by value is set accordingly when the matrix element (ki) and the corresponding vector element (vj) have different signs.
3. The method (1) according to claim 1 or 2, characterized in that: The matrix (M) is checked for multiple identical matrix elements (Mij) in two different rows (Mi) and the same column (Mj) of the matrix (M), since this corresponds to identical sums or partial sums in the result vector (r), wherein such sums or partial sums are calculated only once and only the calculation results with identical sums or partial sums in other rows are called up and not recalculated for calculating the result vector (r).
4. The method (1) according to any one of claims 1 to 3, characterized in that If another element (Mij) of the matrix (M) has an element value not equal to 0 in the same row (Mi) of the matrix (M) and therefore this element (Mij) in principle participates in the summation in its row, then the sum availability (Pij) of the element (Mij) of the matrix (M) is evaluated as 1 in the case of an element value not equal to 0, wherein the sum availability (Pij) is increased by the value 1 for each conceivable addend pair in the row (Mi) of the matrix (M) that occurs with the same value in another row of the matrix (M).
5. The method (1) according to any one of claims 1 to 4, characterized in that In the case of a plurality of identically occupied top rows (Mi) of a matrix (M) in the sequence determination step (8), a total sum availability (qi) is determined for each of these rows (Mi) of the matrix (M), which corresponds to the sum of the sum availability (Pij) of the matrix elements (Mij) of the corresponding row (Mi), and the row (Mi) having the highest total sum availability (qi) is selected.
6. The method (1) according to claim 5, characterized in that: In the case where there are multiple rows (Mi) with the same highest occupancy (si) and with the same total and availability (qi) in the matrix (M), one of the multiple rows (Mi) is selected randomly or by selecting the row with the smallest row number or by selecting the row with the largest row number.
7. The method (1) according to any one of claims 1 to 6, characterized in that In the last summation step (9), an auxiliary matrix (M") is formed, which has a number of rows corresponding to the number of rows of the matrix (M) and a number of columns corresponding to the number of sums (b) in the determined sequence of sums (b); the sums (b) of the determined sequence of sums (b) are entered in each column, i.e. in the row for which the sum (b) provides the value in the result vector (r); the sequence determination step (8) is carried out using the auxiliary matrix (M"); and this is repeated several times with the auxiliary residual matrix (M'") replacing the auxiliary matrix (M"). The sequence determines step (8) until the auxiliary residual matrix (M'") no longer has any matrix elements that are not equal to zero, wherein the auxiliary residual matrix (M'") is generated from the auxiliary matrix (M") by setting all the following matrix elements (M"ij) in the auxiliary matrix (M") to zero, which matrix elements participate in the summation (b) arranged in the sequence; implementing the summation (b) in the now extended planned sequence; and calculating the sum generated in the previously extended summation (b) in each row of the result vector (r) by successive pairwise additions.
8. The method (1) according to claim 7, characterized in that The method steps according to claim 7 are repeated a number of times by analogy until the required number of summations (b) for the matrix-vector multiplication has been completely decomposed into a sequence of summations (b) of two addends.
9. The method (1) according to any one of claims 1 to 8, characterized in that The control device (2) is a real electronic control device (2) or a virtual electronic control device (2).
10. The method (1) according to any one of claims 1 to 9, characterized in that In the context of an environment model (4), the determined sequence for summing (b) is used as a basis for calculating matrix-vector multiplications and the environment model (4) is transferred to a hardware description for a programmable logic module, wherein the programmable logic module is a computing unit of a simulator (3) and is configured using the hardware description.
11. Computer program comprising instructions which, when executed by a simulator (3), cause the simulator (3) to carry out the method (1) according to one of claims 1 to 10.
