A comprehensive tool logic simplification method for removing redundant resources, a computer-readable storage medium and an electronic device

Abstract

The present invention provides a method for simplifying the logic of a synthesis tool for removing redundant resources, including obtaining a mapping set of output port signals of a logic unit c to a logic unit output of the logic unit c, inserting the logic unit c into a redundant logic unit set; processing the redundant logic unit set, including traversing each wire net in a circuit netlist, finding a logic unit c whose output port signal s is an output wire net or a wire net with a keep attribute from the logic unit mapping set, or deleting the logic unit c from the redundant logic unit set when there is an input port signal of the logic unit c1 in the logic unit output mapping set that is the same as the output port signal s of the logic unit c; obtaining a redundant wire net set in the circuit netlist, and deleting all wire nets in the redundant wire net set from the circuit netlist. The present invention also provides a computer-readable storage medium and an electronic device to implement the steps in the above-mentioned method for simplifying the logic of a synthesis tool for removing redundant resources.

Description

Technical Field

[0001] The present invention belongs to the technical field of FPGA synthesis tools, and in particular relates to a synthesis tool logic simplification method for removing redundant resources, a computer-readable storage medium and an electronic device. Background Art

[0002] Logic synthesis is an important step in the FPGA EDA software design process. It converts the Verilog / VHDL circuit files at the behavioral level or register transfer level (RTL) input by the user into a netlist file composed of FPGA basic logic units such as lookup tables (LUTs) and flip-flops (FFs). FPGA logic synthesis includes two stages: synthesis and mapping. Synthesis is to convert the circuit files at the behavioral level or RTL into a logic netlist composed of gate circuits; mapping is to map the logic netlist composed of gate circuits into a netlist file composed of FPGA basic logic units.

[0003] Area, that is, the number of resources, is an important indicator of FPGA logic synthesis tools. Reducing the number of resources after FPGA logic synthesis plays a very important role in improving the routing rate and timing performance of FPGA software. In the processing of FPGA synthesis tools, a large number of redundant resources will be generated. As the scale of user circuits becomes larger and larger, the number of integrated logic units is also very large. Therefore, it is very important to remove redundant logic resources and simplify the logic of the circuit netlist generated by FPGA synthesis to reduce the area of ​​FPGA synthesis. At the same time, this process is also a very time-consuming process.

[0004] Therefore, it is necessary to design a method for logical simplification of FPGA circuit netlist, which can quickly and accurately remove redundant resources and realize logical simplification of FPGA circuit netlist. Summary of the invention

[0005] The present invention provides a synthesis tool logic simplification method for removing redundant resources, which can quickly and accurately remove redundant resources and realize the logic simplification of FPGA circuit netlist.

[0006] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0007] In order to achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides a method for removing redundant resources from a synthesis tool logic simplification method, including traversing each logic unit c in the circuit netlist, storing the mapping relationship between the output port signal of the logic unit c and the logic unit c in the logic unit output mapping set, and inserting the logic unit c into the redundant logic unit set; processing the redundant logic unit set, including traversing each wire net in the circuit netlist, finding the logic unit c whose output port signal s is an output wire net or a wire net with a keep attribute from the logic unit output mapping set, or deleting the logic unit c in the redundant logic unit set when the input port signal of the logic unit c1 in the logic unit output mapping set is the same as the output port signal s of the logic unit c; obtaining the redundant wire net set in the circuit netlist, and deleting all the wire nets in the redundant wire net set from the circuit netlist. The beneficial effect of this technical solution is that it can remove redundant resources in the circuit netlist, realize the logic simplification of the FPGA circuit netlist, thereby reducing the number of logic resources after circuit synthesis and improving the performance after circuit synthesis.

[0008] The processing of the redundant logic unit set includes traversing each wire net w in the circuit netlist, and if the wire net w is an output wire net or has a keep attribute, searching for a logic unit c whose output port signal is the wire net w from a logic unit output mapping set, inserting the logic unit c whose output port signal is the wire net w into a queue, and deleting the logic unit c from the logic unit output mapping set; taking out a logic unit c from the queue each time, finding a logic unit c1 in the logic unit output mapping set, the output port signal of the logic unit c1 being the same as the input port signal s of the logic unit c, inserting the logic unit c1 into the queue, and deleting the logic unit c from the redundant logic unit set at the same time.

[0009] Repeatedly taking out logic units c from the queue for processing until all logic units c in the queue have been processed; after completing the processing of the redundant logic unit set, all logic units c in the redundant logic unit set are deleted from the netlist.

[0010] Obtain a set of redundant nets in a circuit netlist, including traversing each connection in the circuit netlist, obtaining two nets equivalent to the connection, comparing the priorities of the two nets, and inserting the net with a lower priority into the set of nets to be deleted; traversing each logic unit c in the netlist, and for each input port signal s of the logic unit c, adding the input port signal s to the set of used signals; traversing each net w in the circuit netlist, if the net w is neither an input or output net nor has a keep attribute, and the net w cannot be found in the set of used signals, then adding the net w to the set of redundant nets.

[0011] After inserting the low-priority nets into the set of nets to be deleted, all the places where the low-priority nets appear in the netlist are replaced with the high-priority nets.

[0012] Comparing the priorities of two equivalently connected nets, including comparing the priorities of the nets based on the properties of the two nets to be compared: whether they are input nets, output nets, output signals, or input signals; and the length of the net name character string.

[0013] Set the two nets that are compared for equivalent connection to be net s1 and net s2; if net s1 is an input net and net s2 is an input net, the net with a smaller net name string length has priority; if net s1 is an input net and net s2 is not an input net, net s1 has a higher priority and net s2 is a redundant net; if net s1 is an output net and net s2 is an output net, the net with a smaller net name string length has priority; if net s1 is an output net and net s2 is not an output net, net s1 has a higher priority and net s2 is a redundant net; if net s1 is not an output net and net s2 is an input or output signal, net s2 has a higher priority and net s1 is a redundant net; if net s1 is not an output net and net s2 is an input or output signal, net s2 has a higher priority and net s1 is a redundant net; if net s1 is not an output net and net s2 is not an input or output signal, the net with a smaller net name string length has priority.

[0014] If the number of elements in the redundant net set is greater than 0, the elements in the redundant net set continue to be cleared, and the next operation of obtaining the redundant net set in the circuit netlist is entered until the number of elements in the redundant net set is 0, and the process is exited.

[0015] Another technical solution of the present invention provides a computer-readable storage medium, in which program codes are stored. The program codes are called by a processor to execute the above-mentioned synthesis tool logic simplification method for removing redundant resources.

[0016] Another technical solution of the present invention provides an electronic device, comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the above-mentioned synthesis tool logic simplification method for removing redundant resources.

[0017] Compared with the prior art, the beneficial effects of the present invention mainly include that it can accurately and comprehensively remove redundant resources in the circuit netlist, realize the logic simplification of the FPGA circuit netlist, thereby reducing the number of logic resources after circuit synthesis and improving the performance of the circuit after synthesis.

[0018] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 The present invention is a flow chart of a method for simplifying logic of an FPGA synthesis tool for removing redundant resources.

[0021] Figure 2 It is a flowchart of the redundant logic unit set processing method in the present invention.

[0022] Figure 3 The present invention is a flow chart of a method for obtaining a redundant network set in a circuit netlist.

[0023] Figure 4 It is a flowchart of the method for comparing the priorities of two network lines according to the present invention. DETAILED DESCRIPTION

[0024] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0025] Example 1

[0026] Embodiment 1 provides a synthesis tool logic simplification method for removing redundant resources, including the following steps: first, traverse each logic unit c in the circuit netlist, store the mapping relationship between the output port signal of the logic unit c and the logic unit c in the logic unit output mapping set, and insert the logic unit c into the redundant logic unit set; then process the redundant logic unit set, including traversing each wire net in the circuit netlist, finding out from the logic unit output mapping set the logic unit c whose output port signal s is an output wire net or a wire net with a keep attribute, wherein the keep attribute indicates that the wire net remains as it is without adjustment, or when there is a logic unit c1 in the logic unit output mapping set whose input port signal is the same as the output port signal s of the logic unit c, the logic unit c in the redundant logic unit set is deleted; finally, the redundant wire net set in the circuit netlist is obtained, and all the wire nets in the redundant wire net set are deleted from the circuit netlist.

[0027] For the specific process, see Figure 1 The flowchart in includes the following specific steps:

[0028] Step 1-1: traverse each logic unit c in the circuit netlist, store the mapping relationship from the output port signal of the logic unit c to the logic unit c in the logic unit output mapping set M; and insert the logic unit c into the redundant logic unit set U.

[0029] Step 1-2: Processing the redundant logic unit set includes traversing each line net w in the circuit netlist. If the line net w is an output line net or w has a keep attribute, searching the logic unit c whose output port signal is the line net w from the logic unit output mapping set M, inserting the logic unit c into the queue Q, and deleting the logic unit c from the redundant logic unit set U.

[0030] Step 1-3: Take out the first logic unit c from the queue Q, and for each input port signal s of the logic unit c, search for the logic unit c1 with the output port signal s from the logic unit output mapping set M, then insert the logic unit c1 into the queue Q, and delete the logic unit c from the redundant logic unit set U.

[0031] Step 1-4: Continue step 3 until all logical units c in queue Q have been processed.

[0032] Step 1-5: Delete all logic cells c in the set of redundant logic cells U from the circuit netlist.

[0033] Step 1-6: Get the redundant net set D in the circuit netlist. First, traverse each connection in the circuit netlist, get the two nets s1 and s2 that are equivalent to the connection, compare the priorities of s1 and s2, if s1 has a higher priority than s2, then insert s2 into the redundant net set D to be deleted, and replace all occurrences of s2 in the netlist with s1; vice versa. Next, traverse each logic unit c in the netlist, and for each port signal s of c, add s to the used signal set Used. Then traverse each net w in the netlist, if net w is neither an input or output net, nor does it have the keep attribute, and net w cannot be found in the used signal set Used, then insert net w into the redundant net set D.

[0034] Step 1-7: Delete each net w in the redundant net set D from the netlist.

[0035] Step 1-8: If the number of elements in the redundant network set D is greater than 0, clear the elements in the redundant network set D and proceed to the next iteration. The iteration here means repeating steps 1-6 and 1-7 until there are no elements in the redundant network set D, then you can exit the process.

[0036] See also Figure 2 The main function of the redundant logic unit set processing method is to obtain a redundant logic unit set U. It mainly includes the following steps:

[0037] Step 2-1: Queue Q takes out the first logical unit c and executes step 2-2.

[0038] Step 2-2: For each input port signal s of the logic unit c, execute step 2-3.

[0039] Step 2-3: Search the logic cell c1 whose output port signal is s from the logic cell output mapping set M.

[0040] Step 2-4: Insert the logical unit c1 into the queue Q.

[0041] Step 2-5: Delete the logical unit c from the redundant logical unit set U.

[0042] Step 2-6: If there is an unprocessed logical unit c in the queue Q, go to step 2-1 and enter the next iteration; otherwise, exit the processing of this process.

[0043] The process of obtaining the redundant network set D in the circuit netlist can be found in Figure 3 , specifically including the following steps:

[0044] Step 3-1: Traverse each connection in the circuit netlist, obtain two equivalent line nets (s1, s2), and execute step 3-2.

[0045] Step 3-2: Compare the priorities of net s1 and net s2. If the priority of net s1 is higher than that of net s2, execute step 3-3; otherwise, execute step 3-4.

[0046] Step 3-3: Insert net s2 into the redundant net set D, and replace all occurrences of net s2 in the netlist with net s1.

[0047] Step 3-4: Insert net s1 into the redundant net set D, and replace all occurrences of net s1 in the netlist with net s2.

[0048] Step 3-5: Traverse each logic cell c in the netlist, and execute step 3-6 for each input port signal s of the logic cell c.

[0049] Step 3-6: Add each input port signal s of the logic unit c to the used signal set Used.

[0050] Step 3-7: Traverse each wire net w in the netlist and execute step 3-8.

[0051] Step 3-8: If the net w is neither an input nor an output net, nor has the keep attribute, and the net w cannot be found in the used signal set Used, execute step 3-9.

[0052] Step 3-9: Insert the wire net w into the redundant wire net set D.

[0053] For the comparison of the priorities of nets s1 and s2 above, see Figure 4 The flowchart in the figure includes the following steps:

[0054] Step 4-1: If the line net s1 is an input line net, execute step 4-2; otherwise, execute step 4-3.

[0055] Step 4-2: If the line net s2 is an input line net, execute step 4-6; otherwise, execute step 4-7.

[0056] Step 4-3: If the line net s1 is an output line net, execute step 4-4; otherwise, execute step 4-5.

[0057] Step 4-4: If the line net s2 is an output line net, execute step 4-6; otherwise, execute step 4-7.

[0058] Step 4-5: If the line network s2 is an input or output signal, execute step 4-8, otherwise execute step 4-6.

[0059] Step 4-6: If the name string of the wire net s1 is smaller than the name string of the wire net s2, execute step 4-7; otherwise, execute step 4-8.

[0060] Step 4-7: The priority of network s1 is higher than that of network s2, so network s2 is a redundant network.

[0061] Step 4-8: The priority of network s2 is higher than that of network s1, so network s1 is a redundant network.

[0062] Example 2

[0063] Embodiment 2 provides a computer-readable storage medium, in which a program code is stored, and the program code is called by a processor to execute a method for simplifying the logic of a comprehensive tool for removing redundant resources in Embodiment 1. By storing a program for implementing the method for simplifying the logic of a comprehensive tool for removing redundant resources in a computer-readable storage medium and calling and executing it by a processor, the execution efficiency of the method for simplifying the logic of a comprehensive tool for removing redundant resources can be effectively improved, while ensuring that no error occurs during each execution.

[0064] Example 3

[0065] Embodiment 3 provides an electronic device comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute a synthesis tool logic simplification method for removing redundant resources in Embodiment 1.

[0066] The above is a detailed introduction to a comprehensive tool logic simplification method for removing redundant resources, a computer-readable storage medium, and an electronic device provided by the present invention. This article uses specific examples to illustrate the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for simplifying the logic of a synthesis tool by removing redundant resources, characterized in that: The method comprises traversing each logic unit c in the circuit netlist, storing a mapping relationship between an output port signal of the logic unit c and the logic unit c in a logic unit output mapping set, and inserting the logic unit c into a redundant logic unit set; Processing the redundant logic unit set includes traversing each line net in the circuit netlist, finding a logic unit c whose output port signal s is an output line net or a line net with a property of keeping the same from the logic unit output mapping set, or deleting the logic unit c in the redundant logic unit set when there is a logic unit c1 whose input port signal is the same as the output port signal s of the logic unit c in the logic unit output mapping set; Obtaining a redundant net set in a circuit netlist, including: traversing each connection in the circuit netlist, obtaining two nets equivalent to the connection, comparing the priorities of the two nets, and inserting the net with a lower priority into the set of nets to be deleted; traversing each logic unit c in the netlist, and for each input port signal s of the logic unit c, adding the input port signal s to the used signal set; traversing each net w in the circuit netlist, if the net w is neither an input or output net nor has a keep-as-is property, and the net w cannot be found in the used signal set, then adding the net w to the redundant net set, and deleting all the nets in the redundant net set from the circuit netlist.

2. The method for simplifying the logic of a synthesis tool for removing redundant resources according to claim 1, characterized in that: Processing the redundant logic unit set includes traversing each wire net w in the circuit netlist, and if the wire net w is an output wire net or has a keep-as-is attribute, searching for a logic unit c whose output port signal is the wire net w from a logic unit output mapping set, inserting the logic unit c whose output port signal is the wire net w into a queue, and deleting the logic unit c from the logic unit output mapping set; Each time a logic unit c is taken out from the queue, the logic unit c1 is found in the logic unit output mapping set, the output port signal of the logic unit c1 is the same as the input port signal s of the logic unit c, the logic unit c1 is inserted into the queue, and the logic unit c is deleted from the redundant logic unit set.

3. The method for simplifying the logic of a synthesis tool for removing redundant resources according to claim 2, characterized in that: Repeatedly take out logical unit c from the queue for processing until all logical units c in the queue have been processed; After the processing of the redundant logic cell set is completed, all logic cells c in the redundant logic cell set are deleted from the netlist.

4. The method for simplifying the logic of a synthesis tool for removing redundant resources according to claim 1, characterized in that: After inserting the low-priority nets into the set of nets to be deleted, all the places where the low-priority nets appear in the netlist are replaced with the high-priority nets.

5. The method for simplifying the logic of a synthesis tool for removing redundant resources according to claim 1, characterized in that: Compare the priorities of two equivalent line nets. Including, according to the properties of the two wire nets to be compared: whether they are input wire nets, output wire nets, output signals, input signals; And the length of the line network name string, and then compare the line network priority.

6. The method for simplifying the logic of a synthesis tool for removing redundant resources according to claim 5, characterized in that: The two wire nets to be compared for equivalent connection are wire net s1 and wire net s2; If net s1 is an input net and net s2 is an input net, the net with a smaller net name string length has priority; If network s1 is an input network and network s2 is not an input network, network s1 has a higher priority and network s2 is a redundant network. If net s1 is an output net and net s2 is an output net, the net with a smaller net name string length has priority; If network s1 is an output network and network s2 is not an output network, network s1 has a higher priority and network s2 is a redundant network. If network s1 is not an output network and network s2 is an input or output signal, network s2 has a higher priority and network s1 is a redundant network. If net s1 is not an output net and net s2 is not an input or output signal, the net with the smaller net name string length has priority.

7. The method for simplifying the logic of a synthesis tool for removing redundant resources according to claim 1, characterized in that: If the number of elements in the redundant net set is greater than 0, the elements in the redundant net set continue to be cleared, and the next operation of obtaining the redundant net set in the circuit netlist is entered until the number of elements in the redundant net set is 0, and the process is exited.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program codes, and the program codes are called by a processor to execute the logic simplification method for removing redundant resources from a synthesis tool as described in any one of claims 1 to 7.

9. An electronic device, characterized in that: comprising one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the synthesis tool logic simplification method for removing redundant resources as described in any one of claims 1-7.

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