An AI algorithm-driven method for extracting parasitic capacitance of 2.5-D wiring layer parameterized structures

Abstract

The present invention discloses a parasitic capacitance extraction method of a 2.5-D parasitic capacitance of a wiring layer parameterized structure driven by an AI algorithm, which relates to integrated circuit EDA technology, and proposes this solution to solve the problems of slow solution in the prior art. The AI ​​Model is used to solve the INPUT file of a known pattern type; the BEM field solver is used to solve the INPUT file of an unknown pattern type, and all the parametric features of the unknown pattern type are automatically extracted at the same time, and the principal component analysis method is used to automatically reduce the dimension of all the parametric features, obtain the parametric structure feature vector of the unknown pattern type, call the layout pattern generator that can add process fluctuations to generate the training data of the unknown pattern type, and use it to train the ANN model of the unknown pattern type, update the training results to the AI ​​Model, and convert the unknown pattern type into a known pattern type. The advantage is that extraction can be performed for each sampling point, the AI ​​Model library can be automatically improved, and the unknown pattern type can be converted into a known pattern type, thereby gradually accelerating the speed of parasitic capacitance extraction.

Description

Technical Field

[0001] The present invention relates to integrated circuit EDA technology, and in particular to an AI algorithm-driven wiring layer parameterized structure 2.5-D parasitic capacitance extraction method. Background Art

[0002] With the rapid development of the integrated circuit (IC) industry, the characteristic size of transistors has been continuously reduced, which has led to an increase in the number of transistors in the IC and the density of metal interconnects in the wiring layer, which will greatly increase the parasitic effects on the chip. At the same time, the RC delay caused by the parasitic effects of interconnects in the wiring layer will be more obvious at advanced process nodes, especially parasitic capacitance. The performance of high-speed circuits, especially high-speed digital circuits, is closely related to the RC delay of the circuit. Therefore, high-precision wiring layer parasitic capacitance extraction has become one of the important links in the IC back-end design process.

[0003] The traditional 2.5-D wiring layer parasitic capacitance extraction process obtains a large number of 2-D vertical cross-sectional images of the wiring layer by discretizing the cross-section in the vertical direction. The 2-D vertical cross-sectional images of each wiring layer generated after discretization are discretized by sampling windows, and the spatial electromagnetic field around the main conductor in the sampling window is solved using a field solver based on the boundary element method (Boundary Element Method, BEM) or the finite element method (Finite Element Method, FEM). Finally, the parasitic capacitance extraction results of the main conductor with the same name in all sampling windows are accumulated to obtain the total parasitic capacitance value of the main conductor in the 2-D vertical cross-sectional image of a single wiring layer. A type of cross-sectional images with similar topological relationships between metal conductors in the sampling window are classified, and this type of sampling window is called a pattern. The formula for calculating the parasitic capacitance of each conductor in a certain type of pattern is fitted, and the corresponding pattern library is constructed, so that the corresponding formula can be directly called for calculation when the parasitic capacitance in the same pattern is extracted next time. The parasitic capacitance extraction process is as follows: Figure 1 shown.

[0004] However, facing the very large scale integrated circuit (VLSI) under advanced process nodes, the number of parasitic capacitance elements in the on-chip wiring layer exceeds billions, which leads to the parasitic capacitance extraction process based on the field solver taking days or even months in a single iteration of chip layout design, which greatly reduces the speed of chip iteration under advanced process. At the same time, for the large number of pattern types generated by different processes, parasitic parameter extraction (PEX) engineers are required to continuously adjust the pattern library and the fitting formulas in the pattern library to ensure the accuracy of the subsequent calls to the fitting formulas in the pattern library for parasitic capacitance extraction. This process greatly increases the construction cycle, update frequency and labor cost of the pattern library.

[0005] In recent years, some scholars have also conducted research in this direction. However, due to the different description methods of sampling point files between different processes, there is no unified standard for the complexity of the parameterized structure design of the INPUT file at a single sampling point, which makes the parasitic capacitance extraction of the wiring layer driven by AI algorithms still remain in the academic research stage. In 2019, scholars from Hirosaki University in Japan proposed a 3-D parasitic capacitance extraction method based on the ANN model [1]. This method extracts features from a specific 3-D structure as the structural parameter feature vector of the 3-D structure, constructs an ANN model, and extracts the corresponding 3-D structure parasitic capacitance. Although this method can directly extract the parasitic capacitance of the 3-D structure, since the pattern types of 3-D structures are far more than those of 2-D structures, this method can only be applied to the parasitic capacitance extraction of some specific 3-D structures, and the extracted structural parameter feature vector of the 3-D structure will cause matching errors when identifying the pattern type of the 3-D structure.

[0006] Scholars from the American University of Cairo and engineers from Siemens Electronic Design Automation proposed three neural network-based wiring layer parasitic capacitance extraction methods [2]-[4] between 2021 and 2022. They modeled different pattern types and constructed a deep neural network (DNN) to extract parasitic capacitance of known pattern types. However, when the three methods describe the INPUT files of different pattern types in parameterized structures, the dimension of the parameterized structure feature vectors generated is high, resulting in a heavy burden on model training and difficulty in automatically building a DNN model. When targeting unknown pattern types, it is still necessary to manually build a DNN model for the corresponding pattern type.

[0007] [1] Kasai R, Kanamoto T, Imai M, et al. Neural network-based 3D IC interconnect capacitance extraction[C] / / 2019 2nd International Conference on Communication Engineering and Technology(ICCET). IEEE, 2019:168-172.

[0008] [2] Abouelyazid M S, Hammouda S, Ismail Y. Connectivity-based machine learning compact models for interconnect parasitic capacitances[C] / / 2021 ACM / IEEE 3rd Workshop on Machine Learning for CAD(MLCAD). IEEE, 2021:1-6.

[0009] [3] Abouelyazid M S, Hammouda S, Ismail Y. Fast and accurate machine learning compact models for interconnect parasitic capacitances considering systematic process variations[J]. IEEE Access, 2022, 10:7533-7553.

[0010] [4] Abouelyazid M S, Hammouda S, Ismail Y. Accuracy-based hybrid parasitic capacitance extraction using rule-based, neural-networks, and field-solver methods[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 41(12):5681-5694. Summary of the Invention

[0011] The purpose of the present invention is to provide an AI algorithm driven wiring layer parameterized structure 2.5-D parasitic capacitance extraction method to solve the problems existing in the above-mentioned prior art.

[0012] The present invention describes an AI algorithm driven wiring layer parameterized structure 2.5-D parasitic capacitance extraction method, which uses an AI Model to solve an INPUT file of a known pattern type; uses a BEM field solver to solve an INPUT file of an unknown pattern type, and automatically extracts all parameterized features of the unknown pattern type at the same time, uses principal component analysis to automatically reduce the dimension of all parameterized features, obtains a parameterized structural feature vector of the unknown pattern type, calls a layout pattern generator that can add process fluctuations to generate training data for the unknown pattern type, and uses the ANN model of the unknown pattern type to update the training results to the AI ​​Model to convert the unknown pattern type into a known pattern type.

[0013] The advantage of the AI ​​algorithm-driven 2.5-D parasitic capacitance extraction method for the wiring layer parameterized structure described in the present invention is that the parasitic capacitance can be extracted from the INPUT file generated by each sampling point in the 2.5-D parasitic capacitance extraction process, and the AI ​​Model library can be automatically improved to realize the conversion of unknown pattern types into known pattern types, thereby gradually accelerating the speed of parasitic capacitance extraction. This method has been verified on 9 pattern types under a 28nm process. Compared with the 9 pattern types that are all unknown pattern types, after the 9 pattern types are converted into known pattern types, under the premise of higher parasitic capacitance extraction accuracy (average relative error of a single sampling point ≤1%), the parasitic capacitance extraction speed is increased by 192.9% to 598.8%. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a flow chart of a method for extracting parasitic capacitance in the prior art.

[0015] Figure 2 It is a schematic diagram of the process of the method described in the present invention.

[0016] Figure 3 It is a visualization diagram of an INPUT file of a specified Pattern type in an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The sampling window for extracting parasitic capacitance under a specific process node, i.e., the INPUT file, includes N metal conductors, one-to-one corresponding metal conductor information; M polygonal media, one-to-one corresponding polygonal media information; sampling window information. The N metal conductors specifically include 1 main conductor and N-1 environmental conductors. The information of each metal conductor includes: conductor name, number of conductor edges, and coordinates of each vertex of the conductor. The information of each polygonal medium includes: medium name, number of medium edges, coordinates of each vertex of the medium, and dielectric constant of the medium. The sampling window information includes the coordinates of the four vertices of the sampling window reflected by the INPUT file.

[0018] The process of the AI ​​algorithm driven wiring layer parameterized structure 2.5-D parasitic capacitance extraction method described in the present invention is as follows: Figure 2 As shown, it is divided into the parasitic capacitance extraction part and the AI ​​Model training part.

[0019] The INPUT file is firstly subjected to multi-modal recognition to determine whether the INPUT file is of a known pattern type or an unknown pattern type. The multi-modal information includes the name of the main conductor, the name of the environmental conductor, and the topological relationship between the main conductor and each environmental conductor.

[0020] For an INPUT file of a known pattern type, extract the parameterized structural feature vector corresponding to the pattern type, describe the INPUT file through the parameterized structural feature vector of the pattern type, call the corresponding ANN model from the AI ​​Model library, use the parameterized structural feature vector as input to solve the AI ​​Model, and obtain the parasitic capacitance that needs to be extracted.

[0021] For example, if the pattern type is PLATE3L_c1, the visualization effect of an INPUT file of this pattern type is as follows Figure 3 As shown. The parasitic capacitances that need to be extracted in the INPUT file include the total parasitic capacitance c1 of the main conductor, the N-1 coupling capacitances formed by the main conductor and the N-1 environmental conductors, namely c2, lEnv, rEnv, topleft, topright, botleft and botright. When the INPUT file is described using the parameterized structure feature vector of the pattern type, the corresponding parameterized structure feature vector is [w1, w2, space, edgeSpcae, bot_hight, top_hight, c1_thick].

[0022] For the INPUT file of unknown pattern type, it is used as input and sent to the BEM field solver for field solution to obtain the parasitic capacitance to be extracted. At the same time, the unknown pattern type is converted into a known pattern type through the following steps:

[0023] First, the overall parametric features of the unknown pattern type are extracted, that is, the geometric dimensions, spatial distribution, material properties and other information of all conductors and media in the INPUT file of the unknown pattern type are obtained. The collection of this information is called the overall parametric features of the unknown pattern type.

[0024] Using principal component analysis (PCA), under the premise of ensuring that the proportion of principal components is greater than 99%, the amount of information in all parameterized features of the unknown pattern type is reduced as much as possible, that is, the dimension of the parameterized structural feature vector is reduced, and the remaining information is the parameterized structural feature vector of the unknown pattern type;

[0025] The parameterized structural feature vector of the unknown pattern type and the legal variation range of each dimension of the feature vector are sent to the layout pattern generator LSG that can add process fluctuations, generate a large number of legal INPUT files of the unknown pattern type, and extract the parameterized structural features of these INPUT files as the input for ANN model training. At this time, the user can add specified process fluctuations as needed. The process fluctuations that can be added include changes in metal thickness and width, load effects of the medium, and trapezoidal changes in the metal. The INPUT file containing the process fluctuations is sent to the BEM field solver to obtain the output of the corresponding INPUT file as the output of the ANN model training. The obtained training input and output are merged and called the training set of the unknown pattern type;

[0026] Use TensorFlow architecture to build an ANN model to train the AI ​​Model of the unknown pattern type. Use a custom loss function: where y i,pre is the predicted value of the ith parasitic capacitance; y i,true is the true value of the i-th parasitic capacitor. The training set of the unknown pattern type is divided into a training set and a validation set in a ratio of 7:3 to train the ANN model of the unknown pattern type. When the training set loss and the validation set loss are both less than 0.01, the training is stopped. At this time, the ANN model of the unknown pattern type after training is output, and the unknown pattern type is named. The trained ANN model is expanded to the AI ​​Model library to complete the process of converting the unknown pattern type to a known pattern type.

[0027] After the unknown pattern type is converted into a known pattern type, the parasitic capacitance of the pattern type is extracted again and solved using the AI ​​Model, thereby improving the speed of extracting the parasitic capacitance of the pattern type while ensuring the extraction accuracy.

[0028] When the input INPUT files of the method described in the present invention are all of unknown pattern type, the parasitic extraction speed is consistent with the traditional method of extracting parasitic capacitance using a BEM field solver. However, after completing the parasitic capacitance extraction of the INPUT file of unknown pattern type, the present invention will construct an ANN model of the unknown pattern type, improve the AI ​​Model library, and convert the unknown pattern type into a known pattern type. Since the speed of extracting parasitic capacitance using the AI ​​Model on a single INPUT file is faster than the speed of extracting parasitic capacitance using the BEM field solver, as the number of repetitions of the method of the present invention increases, the unknown pattern types will gradually decrease, the known pattern types will gradually increase, and the extraction speed of parasitic capacitance will gradually increase. The test results are shown in the following table:

[0029]

[0030] For those skilled in the art, various other corresponding changes and deformations can be made according to the technical solutions and concepts described above, and all of these changes and deformations should fall within the protection scope of the claims of the present invention.

Claims

1. An AI algorithm driven 2.5-D parasitic capacitance extraction method for wiring layer parameterized structure, It is characterized in that Use AI Model to solve INPUT files of known pattern types; The INPUT file of the unknown pattern type is solved by using the BEM field solver, and all the parametric features of the unknown pattern type are automatically extracted. The principal component analysis method is used to automatically reduce the dimension of all the parametric features, and the parametric structural feature vector of the unknown pattern type is obtained. The layout pattern generator that can add process fluctuations is called to generate training data of the unknown pattern type for training the ANN model of the unknown pattern type, and the training results are updated to the AIModel to convert the unknown pattern type into a known pattern type. After the unknown pattern type is converted to a known pattern type, the parasitic capacitance of the pattern type is extracted again and solved using the AI ​​Model; The INPUT file first undergoes multimodal recognition to determine whether the INPUT file is of a known pattern type or an unknown pattern type; The multimodal information includes the name of the main conductor, the name of the environmental conductor, and the topological relationship between the main conductor and each environmental conductor; For an INPUT file of a known pattern type, the specific steps are as follows: Extract the parameterized structural feature vector corresponding to the pattern type, describe it through the parameterized structural feature vector of the pattern type, call the corresponding ANN model from the AI ​​Model library, use the parameterized structural feature vector as input to solve the AIModel, and obtain the parasitic capacitance to be extracted; For an INPUT file of unknown pattern type, convert the unknown pattern type into a known pattern type through the following steps: First, all parameterized features of the unknown pattern type are extracted, and the information set of all parameterized features is called the all parameterized features of the unknown pattern type; Using principal component analysis, under the premise that the principal component accounts for more than 99%, the amount of information in all parameterized features is reduced, and the remaining information is the parameterized structural feature vector of the unknown pattern type; The parameterized structural feature vector of the unknown pattern type and the legal variation range of each dimension of the feature vector are sent to a layout pattern generator that can add process fluctuations to generate a legal INPUT file of the unknown pattern type, and the parameterized structural features of these INPUT files are extracted as input for ANN model training; the INPUT file containing process fluctuations is sent to a BEM field solver to obtain the output of the corresponding INPUT file as the output of ANN model training; the obtained training input and output are merged to be called the training set of the unknown pattern type; Use the TensorFlow architecture to build an ANN model to train the AIModel of the unknown pattern type; use a custom loss function: where y i,pre is the predicted value of the ith parasitic capacitance; y i,true is the true value of the i-th parasitic capacitance; the training set of the unknown pattern type is divided into a training set and a validation set in a ratio of 7:3 to train the ANN model of the unknown pattern type; the training is stopped when the training set loss and the validation set loss are both less than 0.01, at which time the trained ANN model of the unknown pattern type is output, and the unknown pattern type is named, and the trained ANN model is expanded to the AI ​​Model library to complete the process of converting the unknown pattern type into a known pattern type.

2. According to the AI ​​algorithm driven wiring layer parameterized structure 2.5-D parasitic capacitance extraction method of claim 1, it is characterized in that: Additive process variations include metal thickness and width variations, dielectric loading effects, and metal trapezoidal variations.

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