Grid driving circuit, grid driving chip, intelligent power module and equipment

Abstract

The invention provides a gate driving circuit, a gate driving chip, an intelligent power module and equipment. The gate drive circuit comprises a first signal output circuit and a second signal output circuit which are connected with a signal output port of the gate drive circuit, and each of the first signal output circuit and the second signal output circuit comprises a switching circuit which is connected with a signal input port of the gate drive circuit. The switch is configured to be switched on or switched off based on a control signal input by the signal input port; the at least two resistors connected in series are connected between the switching circuit and the signal output port; the at least one resistor trimming bonding pad is connected with a node between the two resistors which are connected in series; wherein the electrical connection mode between the resistance trimming bonding pads is changed by adjusting the lead, and the total resistance value of the resistors between the switching circuit and the signal output port is adjusted so as to adjust the grid current, so that the optimal driving of various types of power elements can be realized by adopting one grid driving chip.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a gate drive circuit, a gate drive chip, an intelligent power module and a device. Background Art

[0002] The traditional high-side gate driver chip is mainly based on a high-voltage double-pulse trigger level shift circuit (LEVEL_SHIFTER), a pulse filter (NOISE CANCELLER), an RS latch (RS LATCH), a gate driver circuit (DRIVER), etc. When it is integrated into an intelligent power module (IPM), it is applied to a high-voltage and high-speed environment.

[0003] The gate drive circuit needs to select the appropriate drive current according to the characteristics of the power tube. At present, the fine-tuning of the drive current IO+ and IO- is mainly carried out by selecting the channel through fuse trimming and modifying the metal layer mask. The above methods often sacrifice a large chip area to meet the requirements of the drive tube current density. In addition, the trimming circuit module will also occupy a large chip area, and there is a risk of unsuccessful fuse burning. Modifying the metal layer mask of the chip has the risk of long delivery time and affecting the chip delivery node. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] On one hand, the present application provides a gate driving circuit, comprising: a first signal output circuit and a second signal output circuit connected to a signal output port of the gate driving circuit, wherein each of the first signal output circuit and the second signal output circuit comprises:

[0006] A switch circuit, the switch circuit is connected to the signal input port of the gate drive circuit and is configured to: turn on or off based on a control signal input from the signal input port;

[0007] At least two resistors connected in series, connected between the switch circuit and the signal output port;

[0008] at least one resistance trimming pad connected to a node between two series connected resistors;

[0009] The electrical connection mode between the resistance trimming pads is changed by adjusting the leads, and the total resistance value of the resistor between the switch circuit and the signal output port is adjusted to adjust the gate current.

[0010] The above technical solution has the following advantages or beneficial effects: by adjusting the leads to change the electrical connection mode between the resistance trimming pads, the total resistance value of the resistor between the switch circuit and the signal output port is adjusted to adjust the gate current. The gate current can be adjusted by such a trimming method. Without sacrificing the chip area, the bonding wire (WireBonding) connection method is adopted for programmability to adjust the gate turn-on resistance and the gate turn-off resistance, and then adjust the gate current, so that the optimal drive of various types of power components can be achieved by using one gate drive chip. Therefore, the gate drive circuit trimming method of the present application will not occupy a large chip area. In addition, compared with the traditional fuse trimming method, the resistance trimming method of the present application is simpler, easier to operate and has a high success rate, which can greatly shorten the development cycle of the gate drive chip, reduce development costs, and reduce risks such as affecting chip delivery nodes.

[0011] In some embodiments of the present application, the electrical connection between the resistance trimming pads is changed by adjusting the leads, including:

[0012] Connecting the resistance trimming pad of the first signal output circuit and the resistance trimming pad of the second signal output circuit via a lead; and / or

[0013] When the first signal output circuit includes at least two resistance trimming pads, the two resistance trimming pads of the first signal output circuit are electrically connected via leads; and / or

[0014] When the second signal output circuit includes at least two resistance trimming pads, the two resistance trimming pads of the second signal output circuit are electrically connected through a lead wire.

[0015] The above technical solution has the following advantages or beneficial effects: the gate current can be adjusted by such a trimming method, and the gate opening resistance and the gate closing resistance can be adjusted by programming by means of a wire bonding connection without sacrificing the chip area, so as to adjust the gate current. In some embodiments of the present application, the switch circuit includes:

[0016] A signal input circuit, used for receiving a control signal and processing the control signal to obtain a drive signal;

[0017] The switch module is also connected to the signal input circuit and is configured to be turned on or off at least based on the drive signal output by the signal input circuit. The switch module of the first signal output circuit is connected to the floating power supply, and the switch module of the second signal output circuit is connected to the floating ground.

[0018] The above technical solution has the following advantages or beneficial effects: by processing the signal input circuit and the input control signal, the signal amplification, phase shift and filtering functions can be realized to improve the driving ability of the switch circuit. The output of the drive signal can be realized by turning on and off the switch circuit, thereby controlling the turning on and off of the target power device.

[0019] In some embodiments of the present application, the switch module includes:

[0020] At least two switch tubes connected in parallel, wherein the at least two switch tubes connected in parallel include a first switch tube and a second switch tube, and a control end of the first switch tube is connected to a signal input circuit and is configured to be turned on or off based on at least a driving signal output by the signal input circuit;

[0021] A gate transmission gate connected to the control end of the second switch tube and configured to: turn on the second switch tube when it is gated, and turn off the second switch tube when it is not gated;

[0022] The switch trim pad is connected to the enable transmission gate and is configured as follows: the switch trim pad is suspended so that the enable transmission gate is not enabled, and the switch trim pad is connected to the floating ground through a lead so that the enable transmission gate is enabled.

[0023] The above technical solution has the following advantages or beneficial effects: by setting at least two parallel switch tubes, the gate drive current can be adjusted by controlling the number of switch tubes that are turned on, thereby realizing the adjustable gate current. By setting the selection transmission gate TG, it is possible to control the on and off of the second switch tube, so that the branch where the second switch tube is located can be selectively applied to the gate drive, which is more flexible. By setting a switch adjustment pad on the gate drive chip, which is used to connect to the floating ground through a lead, as an internal element that triggers the selection of the selection transmission gate TG, without adding a new transmission terminal to realize the transmission of external signals, in this way, the pad on the circuit can be used to realize the combination selection of the gate current IO+ and the gate current IO-, making the gate current adjustment method simpler and more efficient.

[0024] In some embodiments of the present application, the switch module further includes:

[0025] The switch signal generating circuit is arranged between the floating power supply and the floating ground, and the switch signal generating circuit is also connected to the switch trimming pad, and the output end of the switch signal generating circuit is connected to the gate transmission gate, and is configured to: output a control signal to control the gate transmission gate to be gated or not gated, wherein,

[0026] When the switch trim pad is suspended, the switch signal generating circuit outputs a switch signal of a high level signal, so that the gate transmission gate is not gated;

[0027] When the switch trim pad is connected to the floating ground through the lead, the switch signal generating circuit outputs a switch signal of a low level signal, so that the enable transmission gate is enabled.

[0028] The above technical solution has the following advantages or beneficial effects: the switch signal generating circuit can generate a control signal that is adapted to the current requirement of the target power switch tube, which is conducive to realizing the combined selection of the gate current IO+ and the gate current IO-, making the gate current adjustment method simpler and more efficient.

[0029] In some embodiments of the present application, a switch signal generating circuit includes:

[0030] A pull-up resistor, wherein a first end of the pull-up resistor is connected to a floating power supply;

[0031] A pull-down resistor, wherein a first end of the pull-down resistor is connected to the switch trimming pad, and a second end of the pull-down resistor is connected to the pull-up resistor;

[0032] A current limiting resistor, wherein a first end of the current limiting resistor is connected to a second end of the pull-up resistor;

[0033] The filter circuit has an input end connected to the second end of the current limiting resistor, and an output end of the filter circuit outputs a switching signal.

[0034] The above technical solution has the following advantages or beneficial effects: the pull-up resistor, the pull-down resistor, and the current-limiting resistor can play the role of current limiting and voltage dividing to make the circuit run stably, and the filter circuit can filter out the noise in the signal.

[0035] In some embodiments of the present application, the switch signal generating circuit further includes:

[0036] The ESD protection circuit is arranged between the floating power supply and the floating ground, wherein the ESD protection circuit comprises:

[0037] A first protection switch tube, wherein the gate and source of the first protection switch tube are connected to a floating power supply;

[0038] A second protection switch tube, wherein the gate and source of the second protection switch tube are connected to a floating ground, and the drain of the second protection switch tube is connected to the drain of the first protection switch tube.

[0039] The above technical solution has the following advantages or beneficial effects: the ESD protection circuit can prevent static electricity (caused by the lead contacting the pad) from affecting the inside of the circuit, thereby playing a role in protecting the circuit.

[0040] In some embodiments of the present application, the switch tube included in the switch module of the first signal output circuit is a PMOS, and the switch tube included in the switch module of the second signal output circuit is an NMOS.

[0041] The above technical solution has the following advantages or beneficial effects: by using different types of MOS tubes, the switch module of the first signal output circuit and the switch module of the second signal output circuit can be prevented from being turned on at the same time, thereby reducing the risk of device damage caused by simultaneous conduction.

[0042] On the other hand, the present application provides a gate driving chip, including: the gate driving circuit as described above.

[0043] In another aspect, the present application provides an intelligent power module, comprising:

[0044] Target power switch tube;

[0045] The aforementioned gate driver chip, the signal output port of the gate driver chip is connected to the gate of the target power switch tube, and is configured to: control the on or off of the target power switch tube.

[0046] On the other hand, the present application provides a device, which includes the aforementioned gate drive circuit, or includes the aforementioned gate drive chip, or includes the aforementioned intelligent power module.

[0047] Since the above-mentioned gate driving chip, intelligent power module and device include the aforementioned gate driving circuit, they also have the above-mentioned advantages or beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0049] Figure 1 A schematic block diagram of a gate driving circuit in one embodiment of the present application is shown;

[0050] Figure 2 A schematic diagram of the circuit structure of a gate driving circuit in one embodiment of the present application is shown;

[0051] Figure 3 A schematic diagram showing the structure of a switch signal generating circuit of a first signal output circuit in an embodiment of the present application is shown;

[0052] Figure 4 A schematic diagram showing the structure of a switch signal generating circuit of a second signal output circuit in one embodiment of the present application is shown;

[0053] Figure 5A schematic top view of a gate driving chip layout corresponding to a gate driving circuit when a resistance trimming pad is suspended in one embodiment of the present application is shown;

[0054] Figure 6 A schematic top view of a gate drive chip layout corresponding to a gate drive circuit when resistance trimming pads T0T3, T1T4, and T2T5 are connected using wires in one embodiment of the present application is shown;

[0055] Figure 7 A schematic diagram of the circuit structure of a gate drive chip in one embodiment of the present application is shown;

[0056] Figure 8 A schematic structural diagram of an intelligent power module (IPM) in one embodiment of the present application is shown. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the present application more obvious, the example embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the example embodiments described herein. Based on the embodiments of the present application described in the present application, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present application.

[0058] High-voltage gate driver chips are mainly divided into low-side, high-side, single-channel, dual-channel, isolated, half-bridge, full-bridge and other power driver chips. It integrates low-voltage signal transmission logic control circuits to process front-end input signals more accurately. At the same time, in order to drive high-power devices at the back end, it is also equipped with high-voltage output drive circuits. The core function of this circuit product is to convert the front-end microprocessor (MCU) signal into a switch tube (that is, a power switch tube) drive control signal. In normal operation, the high-voltage gate driver chip not only processes the input signal to drive the power switch tube, but also transmits various operating status signals to the external microprocessor (MCU) to monitor the circuit working condition. The intelligent power module (IPM) integrates high-voltage gate driver chips, over-temperature, over-current and under-voltage protection circuits, fault handling circuits and driven power devices. Thanks to its advantages of high switching frequency, low switching loss and strong anti-noise ability, it has strong application potential in the current power electronics field and has a wide range of application scenarios, especially suitable for variable frequency motors and inverter power supply fields.

[0059] The gate drive circuit needs to select the appropriate drive current according to the characteristics of the power tube. Common trimming technologies mainly include laser trimming, fuse trimming, diode trimming and memory trimming. These technologies are widely used in high-precision, low-offset, low-temperature drift analog integrated circuits, such as operational amplifiers, reference base sources, radio frequency circuits, high-performance analog-to-digital / digital-to-analog converters, and highly complex digital-to-analog hybrid chips. However, these technologies are not applicable to the drive current trimming of high-voltage gate drive circuits. The first reason is that in order to meet the high current density requirements, a large chip area needs to be sacrificed for the trimming circuit. The second reason is that the test cost is increased, and the CP test program and FT test program need to be developed to meet the debugging requirements.

[0060] At present, when designing DRIVER drivers, it is necessary to select a suitable driving current based on the characteristics of the power tube. If the driving current is too small, the driving capability is insufficient and the power device loss is increased. If the current is too large, it may cause turn-on oscillation. Designing the driving current means selecting the gate resistance value. A large driving current means reducing the gate resistance Rg. To minimize the switching loss, it is necessary to find the critical value at which the circuit does not oscillate. When the gate driver chip is used in the IPM module, since the Rg resistor is generally not sealed and occupies a limited package substrate area, the Rg value can only be designed in the gate driver chip. At present, the fine-tuning of IO+ and IO- is mainly carried out by selecting the channel through fuse trimming and modifying the metal layer mask. Either increase or decrease the number of parallel driving MOS tubes, or change the series-parallel mode of the resistor to obtain different Rg values. This method will sacrifice a large chip area to meet the requirements of the current density of the driver tube. In addition, the trimming circuit module will also occupy a large chip area, and there is even a risk of unsuccessful fuse burning. Modifying the metal layer mask of the chip has the risk of long delivery time and affecting the chip delivery node.

[0061] In order to solve the above technical problems, in some embodiments of the present application, a gate driving circuit is provided. Figures 1 to 6 , the structure of the gate driving circuit in the embodiment of the present application is described. It is worth mentioning that the technical features of each embodiment of the present application can be combined with each other without conflict.

[0062] In some embodiments, Figure 1 and Figure 2 As shown, the gate driving circuit includes: a first signal output circuit 100 connected to the signal output port VOUT of the gate driving circuit and a second signal output circuit 200. The first signal output circuit (i.e., the high-end driving signal output circuit) and the second signal output circuit 200 (the low-end driving signal output circuit) have basically the same circuit structure.

[0063] The signal output port VOUT of the gate drive circuit is used to connect to the gate of the target power switch tube to output a drive signal to drive the target power switch tube to turn on or off. The target power switch tube (also called a power switch or transistor switch or power transistor) is a power semiconductor device that can be used to drive a load current. For example, the IGBT is turned on or off by activating and deactivating the gate terminal of the IGBT. Applying a positive input voltage signal across the gate and the emitter will keep the device in its "on" state, while making the input gate signal zero or slightly negative will cause it to be "off". There is a turn-on process and a turn-off process for switching the power transistor on and off.

[0064] During the turn-on process, the gate drive circuit can be used to provide a gate current (i.e., a drive current) to the gate of the power transistor to charge the gate to a sufficient voltage for turning on the device. In particular, the current Io+ is a gate driver output current used to boost (i.e., charge) the gate of the power transistor during the turn-on transient. Therefore, the current Io+ is used to turn on the target power switch tube.

[0065] During the turn-off process, the gate drive circuit is used to draw a gate current (i.e., a turn-off current) from the gate of the target power switch tube to discharge the gate voltage sufficiently to turn the device off. Current Io- is the gate driver output current used to discharge the gate of the target power switch tube during the turn-off transient. Therefore, Io- is used to turn off the power transistor.

[0066] The target power switch tube may include an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor field effect transistor (MOSFET) (e.g., a silicon MOSFET or a silicon carbide MOSFET). It should be understood that a MOSFET may replace an IGBT, and vice versa. In this case, when a MOSFET is used to replace an IGBT, in any of the examples described herein, the drain of the MOSFET may replace the collector of the IGBT, the source of the MOSFET may replace the emitter of the IGBT, and the drain-source voltage VDS of the MOSFET may replace the collector-emitter voltage VCE of the IGBT. Therefore, any IGBT module may be replaced by a MOSFET module, and vice versa any MOSFET module may be replaced by an IGBT module.

[0067] In some embodiments, each of the first signal output circuit 100 and the second signal output circuit 200 includes: a switch circuit connected to the signal input port of the gate drive circuit, and configured to: turn on or off based on the control signal input from the signal input port VIN. Figure 1 and Figure 2As shown, the first signal output circuit 100 includes a first switch circuit, and the second signal output circuit 200 includes a second switch circuit. The first switch circuit and the second switch circuit receive an input control signal, which can be based on a pulse width modulation (PWM) scheme, and can be a voltage pulse output from a circuit in the front stage of the gate drive circuit as a control signal. Therefore, during the PWM cycle for controlling the switch circuit, the control signal can be switched between a turn-on voltage level and a turn-off voltage level. Then, the switch circuit is turned on and off respectively.

[0068] In some embodiments, the switch circuit 110, 210 includes a signal input circuit 111, 211 and a switch module 112, 212, which is used for the signal input circuit to receive a control signal VIN and process the control signal to obtain a drive signal; the switch modules 112, 212 are also connected to the corresponding signal input circuits 111, 211, respectively, and are configured as follows: at least based on the drive signal output by the signal input circuit 111, 211, the switch module of the first signal output circuit 100 (that is, the first switch module 112) is connected to the floating power supply VB, and the switch module of the second signal output circuit 200 (that is, the second switch module 212) is connected to the floating ground Vs. Through the signal input circuit and the processing of the input control signal, the signal amplification, phase shift and filtering functions can be realized to improve the driving ability of the switch circuit. The output of the drive signal can be realized by turning on and off the switch circuit, thereby controlling the turning on and off of the target power device.

[0069] In some embodiments, Figure 2 As shown, the first switch circuit 110 includes a first signal input circuit 111 and a first switch module 112. The first signal input circuit 111 is used for the signal input circuit to receive a control signal and process the control signal to obtain a first drive signal; the first switch module 112 is also connected to the first signal input circuit 111 and is configured to be turned on or off based on at least the first drive signal output by the first signal input circuit 111. The second switch circuit includes a second signal input circuit 211 and a first switch module 212. The second signal input circuit 211 is used for the signal input circuit to receive a control signal and process the control signal to obtain a second drive signal; the first switch module 212 is also connected to the second signal input circuit 211 and is configured to be turned on or off based on at least the second drive signal output by the second signal input circuit 211.

[0070] like Figure 2As shown, the control signal, i.e., the VIN signal, is the output of the previous high-end undervoltage protection circuit and the RS trigger, and VOUT is the final output signal HO of the chip circuit. Since the current flowing through the first switch tube P0, the second switch tube P1 of the first signal output circuit 100 and the first switch tube N0, the second switch tube N1 of the second signal output circuit 200 is very large, if the high and low ends of P0, P1 and N0, N1 in the driving signal output circuit are turned on at the same time, it will cause the dynamic switch power consumption of the driving chip to be too large, and even damage the chip. Therefore, it is necessary to set a dead time between the signals driving P0, P1 and N0, N1. The dead time here is adjusted by the T_DEAD unit, which is generally around tens of nanoseconds and is realized by using the RC delay unit. A short delay time can be set by the RC delay unit, and the delay time is the dead time. The setting of the dead time can effectively prevent P0, P1 and N0, N1 from being turned on at the same time, thereby solving the problem that the dynamic switch power consumption of the driving chip is too large due to simultaneous conduction, and even damages the chip.

[0071] In an example, the T_DEAD unit may be provided in the first signal input circuit 111 of the first signal output circuit 100 , or may also be provided in the second signal input circuit 211 of the second signal output circuit 200 .

[0072] In some embodiments, the signal input circuit 111 , 211 may further include at least two inverters INV connected in series, for example, three inverters INV connected in series, to filter and shape the VIN signal.

[0073] In some embodiments, the switch module includes 112, 212: at least two switch tubes connected in parallel, wherein the at least two switch tubes connected in parallel include a first switch tube and a second switch tube, and the control end of the first switch tube is connected to the signal input circuit, and is configured to be turned on or off based on at least the drive signal output by the signal input circuit 111, 211. By setting at least two switch tubes connected in parallel, the gate drive current can be adjusted by controlling the number of switch tubes turned on, thereby achieving adjustable gate current. Figure 2 As shown, the first switch tube and the second switch tube of the first switch module 112 may be PMOS or other suitable types of switch tubes. The first switch tube and the second switch tube of the second switch module 212 may be NMOS or other suitable types of switch tubes.

[0074] In some embodiments, the switch circuit further includes a gate transmission gate TG, which is connected to the control end of the second switch tube and is configured to: turn on the second switch tube when it is gated, and turn off the second switch tube when it is not gated. By setting the gate transmission gate TG, the on and off control of the second switch tube can be achieved, so that the branch where the second switch tube is located can be selectively applied to the gate drive, which is more flexible.

[0075] Optionally, the transmission gate TG may be a controllable switch circuit, which may be composed of two complementary transistors in parallel, such as a PMOS and an NMOS in parallel, and the on and off of the two transistors may be controlled by a control signal to achieve signal transmission or blocking.

[0076] In some embodiments, the switch circuit further includes a switch trim pad connected to a gate transmission gate TG, and is configured as follows: by making the switch trim pad suspended, the gate transmission gate TG is not gated, and by connecting the switch trim pad to a floating ground through a lead, the gate transmission gate TG is gated. It is worth mentioning that in this article, the pad being suspended also means that the pad does not use a lead (also referred to as a bonding wire in this article) to connect to other devices or power supplies.

[0077] Those skilled in the art can understand that a pad is a group of metal pins on a chip that can be used to connect other electronic components or printed circuit boards. In this embodiment, a switch adjustment pad and a subsequent resistance adjustment pad are provided on the gate driver chip, which are used to connect to a floating ground through a lead, and serve as an internal element that triggers the gate transmission gate TG to be selected, without adding a new transmission terminal to achieve the transmission of an external signal. In this way, the pads on the circuit can be used to achieve the combination selection of the gate current IO+ and the gate current IO-, making the gate current adjustment method simpler and more efficient.

[0078] In one example, the switch module also includes: a switch signal generating circuit, which is arranged between a floating power supply and a floating ground, and the switch signal generating circuit is also connected to a switch adjustment pad, and the output end of the switch signal generating circuit is connected to a selection transmission gate TG, and is configured to: output a control signal to control whether the selection transmission gate TG is selected or not, wherein, when the switch adjustment pad is suspended, the switch signal generating circuit outputs a switch signal of a high-level signal, so that the selection transmission gate TG is not selected; when the switch adjustment pad is connected to the floating ground through a lead, the switch signal generating circuit outputs a switch signal of a low-level signal, so that the selection transmission gate TG is selected.

[0079] The switch signal generating circuit can generate a control signal adapted to the current requirement of the target power switch tube, which is conducive to realizing the combined selection of the gate current IO+ and the gate current IO-, making the gate current adjustment method simpler and more efficient.

[0080] The switch signal generating circuit can be implemented as any suitable circuit, for example Figure 3 The switch signal generating circuit shown may include a pull-up resistor R10, a pull-down resistor R8, a current limiting resistor R9 and a filter circuit, wherein the first end of the pull-up resistor R10 is connected to a floating power supply VB; the first end of the pull-down resistor R8 is connected to a switch adjustment pad T7, and the second end of the pull-down resistor R8 is connected to the pull-up resistor R10; the first end of the current limiting resistor R9 is connected to the second end of the pull-up resistor R10; the input end of the filter circuit is connected to the second end of the current limiting resistor R9, and the output end of the filter circuit outputs a first switch signal T7-IN to drive the selection transmission gate TG in the first signal output circuit 100 to be selected or not selected (that is, not selected). Figure 4 As shown, the structure of the switch signal generating circuit and Figure 3 The structure of the second switching signal T6_IN is basically the same as that of the first switching signal T6_IN, which is used to output the second switching signal T6_IN to drive the gate transmission gate TG in the second signal output circuit 200 to be gated or not gated (that is, not gated). The pull-up resistor, the pull-down resistor, and the current limiting resistor can play the role of current limiting and voltage division to ensure stable operation of the circuit.

[0081] The filter circuit may include a Schmitt trigger SMIT or other suitable devices. The Schmitt trigger SMIT may be composed of multiple electronic components, including but not limited to CMOS inverters, resistors, diodes, and transistors. For example, two CMOS inverters may be connected in series, and the voltage at the output end may be fed back to the input end through a voltage divider resistor, thereby forming a circuit with Schmitt trigger characteristics. Specifically, the present application does not limit the structure of the Schmitt trigger.

[0082] The Schmitt trigger SMIT has two different threshold voltage levels. When the input signal exceeds the rising threshold, the output changes from low level to high level; when the input signal is lower than the falling threshold, the output changes from high level to low level. This dual threshold structure makes the Schmitt trigger more sensitive to changes in the input signal, and can resist noise interference to a certain extent, playing a role in filtering out noise in the signal.

[0083] In some embodiments, Figure 3 As shown, the switch signal generating circuit also includes: an electrostatic discharge (ESD) protection circuit, which is arranged between a floating power supply and a floating ground, wherein the ESD protection circuit includes a first protection switch tube P2 and a second protection switch tube N2, wherein the gate and source of the first protection switch tube P2 are connected to the floating power supply; the gate and source of the second protection switch tube N2 are connected to the floating ground, and the drain of the second protection switch tube N2 is connected to the drain of the first protection switch tube P2. Similarly, Figure 4As shown, the switch signal generating circuit of the second signal output circuit 200 has Figure 3 The switch signal generating circuit in the ESD protection circuit has basically the same structure. The ESD protection circuit includes a third protection switch tube P3 and a fourth protection switch tube N3. The gate and source of the third protection switch tube P3 are connected to the floating power supply VB; the gate and source of the fourth protection switch tube N3 are connected to the floating ground Vs, and the drain of the fourth protection switch tube N3 is connected to the drain of the third protection switch tube P3.

[0084] Optionally, in addition to the above structure, the ESD protection circuit may also be composed of other suitable circuit structures, for example, it may be implemented by an ESD protection diode, etc.

[0085] The ESD protection circuit can prevent static electricity (caused by the lead contacting the pad) from affecting the inside of the circuit, thereby protecting the circuit.

[0086] Optionally, the first protection switch tube P2 and the third protection switch tube P3 may be PMOS tubes, and the fourth protection switch tube N3 and the second protection switch tube N2 may be NMOS tubes.

[0087] In some embodiments, Figure 1 and Figure 2 As shown, the first signal output circuit 100 and the second signal output circuit 200 may also each include at least two resistors connected in series, connected between the switch circuit and the signal output port (ie, corresponding to Vout), for example Figure 1 As shown, the first signal output circuit 100 includes resistors 121, 122 and 123, and the second signal output circuit 200 includes resistors 221, 222 and 223. Optionally, the number of resistors included in the first signal output circuit 100 and the second signal output circuit 200 is the same or different, wherein each resistor in at least two resistors connected in series may have the same resistance value, or may also be a proportional resistor, which may be reasonably selected according to actual needs and is not specifically limited here. The resistors connected in series may be used as the root resistors for adjusting the gate-on resistor Rgon and the gate-off resistor Rgoff, and their resistance values ​​may be determined according to the adjustment gear and the adjustment step value. The total resistance value of the resistors between the switch circuit and the signal output port of the first signal output circuit 100 is also the resistance value of the gate-on resistor Rgon, and the total resistance value of the resistors between the switch circuit and the signal output port of the second signal output circuit 200 is also the resistance value of the gate-off resistor Rgoff.

[0088] In some embodiments, the first signal output circuit 100 and the second signal output circuit 200 may also each include at least one resistance trimming pad, connected to a node between two series-connected resistors, for example, disposed between two series-connected and adjacent resistors, and connected to both resistors. Specifically, the number of resistance trimming pads may be reasonably set according to actual needs. For example, Figure 1 As shown, the first signal output circuit 100 includes resistance trimming pads 131 and 132, and the second signal output circuit 200 includes resistance trimming pads 231 and 232. Figure 2 As shown, the first signal output circuit 100 and the second signal output circuit 200 each include 4 resistors connected in series and 3 resistor trimming pads, and a node between any two adjacent and connected resistors is connected to a resistor trimming pad. The number of resistors and pads is only an example, and it can be less or more, which is not specifically limited here.

[0089] The electrical connection mode between the resistor trimming pads is changed by adjusting the leads, and the total resistance value of the resistor between the switch circuit and the signal output port is adjusted to adjust the gate current. For example, two pads are connected by leads, and other pads are left floating, or both pairs of pads are connected by leads, and other pads are left floating; or, the leads are adjusted to connect two other pads, etc., to adjust the total resistance value of the resistor between the switch circuit and the signal output port and thus adjust the gate current.

[0090] Optionally, the electrical connection mode between the resistance trimming pads is changed by adjusting the lead wire, including: connecting the resistance trimming pad of the first signal output circuit 100 and the resistance trimming pad of the second signal output circuit 200 through the lead wire; and / or when the first signal output circuit 100 includes at least two resistance trimming pads, electrically connecting the two resistance trimming pads of the first signal output circuit 100 through the lead wire; and / or when the second signal output circuit 200 includes at least two resistance trimming pads, electrically connecting the two resistance trimming pads of the second signal output circuit 200 through the lead wire. By such a setting mode, the flexibility of the connection mode is increased, so that the space range of resistance trimming is larger.

[0091] It is worth mentioning that in the present application, the so-called "state in which component A is connected to component B" includes, in addition to the case in which component A and component B are physically directly connected, the case in which component A and component B are indirectly connected via other components that do not substantially affect their electrical connection state or do not damage the function or effect achieved by their coupling, such as indirect connection via a resistor or a diode.

[0092] Below, we will use Figure 2 Taking the gate driving circuit with 8 trimming bits as an example, the trimming methods in some embodiments of the present application are explained.

[0093] Among them, the switch adjustment pads T7 and T6 are used to adjust the driving MOS tube, so that the MOS tubes IOmos+ and IOmos- in the switch module have 4 combinations, and the resistance adjustment pads T5, T4, T3, T2, T1, and T0 are used to adjust the Rg resistance (that is, the resistance Rgon between the switch circuit and the signal output port of the first signal output circuit 100 and the resistance Rgoff between the switch circuit and the signal output port of the second signal output circuit 200), so that the Rg resistance Rgon and the resistance Rgoff can have 60 combinations, minus the situation of wire bonding crossing, thereby solving the problem of unadjustable driving current. By combining MOS tube adjustment and resistance adjustment, 240 IO+ and IO- driving current values ​​can be obtained to meet the driving current requirements of different power tubes.

[0094] like Figure 3 and Figure 4As shown, in order to illustrate the working state of the circuit, "0" represents a low level, and a bonding line is used to connect to the floating ground VS, and "1" represents a high level, and pull-up resistors R10 and R13 are used to connect to the floating power supply VB. In order to save bonding lines, when the switch trimming pads T7 and T6 are suspended, it means that the bonding line is not used, and the switch trimming pads T7 and T6 are respectively connected to the pull-up resistors R10 and R13 to the floating power supply VB. The first switch signal T7-IN and the second switch signal T6_IN are both high levels, that is, T7T6=11, so that the first signal output circuit 100 and the second signal output circuit 100 are connected. The gate transmission gate TG in the circuit 200 is not gated by default, the gate current IO+ is provided by the driving switch tube P0, and the gate current IO- is provided by the driving switch tube N0; when the switch trimming pads T7 and T6 are connected to the floating ground Vs through the binding wires, the pull-up resistors R10 and R13 and the pull-down resistors R8 and R11 form a loop, which pulls down the output voltage of the current limiting resistor, so that the first switch signal T7-IN and the second switch signal T6_IN are both low level, that is, when T7T6=00, the gate transmission gate TG in the first signal output circuit 100 and the second signal output circuit 200 is gated, and the current The current IO+ is provided by the driving switch tubes P0 and P1, and the current IO- is provided by the driving switch tubes N0 and N1; when the switch trimming pad T7 is connected to the floating ground Vs through the binding wire, and the switch trimming pad T6 is suspended, the first switch signal T7-IN is at a low level and the second switch signal T6_IN is at a high level, that is, when T7T6=01, the selection transmission gate TG of the first signal output circuit 100 is selected, and the selection transmission gate TG of the second signal output circuit 200 is not selected, the current IO+ is provided by the driving switch tubes P0 and P1, and the current IO- is provided by the switch tube N0 ... When the pad T7 is suspended and the switch adjustment pad T6 is connected to the floating ground Vs through a binding line, the first switch signal T7-IN is at a high level and the second switch signal T6_IN is at a low level, that is, when T7T6=10, the selection transmission gate TG of the first signal output circuit 100 is not selected, and the selection transmission gate TG of the second signal output circuit 200 is selected, the current IO+ is provided by the driving switch tube P0, and the current IO- is provided by the driving switch tubes N0 and N1; so that only the MOS tubes IOmos+ and IOmos- have 4 combinations to meet the upper and lower limit current requirements of the driving current of different power tubes.

[0095] The resistors R0-R7 in the circuit are used to adjust the root resistance of the gate-on resistance Rgon and the gate-off resistance Rgoff. Their values ​​can be determined according to the adjustment gear and adjustment step value. You can use resistors of the same resistance value or proportional resistors, depending on the specific situation. When the resistor adjustment pads T5-T0 are left floating, that is, no bonding wire is used, the gate-on resistance Rgon = R0 + R1 + R2 + R3, the gate-off resistance Rgoff = R4 + R5 + R6 + R7, and the chip layout TOP VIEW is as follows Figure 5 As shown, this is the default situation without adjustment. Since there are 60 combinations of changing the gate-on resistance Rgon and the gate-off resistance Rgoff through the leads, they are not listed here one by one.

[0096] In one embodiment, Figure 6 As shown, the resistor trimming pad T0 and the resistor trimming pad T3, the resistor trimming pad T1 and the resistor trimming pad T4, the resistor trimming pad T2 and the resistor trimming pad T5 are connected by bonding wires, and the switch trimming pad T7 and the switch trimming pad T6 are connected to the floating ground VS by bonding wires as an example. The chip layout, the package substrate and the bonding wires are shown in FIG. Figure 6 As shown. At this time, the current IO+ is provided by the driving switch tubes P0 and P1, and the current IO- is provided by the driving switch tubes N0 and N1; the gate-on resistance Rgon=R0+R1 / / R5+R2 / / R6+R3 / / R7, and the gate-off resistance Rgoff=R4+R1 / / R5+R2 / / R6+R3 / / R7. The symbol " / / " represents parallel connection. That is, by adjusting the connection mode of the binding wires, the series-parallel connection mode between the resistors can be changed, thereby playing the role of adjusting the resistors.

[0097] In summary, the gate drive circuit (DRIVER) in some embodiments of the present application includes at least two resistors connected in series between the switch circuit and the signal output port, and at least one resistor trimming pad connected to the node between the two resistors in series. The electrical connection between the resistor trimming pads can be changed by adjusting the leads, and the total resistance of the resistors between the switch circuit and the signal output port can be adjusted to adjust the gate current. The gate current can be adjusted by such a trimming method, and since the method of the present application utilizes the circuit under the pad in the bipolar-complementary metal oxide semiconductor-double diffused metal oxide semiconductor (Bipolar-CMOS-DMOS, referred to as BCD) process, The invention discloses a gate driver circuit of the present invention, which has the characteristics of a power supply unit (PSU), and a power supply unit (PSU) of the present invention. The gate driver circuit of the present invention has the characteristics of a power supply unit (PSU), and a power supply unit (PSU) of the present invention is programmable by means of a bonding wire (WireBonding) connection without sacrificing the chip area, so as to adjust the gate turn-on resistance and the gate turn-off resistance, and then adjust the gate current, so as to achieve the optimal drive of various types of power components by using one gate driver chip. Therefore, the gate driver circuit adjustment method of the present invention does not occupy a large chip area additionally, and compared with the traditional fuse adjustment method, the resistance adjustment method of the present invention is simpler, easier to operate and has a high success rate, which can greatly shorten the development cycle of the gate driver chip, reduce the development cost, and reduce the risk of affecting the chip delivery node.

[0098] Further, if Figure 7 As shown, the present application also provides a gate drive chip, which includes a high-side gate drive chip HVIC. The gate drive chip can be a PWM drive chip or an ordinary drive chip, wherein the PWM drive chip is a drive chip that can transmit three-phase pulse signals of U phase, V phase and W phase, and the ordinary drive chip usually only transmits one pulse signal. Compared with the ordinary drive chip, the number of signal input ports of the PWM drive chip itself (hereinafter referred to as IO port) is two more than the signal input ports of the ordinary chip.

[0099] The gate drive chip includes a pulse generating circuit 710, which is used to encode the rising edge and falling edge of the received PWM pulse width modulation signal into a first pulse signal SET and a second pulse signal RESET respectively. The pulse generating circuit 710 may include a filtering and shaping circuit, a low-voltage level shifting circuit and a narrow pulse generating circuit. The filtering and shaping circuit receives the PWM pulse width modulation signal and filters and shapes it; the low-voltage level shifting circuit is used to process the PWM pulse width modulation signal to obtain a level shifting signal; the narrow pulse generating circuit is used to encode the rising edge and falling edge of the level shifting signal into a first pulse signal and a second pulse signal respectively. The narrow pulse generating circuit can accurately control the triggering time of the signal and realize high-precision timing control.

[0100] Optionally, the filtering and shaping circuit may include a Schmitt trigger SMIT and an input signal filter INPUTFILTER.

[0101] Specifically, Figure 7 The circuit structure of the high-voltage gate driver chip shown in the figure has three voltage domains, which are divided into a low-voltage area, an operating voltage area, and a high-voltage area. The power supply VDD in the low-voltage area is provided by the operating voltage VCC through the linear load regulator REG, mainly for compatibility with the upper-level driving capability. The power supply in the high-voltage area is provided by the operating voltage VCC through a bootstrap boost circuit, mainly for compatibility with driving the lower-level load. The output control signal directly drives the gate of the power tube. In order to ensure the normal operation of the circuit function, both the high-voltage area and the operating voltage area require undervoltage protection circuits, which are HSUVLO and LSUVLO respectively. Except for the device type, the circuit structure and parameters of the two circuits are the same. The devices in the high-voltage area must be replaced with isolation devices because they are integrated in the high-voltage isolation island.

[0102] HIN receives a PWM pulse width modulation signal from a controller such as an MCU. The input signal is a 3.3V CMOS level or a 5V TTL level. After the signal is filtered and shaped by a Schmitt trigger SMIT and an input signal filter INPUT FILTER, a clean signal HIN_PWM is obtained. After the signal passes through a level shift circuit (LS_L2H), it is transferred from a low voltage area to a working voltage area, and an LS_PWM signal (also known as a level shift signal) is output. The narrow pulse generating circuit (PULSE GEN) encodes the rising edge and falling edge of the high side signal of the LS_PWM signal into two narrow pulse signals, namely, a first pulse signal PWM1 and a second pulse signal PWM2.

[0103] Further, if Figure 7 As shown, the high-voltage gate driver chip of the present application also includes a high-voltage level shift circuit 720, which can be implemented as the high-voltage level shift circuit in the aforementioned embodiment, thereby having the function of the aforementioned high-voltage level shift circuit to resist noise signal interference.

[0104] The narrow pulse signal is used as the gate input of two high-voltage LDMOS (such as the first input switch tube and the second input switch tube) of the high-voltage level shift circuit (LEVEL_SHIFTER), and two inverse phase narrow pulse signals are generated at the drain end of the high-voltage LDMOS, and then after passing through the common mode noise filtering circuit, a reset signal RD and a set signal SD are generated. The signal is shifted from the working voltage area to the high voltage area through the high-voltage level shift circuit 720.

[0105] In one example, a noise cancelling circuit 730 is further included, one end of which is connected to the high-voltage level shifting circuit 720 and the other end is connected to the trigger circuit, and is used to filter the noise of the reset signal RD and the set signal SD and then output them to the trigger circuit 740. After the reset signal RD and the set signal SD pass through the noise cancelling circuit (NOISE CANCELLER), the differential mode noise in the signal is filtered out to obtain RD' and SD' signals.

[0106] In one example, a trigger circuit (EDGE TRIGGER) is further included, and the RD' and SD' signals pass through the trigger circuit (EDGE TRIGGER) to prevent false triggering caused by the negative voltage of VS and the narrow pulse width of HIN, thereby obtaining a clean signal.

[0107] In one example, a latch 750 and a gate drive circuit 760 are also included. The latch 750 is electrically connected to the trigger circuit 740, and is used to process the signal output by the trigger circuit 740 to obtain a switch signal to drive the device to be driven to turn on or off. The gate drive circuit 760 is connected to the gate of the target switch tube (for example, the high-side power tube IGBT1), and is used to drive the target power switch tube to turn on or off. The gate drive circuit (DRIVER) 760 includes the device to be driven, and the output end of the latch 750 is connected to the gate of the device to be driven. The device to be driven is a switch tube. The switch tube is turned on or off by the signal output by the latch 750, thereby controlling the gate drive circuit 760 to turn on or off. In a specific example, the latch 750 restores the signal output by the trigger circuit 740 to a normal floating voltage switch signal and outputs it to the drive circuit to control the drive circuit to turn on or off, and obtain the HO signal. The HO signal is output to the high-side power tube IGBT1 through the gate driving circuit 760 to realize the on / off of the high-side power tube IGBT1.

[0108] Optionally, the latch 750 may be an RS latch, which may be a low-level effective trigger, which may include a first trigger terminal S, a second trigger terminal R, and a trigger output terminal Q. Optionally, the first trigger terminal S receives the above-mentioned SD' signal and changes its level state. The second trigger terminal R receives the above-mentioned RD' signal and changes its level state. The trigger output terminal Q outputs a control signal (i.e., a switch signal) of the driving circuit according to the level state of the first trigger terminal S and the level state of the second trigger terminal R.

[0109] Specifically, the structure of the gate driving circuit 760 can adopt any suitable circuit, which is not specifically limited here.

[0110] Since the gate driving chip of the present application has the aforementioned gate driving circuit, it has the same advantages as the aforementioned gate driving circuit.

[0111] The present application also provides an intelligent power module, comprising the aforementioned gate drive chip.

[0112] The gate driver chip of the present application is a high-voltage gate driver chip, which belongs to a high-side gate driver chip and is used in an intelligent power module (IPM). Optionally, three single-channel high-side gate driver chips, one three-channel low-side gate driver chip and six power tubes can be sealed together in the IPM for driving a three-phase motor. The intelligent power module has a target power switch tube, such as a high-side power tube IGBT1, and the signal output port of the gate driver chip is connected to the gate of the target power switch tube, and is configured to: control the conduction or shutdown of the target power switch tube.

[0113] IPM is an advanced power switching device commonly used in three-phase inverter circuits of household appliances (such as variable frequency air conditioners), industrial machines and automotive products. IPM is usually composed of high-speed and low-power power components - Insulated Gate Bipolar Transistor (IGBT) and gate drive IC and other circuits.

[0114] by Figure 8 Take the intelligent power module with a half-bridge circuit structure as an example, which includes a high-side gate driver chip HVIC and a low-side gate driver chip LVIC. Figure 5 As shown, the intelligent power module includes a high-side gate driver chip HVIC and a low-side gate driver chip LVIC. They receive control signals from a microcontroller (MCU) or other control unit, amplify the signal and perform logic processing through internal circuits, and finally output sufficient voltage and current to drive the gate of the power switching device to turn it on and off. Among them, the high-side gate driver chip HVIC outputs a high-voltage drive output HO to control the high-side power tube IGBT1. The low-side gate driver chip LVIC outputs a low-voltage drive output LO to control the low-side power tube IGBT2.

[0115] Optionally, the high-side power tube IGBT1 and the low-side power tube IGBT2 are connected in series between the DC voltage VH and the ground voltage. The voltage at the connection point between the high-side power tube IGBT1 and the low-side power tube IGBT2 is the high-side floating ground VS terminal Vs. Optionally, the high-side power tube IGBT1 and the low-side power tube IGBT2 are turned on alternately.

[0116] Optionally, the high-side power tube IGBT1 and the low-side power tube IGBT2 are connected in series between the DC voltage VH and the ground voltage. The voltage at the connection point between the high-side power tube IGBT1 and the low-side power tube IGBT2 is the high-side floating ground VS terminal Vs. Optionally, the high-side power tube IGBT1 and the low-side power tube IGBT2 are alternately turned on. When the high-side power tube IGBT1 is turned on and the low-side power tube IGBT2 is turned off, the high-side floating ground VS terminal Vs is approximately equal to the bus voltage VH, that is, Vs is at a high potential. When the high-side power tube IGBT1 is turned off and the low-side power tube IGBT2 is turned on, the high-side floating ground VS terminal Vs is approximately equal to the ground voltage GND. Optionally, a load (not shown in the accompanying drawings) is connected between the voltage Vs of the high-side floating ground VS terminal and the ground voltage. Optionally, the high-side floating power supply voltage VB (also called the operating voltage VB) is bootstrapped and connected to the power supply voltage VCC through a bootstrap diode D1". Optionally, the high-side floating power supply voltage VB is bootstrapped and connected to the high-side floating ground Vs terminal through a bootstrap capacitor C1.

[0117] Since the IPM of the present application has the aforementioned gate driving chip, it also has the advantages of the aforementioned gate driving chip.

[0118] Furthermore, the present application also provides a device, which may include the aforementioned gate drive circuit, or, include the aforementioned gate drive chip, or, include the aforementioned intelligent power module.

[0119] The device can be any electronic product or device such as household appliances (such as variable frequency air conditioners, washing machines, etc.), televisions, mobile phones, tablet computers, laptops, netbooks, game consoles, televisions, VCDs, DVDs, navigators, cameras, camcorders, voice recorders, MP3s, MP4s, PSPs, etc., or the device can also be transportation equipment such as vehicles.

[0120] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and that those skilled in the art may design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of multiple such elements. The present application may be implemented with the aid of hardware including several different elements and with the aid of appropriately programmed computers. In a unit claim listing several on-board systems, several of these on-board systems may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

[0121] The above is only a specific implementation method or description of a specific implementation method of the present application, and the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A gate drive circuit, characterized in that: include: A first signal output circuit and a second signal output circuit connected to the signal output port of the gate drive circuit, wherein each of the first signal output circuit and the second signal output circuit comprises: A switch circuit, the switch circuit is connected to the signal input port of the gate drive circuit and is configured to be turned on or off based on a control signal input from the signal input port; at least two resistors connected in series, connected between the switch circuit and the signal output port; at least one resistance trimming pad connected to a node between two resistors connected in series; The electrical connection mode between the resistance trimming pads is changed by adjusting the leads, and the total resistance value of the resistor between the switch circuit and the signal output port is adjusted to adjust the gate current.

2. The gate driving circuit according to claim 1, characterized in that: Changing the electrical connection between the resistance trimming pads by adjusting the leads includes: connecting the resistance trimming pad of the first signal output circuit and the resistance trimming pad of the second signal output circuit via a lead; and / or When the first signal output circuit includes at least two resistance trimming pads, the two resistance trimming pads of the first signal output circuit are electrically connected via leads; and / or When the second signal output circuit includes at least two resistance trimming pads, the two resistance trimming pads of the second signal output circuit are electrically connected through a wire.

3. The gate driving circuit according to claim 1, wherein: The switch circuit comprises: A signal input circuit, used for receiving a control signal and processing the control signal to obtain a drive signal; A switch module, which is also connected to the signal input circuit, is configured to: be turned on or off at least based on the drive signal output by the signal input circuit, the switch module of the first signal output circuit is connected to a floating power supply, and the switch module of the second signal output circuit is connected to a floating ground.

4. The gate driving circuit according to claim 3, characterized in that: The switch module comprises: At least two switch tubes connected in parallel, wherein the at least two switch tubes connected in parallel include a first switch tube and a second switch tube, a control end of the first switch tube is connected to the signal input circuit, and is configured to be turned on or off based on at least the drive signal output by the signal input circuit; A gate transmission gate, the gate transmission gate is connected to the control end of the second switch tube, and is configured to: turn on the second switch tube when it is gated, and turn off the second switch tube when it is not gated; The switch trim pad is connected to the enable transmission gate and is configured as follows: by making the switch trim pad suspended, the enable transmission gate is not enabled; and by connecting the switch trim pad to a floating ground through a lead, the enable transmission gate is enabled.

5. The gate driving circuit according to claim 4, characterized in that: The switch module also includes: A switch signal generating circuit is arranged between a floating power supply and a floating ground, and the switch signal generating circuit is also connected to the switch trimming pad, and an output end of the switch signal generating circuit is connected to the gate transmission gate, and is configured to: output a control signal to control the gate transmission gate to be gated or not gated, wherein, When the switch trimming pad is suspended, the switch signal generating circuit outputs a switch signal of a high level signal, so that the gate transmission gate is not gated; When the switch trimming pad is connected to the floating ground through a lead, the switch signal generating circuit outputs a switch signal of a low level signal, so that the enable transmission gate is enabled.

6. The gate driving circuit according to claim 5, characterized in that: The switch signal generating circuit comprises: A pull-up resistor, a first end of which is connected to the floating power supply; A pull-down resistor, wherein a first end of the pull-down resistor is connected to the switch trimming pad, and a second end of the pull-down resistor is connected to the pull-up resistor; a current limiting resistor, wherein a first end of the current limiting resistor is connected to a second end of the pull-up resistor; A filter circuit, wherein the input end of the filter circuit is connected to the second end of the current limiting resistor, and the output end of the filter circuit outputs the switching signal.

7. The gate driving circuit according to claim 6, characterized in that: The switch signal generating circuit further includes: An ESD protection circuit is arranged between the floating power supply and the floating ground, wherein the ESD protection circuit comprises: A first protection switch tube, wherein the gate and the source of the first protection switch tube are connected to the floating power supply; A second protection switch tube, wherein the gate and source of the second protection switch tube are connected to the floating ground, and the drain of the second protection switch tube is connected to the drain of the first protection switch tube.

8. The gate driving circuit according to claim 3, characterized in that: The switch tube included in the switch module of the first signal output circuit is a PMOS, and the switch tube included in the switch module of the second signal output circuit is an NMOS.

9. A gate driver chip, characterized in that: include: The gate drive circuit according to any one of claims 1 to 8.

10. An intelligent power module, characterized in that: include: Target power switch tube; The gate driver chip according to claim 9, wherein the signal output port of the gate driver chip is connected to the gate of the target power switch tube and is configured to control the on or off of the target power switch tube.

11. A device, characterized in that: It comprises the gate drive circuit as claimed in any one of claims 1 to 8, or comprises the gate drive chip as claimed in claim 9, or comprises the intelligent power module as claimed in claim 10.

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