Gate drive circuit, gate drive chip, smart power module and device

Abstract

This application provides a gate driving circuit, a gate driving chip, a smart power module, and a device. The gate driving circuit includes: a first signal output circuit and a second signal output circuit connected to a signal output port of the gate driving circuit. Each of the first and second signal output circuits includes: a switching circuit connected to a signal input port of the gate driving circuit, configured to turn on or off based on a control signal input to the signal input port; at least two resistors connected in series between the switching circuit and the signal output port; and at least one resistor adjustment pad connecting the node between the two series resistors. By adjusting the leads to change the electrical connection between the resistor adjustment pads, the total resistance between the switching circuit and the signal output port is adjusted, thereby adjusting the gate current. This allows for optimal driving of various types of power components using a single gate driving chip.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and more specifically to a gate drive circuit, a gate drive chip, a smart power module, and a device. Background Technology

[0002] Traditional high-side gate driver chips are mainly composed of high-voltage dual-pulse triggered level shifter circuits (LEVEL_SHIFTER), pulse filters (NOISE CANCELLER), RS latches (RS LATCH), and gate driver circuits (DRIVER). When integrated into intelligent power modules (IPMs), they are used in high-voltage and high-speed environments.

[0003] The gate drive circuit needs to select a suitable drive current based on the characteristics of the power transistor. Currently, the fine-tuning of the drive current IO+ and IO- is mainly done by adjusting the fuse to select the channel and modifying the metal layer mask. These methods often sacrifice a large chip area to meet the current density requirements of the drive transistor. In addition, the adjustment circuit module also occupies a large chip area and has the risk of unsuccessful fuse burning. Modifying the chip metal layer mask has the risk of long lead time and affecting chip delivery nodes. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] This application provides a gate driving circuit, including: a first signal output circuit and a second signal output circuit connected to a signal output port of the gate driving circuit, wherein each of the first signal output circuit and the second signal output circuit includes:

[0006] A switching circuit, which is connected to the signal input port of the gate drive circuit, is configured to turn on or off based on the control signal input to the signal input port.

[0007] At least two resistors connected in series are connected between the switching circuit and the signal output port;

[0008] At least one resistor adjustment pad connects the node between two resistors connected in series;

[0009] Specifically, by adjusting the leads to change the electrical connection between the resistance adjustment pads, the total resistance between the switching circuit and the signal output port is adjusted, thereby adjusting the gate current.

[0010] The above technical solution has the following advantages or beneficial effects: By adjusting the leads to change the electrical connection between the resistance adjustment pads, the total resistance between the switching circuit and the signal output port is adjusted, thereby adjusting the gate current. This adjustment method can achieve adjustable gate current. Without sacrificing chip area, programmable wiring is used to adjust the gate turn-on resistance and gate turn-off resistance, thereby adjusting the gate current. This allows for optimal driving of multiple types of power devices using a single gate driver chip. Therefore, the gate driver circuit adjustment method of this application does not occupy a large additional chip area. Furthermore, compared with the traditional fuse adjustment method, the resistance adjustment method of this application is simpler, easier to operate, and has a higher success rate. It can significantly shorten the development cycle of the gate driver chip, reduce development costs, and reduce risks such as affecting chip delivery nodes.

[0011] In some embodiments of this application, the electrical connection between resistance adjustment pads is changed by adjusting the leads, including:

[0012] Connect the resistance adjustment pads of the first signal output circuit and the second signal output circuit via leads; and / or

[0013] When the first signal output circuit includes at least two resistor adjustment pads, the two resistor adjustment pads of the first signal output circuit are electrically connected by leads; and / or

[0014] When the second signal output circuit includes at least two resistor adjustment pads, the two resistor adjustment pads of the second signal output circuit are electrically connected by leads.

[0015] The above technical solutions have the following advantages or beneficial effects: This adjustment method enables adjustable gate current. Without sacrificing chip area, programmable wiring is used to adjust the gate turn-on resistance and gate turn-off resistance, thereby adjusting the gate current. In some embodiments of this application, the switching circuit includes:

[0016] The signal input circuit is used to receive control signals and process them to obtain drive signals.

[0017] The switching module, which is also connected to the signal input circuit, is configured to turn on or off based at least on the drive signal output by the signal input circuit. The switching module of the first signal output circuit is connected to a floating power supply, and the switching module of the second signal output circuit is connected to a floating ground.

[0018] The above technical solution has the following advantages or beneficial effects: By processing the signal input circuit and the input control signal, signal amplification, phase shifting, and filtering functions can be achieved to improve the driving capability of the switching circuit. The output of the driving signal can be realized by turning the switching circuit on and off, thereby controlling the on and off of the target power device.

[0019] In some embodiments of this application, the switch module includes:

[0020] At least two parallel switching transistors, wherein the at least two parallel switching transistors include a first switching transistor and a second switching transistor, the control terminal of the first switching transistor is connected to a signal input circuit and is configured to: turn on or off based at least on a drive signal output by the signal input circuit;

[0021] The gating transmission gate, which is connected to the control terminal of the second switch, is configured to turn on the second switch when it is gated and turn off the second switch when it is not gated.

[0022] The switch adjustment pad is connected to the gating transmission gate and configured such that: by suspending the switch adjustment pad, the gating transmission gate is not selected; by connecting the switch adjustment pad to the floating ground via a lead wire, the gating transmission gate is selected.

[0023] The above technical solutions have the following advantages or beneficial effects: By setting at least two parallel switching transistors, the gate drive current can be adjusted by controlling the number of conducting switching transistors, thereby achieving adjustable gate current. By setting a gating transmission gate TG, the conduction and turn-off of the second switching transistor can be controlled, allowing the branch containing the second switching transistor to be selectively applied to the gate drive, thus increasing flexibility. By setting a switch adjustment pad on the gate drive chip, which is connected to the floating ground via a lead, it serves as an internal element that triggers the gating transmission gate TG to be selected, without the need to add new transmission terminals to transmit external signals. In this way, the combination selection of gate current IO+ and gate current IO- can be achieved using the pads on the circuit, making the gate current adjustment method simpler and more efficient.

[0024] In some embodiments of this application, the switch module further includes:

[0025] A switch signal generation circuit is positioned between the floating power supply and the floating ground. This circuit is also connected to a switch adjustment pad. The output of the switch signal generation circuit is connected to a gating gate and configured to output a control signal to control whether the gating gate is selected or not.

[0026] When the switch adjustment pad is floating, the switch signal generation circuit outputs a high-level switch signal, which prevents the gating transmission gate from being selected.

[0027] When the switch adjustment pad is connected to the floating ground via a lead wire, the switch signal generation circuit outputs a low-level switch signal, which turns on the gating transmission gate.

[0028] The above technical solution has the following advantages or beneficial effects: the switching signal generation circuit can generate a control signal that is adapted to the current demand of the target power switch, which is conducive to realizing the combined selection of gate current IO+ and gate current IO-, making the gate current adjustment method simpler and more efficient.

[0029] In some embodiments of this application, the switch signal generation circuit includes:

[0030] Pull-up resistor, with its first end connected to a floating power supply;

[0031] The pull-down resistor has its first end connected to the switch adjustment pad and its second end connected to the pull-up resistor.

[0032] The current-limiting resistor is connected at its first end to the second end of the pull-up resistor.

[0033] The filter circuit has its input terminal connected to the second terminal of the current-limiting resistor, and its output terminal outputs a switching signal.

[0034] The above technical solutions have the following advantages or beneficial effects: pull-up resistors, pull-down resistors, and current-limiting resistors can limit current and divide voltage to ensure stable circuit operation, and the filter circuit can filter out noise in the signal.

[0035] In some embodiments of this application, the switch signal generation circuit further includes:

[0036] An ESD protection circuit is installed between the floating power supply and the floating ground. The ESD protection circuit includes:

[0037] The first protective switch transistor has its gate and source connected to a floating power supply.

[0038] The second protection switch has its gate and source connected to a floating ground, and its drain is connected to the drain of the first protection switch.

[0039] The above technical solutions have the following advantages or beneficial effects: ESD protection circuits can prevent static electricity (caused by lead wires contacting pads) from affecting the internal circuit, thereby protecting the circuit.

[0040] In some embodiments of this application, the switching module of the first signal output circuit includes a PMOS transistor, and the switching module of the second signal output circuit includes an NMOS transistor.

[0041] The above technical solutions have the following advantages or beneficial effects: by using different types of MOSFETs, the switching modules of the first signal output circuit and the second signal output circuit can be prevented from being turned on simultaneously, thereby reducing the risk of device damage caused by simultaneous conduction.

[0042] In another aspect, this application provides a gate driver chip, including: the gate driver circuit as described above.

[0043] This application also provides an intelligent power module, comprising:

[0044] Target power switching transistor;

[0045] The aforementioned gate driver chip has its signal output port connected to the gate of the target power switch and is configured to control the turn-on or turn-off of the target power switch.

[0046] In another aspect, this application provides an apparatus that includes the aforementioned gate drive circuit, or the aforementioned gate drive chip, or the aforementioned smart power module.

[0047] Since the aforementioned gate drive chip, smart power module, and device include the aforementioned gate drive circuit, they also have the above-mentioned advantages or beneficial effects. Attached Figure Description

[0048] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0049] Figure 1 A schematic block diagram of a gate drive circuit in one embodiment of this application is shown;

[0050] Figure 2 A schematic diagram of the gate drive circuit in one embodiment of this application is shown;

[0051] Figure 3 This paper shows a schematic diagram of the switching signal generation circuit of the first signal output circuit in one embodiment of the present application;

[0052] Figure 4 This paper shows a schematic diagram of the switching signal generation circuit of the second signal output circuit in one embodiment of the present application;

[0053] Figure 5This is a top view of the gate driver chip layout corresponding to the gate driver circuit when the resistor adjustment pad is floating in one embodiment of this application.

[0054] Figure 6 This is a top view of the gate driver chip layout corresponding to the gate driver circuit when the resistor adjustment pads T0T3, T1T4, and T2T5 are connected by leads in one embodiment of this application.

[0055] Figure 7 A schematic diagram of the circuit structure of a gate driver chip in one embodiment of this application is shown;

[0056] Figure 8 A schematic diagram of the structure of an intelligent power module (IPM) according to one embodiment of this application is shown. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application more apparent, exemplary embodiments according to this application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely a part of the embodiments of this application, and not all of the embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein. Based on the embodiments of this application described herein, all other embodiments obtained by those skilled in the art without inventive effort should fall within the protection scope of this application.

[0058] High-voltage gate driver chips are mainly classified into low-side, high-side, single-channel, dual-channel, isolated, half-bridge, and full-bridge power driver chips. They integrate low-voltage signal transmission logic control circuits for more precise processing of front-end input signals. Simultaneously, to drive high-power downstream devices, they are also equipped with high-voltage output drive circuits. The core function of this circuit product is to convert front-end microprocessor (MCU) signals into switching transistor (i.e., power switch) drive control signals. During normal operation, the high-voltage gate driver chip not only processes input signals to drive the power switch, but also transmits various operating status signals to an external microprocessor (MCU) for monitoring circuit operation. Intelligent power modules (IPMs) integrate high-voltage gate driver chips, over-temperature, over-current, and under-voltage protection circuits, fault handling circuits, and driven power devices. Benefiting from their high switching frequency, low switching losses, and strong noise immunity, they have strong application potential in the current power electronics field and a wide range of application scenarios, especially suitable for variable frequency motors and inverter power supplies.

[0059] Gate drive circuits require the selection of appropriate drive current based on the characteristics of the power transistor. Common tuning techniques include laser tuning, fuse tuning, diode tuning, and memory tuning. These techniques are widely used in high-precision, low-offset, and low-temperature-drift analog integrated circuits, such as operational amplifiers, reference sources, RF circuits, high-performance analog-to-digital / digital-to-analog converters, and complex mixed-signal chips. However, these techniques are not suitable for tuning the drive current of high-voltage gate drive circuits. Firstly, to meet high current density requirements, a larger chip area needs to be sacrificed for the tuning circuit. Secondly, it increases testing costs, requiring the development of CP and FT test programs to meet debugging needs.

[0060] Currently, driver design requires selecting an appropriate drive current based on the characteristics of the power transistors. Too small a current results in insufficient drive capability and increased power device losses, while too large a current may cause turn-on oscillations. Designing the drive current involves selecting the gate resistor value; a larger drive current means reducing the gate resistor Rg. To minimize switching losses, a critical value that prevents circuit oscillation must be found. When the gate driver chip is packaged in an IPM module, the Rg resistor is generally not packaged, occupying limited package substrate area; therefore, the Rg value must be designed into the gate driver chip. Currently, fine-tuning of IO+ and IO- is mainly achieved through fuse tuning to select channels and modifying the metal layer mask. This involves either increasing or decreasing the number of parallel drive MOSFETs or changing the series-parallel connection of resistors to obtain different Rg values. However, this method sacrifices a significant amount of chip area to meet the current density requirements of the drive transistors. Furthermore, the tuning circuit module also occupies a large chip area and carries the risk of unsuccessful fuse programming. Modifying the chip's metal layer mask also carries risks such as long lead times and impacting chip delivery milestones.

[0061] To address the above technical problems, some embodiments of this application provide a gate driving circuit, which will be referred to below. Figures 1 to 6 The structure of the gate drive circuit in the embodiments of this application is described. It is worth mentioning that, without conflict, the technical features of the various embodiments of this application can be combined with each other.

[0062] In some embodiments, such as Figure 1 and Figure 2 As shown, the gate drive circuit includes a first signal output circuit 100 and a second signal output circuit 200 connected to the signal output port VOUT of the gate drive circuit. The first signal output circuit (i.e., the high-side drive signal output circuit) and the second signal output circuit 200 (the low-side drive signal output circuit) have essentially the same circuit structure.

[0063] The signal output port VOUT of the gate drive circuit is connected to the gate of the target power switch to output a drive signal to turn the target power switch on or off. The target power switch (also called a power switch, transistor switch, or power transistor) is a power semiconductor device that can be used to drive load current. For example, an IGBT is turned on or off by activating and deactivating its gate terminal. Applying a positive input voltage signal across the gate and emitter will keep the device in its "on" state, while making the input gate signal zero or slightly negative will cause it to be "off". There are turn-on and turn-off processes for switching the power transistor on and off.

[0064] During the conduction process, the gate drive circuit can be used to provide a gate current (i.e., drive current) to the gate of the power transistor to charge the gate to a sufficient voltage to turn the device on. Specifically, the current Io+ is the gate driver output current used to boost (i.e., charge) the gate of the power transistor during the conduction transient. Therefore, the current Io+ is used to turn on the target power switch.

[0065] During the turn-off process, the gate drive circuit draws gate current (i.e., turn-off current) from the gate of the target power switch to fully discharge the gate voltage and turn off the device. The current Io- is the gate driver output current used to discharge the gate of the target power switch during the turn-off transient. Therefore, Io- is used to turn off the power transistor.

[0066] The target power switch can include an insulated-gate bipolar transistor (IGBT) and a metal-oxide-semiconductor field-effect transistor (MOSFET) (e.g., a silicon MOSFET or a silicon carbide MOSFET). It should be understood that a MOSFET can replace an IGBT, and vice versa. In this case, when a MOSFET is used instead of an IGBT, in any of the examples described herein, the drain of the MOSFET can replace the collector of the IGBT, the source of the MOSFET can replace the emitter of the IGBT, and the drain-source voltage VDS of the MOSFET can replace the collector-emitter voltage VCE of the IGBT. Therefore, any IGBT module can be replaced by a MOSFET module, and vice versa.

[0067] In some embodiments, each of the first signal output circuit 100 and the second signal output circuit 200 includes a switching circuit connected to the signal input port of the gate drive circuit, configured to turn on or off based on a control signal input to the signal input port VIN. For example, as Figure 1 and Figure 2As shown, the first signal output circuit 100 includes a first switching circuit, and the second signal output circuit 200 includes a second switching circuit. Both the first and second switching circuits receive an input control signal, which can be based on a pulse width modulation (PWM) scheme and can use a voltage pulse output from the circuit preceding the gate drive circuit as the control signal. Therefore, during the PWM cycle used to control the switching circuit, the control signal can be switched between the on-state voltage level and the off-state voltage level, thereby turning the switching circuit on and off respectively.

[0068] In some embodiments, switching circuits 110 and 210 include signal input circuits 111 and 211 and switching modules 112 and 212, for receiving control signal VIN and processing the control signal to obtain a drive signal; switching modules 112 and 212 are also connected to their respective corresponding signal input circuits 111 and 211, and are configured to turn on or off based at least on the drive signal output by signal input circuits 111 and 211. The switching module of the first signal output circuit 100 (i.e., the first switching module 112) is connected to the floating power supply VB, and the switching module of the second signal output circuit 200 (i.e., the second switching module 212) is connected to the floating ground Vs. By processing the input control signal through the signal input circuits, signal amplification, phase shifting, and filtering functions can be achieved to improve the driving capability of the switching circuits. By turning the switching circuits on and off, the drive signal can be output, thereby controlling the on and off of the target power device.

[0069] In some embodiments, such as Figure 2 As shown, the first switching circuit 110 includes a first signal input circuit 111 and a first switching module 112. The first signal input circuit 111 is used to receive control signals and process the control signals to obtain a first driving signal. The first switching module 112 is also connected to the first signal input circuit 111 and is configured to turn on or off based on the first driving signal output by the first signal input circuit 111. The second switching circuit includes a second signal input circuit 211 and a first switching module 212. The second signal input circuit 211 is used to receive control signals and process the control signals to obtain a second driving signal. The first switching module 212 is also connected to the second signal input circuit 211 and is configured to turn on or off based on the second driving signal output by the second signal input circuit 211.

[0070] like Figure 2As shown, the control signal, VIN, is the output of the high-side undervoltage protection circuit and the RS flip-flop, while VOUT is the final output signal HO of the chip circuit. Since the current flowing through the first switch P0 and the second switch P1 of the first signal output circuit 100, and the first switch N0 and the second switch N1 of the second signal output circuit 200, is very large, if the high and low sides of P0, P1 and N0, N1 in the drive signal output circuit are simultaneously turned on, it will cause excessive dynamic switching power consumption of the drive chip, and may even damage the chip. Therefore, a dead time needs to be set between the signals driving P0, P1, and N0, N1. This dead time is adjusted by the T_DEAD unit, typically around tens of nanoseconds, and is implemented using an RC delay unit. The RC delay unit allows setting a short delay time, which is the dead time. Setting the dead time effectively prevents P0, P1, and N0, N1 from being turned on simultaneously, thus solving the problem of excessive dynamic switching power consumption of the drive chip caused by simultaneous conduction, which could even damage the chip.

[0071] In one example, the T_DEAD unit can be located in the first signal input circuit 111 of the first signal output circuit 100, or it can be located in the second signal input circuit 211 of the second signal output circuit 200.

[0072] In some embodiments, the signal input circuits 111 and 211 may further include at least two inverters INV connected in series, such as three inverters INV connected in series, to filter and shape the VIN signal.

[0073] In some embodiments, the switching module includes 112 and 212: at least two parallel switching transistors, wherein the at least two parallel switching transistors include a first switching transistor and a second switching transistor. The control terminal of the first switching transistor is connected to a signal input circuit and configured to turn on or off based on a drive signal output by the signal input circuits 111 and 211. By providing at least two parallel switching transistors, the gate drive current can be adjusted by controlling the number of conducting switching transistors, thereby achieving adjustable gate current. For example, Figure 2 As shown, the first and second switching transistors of the first switching module 112 can be PMOS or other suitable types of switching transistors. The first and second switching transistors of the second switching module 212 can be NMOS or other suitable types of switching transistors.

[0074] In some embodiments, the switching circuit further includes a gating transmission gate TG, which is connected to the control terminal of the second switch and configured to turn on the second switch when it is selected and turn off the second switch when it is not selected. By setting the gating transmission gate TG, the turning on and off of the second switch can be controlled, thereby allowing the branch containing the second switch to be selectively applied to the gate drive, thus providing greater flexibility.

[0075] Optionally, the pass gate TG can be a controllable switching circuit, which can be composed of two complementary transistors connected in parallel, such as PMOS and NMOS connected in parallel. The two transistors are turned on and off by a control signal, thereby realizing the transmission or blocking of the signal.

[0076] In some embodiments, the switching circuit further includes a switch adjustment pad connected to a gating transmission gate TG, configured to: deselect the gating transmission gate TG by leaving the switch adjustment pad floating, and select the gating transmission gate TG by connecting the switch adjustment pad to a floating ground via a lead. It is worth noting that, in this document, "floating pad" means that the pad is not connected to other devices or power supplies using leads (also referred to as wire bonding).

[0077] Those skilled in the art will understand that a pad is a set of metal pins on a chip that can be used to connect other electronic components or printed circuit boards. This embodiment provides switch adjustment pads and subsequent resistor adjustment pads on the gate driver chip, which are connected to a floating ground via leads. These serve as internal components that trigger the selection of the transmission gate TG, eliminating the need to add new transmission terminals for external signal transmission. In this way, the combination selection of gate current IO+ and gate current IO- can be achieved using the pads on the circuit, making the gate current adjustment method simpler and more efficient.

[0078] In one example, the switching module further includes a switching signal generation circuit disposed between the floating power supply and the floating ground. The switching signal generation circuit is also connected to a switch adjustment pad. The output of the switching signal generation circuit is connected to a gating transmission gate TG and is configured to output a control signal to control whether the gating transmission gate TG is selected or not. When the switch adjustment pad is floating, the switching signal generation circuit outputs a high-level switching signal to deselect the gating transmission gate TG. When the switch adjustment pad is connected to the floating ground via a lead, the switching signal generation circuit outputs a low-level switching signal to select the gating transmission gate TG.

[0079] This switching signal generation circuit can generate a control signal that adapts to the current requirements of the target power switch, which is beneficial for achieving a combination selection of gate current IO+ and gate current IO-, making the gate current adjustment method simpler and more efficient.

[0080] The switching signal generation circuit can be implemented as any suitable circuit, for example... Figure 3 The switch signal generation circuit shown may include a pull-up resistor R10, a pull-down resistor R8, a current-limiting resistor R9, and a filter circuit. The first terminal of the pull-up resistor R10 is connected to the floating power supply VB; the first terminal of the pull-down resistor R8 is connected to the switch adjustment pad T7, and the second terminal of the pull-down resistor R8 is connected to the pull-up resistor R10; the first terminal of the current-limiting resistor R9 is connected to the second terminal of the pull-up resistor R10; the input terminal of the filter circuit is connected to the second terminal of the current-limiting resistor R9, and the output terminal of the filter circuit outputs a first switch signal T7-IN to drive the gating transmission gate TG in the first signal output circuit 100 to be selected or not selected (i.e., not selected). Figure 4 As shown, the structure of the switch signal generation circuit and Figure 3 The structure is basically the same as that in the previous circuit, which is used to output the second switching signal T6_IN to drive the gating transmission gate TG in the second signal output circuit 200 to be selected or not selected (i.e., not selected). Pull-up resistors, pull-down resistors, and current-limiting resistors can play the roles of current limiting and voltage division to ensure stable circuit operation.

[0081] The filter circuit may include a Schmitt trigger (SMIT) or other suitable devices. A Schmitt trigger (SMIT) can consist of multiple electronic components, including but not limited to CMOS inverters, resistors, diodes, and transistors. For example, two CMOS inverters can be connected in series, and the output voltage can be fed back to the input through a voltage divider resistor, thereby forming a circuit with Schmitt triggering characteristics. Specifically, this application does not limit the structure of the Schmitt trigger.

[0082] The Schmitt trigger (SMIT) has two different threshold voltage levels. When the input signal exceeds the rising threshold, the output changes from low to high; when the input signal falls below the falling threshold, the output changes from high to low. This dual threshold structure makes the Schmitt trigger more sensitive to changes in the input signal and can resist noise interference to a certain extent, thus filtering out noise from the signal.

[0083] In some embodiments, such as Figure 3 As shown, the switching signal generation circuit also includes an electrostatic discharge (ESD) protection circuit, which is located between the floating power supply and the floating ground. The ESD protection circuit includes a first protection switch P2 and a second protection switch N2. The gate and source of the first protection switch P2 are connected to the floating power supply; the gate and source of the second protection switch N2 are connected to the floating ground, and the drain of the second protection switch N2 is connected to the drain of the first protection switch P2. Similarly, as... Figure 4As shown, the switching signal generation circuit of the second signal output circuit 200 has and Figure 3 The switching signal generation circuits in the circuits are basically the same. The ESD protection circuit includes a third protection switch P3 and a fourth protection switch N3. The gate and source of the third protection switch P3 are connected to the floating power supply VB. The gate and source of the fourth protection switch N3 are connected to the floating ground Vs. The drain of the fourth protection switch N3 is connected to the drain of the third protection switch P3.

[0084] Alternatively, in addition to the above-mentioned structure, the ESD protection circuit can also be constructed by other suitable circuit structures, such as by using ESD protection diodes.

[0085] ESD protection circuits can prevent static electricity (caused by leads contacting pads) from affecting the internal circuitry, thus protecting the circuit.

[0086] Optionally, the first protection switch P2 and the third protection switch P3 can be PMOS transistors, and the fourth protection switch N3 and the second protection switch N2 can be NMOS transistors.

[0087] In some embodiments, such as Figure 1 and Figure 2 As shown, both the first signal output circuit 100 and the second signal output circuit 200 may further include at least two resistors connected in series between the switching circuit and the signal output port (i.e., corresponding to Vout), for example... Figure 1 As shown, the first signal output circuit 100 includes resistors 121, 122, and 123, and the second signal output circuit 200 includes resistors 221, 222, and 223. Optionally, the number of resistors in the first signal output circuit 100 and the second signal output circuit 200 may be the same or different. Each resistor in at least two series-connected resistors may have the same resistance value, or they may be proportional resistors. The specific selection can be made according to actual needs and is not specifically limited here. The series-connected resistors can be used as the root resistors for adjusting the gate turn-on resistor Rgon and the gate turn-off resistor Rgoff, and their resistance values ​​can be determined according to the adjustment range and adjustment step value. The total resistance between the switching circuit and the signal output port of the first signal output circuit 100 is also the resistance value of the gate turn-on resistor Rgon, and the total resistance between the switching circuit and the signal output port of the second signal output circuit 200 is also the resistance value of the gate turn-off resistor Rgoff.

[0088] In some embodiments, the first signal output circuit 100 and the second signal output circuit 200 may each include at least one resistor adjustment pad, connecting the node between two series-connected resistors, for example, positioned between two series-connected and adjacent resistors, and connected to both resistors. Specifically, the number of resistor adjustment pads can be reasonably set according to actual needs. For example, such as... Figure 1 As shown, the first signal output circuit 100 includes resistor adjustment pads 131 and 132, and the second signal output circuit 200 includes resistor adjustment pads 231 and 232. For example, as... Figure 2 As shown, both the first signal output circuit 100 and the second signal output circuit 200 include four resistors connected in series and three resistor adjustment pads. A resistor adjustment pad is connected to the node between any two adjacent and connected resistors. The number of resistors and pads is only an example; they can be fewer or more, and no specific limitation is made here.

[0089] The gate current can be adjusted by changing the electrical connection between the pads by adjusting the leads, thereby adjusting the total resistance between the switching circuit and the signal output port. For example, two pads can be connected by leads while the other pads are left floating; or, both pairs of pads can be connected by leads while the other pads are left floating; or, the leads can be adjusted to connect to two other pads.

[0090] Optionally, the electrical connection between the resistance adjustment pads can be changed by adjusting the leads, including: connecting the resistance adjustment pads of the first signal output circuit 100 and the second signal output circuit 200 via leads; and / or when the first signal output circuit 100 includes at least two resistance adjustment pads, electrically connecting the two resistance adjustment pads of the first signal output circuit 100 via leads; and / or when the second signal output circuit 200 includes at least two resistance adjustment pads, electrically connecting the two resistance adjustment pads of the second signal output circuit 200 via leads. This arrangement increases the flexibility of the connection method, allowing for a wider range of resistance adjustment.

[0091] It is worth noting that, in this application, the term "the connection state of component A and component B" includes not only the case where component A and component B are physically and directly connected, but also the case where component A and component B are indirectly connected via other components that do not substantially affect their electrical connection state or impair the function or effect achieved through their coupling. For example, indirect connection via resistors or diodes.

[0092] Below, we will use the following as an example Figure 2 Taking the 8-bit trimming gate drive circuit shown as an example, the trimming methods in some embodiments of this application will be explained.

[0093] Specifically, the switch adjustment pads T7 and T6 are used to adjust the driving MOSFETs, allowing for four combinations of IOmos+ and IOmos- in the switching module. The resistor adjustment pads T5, T4, T3, T2, T1, and T0 are used to adjust the Rg resistors (i.e., the resistor Rgon between the switching circuit and the signal output port of the first signal output circuit 100 and the resistor Rgoff between the switching circuit and the signal output port of the second signal output circuit 200). This allows for 60 combinations of Rg resistors Rgon and Rgoff, eliminating the possibility of wire bonding crossovers and thus solving the problem of unadjustable drive current. By combining MOSFET adjustment and resistor adjustment, 240 IO+ and IO- drive current values ​​can be obtained to meet the drive current requirements of different power transistors.

[0094] like Figure 3 and Figure 4As shown, to illustrate the circuit's operating state, "0" represents a low level, connected to the floating ground VS using a bonding wire; "1" represents a high level, connected to the floating power supply VB using pull-up resistors R10 and R13. To conserve bonding wire, when the switch adjustment pads T7 and T6 are floating (i.e., no bonding wire is used), the switch adjustment pads T7 and T6 are connected to pull-up resistors R10 and R13 respectively to the floating power supply VB. The first switch signal T7-IN and the second switch signal T6-IN are both high, i.e., T7T6 = 11, making the first signal output circuit 100 and the second signal output... The gate TG in circuit 200 is disabled by default. The gate current IO+ is provided by the driving switch P0, and the gate current IO- is provided by the driving switch N0. When the switch adjustment pads T7 and T6 are both connected to the floating ground Vs through the bonding wire, the pull-up resistors R10 and R13 and the pull-down resistors R8 and R11 form a loop, pulling down the output voltage of the current limiting resistor. This makes both the first switch signal T7-IN and the second switch signal T6_IN low, i.e., when T7T6 = 00. At this point, the gate TG in the first signal output circuit 100 and the second signal output circuit 200 is enabled. The current IO+ is provided by driving switches P0 and P1, and the current IO- is provided by driving switches N0 and N1. When switch adjustment pad T7 is connected to floating ground Vs via a bonding wire and switch adjustment pad T6 is floating, the first switch signal T7-IN is low and the second switch signal T6-IN is high, that is, when T7T6=01, the gating gate TG of the first signal output circuit 100 is turned on, and the gating gate TG of the second signal output circuit 200 is not turned on. The current IO+ is provided by driving switches P0 and P1, and the current IO- is provided by switch N0. With pad T7 floating and switch adjustment pad T6 connected to floating ground Vs via a bonding wire, the first switch signal T7-IN is high and the second switch signal T6_IN is low. That is, when T7T6=10, the gating transmission gate TG of the first signal output circuit 100 is deactivated, and the gating transmission gate TG of the second signal output circuit 200 is activated. The current IO+ is provided by the driving switch P0, and the current IO- is provided by the driving switches N0 and N1. This gives the MOSFETs IOmos+ and IOmos- four possible combinations to meet the upper and lower limit current requirements of different power transistors.

[0095] Resistors R0-R7 in the circuit are the root resistors used to adjust the gate turn-on resistor Rgon and the gate turn-off resistor Rgoff. Their values ​​can be determined according to the adjustment range and adjustment step value. Resistors of the same resistance value or proportional resistors can be used, depending on the specific situation. When the resistor adjustment pads T5-T0 are floating, i.e., no bonding wire connection is used, the gate turn-on resistor Rgon = R0 + R1 + R2 + R3, and the gate turn-off resistor Rgoff = R4 + R5 + R6 + R7. The chip layout TOP VIEW is as follows. Figure 5 As shown, this is the default setting without any adjustments. Since there are 60 ways to change the gate turn-on resistance Rgon and gate turn-off resistance Rgoff by changing the leads, they will not be listed here.

[0096] In one embodiment, such as Figure 6 As shown, resistor adjustment pads T0 and T3, T1 and T4, T2 and T5 are connected using bonding wires, and switch adjustment pads T7 and T6 are connected to the floating ground VS using bonding wires. The chip layout, package substrate, and bonding wires are illustrated as follows. Figure 6 As shown. At this time, the current IO+ is provided by driving switches P0 and P1, and the current IO- is provided by driving switches N0 and N1; the gate turn-on resistance Rgon = R0 + R1 / / R5 + R2 / / R6 + R3 / / R7, and the gate turn-off resistance Rgoff = R4 + R1 / / R5 + R2 / / R6 + R3 / / R7. The symbol " / / " indicates parallel connection. That is, by adjusting the connection method of the bonding wires, the series and parallel connection method between resistors can be changed, thereby adjusting the resistance.

[0097] In summary, the gate drive circuit in some embodiments of this application includes at least two resistors connected in series between the switching circuit and the signal output port, and at least one resistor adjustment pad connecting the node between the two series resistors. This allows for adjustment of the electrical connection between the resistor adjustment pads by adjusting the leads, thereby adjusting the total resistance between the switching circuit and the signal output port and thus the gate current. This adjustment method enables adjustable gate current. Furthermore, because this application utilizes the Bipolar-CMOS-DMOS (BCD) process, where the circuit is placed under the pads (Circuit Under...), the gate current can be adjusted. The gate driver chip (CUP) is characterized by its programmability via wire bonding without sacrificing chip area. This allows for adjustment of the gate turn-on and gate turn-off resistances, thereby adjusting the gate current. This enables optimal driving of various types of power devices using a single gate driver chip. Therefore, the gate driver circuit adjustment method of this application does not occupy a large additional chip area. Furthermore, compared to the traditional fuse adjustment method, the resistor adjustment method of this application is simpler, easier to operate, and has a higher success rate. This can significantly shorten the development cycle of the gate driver chip, reduce development costs, and mitigate risks such as affecting chip delivery nodes.

[0098] Furthermore, such as Figure 7 As shown, this application also provides a gate driver chip, which includes a high-side gate driver chip (HVIC). The gate driver chip can be a PWM driver chip or a general-purpose driver chip. The PWM driver chip is a driver chip that can transmit three-phase pulse signals (U-phase, V-phase, and W-phase), while a general-purpose driver chip typically transmits only one pulse signal. Compared to a general-purpose driver chip, the PWM driver chip has two more signal input ports (hereinafter referred to as I / O ports) than a general-purpose chip.

[0099] The gate driver chip includes a pulse generation circuit 710, which encodes the rising and falling edges of the received PWM pulse width modulation signal into a first pulse signal SET and a second pulse signal RESET, respectively. The pulse generation circuit 710 may include a filtering and shaping circuit, a low-voltage level shifting circuit, and a narrow pulse generation circuit. The filtering and shaping circuit receives the PWM pulse width modulation signal and filters and shapes it; the low-voltage level shifting circuit processes the PWM pulse width modulation signal to obtain a level-shifted signal; and the narrow pulse generation circuit encodes the rising and falling edges of the level-shifted signal into the first pulse signal and the second pulse signal, respectively. The narrow pulse generation circuit enables precise control of the signal triggering time, achieving high-precision timing control.

[0100] Optionally, the filtering and shaping circuit may include a Schmitt trigger (SMIT) and an input signal filter (INPUTFILTER).

[0101] Specifically, such as Figure 7 The high-voltage gate driver chip circuit structure shown has three voltage domains: a low-voltage region, a working voltage region, and a high-voltage region. The low-voltage region power supply VDD is provided by the working voltage VCC through a linear load regulator REG, primarily for compatibility with the upstream drive capability. The high-voltage region power supply is provided by the working voltage VCC through a bootstrap boost circuit, primarily for compatibility with driving downstream loads. The output control signal directly drives the gate of the power transistor. To ensure normal circuit operation, both the high-voltage and working voltage regions require undervoltage protection circuits, namely HSUVLO and LSUVLO, respectively. The two circuits are identical in structure and parameters except for the device type. Because the devices in the high-voltage region are integrated in a high-voltage isolation island, they must be replaced with isolated devices.

[0102] HIN receives a PWM pulse width modulation signal from a controller such as an MCU. This input signal is at 3.3V CMOS level or 5V TTL level. After the signal is filtered and shaped by a Schmitt trigger (SMIT) and an input signal filter (INPUT FILTER), a clean signal HIN_PWM is obtained. This signal is then transferred from the low voltage region to the operating voltage region by a level shifting circuit (LS_L2H), and the LS_PWM signal (i.e., the level shifted signal) is output. The narrow pulse generation circuit (PULSE GEN) encodes the rising and falling edges of the high-side signal of the LS_PWM signal into two narrow pulse signals, namely the first pulse signal PWM1 and the second pulse signal PWM2.

[0103] Furthermore, such as Figure 7 As shown, the high-voltage gate driver chip of this application also includes a high-voltage level shifting circuit 720, which can be implemented as the high-voltage level shifting circuit in the aforementioned embodiments, thereby having the aforementioned high-voltage level shifting circuit's function of resisting noise signal interference.

[0104] The narrow pulse signals are used as the gate inputs of two high-voltage LDMOS transistors (e.g., the first and second input switches) in the high-voltage level shifter circuit (LEVEL_SHIFTER). Two inverted narrow pulse signals are generated at the drain of the high-voltage LDMOS transistors. After passing through the common-mode noise filtering circuit, a reset signal RD and a set signal SD are generated. The high-voltage level shifter circuit 720 then shifts the signals from the operating voltage region to the high-voltage region.

[0105] In one example, a noise cancellation circuit 730 is also included, with one end connected to a high-voltage level shift circuit 720 and the other end connected to a trigger circuit. This circuit filters out noise from the reset signal RD and the set signal SD before outputting them to the trigger circuit 740. After passing through the noise cancellation circuit, the differential-mode noise in the reset signal RD and the set signal SD is filtered out, resulting in the RD' and SD' signals.

[0106] In one example, a trigger circuit (EDGE TRIGGER) is also included. The RD' and SD' signals pass through the trigger circuit (EDGE TRIGGER) to prevent false triggering caused by the negative VS voltage and the narrow pulse width HIN, thus obtaining a clean signal.

[0107] In one example, a latch 750 and a gate drive circuit 760 are also included. The latch 750 is electrically connected to a trigger circuit 740 and is used to process the signal output by the trigger circuit 740 to obtain a switching signal to drive the device to be driven to turn on or off. The gate drive circuit 760 is connected to the gate of the target switching transistor (e.g., a high-side power transistor IGBT1) and is used to drive the target power switching transistor to turn on or off. The gate drive circuit 760 includes the device to be driven, and the output of the latch 750 is connected to the gate of the device to be driven, which is a switching transistor. The signal output by the latch 750 controls the switching transistor to turn on or off, thereby controlling the gate drive circuit 760 to turn on or off. In a specific example, the latch 750 restores the signal output by the trigger circuit 740 to a normal floating voltage switching signal and outputs it to the drive circuit to control the drive circuit to turn on or off, obtaining a HO signal. The gate drive circuit 760 outputs the HO signal to the high-side power transistor IGBT1 to realize the turn-on / turn-off of the high-side power transistor IGBT1.

[0108] Optionally, latch 750 can be an RS latch, which can be a low-level active flip-flop, and may include a first trigger terminal S, a second trigger terminal R, and a flip-flop output terminal Q. Optionally, the first trigger terminal S receives the aforementioned SD' signal and changes its level state. The second trigger terminal R receives the aforementioned RD' signal and changes its level state. The flip-flop output terminal Q outputs a control signal (i.e., a switching signal) for the drive circuit based on the level states of the first trigger terminal S and the second trigger terminal R.

[0109] Specifically, the structure of the gate drive circuit 760 can be any suitable circuit, and no specific limitation is made here.

[0110] Since the gate driver chip of this application has the aforementioned gate driver circuit, it has the same advantages as the aforementioned gate driver circuit.

[0111] This application also provides a smart power module, including the aforementioned gate driver chip.

[0112] The gate driver chip in this application is a high-voltage gate driver chip, belonging to the high-side gate driver chip category, and is used in intelligent power modules (IPMs). Optionally, three single-channel high-side gate driver chips, one three-channel low-side gate driver chip, and six power transistors can be packaged together in an IPM for driving a three-phase motor. The intelligent power module has a target power switch, such as a high-side power transistor IGBT1. The signal output port of the gate driver chip is connected to the gate of the target power switch and is configured to control the turn-on or turn-off of the target power switch.

[0113] IPMs are commonly used in three-phase inverter circuits of household appliances (such as inverter air conditioners), industrial machinery, and automotive products. They are advanced power switching devices. IPMs typically consist of high-speed, low-power power components—Insulated Gate Bipolar Transistors (IGBTs)—and gate driver ICs, among other circuitry.

[0114] by Figure 8 Taking a smart power module with a half-bridge circuit structure as an example, it includes a high-side gate driver chip (HVIC) and a low-side gate driver chip (LVIC). Figure 5 As shown, the intelligent power module includes a high-side gate driver chip (HVIC) and a low-side gate driver chip (LVIC). They receive control signals from a microcontroller (MCU) or other control unit, amplify and process the signals through internal circuitry, and ultimately output sufficient voltage and current to drive the gates of the power switching devices, enabling their turn-on and turn-off. Specifically, the high-side gate driver chip (HVIC) outputs a high-voltage drive output (HO) to control the high-side power transistor IGBT1. The low-side gate driver chip (LVIC) outputs a low-voltage drive output (LO) to control the low-side power transistor IGBT2.

[0115] Optionally, the high-side power transistor IGBT1 and the low-side power transistor IGBT2 are connected in series between the DC voltage VH and the ground voltage. The voltage at the connection point between the high-side power transistor IGBT1 and the low-side power transistor IGBT2 is the high-side floating ground VS terminal Vs. Optionally, the high-side power transistor IGBT1 and the low-side power transistor IGBT2 are turned on alternately.

[0116] Optionally, the high-side power transistor IGBT1 and the low-side power transistor IGBT2 are connected in series between the DC voltage VH and the ground voltage. The voltage at the connection point between the high-side power transistor IGBT1 and the low-side power transistor IGBT2 is Vs at the high-side floating ground VS terminal. Optionally, the high-side power transistor IGBT1 and the low-side power transistor IGBT2 are alternately turned on. When the high-side power transistor IGBT1 is on and the low-side power transistor IGBT2 is off, the high-side floating ground VS terminal Vs is approximately equal to the bus voltage VH, that is, Vs is at a high potential. When the high-side power transistor IGBT1 is off and the low-side power transistor IGBT2 is on, the high-side floating ground VS terminal Vs is approximately equal to the ground voltage GND. Optionally, a load (not shown in the attached figure) is connected between the voltage Vs at the high-side floating ground VS terminal and the ground voltage. Optionally, the high-side floating power supply voltage VB (also known as the operating voltage VB) is bootstrap connected to the power supply voltage VCC through a bootstrap diode D1. Optionally, the high-side floating power supply voltage VB is bootstrap connected to the high-side floating ground Vs terminal through a bootstrap capacitor C1.

[0117] The IPM of this application has the aforementioned gate driver chip, and therefore also has the advantages of the aforementioned gate driver chip.

[0118] Furthermore, this application also provides an apparatus that may include the aforementioned gate drive circuit, or the aforementioned gate drive chip, or the aforementioned smart power module.

[0119] The device can be any electronic product or device, such as household appliances (e.g., inverter air conditioners, washing machines, etc.), televisions, mobile phones, tablets, laptops, netbooks, game consoles, television sets, VCDs, DVDs, navigation devices, cameras, camcorders, voice recorders, MP3 players, MP4 players, PSPs, etc. Alternatively, the device can also be a vehicle or other transportation equipment.

[0120] It should be noted that the above embodiments are illustrative of this application and not limiting of it, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several vehicle systems, several of these vehicle systems may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0121] The above are merely specific embodiments or descriptions of specific embodiments of this application. The scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. The scope of protection of this application shall be determined by the scope of the claims.

Claims

1. A gate driving circuit, characterized in that, include: A first signal output circuit and a second signal output circuit are connected to the signal output port of the gate drive circuit, wherein each of the first signal output circuit and the second signal output circuit includes: A switching circuit, which is connected to the signal input port of the gate drive circuit, is configured to turn on or off based on a control signal input to the signal input port. At least two resistors connected in series are connected between the switching circuit and the signal output port; At least one resistor adjustment pad connects the node between two resistors connected in series; Specifically, by adjusting the leads to change the electrical connection between the resistor adjustment pads, the total resistance between the switching circuit and the signal output port is adjusted, thereby adjusting the gate current.

2. The gate driving circuit as described in claim 1, characterized in that, Changing the electrical connection between the resistance adjustment pads by adjusting the leads includes: The resistor adjustment pads of the first signal output circuit and the second signal output circuit are connected by leads; and / or When the first signal output circuit includes at least two resistor adjustment pads, the two resistor adjustment pads of the first signal output circuit are electrically connected by leads; and / or When the second signal output circuit includes at least two resistor adjustment pads, the two resistor adjustment pads of the second signal output circuit are electrically connected by leads.

3. The gate driving circuit as described in claim 1, characterized in that, The switching circuit includes: A signal input circuit is used to receive control signals and process the control signals to obtain drive signals; A switching module, which is also connected to the signal input circuit, is configured to turn on or off based at least on the drive signal output by the signal input circuit. The switching module of the first signal output circuit is connected to a floating power supply, and the switching module of the second signal output circuit is connected to a floating ground.

4. The gate driving circuit as described in claim 3, characterized in that, The switching module includes: At least two parallel switching transistors, wherein the at least two parallel switching transistors include a first switching transistor and a second switching transistor, the control terminal of the first switching transistor is connected to the signal input circuit and is configured to: turn on or off based on the drive signal output by the signal input circuit at least; A gating transmission gate, which is connected to the control terminal of the second switch, is configured to: turn on the second switch when it is gated, and turn off the second switch when it is not gated; A switch adjustment pad, connected to the gating transmission gate, is configured such that: by suspending the switch adjustment pad, the gating transmission gate is not selected; and by connecting the switch adjustment pad to a floating ground via a lead, the gating transmission gate is selected.

5. The gate driving circuit as described in claim 4, characterized in that, The switching module also includes: A switch signal generation circuit is disposed between the floating power supply and the floating ground, and the switch signal generation circuit is also connected to the switch adjustment pad. The output terminal of the switch signal generation circuit is connected to the gating transmission gate and is configured to output a control signal to control the gating transmission gate to be selected or not selected. When the switch adjustment pad is floating, the switch signal generation circuit outputs a high-level switch signal, which prevents the gating transmission gate from being selected. When the switch adjustment pad is connected to the floating ground via a lead wire, the switch signal generation circuit outputs a low-level switch signal, which turns on the gating transmission gate.

6. The gate driving circuit as described in claim 5, characterized in that, The switching signal generation circuit includes: A pull-up resistor, the first end of which is connected to the floating power supply; A pull-down resistor, the first end of which is connected to the switch adjustment pad, and the second end of which is connected to the pull-up resistor; A current-limiting resistor, wherein the first end of the current-limiting resistor is connected to the second end of the pull-up resistor; A filter circuit, wherein the input terminal of the filter circuit is connected to the second terminal of the current-limiting resistor, and the output terminal of the filter circuit outputs the switching signal.

7. The gate driving circuit as described in claim 6, characterized in that, The switching signal generation circuit further includes: An ESD protection circuit is disposed between the floating power supply and the floating ground, wherein the ESD protection circuit includes: The first protective switch transistor has its gate and source connected to the floating power supply. The second protection switch has its gate and source connected to the floating ground, and its drain is connected to the drain of the first protection switch.

8. The gate driving circuit as described in claim 3, characterized in that, The switching module of the first signal output circuit includes a PMOS transistor, and the switching module of the second signal output circuit includes an NMOS transistor.

9. A gate driver chip, characterized in that, include: The gate drive circuit as described in any one of claims 1 to 8.

10. A smart power module, characterized in that, include: Target power switching transistor; The gate driver chip as described in claim 9, wherein the signal output port of the gate driver chip is connected to the gate of the target power switch and is configured to control the turn-on or turn-off of the target power switch.

11. A device, characterized in that, It includes the gate drive circuit as described in any one of claims 1 to 8, or the gate drive chip as described in claim 9, or the smart power module as described in claim 10.

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