Gate drive circuit

Abstract

There is provided a gate driving circuit including a plurality of stages, in which each stage of the plurality of stages includes a transistor that controls a voltage of a control node by a carry signal output from a previous stage and a carry signal output from a next stage, and a transistor that reduces a leakage current of a first control node.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0085279 filed in the Korean Intellectual Property Office on June 30, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] One or more embodiments relate to a display device, and more particularly, to a gate driving circuit outputting a gate signal and a display device including the gate driving circuit. Background Art

[0003] The display device includes a pixel portion including a plurality of pixels, a gate driving circuit, a data driving circuit, a controller, etc. The gate driving circuit includes a stage connected to a gate line, and the stage supplies a gate signal to the gate line connected to the stage in response to a signal from the controller. Summary of the invention

[0004] One or more embodiments include a gate drive circuit for stably outputting a gate signal and a display device including the gate drive circuit. The technical features implemented by the embodiments are not limited to the above-mentioned technical features, and a person of ordinary skill in the art will clearly understand other technical features not mentioned through the disclosed description.

[0005] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed presented embodiments.

[0006] According to one or more embodiments, the gate drive circuit includes a plurality of stages, wherein each of the plurality of stages includes a first controller, a second controller, a first output portion, and a second output portion. The first controller is connected to a first voltage input terminal and a second voltage input terminal, and is configured to control the voltage of a first control node and a voltage of a second control node during a display period of a frame. The second controller is connected to the first voltage input terminal and the first control node, and is configured to control the voltage of the first control node during a sensing period of a frame. The first output portion is connected to a first clock terminal and a third voltage input terminal, and is configured to output a gate signal. The second output portion is connected to a second clock terminal and a second voltage input terminal, and is configured to output a carry signal. The first controller includes a first transistor, a second transistor, and a third transistor. The first transistor is configured to be turned on by a third clock signal input to a third clock terminal, and to control the voltage of the first control node using the voltage of a previous carry signal, which is a carry signal input from a previous stage. The second transistor is configured to be turned on when the first control node is at a first level voltage, and to control the voltage of the second control node using a second voltage input to a second voltage input terminal. The third transistor is configured to be turned on by a next carry signal which is a carry signal input from a next stage, and to control a voltage of the second control node using a first voltage input to the first voltage input terminal.

[0007] The second voltage may be lower than the third voltage input to the third voltage input terminal, and the first voltage may be higher than the second voltage and the third voltage.

[0008] A first level voltage and a second level voltage lower than the first level voltage of each of the first and second clock signals may be alternately input during the display period, wherein the first level voltage of the first clock signal and the first level voltage of the second clock signal may be input during the sensing period.

[0009] The third clock signal may be an inverted signal of the second clock signal, wherein a period during which the second clock signal is at a first level voltage may overlap with a period during which the first clock signal is at a first level voltage, and a period during which the first clock signal is at the first level voltage may be shorter than a period during which the second clock signal is at the first level voltage.

[0010] Each of the first transistor and the second transistor may include a first sub-transistor and a second sub-transistor connected in series.

[0011] The first controller may further include a fourth transistor connected to the first voltage input terminal and an intermediate node between the first sub-transistor and the second sub-transistor of the first transistor and having a gate connected to the first control node.

[0012] The first controller may further include a fifth transistor connected to the first voltage input terminal and an intermediate node between the first sub-transistor and the second sub-transistor of the second transistor and having a gate connected to the second control node.

[0013] The first controller may further include a sixth transistor connected to the first voltage input terminal and the second control node and having a gate receiving a reset signal.

[0014] The second controller may include a first capacitor, a seventh transistor, an eighth transistor, and a ninth transistor. The first capacitor is connected to a first voltage input terminal and a sensing node. The seventh transistor is connected to the sensing node and the second output portion, and includes a first sub-transistor and a second sub-transistor connected in series. The eighth transistor is connected to the first voltage input terminal and an intermediate node between the first sub-transistor and the second sub-transistor of the seventh transistor, and has a gate connected to the sensing node. The ninth transistor is connected to the intermediate node of the seventh transistor and the first control node.

[0015] The seventh transistor may be configured to be turned on by the first control signal synchronized with the carry signal output from the second output part during the display period and to set the voltage of the sense node to the voltage of the carry signal.

[0016] The first capacitor may store a voltage difference between a terminal connected to the first voltage input terminal and a terminal connected to the sensing node.

[0017] The ninth transistor may be configured to be turned on by the second control signal input during the sensing period and set the voltage of the first control node to the first voltage transmitted through the turned-on eighth transistor.

[0018] The second output part may include a second capacitor connected between the first control node and an output terminal of the second output part.

[0019] The first output portion may include a plurality of sub-output portions, wherein one of a plurality of first clock signals may be input to a first clock terminal of each of the plurality of sub-output portions, and the plurality of first clock signals may be signals having the same waveform and having phases shifted at specific intervals.

[0020] The second output part may include a first sub-output part and a second sub-output part, wherein the first sub-output part may output a first carry signal synchronized with a 2-1 clock signal input to a second clock terminal of the first sub-output part to a next stage, and the second sub-output part may output a second carry signal synchronized with a 2-2 clock signal input to a second clock terminal of the second sub-output part to a previous stage.

[0021] The period in which the 2-1 clock signal is at the first level voltage may overlap with the period in which multiple first clock signals of multiple sub-output parts input to the first output part are at the first level voltage, the period in which the 2-1 clock signal is at the first level voltage may overlap with the period in which the 2-2 clock signal is at the first level voltage, and the period in which the 2-2 clock signal is at the first level voltage may be shorter than the period in which the 2-1 clock signal is at the first level voltage.

[0022] The first controller may further include a tenth transistor connected between the first transistor and the first control node and having a gate connected to the first voltage input terminal.

[0023] The second controller may include: an eleventh transistor connected to the first control node and the second voltage input terminal and having a gate connected to the sensing node; and a twelfth transistor connected between the first control node and the eleventh transistor.

[0024] The twelfth transistor may be configured to be turned on by the third control signal input after the sensing period, and set the voltage of the first control node to the second voltage transmitted through the turned-on eleventh transistor.

[0025] According to one or more embodiments, the gate drive circuit includes a plurality of stages, wherein each of the plurality of stages includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first capacitor, a sixth transistor, a seventh transistor, and an eighth transistor. The first transistor is connected between a first input terminal receiving a start signal and a first control node, and has a gate connected to a first clock terminal. The second transistor is connected to a first voltage input terminal and an intermediate node between a first sub-transistor and a second sub-transistor of the first transistor, and has a gate connected to the first control node. The third transistor is connected between a second control node and a second voltage input terminal, and has a gate connected to the first control node. The fourth transistor is connected to a first voltage input terminal and an intermediate node between a first sub-transistor and a second sub-transistor of the third transistor, and has a gate connected to the second control node. The fifth transistor is connected between a first voltage input terminal and a second control node, and has a gate connected to a second input terminal, and a carry signal of a next stage is input to the second input terminal. The first pull-up transistor is connected between a second clock terminal and a first output terminal, and has a gate connected to the first control node. The first pull-down transistor is connected between the first output terminal and the third voltage input terminal and has a gate connected to the second control node. The second pull-up transistor is connected between the third clock terminal and the second output terminal and has a gate connected to the first control node. The second pull-down transistor is connected between the second output terminal and the second voltage input terminal and has a gate connected to the second control node. The first capacitor is connected between the first voltage input terminal and the sensing node. The sixth transistor is connected between the sensing node and the second output terminal and has a gate connected to the first control signal terminal. The seventh transistor is connected to the first voltage input terminal and the intermediate node between the first sub-transistor and the second sub-transistor of the sixth transistor and has a gate connected to the sensing node. The eighth transistor is connected between the intermediate node of the sixth transistor and the first control node and has a gate connected to the second control signal terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects and features of certain disclosed embodiments will become more apparent from the following description in conjunction with the accompanying drawings.

[0027] Figure 1 is a schematic block diagram of a display device according to an embodiment.

[0028] Figure 2 is an equivalent circuit diagram of a pixel according to the embodiment.

[0029] Figure 3 is a diagram for explaining driving of a display device according to an embodiment.

[0030] Figure 4 is a schematic diagram of a gate driving circuit according to an embodiment.

[0031] Figure 5 yes Figure 4 Schematic diagram of one stage of the gate drive circuit shown in .

[0032] Figure 6 It shows the input to Figure 4 The gate drive circuit shown in the figure is a stage signal and a Figure 4 FIG. 5 is a diagram of a signal output by a stage of a gate drive circuit shown in FIG.

[0033] Figure 7 is a circuit diagram showing an example of stages included in a gate driving circuit according to an embodiment.

[0034] Fig. 8A and Figure 8B is shown for explanation Figure 7 Diagram of the stage drive signal.

[0035] Fig. 9 is a schematic diagram of a gate driving circuit according to an embodiment.

[0036] Fig.10 yes Fig. 9 Schematic diagram of one stage of the gate drive circuit shown in .

[0037] Fig.11 is a circuit diagram showing an example of stages included in a gate driving circuit according to an embodiment.

[0038] Fig.12 is shown for explanation Fig.11 Diagram of the stage drive signal.

[0039] Fig.13 is a schematic diagram of a gate driving circuit according to an embodiment.

[0040] Fig.14 yes Fig.13 Schematic diagram of one stage of the gate drive circuit shown in .

[0041] Fig.15 is a circuit diagram showing an example of stages included in a gate driving circuit according to an embodiment.

[0042] Fig.16 , Fig.17A , Fig. 17B and Fig.18 is shown for explanation Fig.15 Diagram of the stage drive signal. DETAILED DESCRIPTION

[0043] Now will be referred to in detail embodiment, the example of embodiment is shown in the accompanying drawings, and the same reference numerals refer to the same elements throughout the drawings. In this regard, the embodiment provided can have different forms, and should not be interpreted as being limited to the description set forth herein. Therefore, the embodiment is described below only by reference to the accompanying drawings to explain the aspects of this specification. As used herein, the term "and / or" includes any combination and all combinations of one or more of the relevant listed items. Throughout the disclosure, the statement "at least one (kind / person) of a, b and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or its variant.

[0044] Since the disclosure allows various changes and many embodiments, certain embodiments will be shown in the drawings and described in the written description. The effects and features of the disclosure and methods for implementing them will be explained with reference to the embodiments described in detail below with reference to the drawings. However, the disclosure is not limited to the following embodiments and can be implemented in various forms.

[0045] Although terms such as "first" and "second" may be used to describe various elements, such elements must not be limited to the above terms. The above terms are used to distinguish one element from another element.

[0046] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0047] It will be understood that the terms “comprises,” “comprising,” and / or variations thereof as used herein specify the presence of stated features or elements, but do not preclude the addition of one or more other features or elements.

[0048] It will also be understood that when a layer, region or element is referred to as being “on” another layer, region or element, it can be directly or indirectly on the other layer, region or element. That is, for example, intervening layers, regions or elements may be present.

[0049] For convenience of explanation, the size of the elements in the drawings may be exaggerated or reduced. As an example, for convenience of description, the size and thickness of each element shown in the drawings are arbitrarily represented, and therefore, the present disclosure is not necessarily limited thereto.

[0050] In the present specification, "A and / or B" means A or B or A and B. In the present specification, "at least one of A and B" means A or B or A and B.

[0051] In the following embodiments, when it is described that X is connected to Y, X may be electrically connected to Y, X may be functionally connected to Y, or X may be physically connected to Y with or without an intervening element (e.g., direct or indirect connection). Here, X and Y may be objects (e.g., devices, elements, circuits, wirings, electrodes, terminals, conductive layers, layers, etc.). Therefore, X and Y are not limited to the preset connection relationships and connection relationships shown and made in the drawings and detailed descriptions, but may include connection relationships other than the connection relationships shown and made in the drawings and detailed descriptions.

[0052] The case where X is electrically connected to Y may include, for example, a case where X and Y are directly connected to each other and a case where at least one element (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, etc.) capable of achieving electrical connection between X and Y is connected between X and Y.

[0053] In the following embodiments, the "ON" used in association with the element state can represent the activated state of the element, and "OFF" can represent the inactivated state of the element. The "ON" used in association with the signal received by the element can represent the signal that activates the element, and "OFF" can represent the signal that makes the element inactivated. The element can be activated by a high level voltage or a low level voltage. As an example, a P-channel transistor (P-type transistor) can be activated by a low level voltage, and an N-channel transistor (N-type transistor) can be activated by a high level voltage. Therefore, it should be understood that the "ON" voltage for a P-type transistor and an N-type transistor is an opposite voltage (low voltage and high voltage).

[0054] In the embodiments described below, the x-direction, y-direction, and z-direction are not limited to the directions on the three axes on the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-direction, y-direction, and z-direction may be perpendicular to each other, or may refer to different directions that are not perpendicular to each other.

[0055] The display device according to some disclosed embodiments may be a device for displaying a video or a static image. The display device may be used as a display screen for various devices such as televisions, notebook computers, monitors, broadcast panels, and Internet of Things (IOT) devices, as well as portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). In addition, the display device according to the embodiment may be used in wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). In addition, the display device according to the embodiment may be used as: a center information display (CID) on a vehicle's instrument panel or a center instrument panel or dashboard of a vehicle; an interior mirror display that replaces a vehicle's side mirror; or a display arranged on the rear surface of a front seat as an entertainment device for a rear seat of a vehicle. In addition, the display device may be a flexible device.

[0056] Figure 1 is a schematic block diagram of a display device 10 according to an embodiment.

[0057] Reference Figure 1 , the display device 10 may include a pixel portion 110 , a gate driving circuit 130 , a data driving circuit 150 , a sensing circuit 170 , and a controller 190 .

[0058] The pixel portion 110 may be disposed in the display area. In the peripheral area outside the display area, various conductive lines for transmitting electrical signals to be applied to the display area, external circuits electrically connected to the pixel circuit, and pads (or "pads") to which a printed circuit board or a driver IC chip is attached may be located. For example, the gate drive circuit 130, the data drive circuit 150, the sensing circuit 170, and the controller 190 may be disposed in the peripheral area.

[0059] A plurality of gate lines GL, a plurality of data lines DL, a plurality of sensing lines SL, and a plurality of pixels PX connected thereto may be arranged in the pixel portion 110. The plurality of pixels PX may be arranged in various forms such as stripe arrangement, The pixels PX may be arranged in a pattern (diamond arrangement, mosaic arrangement, etc.) to realize an image. Each of the pixels PX may include an organic light emitting diode as a display element (light emitting element), and the organic light emitting diode may be connected to a pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. The pixel PX may emit, for example, red light, green light, blue light, or white light through the organic light emitting diode. Each pixel PX may be connected to a corresponding gate line among a plurality of gate lines GL, a corresponding sensing line among a plurality of sensing lines SL, and a corresponding data line among a plurality of data lines DL.

[0060] The plurality of pixels PX may be arranged to overlap the gate driving circuit 130 at at least one corner of the display device 10. Therefore, an ineffective area may be reduced and a display area may be expanded.

[0061] Each of the gate lines GL may extend in the x direction (row direction) and be connected to the pixels PX located in the same row. Each of the gate lines GL may transmit a gate signal to each of the pixels PX located in the same row. Each of the data lines DL may extend in the y direction (column direction) and be connected to the pixels PX located in the same column. Each of the data lines DL may transmit a data signal DATA to each of the pixels PX in the same column in synchronization with the gate signal. Each of the sensing lines SL may extend in the y direction (column direction) and be connected to the pixels PX located in the same column.

[0062] The gate driving circuit 130 may be connected to a plurality of gate lines GL, generate a gate signal GS in response to a gate control signal GCS from the controller 190, and sequentially supply the gate signal GS to the gate lines GL. The gate line GL may be connected to the gate of a transistor included in the pixel PX. The gate signal GS may be a gate control signal for controlling the turning on and off of the transistor whose gate is connected to the gate line GL. The gate signal GS may be a square wave signal including a gate-on voltage that may turn on the transistor and a gate-off voltage that may turn off the transistor.

[0063] The data driving circuit 150 may be connected to a plurality of data lines DL and supply data signals DATA to the data lines DL in response to data control signals DCS from the controller 190. The data signals DATA supplied to the data lines DL may be supplied to the pixels PX supplied with the gate signals GS. The data driving circuit 150 may convert input image data having a grayscale input from the controller 190 into data signals DATA in the form of voltage or current.

[0064] The sensing circuit 170 may be connected to a plurality of sensing lines SL, and may sense the state information of the pixel PX through the sensing line SL during the sensing period in response to the sensing control signal SCS from the controller 190. In an embodiment, the sensing line SL may be provided for each vertical line (column). In an embodiment, the pixels PX of a plurality of columns may share one sensing line SL. The sensing circuit 170 may measure the state information of the pixel PX based on the current and / or voltage fed back through the sensing line SL. The state information may include at least one of the threshold voltage and mobility of the driving transistor included in the pixel PX and degradation information of the organic light emitting diode as a display element. The state information of the pixel PX may be transmitted to the controller 190 and / or the data driving circuit 150, and may be used to correct the data signal DATA.

[0065] The controller 190 may generate control signals GCS, DCS, and SCS based on signals input from the outside, and selectively supply them to the gate driving circuit 130, the data driving circuit 150, and the sensing circuit 170. The gate control signal GCS output to the gate driving circuit 130 may include a plurality of clock signals and a start signal. The data control signal DCS output to the data driving circuit 150 may include a start signal and a plurality of clock signals.

[0066] The display device 10 may supply a driving voltage ELVDD and a common voltage ELVSS to the pixel PX. The driving voltage ELVDD may be a high-level voltage applied to a driving transistor electrically connected to a first electrode (pixel electrode or anode) of a display element included in the pixel PX. The common voltage ELVSS may be a low-level voltage provided to a second electrode (counter electrode or cathode) of a display element included in the pixel PX.

[0067] The display device 10 includes a display panel, and the display panel may include a substrate. The pixel PX may be arranged in the display area of ​​the substrate. During the process of forming the transistor constituting the pixel circuit in the display area of ​​the substrate, part or all of the gate drive circuit 130 may be directly formed in the peripheral area of ​​the substrate. The data drive circuit 150, the sensing circuit 170, and the controller 190 may be formed as separate integrated circuit chips or as a single integrated circuit chip, and may be arranged on a flexible printed circuit board (FPCB), which is electrically connected to a pad arranged on one side of the substrate. In an embodiment, the data drive circuit 150, the sensing circuit 170, and the controller 190 may be directly arranged on the substrate by using a chip on glass (COG) or a chip on plastic (COP) method.

[0068] Hereinafter, an organic light-emitting display device will be described as an example of a display device according to a disclosed embodiment. However, the disclosed display device is not limited thereto. In an embodiment, the disclosed display device may be a display device such as an inorganic light-emitting display (or an inorganic electroluminescent (EL) display) and a quantum dot light-emitting display.

[0069] Figure 2 is an equivalent circuit diagram of a pixel PX according to an embodiment.

[0070] Reference Figure 2, each pixel PX may include a pixel circuit PC and an organic light emitting diode OLED as a display element connected to the pixel circuit PC. The pixel circuit PC includes a first transistor M1, a second transistor M2, a third transistor M3 and a capacitor Cst. The first transistor M1 may be a driving transistor that outputs a driving current corresponding to the data signal DATA, and the second transistor M2 and the third transistor M3 may be switching transistors that transmit signals. The first terminal (first electrode) and the second terminal (second electrode) of each of the first transistor M1 to the third transistor M3 may be a source or a drain according to the voltage of the first terminal and the voltage of the second terminal. For example, according to the voltage of the first terminal and the voltage of the second terminal, the first terminal may be a drain and the second terminal may be a source, or the first terminal may be a source and the second terminal may be a drain.

[0071] The first transistor M1 may include a first terminal connected to a first power supply supplying a driving voltage ELVDD and a second terminal connected to a first electrode (pixel electrode) of the organic light emitting diode OLED (or connected to another node N2). The gate of the first transistor M1 may be connected to the node N1. The first transistor M1 may control a driving current flowing from the first power supply to the organic light emitting diode OLED in response to a voltage stored in the capacitor Cst. The organic light emitting diode OLED may emit light having a specific brightness via the driving current.

[0072] The second transistor M2 (write transistor) may include a gate connected to the gate line GL, a first terminal connected to the data line DL, and a second terminal connected to the node N1. The second transistor M2 may be turned on by a gate signal GS supplied to the gate line GL and electrically connect the data line DL to the node N1, and may be configured to transmit a data signal DATA input through the data line DL to the node N1.

[0073] The third transistor M3 (sensing transistor) may include a gate connected to the gate line GL, a first terminal connected to the second terminal of the first transistor M1 and the first electrode of the organic light emitting diode OLED, and a second terminal connected to the sensing line SL. The third transistor M3 may be turned on by a gate signal GS supplied through the gate line GL and electrically connect the sensing line SL to the second terminal of the first transistor M1 and the first electrode of the organic light emitting diode OLED, and may be configured to transmit a current and / or a voltage supplied from the second terminal of the first transistor M1 to the first electrode of the organic light emitting diode OLED to the sensing line SL.

[0074] The capacitor Cst may be connected between the node N1 and the second terminal of the first transistor T1. The capacitor Cst may store a voltage corresponding to a difference between a voltage received from the second transistor M2 and a voltage of the second terminal of the first transistor M1.

[0075] The organic light emitting diode OLED may include a first electrode (pixel electrode) connected to the second terminal of the first transistor M1 and a second electrode (counter electrode) connected to a second power source to which a common voltage ELVSS is applied. The organic light emitting diode OLED may emit light having a brightness corresponding to the amount of driving current supplied from the first transistor M1.

[0076] Although Figure 2 The transistors of the pixel circuit PC in the embodiment are N-type transistors, but the disclosed embodiments are not limited thereto. For example, the transistors of the pixel circuit PC may be P-type transistors, or some transistors of the pixel circuit PC may be P-type transistors and other transistors may be N-type transistors.

[0077] According to an embodiment, at least the first transistor M1 may be an oxide thin film transistor including a semiconductor layer including an amorphous oxide semiconductor or a crystalline oxide semiconductor. For example, the first transistor M1 to the third transistor M3 may be oxide thin film transistors. The oxide thin film transistor has excellent cut-off current characteristics. The oxide semiconductor may include a Zn oxide-based material (such as Zn oxide, In-Zn oxide, or Ga-In-Zn oxide). In some embodiments, the oxide semiconductor may be an In-Ga-Zn-O (IGZO) semiconductor. In some embodiments, the oxide semiconductor may be an In-Sn-Ga-Zn-O (ITGZO) semiconductor. In an embodiment, the oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor. Optionally, according to an embodiment, at least one of the first transistor M1 to the third transistor M3 may be a low temperature polycrystalline silicon (LTPS) thin film transistor including an active layer (semiconductor layer) including polycrystalline silicon. The LTPS thin film transistor has a high electron mobility and therefore has a fast driving characteristic.

[0078] When a gate signal is supplied through a corresponding gate line during a driving period, the pixel PX may receive a data signal from a corresponding data line. The pixel PX receiving the data signal may control the amount of current flowing from the first power source to the second power source via the organic light emitting diode OLED in response to the data signal. In this case, the organic light emitting diode OLED may generate light of a specific brightness in response to the amount of current.

[0079] When a gate signal is supplied through a corresponding gate line during a sensing period, the pixel PX may output a current and / or a voltage through the sensing line based on a sensing signal supplied to the corresponding data line.

[0080] Figure 3 is a diagram for explaining driving of a display device according to an embodiment.

[0081] Reference Figure 3 , the display device can be operated by dividing one frame into a display period DP in which an image is displayed and a vertical blank period VBP. Because the state information of the pixel is sensed in the vertical blank period VBP, it can be understood that the vertical blank period VBP includes a sensing period SP.

[0082] The display period DP may be a period during which the pixel PX displays a specific image in response to a data signal. The second transistor M2 and the third transistor M3 of the pixel PX may be turned on according to the gate signal GS supplied during the display period DP, so that the node N1 (eg, see Figure 2 ) and a voltage between the second terminal of the first transistor M1 may be set to match the driving current. When the gate signal GS is supplied, the data signal DATA may be supplied to the data line DL, and the initialization voltage may be supplied to the sensing line SL. In an embodiment, the initialization voltage may be set in response to degradation of the organic light emitting diode OLED. When the initialization voltage is supplied to the pixel PX during the display period DP, the required voltage may be charged to the capacitor Cst without being affected by degradation of the organic light emitting diode OLED.

[0083] The sensing period SP may be activated in any frame by a specific frame cycle or a user's setting. Any row for pixel sensing may be selected during the sensing period SP. Figure 3 An example is shown in which the pixels PX in the k-th row are sensed during the sensing period SP.

[0084] The second transistor M2 and the third transistor M3 of the pixel PX that receive the gate signal GS during the sensing period SP may be turned on. When the gate signal GS is supplied, the sensing voltage for pixel sensing may be supplied to the data line DL, and the mobility and / or threshold voltage of the first transistor M1 may be measured by measuring the current and / or voltage of the sensing line SL. In an embodiment, the sensing voltage may be a black grayscale voltage at which the first transistor M1 is turned off. In an embodiment, the sensing voltage may be a preset reference voltage. The reference voltage may be set to a voltage at which the first transistor M1 may be turned on. The voltage applied to the first electrode of the organic light emitting diode OLED may include degradation information of the organic light emitting diode OLED. In various embodiments, after the sensing period SP, a period for initializing the voltage of the node N1 and / or the voltage of the first electrode of the organic light emitting diode OLED or for resetting the voltage to a voltage set before the sensing period SP may be further set.

[0085] Figure 4 is a schematic diagram of a gate driving circuit 130 a according to an embodiment. Figure 5 yes Figure 4 Schematic diagram of one stage of the gate drive circuit 130a shown in FIG. Figure 6 It shows the input to Figure 4 The gate drive circuit 130a shown in the stage of the signal and from Figure 4 2 is a diagram of a signal output by a stage of the gate drive circuit 130 a shown in FIG. Figure 5 The kth stage STk outputting the kth gate signal GS[k] to the gate line of the kth row is shown as an example.

[0086] Reference Figure 4 , the gate driving circuit 130a according to the embodiment may include a plurality of stages ST1 to STn. The plurality of stages ST1 to STn may sequentially output gate signals GS[1] to GS[n] to the gate lines. The number of stages provided in the gate driving circuit 130a may vary according to the number of rows (horizontal lines) provided in the pixel portion 110.

[0087] Each of the stages ST1 to STn may be connected to a gate line of a corresponding row. Each of the stages ST1 to STn may receive at least one clock signal and at least one voltage signal, generate a gate signal GS, and supply the gate signal GS to the connected gate line GL. That is, the plurality of stages ST1 to STn may output gate signals GS[1], GS[2], GS[3], ..., GS[n] to the gate lines GL disposed in the corresponding rows, respectively. For example, the first stage ST1 may output the first gate signal GS[1] through the first gate line, and the nth stage STn may output the nth gate signal GS[n] through the nth gate line.

[0088] Reference Figure 5 Each of the stages ST1 to STn may include a first input terminal IN1, a second input terminal IN2, a first voltage input terminal V1, a second voltage input terminal V2, a third voltage input terminal V3, a carry clock terminal CCLK, a scan clock terminal SCLK, a gate clock terminal GCLK, a first control signal terminal SN1, a second control signal terminal SN2, a third control signal terminal SN3, a first output terminal OUT1, and a second output terminal OUT2.

[0089] A start signal STV or a carry signal (hereinafter, referred to as a "previous carry signal") output from a previous stage may be input to the first input terminal IN1. For example, the start signal STV may be input to the first input terminal IN1 of the first stage ST1, and the previous carry signal may be input as a start signal to the first input terminal IN1 of each of the second stage ST2 to the nth stage STn. The previous stage may be at least one previous stage. Figure 4 and Figure 5 An example is shown in which the previous stage is the immediately previous stage. Figure 5As shown in , the carry signal CR[k-1] output from the k-1th stage may be input to the first input terminal IN1 of the k-th stage STk as a start signal.

[0090] A carry signal output from a next stage (hereinafter, referred to as a 'next carry signal') may be input to the second input terminal IN2. The next stage may be at least one next stage. Figure 4 and Figure 5 An example is shown in which the next stage is the stage two stages later. Figure 5 As shown in , the carry signal CR[k+2] output from the k+2th stage may be input to the second input terminal IN2 of the kth stage STk.

[0091] The first voltage VGH may be input to the first voltage input terminal V1, the second voltage VGL1 may be input to the second voltage input terminal V2, and the third voltage VGL2 may be input to the third voltage input terminal V3. The second voltage VGL1 may have a voltage lower than the first voltage VGH. The third voltage VGL2 may have a voltage lower than the second voltage VGL1. The first voltage VGH, the second voltage VGL1, and the third voltage VGL2 may be provided as global signals from Figure 1 Controller 190 shown in and / or power circuit input not shown.

[0092] The first carry clock signal CR_CK1 or the second carry clock signal CR_CK2 may be input to the carry clock terminal CCLK. The first carry clock signal CR_CK1 and the second carry clock signal CR_CK2 may be alternately input to the carry clock terminals CCLK of the stages ST1 to STn. For example, the first carry clock signal CR_CK1 may be input to the carry clock terminals CCLK of the odd-numbered stages ST1, ST3, ... The second carry clock signal CR_CK2 may be input to the carry clock terminals CCLK of the even-numbered stages ST2, ST4, ...

[0093] like Figure 6As shown in , the first carry clock signal CR_CK1 and the second carry clock signal CR_CK2 can be square wave signals that repeat a high level voltage and a low level voltage. The high level voltage can be a gate-on voltage for turning on an N-type transistor, and the low level voltage can be a gate-off voltage for turning off an N-type transistor. The first carry clock signal CR_CK1 and the second carry clock signal CR_CK2 can have the same waveform and can be a phase-shifted signal. For example, the second carry clock signal CR_CK2 can have the same waveform as the first carry clock signal CR_CK1 and can be input by phase shifting (phase delay) at a specific interval. The second carry clock signal CR_CK2 can be shifted from the first carry clock signal CR_CK1 by half a cycle. The gate-on voltage period of each of the first carry clock signal CR_CK1 and the second carry clock signal CR_CK2 can be set to be longer than its gate-off voltage period in one cycle. However, the disclosure is not limited thereto, and the gate-on voltage period of each of the first carry clock signal CR_CK1 and the second carry clock signal CR_CK2 may be equal to or shorter than the gate-off voltage period thereof in one cycle. The gate-on voltage of each of the first carry clock signal CR_CK1 and the second carry clock signal CR_CK2 may be 18 volts (V), and the gate-off voltage thereof may be -10 V. However, the disclosure is not limited thereto.

[0094] A gate-on voltage and a gate-off voltage of each of the first carry clock signal CR_CK1 and the second carry clock signal CR_CK2 may be alternately input in the display period DP, and the gate-off voltage may be input in the vertical blank period VBP.

[0095] The first scan clock signal SC_CK1 or the second scan clock signal SC_CK2 may be input to the scan clock terminal SCLK. The first scan clock signal SC_CK1 and the second scan clock signal SC_CK2 may be alternately input to the scan clock terminals SCLK of the stages ST1 to STn. For example, the first scan clock signal SC_CK1 may be input to the scan clock terminals SCLK of the odd-numbered stages ST1, ST3, ... The second scan clock signal SC_CK2 may be input to the scan clock terminals SCLK of the even-numbered stages ST2, ST4, ...

[0096] like Figure 6As shown in, the first scan clock signal SC_CK1 and the second scan clock signal SC_CK2 can be square wave signals that repeat a high level voltage (gate-on voltage) and a low level voltage (gate-off voltage). The first scan clock signal SC_CK1 and the second scan clock signal SC_CK2 can have the same waveform and can be phase-shifted signals. For example, the second scan clock signal SC_CK2 can have the same waveform as the first scan clock signal SC_CK1 and be input by phase shifting (phase delay) at specific intervals. The second scan clock signal SC_CK2 can be shifted from the first scan clock signal SC_CK1 by half a cycle. The gate-on voltage period and the gate-off voltage period of each of the first scan clock signal SC_CK1 and the second scan clock signal SC_CK2 can be set to be equal to each other in one cycle. However, the disclosure is not limited thereto, and the gate-on voltage period of each of the first scan clock signal SC_CK1 and the second scan clock signal SC_CK2 can be set to be longer or shorter than its gate-off voltage period in one cycle. A gate-on voltage of each of the first scan clock signal SC_CK1 and the second scan clock signal SC_CK2 may be 20 V, and a gate-off voltage thereof may be −5 V. However, the disclosure is not limited thereto.

[0097] A gate-on voltage and a gate-off voltage of each of the first and second scan clock signals SC_CK1 and SC_CK2 may be alternately input in the display period DP, and the gate-on voltage may be input in the sensing period SP.

[0098] The first gate clock signal GCK1 or the second gate clock signal GCK2 may be input to the gate clock terminal GCLK. The first gate clock signal GCK1 and the second gate clock signal GCK2 may be alternately input to the gate clock terminals GCLK of the stages ST1 to STn. For example, the first gate clock signal GCK1 may be input to the gate clock terminals GCLK of the odd-numbered stages ST1, ST3, ... The second gate clock signal GCK2 may be input to the gate clock terminals GCLK of the even-numbered stages ST2, ST4, ...

[0099] like Figure 6As shown in, the first gate clock signal GCK1 and the second gate clock signal GCK2 may be square wave signals that repeat a high level voltage (gate-on voltage) and a low level voltage (gate-off voltage). The first gate clock signal GCK1 and the second gate clock signal GCK2 may have the same waveform and may be phase-shifted signals. For example, the second gate clock signal GCK2 may have the same waveform as the first gate clock signal GCK1 and may be input by phase shifting (phase delay) at a specific interval. The second gate clock signal GCK2 may be shifted by half a cycle from the first gate clock signal GCK1. The gate-on voltage period of each of the first gate clock signal GCK1 and the second gate clock signal GCK2 may be set to be shorter than its gate-off voltage period in one cycle. However, the disclosure is not limited thereto, and the gate-on voltage period of each of the first gate clock signal GCK1 and the second gate clock signal GCK2 may be set to be equal to or longer than its gate-off voltage period in one cycle. The gate-on voltage of each of the first gate clock signal GCK1 and the second gate clock signal GCK2 may be 20V, and its gate-off voltage may be -12V. However, the disclosure is not limited thereto.

[0100] In an embodiment, the first gate clock signal GCK1 may be an inverted signal of the first carry clock signal CR_CK1, and the second gate clock signal GCK2 may be an inverted signal of the second carry clock signal CR_CK2. The gate-on voltage period of the first carry clock signal CR_CK1 may overlap with the gate-on voltage period of the first scan clock signal SC_CK1, and may be longer than the gate-on voltage period of the first scan clock signal SC_CK1. The gate-on voltage period of the second carry clock signal CR_CK2 may overlap with the gate-on voltage period of the second scan clock signal SC_CK2, and may be longer than the gate-on voltage period of the second scan clock signal SC_CK2.

[0101] A gate-on voltage and a gate-off voltage of each of the first gate clock signal GCK1 and the second gate clock signal GCK2 may be alternately input in the display period DP, and the gate-off voltage may be input in the vertical blank period VBP.

[0102] The first control signal S1 may be input to the first control signal terminal SN1. The first control signal S1 may be selectively supplied as a gate-on voltage to the stages corresponding to the rows on which sensing is to be performed in the corresponding frame, so that the sensing node M (eg, reference 1 to FIG. 1 ) of each of the stages is Figure 7 ) can be charged.

[0103] The second control signal S2 may be input to the second control signal terminal SN2. When the second control signal S2 is supplied as a gate-on voltage, the voltage of the sensing node M charged by the first control signal S1 may be supplied to the first control node Q in each of the stages ST1 to STn (eg, see Figure 7 ).

[0104] The third control signal S3 may be input to the third control signal terminal SN3. When an operation error of the display device occurs, the third control signal S3 may be supplied as a gate-on voltage to each specific time of the stages ST1 to STn, so that the second control node QB (for example, see Figure 7 ) may be set to a first level voltage. The third control signal S3 may be a reset signal for changing the gate signal to a gate-off voltage for inactivating the transistor.

[0105] The gate signal may be output from the first output terminal OUT1. The gate signals GS[1], GS[2], GS[3], ..., GS[n] output from the first output terminals OUT1 of the stages ST1 to STn may be sequentially shifted by a specific period. Each gate signal may be supplied to a pixel through a corresponding gate line.

[0106] The carry signal may be output from the second output terminal OUT2. The carry signals CR[1], CR[2], CR[3], ..., CR[n] output from the second output terminals OUT2 of the stages ST1 to STn may be sequentially shifted by a specific period. The carry signal may be supplied to the first input terminal IN1 of the next stage and the second input terminal IN2 of the previous stage.

[0107] Although not shown in the drawings, the gate driving circuit 130 a may further include at least one previous dummy stage before the first stage ST1 and at least one next dummy stage after the nth stage STn.

[0108] The previous dummy stage may generate a carry signal in response to the start signal STV and output the carry signal to the next stage. For example, the gate driving circuit 130a may include one previous dummy stage, and the previous dummy stage may generate a carry signal in response to the start signal STV and supply the generated carry signal to the first input terminal IN1 of the first stage ST1.

[0109] The next dummy stage may receive the carry signal output from the previous stage as a start signal, generate a carry signal, and output the generated carry signal to the previous stage. For example, the gate drive circuit 130a may include two next dummy stages, and the next dummy stage may generate a carry signal in response to the carry signal input from the previous stage (e.g., the n-1th stage and the nth stage STn) and supply the generated carry signal to the second input terminal IN2 of each of the n-1th stage and the nth stage STn.

[0110] Figure 7 is a circuit diagram showing an example of stages included in a gate driving circuit according to an embodiment. Fig. 8A and Figure 8B is shown for explanation Figure 7 Diagram of the stage drive signal.

[0111] Each of the stages ST1 to STn has a plurality of nodes, and hereinafter, some of the plurality of nodes are referred to as a sensing node M, a first control node Q, and a second control node QB. In an embodiment, a plurality of transistors included in each of the first stage ST1 to the nth stage STn may be an N-type thin film transistor. The N-type thin film transistor may be an oxide thin film transistor. hereinafter, a high level may be represented as a first level, and a low level may be represented as a second level.

[0112] In odd-numbered stages, the first carry clock signal CR_CK1 may be supplied to the carry clock terminal CCLK, the first scan clock signal SC_CK1 may be supplied to the scan clock terminal SCLK, and the first gate clock signal GCK1 may be supplied to the gate clock terminal GCLK. In even-numbered stages, the second carry clock signal CR_CK2 may be supplied to the carry clock terminal CCLK, the second scan clock signal SC_CK2 may be supplied to the scan clock terminal SCLK, and the second gate clock signal GCK2 may be supplied to the gate clock terminal GCLK.

[0113] Hereinafter, the kth stage STk corresponding to the kth row of the pixel portion 110 will be described as an example. The kth stage STk may receive the k-1th carry signal CR[k-1] as a start signal from the k-1th stage as the previous stage, and output the kth gate signal GS[k] to the gate line of the kth row. For ease of description, an example will be described in which the kth stage STk is an odd-numbered stage, the first carry clock signal CR_CK1 is supplied to the carry clock terminal CCLK, the first scan clock signal SC_CK1 is supplied to the scan clock terminal SCLK, and the first gate clock signal GCK1 is supplied to the gate clock terminal GCLK. When k is 1, the first stage ST1 may receive the start signal STV through the first input terminal IN.

[0114] For the convenience of the following description, supplying any signal means supplying a gate-on voltage (e.g., a first-level voltage) as a high-level voltage, and not supplying a signal means supplying a gate-off voltage (e.g., a second-level voltage) as a low-level voltage. The first voltage VGH may be a first-level voltage, and the second voltage VGL1 and the third voltage VGL2 may both be second-level voltages.

[0115] The kth stage STk may include a first controller 131 , a second controller 133 , a first output part 135 , and a second output part 137 .

[0116] The first controller 131 may control the voltage of the first control node Q and the voltage of the second control node QB in response to the signal input through the first input terminal IN1, the second input terminal IN2, the gate clock terminal GCLK, and the third control signal terminal SN3. For example, the first controller 131 may control the voltage of the first control node Q and the voltage of the second control node QB in response to the previous carry signal CR[k-1], the next carry signal CR[k+2], the first gate clock signal GCK1, and the third control signal S3.

[0117] The first controller 131 may include first to sixth transistors T1 to T6 .

[0118] The first transistor T1 may be connected between the first input terminal IN1 and the first control node Q. The first transistor T1 may include a plurality of sub-transistors connected in series. The sub-transistor may include a pair of transistors (i.e., a 1-1 transistor T1-1 and a 1-2 transistor T1-2). The gates of the 1-1 transistor T1-1 and the 1-2 transistor T1-2 may be connected to the gate clock terminal GCLK. The 1-1 transistor T1-1 and the 1-2 transistor T1-2 may be turned on when the first gate clock signal GCK1 is supplied, and the voltage of the first control node Q may be set to the voltage of the previous carry signal CR[k-1].

[0119] The second transistor T2 may be connected between the second control node QB and the third voltage input terminal V3. The second transistor T2 may include a plurality of sub-transistors connected in series. The sub-transistor may include a pair of transistors (i.e., a 2-1 transistor T2-1 and a 2-2 transistor T2-2). The gates of the 2-1 transistor T2-1 and the 2-2 transistor T2-2 may be connected to the first control node Q. The 2-1 transistor T2-1 and the 2-2 transistor T2-2 may be turned on when the first control node Q is at a first level voltage, and therefore, the voltage of the second control node QB may be set to the third voltage VGL2.

[0120] The third transistor T3 may be connected between the first voltage input terminal V1 and the intermediate node (common electrode) between the 2-1st transistor T2-1 and the 2-2nd transistor T2-2. The gate of the third transistor T3 may be connected to the second control node QB. The third transistor T3 may be turned on when the second control node QB is at a first level voltage, and therefore, the voltage of the intermediate node between the 2-1st transistor T2-1 and the 2-2nd transistor T2-2 may be set to the first voltage VGH.

[0121] The fourth transistor T4 may be connected between the first voltage input terminal V1 and the second control node QB. The fourth transistor T4 may include a plurality of sub-transistors connected in series. The sub-transistor may include a pair of transistors (i.e., a 4-1 transistor T4-1 and a 4-2 transistor T4-2). The gates of the 4-1 transistor T4-1 and the 4-2 transistor T4-2 may be connected to the second input terminal IN2. The 4-1 transistor T4-1 and the 4-2 transistor T4-2 may be turned on when the next carry signal CR[k+2] of the first level voltage is supplied, and therefore, the voltage of the second control node QB may be set to the first voltage VGH.

[0122] The fifth transistor T5 may be connected between the first voltage input terminal V1 and the second control node QB. The fifth transistor T5 may include a plurality of sub-transistors connected in series. The sub-transistor may include a pair of transistors (i.e., the 5-1 transistor T5-1 and the 5-2 transistor T5-2). The gates of the 5-1 transistor T5-1 and the 5-2 transistor T5-2 may be connected to the third control signal terminal SN3. The 5-1 transistor T5-1 and the 5-2 transistor T5-2 may be turned on when the third control signal S3 is supplied, and the voltage of the second control node QB may be set to the first voltage VGH.

[0123] The sixth transistor T6 may be between the first voltage input terminal V1 and an intermediate node (common electrode) H between the 1-1st transistor T1-1 and the 1-2nd transistor T1-2. A gate of the sixth transistor T6 may be connected to the first control node Q. The sixth transistor T6 may be turned on when the first control node Q is at a first level voltage, and thus, the intermediate node H between the 1-1st transistor T1-1 and the 1-2nd transistor T1-2 may be set to the first voltage VGH.

[0124] The second controller 133 may supply the first voltage VGH to the first control node Q and the third voltage VGL2 to the second control node QB to sense state information of the pixel PX.

[0125] The second controller 133 may control the voltage of the first control node Q and the voltage of the second control node QB in response to the signals input to the first control signal terminal SN1 and the second control signal terminal SN2. For example, the second controller 133 may control the voltage of the first control node Q and the voltage of the second control node QB in response to the first control signal S1 and the second control signal S2. The second controller 133 may include seventh to ninth transistors T7 to T9 and a first capacitor C1.

[0126] The first control signal S1 may be a signal supplied at any timing during the display period DP. For example, the first control signal S1 may be supplied at the output timing of the k-th carry signal CR[k]. The k-th carry signal CR[k] may be a signal supplied during the display period DP to charge the sensing node M for pixel sensing. The second control signal S2 may be a signal supplied during the vertical blank period VBP to supply the first voltage VGH to the first control node Q for pixel sensing.

[0127] The seventh transistor T7 may be connected between the sensing node M and the second output terminal OUT2. The seventh transistor T7 may be turned on by the first control signal S1 synchronized with the carry signal output from the second output portion 137. The seventh transistor T7 may include a plurality of sub-transistors connected in series. The sub-transistor may include a pair of transistors (i.e., the 7-1st transistor T7-1 and the 7-2nd transistor T7-2). The gates of the 7-1st transistor T7-1 and the 7-2nd transistor T7-2 may be connected to the first control signal terminal SN1. The 7-1st transistor T7-1 and the 7-2nd transistor T7-2 may be turned on when the first control signal S1 is supplied, and therefore, the voltage of the sensing node M may be set to the voltage of the kth carry signal CR[k].

[0128] The eighth transistor T8 may be connected between the intermediate node (common electrode) between the 7-1st transistor T7-1 and the 7-2nd transistor T7-2 and the first control node Q. The eighth transistor T8 may include a plurality of sub-transistors connected in series. The sub-transistor may include a pair of transistors (i.e., the 8-1st transistor T8-1 and the 8-2nd transistor T8-2). The gates of the 8-1st transistor T8-1 and the 8-2nd transistor T8-2 may be connected to the second control signal terminal SN2. The 8-1st transistor T8-1 and the 8-2nd transistor T8-2 may be turned on when the second control signal S2 is supplied, and therefore, the intermediate node between the 7-1st transistor T7-1 and the 7-2nd transistor T7-2 may be electrically connected to the first control node Q. The intermediate node (common electrode) H between the 8-1st transistor T8-1 and the 8-2nd transistor T8-2 may be connected to the intermediate node H between the 1-1st transistor T1-1 and the 1-2nd transistor T1-2, and therefore may be set to the first voltage VGH transmitted by the sixth transistor T6. Therefore, when the eighth transistor T8 is turned off, a voltage drop of the first control node Q due to a leakage current of the eighth transistor T8 can be prevented.

[0129] The ninth transistor T9 may be connected between the first voltage input terminal V1 and an intermediate node between the 7-1st transistor T7-1 and the 7-2nd transistor T7-2. A gate of the ninth transistor T9 may be connected to the sensing node M. The ninth transistor T9 may be turned on when the sensing node M is at a first level voltage, and thus a voltage of an intermediate node between the 7-1st transistor T7-1 and the 7-2nd transistor T7-2 may be set to a first voltage VGH.

[0130] The first capacitor C1 may be connected between the first voltage input terminal V1 and the sensing node M. When the sensing node M is set to the first level voltage of the kth carry signal CR[k], the first capacitor C1 may store a difference between the first voltage VGH and a voltage of the gate of the ninth transistor T9.

[0131] The first output part 135 may output the first scan clock signal SC_CK1 or the second voltage VGL1 to the first output terminal OUT1 according to the voltages of the first and second control nodes Q and QB. The first output part 135 may include tenth and eleventh transistors T10 and T11 connected between the scan clock terminal SCLK and the second voltage input terminal V2.

[0132] The tenth transistor T10 may be connected between the scan clock terminal SCLK and the first output terminal OUT1. The gate of the tenth transistor T10 may be connected to the first control node Q. The tenth transistor T10 may be a pull-up transistor that transmits a first level voltage to the output terminal. The tenth transistor T10 may be turned on or off in response to the voltage of the first control node Q. The tenth transistor T10 may be turned on when the voltage of the first control node Q is set to a first level voltage, and thus may output a first level voltage of the first scan clock signal SC_CK1 as a first level voltage of the kth gate signal GS[k] or output a second level voltage of the first scan clock signal SC_CK1 as a second level voltage of the kth gate signal GS[k].

[0133] The eleventh transistor T11 may be connected between the first output terminal OUT1 and the second voltage input terminal V2. The gate of the eleventh transistor T11 may be connected to the second control node QB. The eleventh transistor T11 may be a pull-down transistor that transmits a second level voltage to the output terminal. The eleventh transistor T11 may be turned on or off in response to the voltage of the second control node QB. The eleventh transistor T11 may be turned on when the voltage of the second control node QB is set to the first level voltage, and thus may output the second voltage VGL1 as the second level voltage of the kth gate signal GS[k].

[0134] The second output portion 137 may output the first carry clock signal CR_CK1 or the third voltage VGL2 to the second output terminal OUT2 according to the voltages of the first control node Q and the second control node QB. The second output portion 137 may include a twelfth transistor T12 and a thirteenth transistor T13 connected between the carry clock terminal CCLK and the third voltage input terminal V3. The second output portion 137 may also include a second capacitor C2.

[0135] The twelfth transistor T12 may be connected between the carry clock terminal CCLK and the second output terminal OUT2. The gate of the twelfth transistor T12 may be connected to the first control node Q. The twelfth transistor T12 may be a pull-up transistor that transmits a first level voltage to the output terminal. The twelfth transistor T12 may be turned on or off in response to the voltage of the first control node Q. The twelfth transistor T12 may be turned on when the voltage of the first control node Q is set to a first level voltage, and thus may output the first level voltage of the first carry clock signal CR_CK1 as the first level voltage of the kth carry signal CR[k] or output the second level voltage of the first carry clock signal CR_CK1 as the second level voltage of the kth carry signal CR[k].

[0136] The thirteenth transistor T13 may be connected between the second output terminal OUT2 and the third voltage input terminal V3. The gate of the thirteenth transistor T13 may be connected to the second control node QB. The thirteenth transistor T13 may be a pull-down transistor that transmits a second level voltage to the output terminal. The thirteenth transistor T13 may be turned on or off in response to the voltage of the second control node QB. The thirteenth transistor T13 may be turned on when the second control node QB is set to the first level voltage, and thus may output the third voltage VGL2 as the second level voltage of the k-th carry signal CR[k].

[0137] The second capacitor C2 may be connected between the first control node Q and the second output terminal OUT2. The twelfth transistor T12 may be turned on when the voltage of the first control node Q is at the first voltage, and the first carry clock signal CR_CK1 may output a first level voltage as the k-th carry signal CR[k]. In this case, the voltage of the first control node Q may be increased by the second capacitor C2.

[0138] In the following, reference will be made to Fig. 8A and Figure 8B The operation of the kth stage STk is described, and this can be applied to the operations of other stages as well. A case in which the third control signal S3 is supplied with the second voltage will be described as an example.

[0139] Fig. 8A The operation of the kth stage STk in the display period DP is shown.

[0140] In the first period P1, a previous carry signal CR[k-1] of a first level voltage from a k-1th stage as a previous stage may be supplied, and a next carry signal CR[k+2] of a second level voltage from a k+2th stage as a next stage may be supplied. In addition, a first gate clock signal GCK1 of a first level voltage may be supplied, and a first scan clock signal SC_CK1 of a second level voltage and a first carry clock signal CR_CK1 of a second level voltage may be supplied.

[0141] The first transistor T1 may be turned on by the first gate clock signal GCK1 having a first level voltage, and the voltage of the first control node Q may be set to the first level voltage of the previous carry signal CR[k-1]. Therefore, the tenth transistor T10 may be turned on, and thus the second level voltage of the first scan clock signal SC_CK1 may be output from the first output terminal OUT1 as the kth gate signal GS[k]. In addition, the twelfth transistor T12 may be turned on, and thus the second level voltage of the first carry clock signal CR_CK1 may be output from the second output terminal OUT2 as the kth carry signal CR[k].

[0142] The second transistor T2 having its gate connected to the first control node Q having the first level voltage may be turned on, and the voltage of the second control node QB may be set to the second level voltage of the third voltage VGL2. Therefore, the eleventh transistor T11 and the thirteenth transistor T13 may be turned off.

[0143] In the second period P2, the previous carry signal CR[k-1] of the second level voltage can be supplied, the next carry signal CR[k+2] of the second level voltage can be supplied, the first gate clock signal GCK1 of the second level voltage can be supplied, and the first scan clock signal SC_CK1 of the first level voltage and the first carry clock signal CR_CK1 of the first level voltage can be supplied.

[0144] The first transistor T1 may be turned off by the first gate clock signal GCK1 having the second level voltage, and the first control node Q may be maintained at the first level voltage. The first level voltage of the first scan clock signal SC_CK1 may be output from the first output terminal OUT1 as the kth gate signal GS[k] through the turned-on tenth transistor T10. In addition, the first level voltage of the first carry clock signal CR_CK1 may be output from the second output terminal OUT2 as the kth carry signal CR[k] through the turned-on twelfth transistor T12. In this case, the voltage of the first control node Q may be increased to a voltage higher than the voltage in the first period P1 through the second capacitor C2.

[0145] The sixth transistor T6 whose gate is connected to the first control node Q can be turned on, and the first voltage VGH can be transmitted to the intermediate node H between the 1-1 transistor T1-1 and the 1-2 transistor T1-2, thereby preventing the voltage drop in the first control node Q caused by the leakage current of the turned-off 1-1 transistor T1-1 and the 1-2 transistor T1-2.

[0146] The voltage of the second control node QB may be maintained at the second level voltage of the third voltage VGL2 .

[0147] In the third period P3, the previous carry signal CR[k-1] of the second level voltage can be supplied, the next carry signal CR[k+2] of the second level voltage can be supplied, the first gate clock signal GCK1 of the first level voltage can be supplied, and the first scan clock signal SC_CK1 of the second level voltage and the first carry clock signal CR_CK1 of the second level voltage can be supplied.

[0148] The first transistor T1 can be turned on by the first gate clock signal GCK1 having a first level voltage, and the voltage of the first control node Q can be set to the second level voltage of the previous carry signal CR[k-1]. Therefore, the tenth transistor T10, the twelfth transistor T12 and the second transistor T2 can be turned off. Because the voltage of the first control node Q and the voltage of the second control node QB are the second level voltages, the kth gate signal GS[k] of the second level voltage and the kth carry signal CR[k] of the second level voltage can be output.

[0149] In the fourth period P4, the previous carry signal CR[k-1] of the second level voltage can be supplied, the next carry signal CR[k+2] of the first level voltage can be supplied, the first gate clock signal GCK1 of the second level voltage can be supplied, and the first scan clock signal SC_CK1 of the first level voltage and the first carry clock signal CR_CK1 of the first level voltage can be supplied.

[0150] The first transistor T1 may be turned off by the first gate clock signal GCK1 having the second level voltage, and the voltage of the first control node Q may be maintained at the second level voltage.

[0151] The fourth transistor T4 can be turned on by the next carry signal CR[k+2] having the first level voltage, and the voltage of the second control node QB can be set to the first voltage VGH by the turned-on fourth transistor T4. Therefore, the eleventh transistor T11 and the thirteenth transistor T13 can be turned on. The second voltage VGL1 can be output from the first output terminal OUT1 as the kth gate signal GS[k] by the turned-on eleventh transistor T11. In addition, the third voltage VGL2 can be output from the second output terminal OUT2 as the kth carry signal CR[k] by the turned-on thirteenth transistor T13.

[0152] The third transistor T3 whose gate is connected to the second control node QB can be turned on, and the first voltage VGH can be transmitted to the intermediate node between the 2-1 transistor T2-1 and the 2-2 transistor T2-2, so the voltage of the second control node QB can be stably maintained by blocking the leakage current caused by the turned-off 2-1 transistor T2-1 and the 2-2 transistor T2-2.

[0153] The k-th carry signal CR[k] and the first control signal S1 may be supplied to the second controller 133 during the display period DP. The seventh transistor T7 may be turned on when the first control signal S1 is supplied, the first level voltage of the k-th carry signal CR[k] may be supplied to the sensing node M, and the first capacitor C1 may be charged. The ninth transistor T9 having a gate connected to the sensing node M may be turned on.

[0154] Figure 8B 1 shows the operation of the kth stage STk in the vertical blank period VBP. During the sensing period SP of the vertical blank period VBP, a first carry clock signal CR_CK1 of a first level voltage may be supplied, a first gate clock signal GCK1 of a second level voltage and a second gate clock signal GCK2 of a second level voltage may be supplied, and a first scan clock signal SC_CK1 of a first level voltage may be supplied. When the stage connected to the pixel to be sensed is an even-numbered stage, a second carry clock signal CR_CK2 of a first level voltage and a second scan clock signal SC_CK2 of a first level voltage may be supplied.

[0155] The second control signal S2 may be supplied to the second controller 133, and the voltage of the first control node Q may be set to the first voltage VGH by the ninth transistor T9 turned on when its gate is connected to the sensing node M having the first level voltage and the eighth transistor T8 turned on by the second control signal S2. Therefore, the tenth transistor T10 and the twelfth transistor T12 may be turned on. The second level voltage of the first scan clock signal SC_CK1 may be output from the first output terminal OUT1 as the kth gate signal GS[k] by the turned-on tenth transistor T10. In addition, the second level voltage of the first carry clock signal CR_CK1 may be output from the second output terminal OUT2 as the kth carry signal CR[k] by the turned-on twelfth transistor T12. When the carry clock signal having the first level voltage is input to the second output portion 137 to which the second capacitor C2 is connected in the sensing period SP, the voltage of the first control node Q may be increased by the second capacitor C2, and thus the gate signal may be stably output.

[0156] The clock signal having the first level voltage (ie, the carry clock signal and the scan clock signal) may be supplied after any point in time when the second control signal S2 is supplied. Figure 8B An example is shown in which a clock signal having a first level voltage is input at an arbitrary time point after the first control node Q is set to the first voltage VGH.

[0157] The second transistor M2 and the third transistor M3 of the pixel PX receiving the kth gate signal GS[k] may be turned on, thereby sensing the first transistor M1 and the organic light emitting diode OLED (eg, see Figure 2 ) status information.

[0158] Fig. 9 is a schematic diagram of a gate driving circuit 130 b according to an embodiment. Fig.10 yes Fig. 9 Schematic diagram of one stage of the gate drive circuit 130b shown in FIG. Fig.11is a circuit diagram showing an example of stages included in a gate driving circuit according to an embodiment. Fig.12 is shown for explanation Fig.11 Diagram of the stage drive signal.

[0159] Figures 9 to 11 The plurality of stages ST1 to STn of the gate driving circuit 130b shown in FIG. Figure 4 and Figure 5 The gate driving circuit 130 a shown in FIG. 1 is different in that the first carry clock signal CR_CK1 or the second carry clock signal CR_CK2 is input to the gate clock terminal GCLK.

[0160] like Figures 9 to 11 As shown in , in the odd-numbered stages ST1, ST3, ..., the first carry clock signal CR_CK1 may be input to the carry clock terminal CCLK, the first scan clock signal SC_CK1 may be input to the scan clock terminal SCLK, and the second carry clock signal CR_CK2 may be input to the gate clock terminal GCLK. In the even-numbered stages ST2, ST4, ..., the second carry clock signal CR_CK2 may be input to the carry clock terminal CCLK, the second scan clock signal SC_CK2 may be input to the scan clock terminal SCLK, and the first carry clock signal CR_CK1 may be input to the gate clock terminal GCLK.

[0161] Fig.12 The operation of the kth stage STk in the display period DP is shown. Fig.12 , the first gate clock signal GCK1 and the second gate clock signal GCK2 are omitted, and in one cycle of each of the first carry clock signal CR_CK1 and the second carry clock signal CR_CK2, the gate-on voltage period may be equal to the gate-off voltage period. In an embodiment, the second carry clock signal CR_CK2 may be an inverted signal of the first carry clock signal CR_CK1.

[0162] like Fig.12 As shown in FIG. 1 , the gate-on voltage period of the first scan clock signal SC_CK1 and the second scan clock signal SC_CK2 can be compared to Fig. 8A The gate-on voltage periods of the first scan clock signal SC_CK1 and the second scan clock signal SC_CK2 shown in FIG. 5 are short.

[0163] In addition, according to Fig.12 The operation of the kth stage STk in the display period DP of the timing of the signals shown in Fig. 8A The operation of the kth stage STk in the display period DP of the timing of the signals shown in is the same. Figure 8BThe timings of the signals shown in can be equally applied to the operation of the kth stage STk in the vertical blank period VBP.

[0164] According to the present embodiment, since the first and second gate clock signals GCK1 and GCK2 may be omitted, there is no need to provide wires for inputting the first and second gate clock signals GCK1 and GCK2 , and an ineffective space may be reduced by reducing an area of ​​a gate driving circuit.

[0165] Fig.13 is a schematic diagram of a gate driving circuit 130c according to an embodiment. Fig.14 yes Fig.13 Schematic diagram of one stage of the gate drive circuit 130c shown in FIG. Fig.15 is a circuit diagram showing an example of stages included in a gate driving circuit according to an embodiment. Figures 16 to 18 is shown for explanation Fig.15 In the following, the following will mainly describe the signal of the drive of the level. Figures 3 to 12 The construction described is different from the construction.

[0166] Each of the plurality of stages ST1 to STn of the gate driving circuit 130c according to the embodiment may generate two or more gate signals corresponding to two or more rows, and output the generated two or more gate signals to two or more gate lines corresponding thereto. Fig.13 As shown in , each of the plurality of stages ST1 to STn may generate four gate signals and sequentially output the four gate signals to four gate lines of corresponding four rows. In this case, the number of stages may be 1 / 4 of the number of rows (horizontal lines) provided in the pixel portion 110.

[0167] Reference Fig.13 and Fig.14 Each of the multiple stages ST1 to STn of the gate driving circuit 130c may include a first input terminal IN1, a second input terminal IN2, a first voltage input terminal V1, a second voltage input terminal V2, a third voltage input terminal V3, a first carry clock terminal CCLK1, a second carry clock terminal CCLK2, a third carry clock terminal CCLK3, a scan clock terminal SCLK, a first control signal terminal SN1, a second control signal terminal SN2, a third control signal terminal SN3, a fourth control signal terminal SN4, a first output terminal OUT1, and a second output terminal OUT2.

[0168] A plurality of first output terminals OUT1 may be arranged to output a plurality of gate signals. For example, each stage may include a 1-1 output terminal OUT11 to a 1-4 output terminal OUT14 to output four gate signals. The first output terminal OUT1 may include a 1-1 output terminal OUT11, a 1-2 output terminal OUT12, a 1-3 output terminal OUT13, and a 1-4 output terminal OUT14. A plurality of scan clock terminals SCLK may be arranged to correspond to the plurality of first output terminals OUT1. For example, each stage may include a first scan clock terminal SCLK1 to a fourth scan clock terminal SCLK4. The second output terminal OUT2 may include a 2-1 output terminal OUT21 that outputs a carry signal to the next stage and a 2-2 output terminal OUT22 that outputs a carry signal to the previous stage.

[0169] Each of the plurality of stages ST1 to STn may generate a lower carry signal (first carry signal) and supply the lower carry signal to the first input terminal IN1 of the next stage, and may generate an upper carry signal (second carry signal) and supply the upper carry signal to the second input terminal IN2 of the previous stage. Fig.14 As shown in , the k-1th carry signal CR_D[k-1] output from the 2-1 output terminal OUT21 of the k-1th stage can be input to the first input terminal IN1 of the kth stage STk. The k+1th carry signal CR_U[k+1] output from the 2-2 output terminal OUT22 of the k+1th stage can be input to the second input terminal IN2 of the kth stage STk.

[0170] The first voltage VGH may be input to the first voltage input terminal V1 , the second voltage VGL1 may be input to the second voltage input terminal V2 , and the third voltage VGL2 may be input to the third voltage input terminal V3 .

[0171] The driving carry clock signal may be input to the first carry clock terminal CCLK1. The driving carry clock signal may include a first driving carry clock signal CR_CK_D and a second driving carry clock signal CR_CKB_D. The first driving carry clock signal CR_CK_D or the second driving carry clock signal CR_CKB_D may be input to the first carry clock terminal CCLK1. The first driving carry clock signal CR_CK_D and the second driving carry clock signal CR_CKB_D may be alternately input to the first carry clock terminal CCLK1 of the stages ST1 to STn. For example, the first driving carry clock signal CR_CK_D may be input to the first carry clock terminal CCLK1 of the odd-numbered stages ST1, ST3, ... For example, the second driving carry clock signal CR_CKB_D may be input to the first carry clock terminal CCLK1 of the even-numbered stages ST2, ST4, ...

[0172] The first drive carry clock signal CR_CK_D and the second drive carry clock signal CR_CKB_D may be square wave signals that repeat a high level voltage and a low level voltage. The first drive carry clock signal CR_CK_D and the second drive carry clock signal CR_CKB_D may have the same waveform and may be a phase shift signal. For example, the second drive carry clock signal CR_CKB_D may have the same waveform as the first drive carry clock signal CR_CK_D and may be input by phase shifting (phase delay) at a specific interval. The second drive carry clock signal CR_CKB_D may be shifted by half a cycle from the first drive carry clock signal CR_CK_D. The gate-on voltage period of each of the first drive carry clock signal CR_CK_D and the second drive carry clock signal CR_CKB_D may be set to be longer than its gate-off voltage period in one cycle. However, the disclosure is not limited thereto, and the gate-on voltage period of each of the first drive carry clock signal CR_CK_D and the second drive carry clock signal CR_CKB_D may be equal to or shorter than its gate-off voltage period in one cycle. A gate-on voltage of each of the first driving carry clock signal CR_CK_D and the second driving carry clock signal CR_CKB_D may be 18 V, and a gate-off voltage thereof may be −10 V. However, the disclosure is not limited thereto.

[0173] A gate-on voltage and a gate-off voltage of each of the first and second driving carry clock signals CR_CK_D and CR_CKB_D may be alternately input in the display period DP, and a gate-off voltage of each of the first and second driving carry clock signals CR_CK_D and CR_CKB_D may be input in the vertical blank period VBP.

[0174] The switch carry clock signal may be input to the second carry clock terminal CCLK2. The switch carry clock signal may include a first switch carry clock signal CR_CK_SW and a second switch carry clock signal CR_CKB_SW. The first switch carry clock signal CR_CK_SW or the second switch carry clock signal CR_CKB_SW may be input to the second carry clock terminal CCLK2. The first switch carry clock signal CR_CK_SW and the second switch carry clock signal CR_CKB_SW may be alternately input to the second carry clock terminal CCLK2 of the stages ST1 to STn. For example, the first switch carry clock signal CR_CK_SW may be input to the second carry clock terminal CCLK2 of the odd-numbered stages ST1, ST3, ... The second switch carry clock signal CR_CKB_SW may be input to the second carry clock terminal CCLK2 of the even-numbered stages ST2, ST4, ...

[0175] The first switching carry clock signal CR_CK_SW or the second switching carry clock signal CR_CKB_SW may be input to the third carry clock terminal CCLK3. The second switching carry clock signal CR_CKB_SW and the first switching carry clock signal CR_CK_SW may be alternately input to the third carry clock terminal CCLK3 of the stages ST1 to STn. For example, the second switching carry clock signal CR_CKB_SW may be input to the third carry clock terminal CCLK3 of the odd-numbered stages ST1, ST3, ... The first switching carry clock signal CR_CK_SW may be input to the third carry clock terminal CCLK3 of the even-numbered stages ST2, ST4, ...

[0176] The first switch carry clock signal CR_CK_SW and the second switch carry clock signal CR_CKB_SW may be square wave signals that repeat a high level voltage and a low level voltage. The first switch carry clock signal CR_CK_SW and the second switch carry clock signal CR_CKB_SW may have the same waveform and may be a phase shift signal. For example, the second switch carry clock signal CR_CKB_SW may have the same waveform as the first switch carry clock signal CR_CK_SW and may be input with a phase shift (phase delay) at a specific interval. The second switch carry clock signal CR_CKB_SW may be shifted by half a cycle from the first switch carry clock signal CR_CK_SW. The gate-on voltage period of each of the first switch carry clock signal CR_CK_SW and the second switch carry clock signal CR_CKB_SW may be set to be shorter than its gate-off voltage period in one cycle. However, the disclosure is not limited thereto, and the gate-on voltage period of each of the first switch carry clock signal CR_CK_SW and the second switch carry clock signal CR_CKB_SW may be set to be equal to or longer than its gate-off voltage period in one cycle. The gate-on voltage of the first switching carry clock signal CR_CK_SW and the second switching carry clock signal CR_CKB_SW may be 20 V, and the gate-off voltage thereof may be −12 V. However, the disclosure is not limited thereto.

[0177] A gate-on voltage and a gate-off voltage of each of the first and second switching carry clock signals CR_CK_SW and CR_CKB_SW may be alternately input in the display period DP, and a gate-off voltage of each of the first and second switching carry clock signals CR_CK_SW and CR_CKB_SW may be input in the vertical blank period VBP.

[0178] The period during which the first drive carry clock signal CR_CK_D is at the gate-on voltage may overlap with the period during which the first switch carry clock signal CR_CK_SW is at the gate-on voltage. The period during which the second drive carry clock signal CR_CKB_D is at the gate-on voltage may overlap with the period during which the second switch carry clock signal CR_CKB_SW is at the gate-on voltage. The period during which the first switch carry clock signal CR_CK_SW is at the gate-on voltage may be shorter than the period during which the first drive carry clock signal CR_CK_D is at the gate-on voltage. The period during which the second switch carry clock signal CR_CKB_SW is at the gate-on voltage may be shorter than the period during which the second drive carry clock signal CR_CKB_D is at the gate-on voltage.

[0179] Each of the plurality of stages ST1 to STn may include a plurality of scan clock terminals. One of the plurality of scan clock signals SC_CK may be input to each of the plurality of scan clock terminals. Each of the plurality of stages ST1 to STn may include i scan clock terminals and may receive i scan clock signals SC_CK among 2i scan clock signals SC_CK. Here, i may be an integer greater than or equal to 2.

[0180] In an embodiment, each stage may include a first scan clock terminal SCLK1 to a fourth scan clock terminal SCLK4, and four scan clock signals among the first scan clock signal SC_CK1 to the eighth scan clock signal SC_CK8 may be respectively input to the first scan clock terminal SCLK1 to the fourth scan clock terminal SCLK4. For example, the first scan clock signal SC_CK1 to the fourth scan clock signal SC_CK4 may be sequentially input to the first scan clock terminal SCLK1 to the fourth scan clock terminal SCLK4 of the odd-numbered stages ST1, ST3, ... The fifth scan clock signal SC_CK5 to the eighth scan clock signal SC_CK8 may be sequentially input to the first scan clock terminal SCLK1 to the fourth scan clock terminal SCLK4 of the even-numbered stages ST2, ST4, ...

[0181] The eight first scan clock signals SC_CK1 to the eighth scan clock signal SC_CK8 may be square wave signals that repeat a high level voltage and a low level voltage. The first scan clock signal SC_CK1 to the eighth scan clock signal SC_CK8 may have the same waveform and may be a phase shift signal. The phases of the first scan clock signal SC_CK1 to the eighth scan clock signal SC_CK8 may be sequentially shifted so that their gate-on voltage periods partially overlap with each other and are supplied to the gate drive circuit 130c. The gate-on voltage period of each of the first scan clock signal SC_CK1 to the eighth scan clock signal SC_CK8 may be set to be shorter than its gate-off voltage period in one cycle. However, the disclosure is not limited thereto, and the gate-on voltage period of each of the first scan clock signal SC_CK1 to the eighth scan clock signal SC_CK8 may be set to be equal to or longer than its gate-off voltage period in one cycle. The gate-on voltage of each of the first scan clock signal SC_CK1 to the eighth scan clock signal SC_CK8 may be 20V, and the gate-off voltage thereof may be -5V. However, the disclosure is not limited thereto.

[0182] A gate-on voltage and a gate-off voltage of each of the first to eighth scan clock signals SC_CK1 to SC_CK8 may be alternately input in the display period DP, and a gate-on voltage of each of the first to eighth scan clock signals SC_CK1 to SC_CK8 may be input in the sensing period SP.

[0183] The gate-on voltage period of the first driving carry clock signal CR_CK_D may overlap with the gate-on voltage period of the first to fourth scanning clock signals SC_CK1 to SC_CK4. Fig.16 As shown in , the first scan clock signal SC_CK1 to the fourth scan clock signal SC_CK4 can sequentially have a gate-on voltage in the gate-on voltage period of the first drive carry clock signal CR_CK_D. The fourth scan clock signal SC_CK4 to the eighth scan clock signal SC_CK8 can sequentially have a gate-on voltage in the gate-on voltage period of the second drive carry clock signal CR_CKB_D. Therefore, a plurality of gate signals can be stably output in response to a plurality of scan clock signals in one stage.

[0184] The first control signal S1 may be input to the first control signal terminal SN1. The second control signal S2 may be input to the second control signal terminal SN2. The third control signal S3 may be input to the third control signal terminal SN3.

[0185] The fourth control signal S4 may be input to the fourth control signal terminal SN4. The fourth control signal S4 may be supplied to discharge (reset) the voltage of the first control node Q before and / or after the sensing period SP in the vertical blank period VBP.

[0186] Each of the plurality of stages ST1 to STn may include a plurality of first output terminals, and may sequentially shift and output a plurality of gate signals at a specific period. The number of first output terminals may be the same as the number of scan clock signals input to each stage. For example, four scan clock signals may be input to each of the plurality of stages ST1 to STn, and each stage may include four first output terminals. Fig.14 As shown in, in the kth stage STk, the pth gate signal GS[p] can be output from the 1-1th output terminal OUT11 to the pth gate line, the p+1th gate signal GS[p+1] can be output from the 1-2th output terminal OUT12 to the p+1th gate line, the p+2th gate signal GS[p+2] can be output from the 1-3rd output terminal OUT13 to the p+2th gate line, and the p+3th gate signal GS[p+3] can be output from the 1-4th output terminal OUT14 to the p+3th gate line. Here, p is a positive integer, and p+3 can be 4k.

[0187] Each of the plurality of stages ST1 to STn may include a 2-1st output terminal OUT21 and a 2-2nd output terminal OUT22. A lower carry signal may be output from the 2-1st output terminal OUT21, and an upper carry signal may be output from the 2-2nd output terminal OUT22. Fig.14 As shown in , the k-th down carry signal CR_D[k] may be output from the 2-1 output terminal OUT21 of the k-th stage STk, and the k-th up carry signal CR_U[k] may be output from the 2-2 output terminal OUT22.

[0188] Reference Fig.15 , the kth stage STk may include a first controller 131 ′, a second controller 133 ′, a first output part 135 ′, and a second output part 137 ′.

[0189] The first controller 131' may also include Figure 714th transistor T14 outside the first controller 131 shown in . The fourteenth transistor T14 may be connected between the third control node QC and the first control node Q. The fourteenth transistor T14 may include a plurality of sub-transistors connected in series. The sub-transistor may include a pair of transistors (i.e., the 14-1 transistor T14-1 and the 14-2 transistor T14-2). The gates of the 14-1 transistor T14-1 and the 14-2 transistor T14-2 may be connected to the first voltage input terminal V1. The fourteenth transistor T14 may be turned on by the first voltage VGH applied to the first voltage input terminal V1, and may connect the third control node QC to the first control node Q.

[0190] The fourteenth transistor T14 may be always turned on. The fourteenth transistor T14 may prevent a line voltage drop between nodes to which both terminals of the fourteenth transistor T14 are connected. For example, the fourteenth transistor T14 may prevent a line voltage drop between the third control node QC and the first control node Q.

[0191] The second controller 133' may also include Figure 7 The fifteenth transistor T15 and the sixteenth transistor T16 outside the second controller 133 are shown in FIG.

[0192] The fifteenth transistor T15 may be connected between the third control node QC and the third voltage input terminal V3. The fifteenth transistor T15 may include a plurality of sub-transistors connected in series. The sub-transistor may include a pair of transistors (i.e., the 15-1 transistor T15-1 and the 15-2 transistor T15-2). The gates of the 15-1 transistor T15-1 and the 15-2 transistor T15-2 may be connected to the fourth control signal terminal SN4. The fifteenth transistor T15 may be turned on by the fourth control signal S4 applied to the fourth control signal terminal SN4.

[0193] The sixteenth transistor T16 may be connected between the fifteenth transistor T15 and the third voltage input terminal V3. The gate of the sixteenth transistor T16 may be connected to the sensing node M. The sixteenth transistor T16 may be turned on when the sensing node M is at a first level voltage, and when the fifteenth transistor T15 is turned on when the fourth control signal S4 is supplied, the voltage of the third control node QC and the voltage of the first control node Q may be set to the third voltage VGL2.

[0194] The first output portion 135' may include a plurality of sub-output portions, and one of the plurality of scan clock signals may be input to a scan clock terminal of each of the plurality of sub-output portions. The plurality of scan clock signals may be signals having the same waveform and phase shifted by a specific interval. In an embodiment, the first output portion 135' may include a first sub-output portion 135a, a second sub-output portion 135b, a third sub-output portion 135c, and a fourth sub-output portion 135d. Each of the first sub-output portion 135a, the second sub-output portion 135b, the third sub-output portion 135c, and the fourth sub-output portion 135d may include a tenth transistor and an eleventh transistor.

[0195] The first sub-output portion 135a may include a 10-1 transistor T10a and an 11-1 transistor T11a. The 10-1 transistor T10a may be connected between the first scan clock terminal SCLK1 and the 1-1 output terminal OUT11. The gate of the 10-1 transistor T10a may be connected to the first control node Q. The 10-1 transistor T10a may be turned on or off in response to the voltage of the first control node Q. The 10-1 transistor T10a may be turned on when the voltage of the first control node Q is set to a first level voltage, and thus may output a first level voltage of the first scan clock signal SC_CK1 as a first level voltage of the p-th gate signal GS[p] or output a second level voltage of the first scan clock signal SC_CK1 as a second level voltage of the p-th gate signal GS[p]. The 11-1 transistor T11a may be connected between the 1-1 output terminal OUT11 and the second voltage input terminal V2. The gate of the 11-1 transistor T11a may be connected to the second control node QB. The 11-1th transistor T11a may be turned on or off in response to the voltage of the second control node QB. The 11-1th transistor T11a may be turned on when the voltage of the second control node QB is set to the first level voltage and thus may output the second voltage VGL1 as the second level voltage of the pth gate signal GS[p].

[0196] The second sub-output part 135b may include a 10-2 transistor T10b and an 11-2 transistor T11b. The 10-2 transistor T10b may be connected between the second scan clock terminal SCLK2 and the 1-2 output terminal OUT12. The gate of the 10-2 transistor T10b may be connected to the first control node Q. The 10-2 transistor T10b may be turned on or off in response to the voltage of the first control node Q. The 10-2 transistor T10b may be turned on when the voltage of the first control node Q is set to a first level voltage, and thus may output a first level voltage of the second scan clock signal SC_CK2 as a first level voltage of the p+1 gate signal GS[p+1] or output a second level voltage of the second scan clock signal SC_CK2 as a second level voltage of the p+1 gate signal GS[p+1]. The 11-2 transistor T11b may be connected between the 1-2 output terminal OUT12 and the second voltage input terminal V2. The gate of the 11-2 transistor T11b may be connected to the second control node QB. The 11-2 th transistor T11b may be turned on or off in response to the voltage of the second control node QB. The 11-2 th transistor T11b may be turned on when the voltage of the second control node QB is set to the first level voltage and thus may output the second voltage VGL1 as the second level voltage of the p+1 th gate signal GS[p+1].

[0197] The third sub-output portion 135c may include a 10-3rd transistor T10c and an 11-3rd transistor T11c. The 10-3rd transistor T10c may be connected between the third scan clock terminal SCLK3 and the 1-3rd output terminal OUT13. The gate of the 10-3rd transistor T10c may be connected to the first control node Q. The 10-3rd transistor T10c may be turned on or off in response to the voltage of the first control node Q. The 10-3rd transistor T10c may be turned on when the voltage of the first control node Q is set to a first level voltage, and thus may output a first level voltage of the third scan clock signal SC_CK3 as a first level voltage of the p+2nd gate signal GS[p+2] or output a second level voltage of the third scan clock signal SC_CK3 as a second level voltage of the p+2nd gate signal GS[p+2]. The 11-3rd transistor T11c may be connected between the 1-3rd output terminal OUT13 and the second voltage input terminal V2. The gate of the 11-3rd transistor T11c may be connected to the second control node QB. The 11-3rd transistor T11c may be turned on or off in response to the voltage of the second control node QB. The 11-3rd transistor T11c may be turned on when the voltage of the second control node QB is set to the first level voltage and thus may output the second voltage VGL1 as the second level voltage of the p+2th gate signal GS[p+2].

[0198] The fourth sub-output portion 135d may include a 10-4th transistor T10d and an 11-4th transistor T11d. The 10-4th transistor T10d may be connected between the fourth scan clock terminal SCLK4 and the 1-4th output terminal OUT14. The gate of the 10-4th transistor T10d may be connected to the first control node Q. The 10-4th transistor T10d may be turned on or off in response to the voltage of the first control node Q. The 10-4th transistor T10d may be turned on when the voltage of the first control node Q is set to a first level voltage, and thus may output a first level voltage of the fourth scan clock signal SC_CK4 as a first level voltage of the p+3th gate signal GS[p+3] or output a second level voltage of the fourth scan clock signal SC_CK4 as a second level voltage of the p+3th gate signal GS[p+3]. The 11-4th transistor T11d may be connected between the 1-4th output terminal OUT14 and the second voltage input terminal V2. The gate of the 11-4th transistor T11d may be connected to the second control node QB. The 11-4th transistor T11d may be turned on or off in response to the voltage of the second control node QB. The 11-4th transistor T11d may be turned on when the voltage of the second control node QB is set to the first level voltage, and thus may output the second voltage VGL1 as the second level voltage of the p+3th gate signal GS[p+3].

[0199] The second output portion 137' may include a first sub-output portion 137a and a second sub-output portion 137b. The first sub-output portion 137a may output a lower carry signal to the next stage, and the lower carry signal is synchronized with the drive carry clock signal input to the first carry clock terminal CCLK1 of the first sub-output portion 137a. The second sub-output portion 137b may output an upper carry signal to the previous stage, and the upper carry signal is synchronized with the switch carry clock signal input to the second carry clock terminal CCLK2 of the second sub-output portion 137b.

[0200] Each of the first and second sub-output portions 137 a and 137 b may include a twelfth transistor and a thirteenth transistor.

[0201] The first sub-output portion 137a may include a 12-1 transistor T12a and a 13-1 transistor T13a. The 12-1 transistor T12a may be connected between the first carry clock terminal CCLK1 and the 2-1 output terminal OUT21. The gate of the 12-1 transistor T12a may be connected to the first control node Q. The 12-1 transistor T12a may be turned on or off in response to the voltage of the first control node Q. The 12-1 transistor T12a may be turned on when the voltage of the first control node Q is set to a first level voltage, and thus may output a first level voltage of the first drive carry clock signal CR_CK_D as a first level voltage of the kth carry signal CR_D[k] or output a second level voltage of the first drive carry clock signal CR_CK_D as a second level voltage of the kth carry signal CR_D[k]. The 13-1 transistor T13a may be connected between the 2-1 output terminal OUT21 and the third voltage input terminal V3. The gate of the 13-1 transistor T13a may be connected to the second control node QB. The 13-1 transistor T13a may be turned on or off in response to the voltage of the second control node QB. The 13-1 transistor T13a may be turned on when the voltage of the second control node QB is set to the first level voltage, and thus may output the third voltage VGL2 as the second level voltage of the k-th carry signal CR_D[k].

[0202] The second sub-output portion 137b may include a 12-2 transistor T12b and a 13-2 transistor T13b. The 12-2 transistor T12b may be connected between the second carry clock terminal CCLK2 and the 2-2 output terminal OUT22. The gate of the 12-2 transistor T12b may be connected to the first control node Q. The 12-2 transistor T12b may be turned on or off in response to the voltage of the first control node Q. The 12-2 transistor T12a may be turned on when the voltage of the first control node Q is set to a first level voltage, and thus may output a first level voltage of the first switching carry clock signal CR_CK_SW as a first level voltage of the k-th carry signal CR_U[k] or output a second level voltage of the first switching carry clock signal CR_CK_SW as a second level voltage of the k-th carry signal CR_U[k]. The 13-2 transistor T13b may be connected between the 2-2 output terminal OUT22 and the third voltage input terminal V3. The gate of the 13-2 transistor T13b may be connected to the second control node QB. The 13-2 transistor T13b may be turned on or off in response to the voltage of the second control node QB. The 13-2 transistor T13b may be turned on when the voltage of the second control node QB is set to the first level voltage, and thus may output the third voltage VGL2 as the second level voltage of the k-th carry signal CR_U[k].

[0203] The second capacitor C2 may be connected between the 12-1 transistor T12a of the first sub output portion 137a and the 2-1 output terminal OUT21. By connecting the second capacitor C2 to the first sub output portion 137a outputting the carry down signal CR_D having a long gate-on voltage period, stable multiple outputs of gate signals may be possible.

[0204] In the following, reference will be made to Fig.17A and Fig. 17B Describe the operation of the kth stage STk.

[0205] Fig.17A The operation of the kth stage STk in the display period DP is shown.

[0206] In the first period P11, the previous carry down signal CR_D[k-1] of the first level voltage from the k-1th stage as the previous stage may be supplied, and the next carry up signal CR_U[k+1] of the second level voltage from the k+1th stage as the next stage may be supplied. In addition, the first drive carry clock signal CR_CK_D of the first level voltage may be supplied, and the first switch carry clock signal CR_CK_SW of the second level voltage and the second switch carry clock signal CR_CKB_SW of the second level voltage may be supplied. The voltage of the first control node Q may be maintained at the second level voltage, and the voltage of the second control node QB may be maintained at the first level voltage.

[0207] In the second period P12, the previous lower carry signal CR_D[k-1] of the first level voltage may be supplied, and the next upper carry signal CR_U[k+1] of the second level voltage may be supplied. In addition, the first driving carry clock signal CR_CK_D of the second level voltage and the first switching carry clock signal CR_CK_SW of the second level voltage may be supplied, and the first scan clock signals SC_CK1 to the fourth scan clock signals SC_CK4 of the second level voltage may be supplied.

[0208] The first transistor T1 may be turned on by the second switching carry clock signal CR_CKB_SW having a first level voltage, and the first control node Q and the third control node QC may be set to the first level voltage of the previous carry signal CR_D[k-1]. Therefore, the 10-1 transistor T10a, the 10-2 transistor T10b, the 10-3 transistor T10c, and the 10-4 transistor T10d may be turned on, and therefore, the second level voltages of the first scan clock signal SC_CK1, the second scan clock signal SC_CK2, the third scan clock signal SC_CK3, and the fourth scan clock signal SC_CK4 may be output from the 1-1 output terminal OUT11 to the 1-4 output terminal OUT14 as the p-th gate signal GS[p] to the p+3-th gate signal GS[p+3], respectively. In addition, the 12-1 transistor T12a may be turned on, and therefore, the second level voltage of the first drive carry clock signal CR_CK_D may be output from the 2-1 output terminal OUT21 as the k-th carry signal CR_D[k]. The 12-2 th transistor T12 b may be turned on, and thus the second level voltage of the first switch carry clock signal CR_CK_SW may be output from the 2-2 th output terminal OUT22 as the k th upper carry signal CR_U[k].

[0209] The second transistor T2 whose gate is connected to the third control node QC may be turned on, and the voltage of the second control node QB may be set to the second level voltage of the third voltage VGL2. Therefore, the 11-1 transistor T11a, the 11-2 transistor T11b, the 11-3 transistor T11c, the 11-4 transistor T11d, the 13-1 transistor T13a, and the 13-2 transistor T13b may remain turned off.

[0210] In the third period P13, the previous carry down signal CR_D[k-1] of the first level voltage may be supplied, and then the previous carry down signal CR_D[k-1] of the first level voltage may be converted into the second level voltage, and the next carry up signal CR_U[k+1] of the second level voltage may be supplied. The first drive carry clock signal CR_CK_D of the first level voltage may be supplied, the first switch carry clock signal CR_CK_SW may be sequentially converted into the second level voltage, the first level voltage, and the second level voltage and supplied as the second level voltage, the first level voltage, and the second level voltage, and the second switch carry clock signal CR_CKB_SW of the second level voltage may be supplied. The first scan clock signal SC_CK1 to the fourth scan clock signal SC_CK4 of the first level voltage may be sequentially supplied.

[0211] The first transistor T1 can be turned off by the second switching carry clock signal CR_CKB_SW having a second level voltage, and the voltage of the first control node Q and the voltage of the third control node QC can be maintained at the first level voltage. The first level voltages of the first scan clock signal SC_CK1, the second scan clock signal SC_CK2, the third scan clock signal SC_CK3, and the fourth scan clock signal SC_CK4 can be sequentially shifted and output from the 1-1 output terminal OUT11 to the 1-4 output terminal OUT14 as the p-th gate signal GS[p] to the p+3-th gate signal GS[p+3] through the turned-on 10-1 transistor T10a, the 10-2 transistor T10b, the 10-3 transistor T10c, and the 10-4 transistor T10d, respectively. In addition, the first level voltage of the first drive carry clock signal CR_CK_D can be output from the 2-1 output terminal OUT21 as the k-th carry signal CR_D[k] through the turned-on 12-1 transistor T12a. The 12-2 transistor T12b may be turned on, and thus, voltages corresponding to the second level voltage, the first level voltage, and the second level voltage of the first switching carry clock signal CR_CK_SW may be sequentially output from the 2-2 output terminal OUT22 as the kth up carry signal CR_U[k]. In this case, the voltage of the first control node Q may be increased to a voltage higher than the voltage in the second period P12 through the second capacitor C2.

[0212] The sixth transistor T6 whose gate is connected to the third control node QC can be turned on, and the first voltage VGH can be transmitted to the intermediate node H between the 1-1 transistor T1-1 and the 1-2 transistor T1-2, so the voltage of the third control node QC can be stably maintained by blocking the leakage current caused by the turned-off 1-1 transistor T1-1 and the 1-2 transistor T1-2.

[0213] The voltage of the second control node QB may be maintained at the second level voltage of the third voltage VGL2 .

[0214] In the fourth period P14, the previous carry down signal CR_D[k-1] of the second level voltage may be supplied, and the next carry up signal CR_U[k+1] of the first level voltage may be supplied. The first drive carry clock signal CR_CK_D of the second level voltage may be supplied, the first switch carry clock signal CR_CK_SW of the second level voltage may be supplied, and the second switch carry clock signal CR_CKB_SW of the first level voltage may be supplied. The first scan clock signal SC_CK1 to the fourth scan clock signal SC_CK4 of the second level voltage may be supplied.

[0215] The first transistor T1 may be turned on by the second switching carry clock signal CR_CKB_SW having a first level voltage, and the voltage of the first control node Q and the voltage of the third control node QC may be set to the second level voltage of the previous carry signal CR_D[k-1]. Therefore, the 10-1st transistor T10a, the 10-2nd transistor T10b, the 10-3rd transistor T10c and the 10-4th transistor T10d, the 12-1st transistor T12a, the 12-2nd transistor T12b and the second transistor T2 may be turned off.

[0216] The fourth transistor T4 may be turned on by the next carry signal CR_U[k+1], and the voltage of the second control node QB may be set to the first voltage VGH by the turned-on fourth transistor T4. Therefore, the 11-1 transistor T11a, the 11-2 transistor T11b, the 11-3 transistor T11c, the 11-4 transistor T11d, the 13-1 transistor T13a, and the 13-2 transistor T13b may be turned on. The second level voltage of the second voltage VGL1 may be output from the 1-1 output terminal OUT11 to the 1-4 output terminal OUT14 as the p-th gate signal GS[p] to the p+3-th gate signal GS[p+3] respectively through the turned-on 11-1 transistor T11a, the 11-2 transistor T11b, the 11-3 transistor T11c, and the 11-4 transistor T11d. The second level voltage of the third voltage VGL2 may be output from the 2-1 output terminal OUT21 as the kth carry signal CR_D[k] through the turned-on 13-1 transistor T13a, and the second level voltage of the third voltage VGL2 may be output from the 2-2 output terminal OUT22 as the kth carry signal CR_U[k] through the turned-on 13-2 transistor T13b.

[0217] The sixth transistor T6 whose gate is connected to the third control node QC can be turned on, and the first voltage VGH can be transmitted to the intermediate node H between the 2-1 transistor T2-1 and the 2-2 transistor T2-2, so the voltage of the second control node QB can be stably maintained by blocking the leakage current caused by the turned-off 2-1 transistor T2-1 and the 2-2 transistor T2-2.

[0218] During the display period DP, the k-th carry signal CR_D[k] and the first control signal S1 may be supplied to the second controller 133'. When the first control signal S1 is supplied, the seventh transistor T7 may be turned on, the first level voltage of the k-th carry signal CR[k] may be supplied to the sensing node M, and the first capacitor C1 may be charged. The ninth transistor T9 having a gate connected to the sensing node M may be turned on.

[0219] Fig. 17B 1 shows the operation of the kth stage STk in the vertical blank period VBP. In the sensing period SP of the vertical blank period VBP, the first driving carry clock signal CR_CK_D of the first level voltage may be supplied, the first switching carry clock signal CR_CK_SW of the second level voltage and the second switching carry clock signal CR_CKB_SW of the second level voltage may be supplied, and the first scanning clock signal SC_CK1 to the fourth scanning clock signal SC_CK4 of the first level voltage may be sequentially supplied. When the stage connected to the pixel to be sensed is an even-numbered stage, the second driving carry clock signal CR_CKB_D of the first level voltage may be supplied.

[0220] The second control signal S2 may be supplied to the second controller 133', and the voltage of the first control node Q and the voltage of the third control node QC may be set to the first voltage VGH by the ninth transistor T9 having a gate connected to the sensing node M having the first level voltage and thus turned on and the eighth transistor T8 turned on by the second control signal S2. Therefore, the 10-1st transistor T10a, the 10-2nd transistor T10b, the 10-3rd transistor T10c, and the 10-4th transistor T10d, the 12-1st transistor T12a, the 12-2nd transistor T12b, and the second transistor T2 may be turned on. The first level voltages of the first scan clock signal SC_CK1, the second scan clock signal SC_CK2, the third scan clock signal SC_CK3, and the fourth scan clock signal SC_CK4 may be sequentially shifted and outputted from the 1-1 output terminal OUT11 to the 1-4 output terminal OUT14 as the p-th gate signal GS[p] to the p+3-th gate signal GS[p+3] through the turned-on 10-1 transistor T10a, the 10-2 transistor T10b, the 10-3 transistor T10c, and the 10-4 transistor T10d, respectively. In addition, the first level voltage of the first drive carry clock signal CR_CK_D may be outputted from the 2-1 output terminal OUT21 as the k-th carry signal CR_D[k] through the turned-on 12-1 transistor T12a. The second level voltage of the first switch carry clock signal CR_CK_SW may be outputted from the 2-2 output terminal OUT22 as the k-th carry signal CR_U[k] through the turned-on 12-2 transistor T12b. When a driving carry clock signal having a first level voltage is input to the second sub output portion 137a to which the second capacitor C2 is connected in the sensing period SP, voltages of the first control node Q and the third control node QC may be boosted by the second capacitor C2, and thus the gate signal may be stably output.

[0221] The clock signal having the first level voltage (ie, the driving carry clock signal and the scan clock signal) may be supplied after any point in time when the second control signal S2 is supplied. Fig. 17B An example is shown in which a clock signal having a first level voltage is input at an arbitrary time point after the first control node Q and the third control node QC are set to the first voltage VGH.

[0222] The second transistor M2 and the third transistor M3 of each of the pth to p+3th rows of pixels PX receiving the pth to p+3th gate signals GS[p] to GS[p+3] may be turned on to sense state information of the first transistor M1 and the organic light emitting diode OLED.

[0223] Fig.18 is a diagram showing a timing relationship between a carry clock signal and a toggle carry clock signal according to an embodiment.

[0224] Fig.18 The second drive carry clock signal CR_CKB_D and the second switch carry clock signal CR_CKB_SW respectively input to the first carry clock terminal CCLK1 and the second carry clock terminal CCLK2 of the k-1th stage corresponding to the k-1th row, the second drive carry clock signal CR_CKB_D and the second switch carry clock signal CR_CKB_SW respectively input to the first carry clock terminal CCLK1 and the second carry clock terminal CCLK2 of the k+1th stage corresponding to the k+1th row, and the first drive carry clock signal CR_CK_D and the first switch carry clock signal CR_CK_SW respectively input to the first carry clock terminal CCLK1 and the second carry clock terminal CCLK2 of the kth stage are shown. The first switch carry clock signal CR_CK_SW can be input to the third carry clock terminal CCLK3 of each of the k-1th stage and the k+1th stage, and the second switch carry clock signal CR_CKB_SW can be input to the third carry clock terminal CCLK3 of the kth stage. The second driving carry clock signal CR_CKB_D may be a phase shift signal of the first driving carry clock signal CR_CK_D, and the second switching carry clock signal CR_CKB_SW may be a phase shift signal of the first switching carry clock signal CR_CK_SW.

[0225] like Fig.15As shown in , the down carry signal CR_D[k] may be outputted corresponding to the first drive carry clock signal CR_CK_D inputted to the kth stage, and the up carry signal CR_U[k] may be outputted corresponding to the first switch carry clock signal CR_CK_SW. Corresponding to the second drive carry clock signal CR_CKB_D inputted to the k-1th stage, the previous down carry signal CR_D[k-1] may be inputted to the kth stage. Corresponding to the second switch carry clock signal CR_CKB_SW inputted to the k+1th stage, the next up carry signal CR_U[k+1] may be inputted to the kth stage.

[0226] The first transistor T1 can be turned on and off according to the voltage of the second switch carry clock signal CR_CKB_SW, and the turned-on first transistor T1 can set the voltage of the previous carry signal CR_D[k-1] to the voltage of the first control node Q and the voltage of the third control node QC. The fourth transistor T4 can be turned on and off according to the voltage of the next carry signal CR_U[k+1], and the turned-on fourth transistor T4 can set the first voltage VGH to the voltage of the second control node QB.

[0227] Reference Fig.18 , after the first time point t1 at which the first drive carry clock signal CR_CK_D input to the kth stage is converted from the gate-on voltage to the gate-off voltage, the second switch carry clock signal CR_CKB_SW input to the k-1th stage can be converted from the gate-off voltage to the gate-on voltage. Therefore, in the k+1th stage, the first control node Q can be stably reset to the second level voltage by the second level voltage of the previous carry signal CR_D[k]. The interval Δt1 between the first time point t1 and the time point at which the second switch carry clock signal CR_CKB_SW is converted from the gate-off voltage to the gate-on voltage can be greater than or equal to zero.

[0228] Before the second time point t2 at which the second drive carry clock signal CR_CKB_D input to the k-1th stage is converted from the gate-on voltage to the gate-off voltage, the second switch carry clock signal CR_CKB_SW input to the k-1th stage can be converted from the gate-on voltage to the gate-off voltage. Therefore, in the kth stage, the first control node Q and the third control node QC can be stably charged by the first level voltage of the previous carry signal CR_D[k-1]. The interval Δt2 between the second time point t2 and the time point at which the second switch carry clock signal CR_CKB_SW is converted from the gate-on voltage to the gate-off voltage can be greater than or equal to the phase delay between the first switch carry clock signal CR_CK_SW and the second switch carry clock signal CR_CKB_SW.

[0229] After the third time point t3 at which the first drive carry clock signal CR_CK_D input to the kth stage is converted from the gate-on voltage to the gate-off voltage, the second switch carry clock signal CR_CKB_SW input to the k+1th stage can be converted from the gate-off voltage to the gate-on voltage. Therefore, the kth stage can stably control the voltage control timing of the first control node Q, the third control node QC, and the second control node QB.

[0230] In the disclosed embodiment, the voltage control timing of the first control node Q, the third control node QC, and the second control node QB may be controlled by a carry signal output from a previous stage and a carry signal output from a next stage.

[0231] In a gate driving circuit including an oxide semiconductor transistor, since the oxide semiconductor transistor operates in a depletion mode, when the threshold voltage distribution due to the negative shift of the threshold voltage of the transistor increases, the circuit may have difficulty in operating normally due to the leakage current near 0V of the gate-source voltage (Vgs) in the transistor. Therefore, in order to make the circuit operate normally even in the case of a negative shift of the threshold voltage, a method of reducing the leakage current is required. In the disclosed embodiments, the transistor (e.g., Figure 7 The sixth transistor T6 in the circuit is used to reduce the leakage current in the circuit, and the transistor controls the voltage of the first control node (for example, Figure 7 The first level voltage is supplied to an intermediate node between the first transistor T1 and the eighth transistor T8 in the transistor. Therefore, the disclosed embodiments can provide a gate drive circuit that is robust against defects caused by leakage current caused by a negative shift in the transistor threshold voltage.

[0232] In the disclosed embodiment, since the gate output portion outputting two or more rows of gate signals shares the first control node Q, the second control node QB, and the third control node QC in one stage, multiple outputs of gate signals are possible, and the mounting area of ​​the gate driving circuit can be reduced by reducing the total number of transistors in the gate driving circuit. According to the disclosed embodiment, multiple gate signals can be generated in one stage by driving the conduction of the first drive carry clock signal CR_CK_D and the second drive carry clock signal CR_CKB_D to 50% or more.

[0233] According to the disclosed embodiments, a gate driving circuit capable of stably outputting a gate signal and a display device including the gate driving circuit can be provided. The disclosed effects are not limited to the above effects and can be variously extended without departing from the spirit of the disclosure.

[0234] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for the purpose of limitation. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. A gate drive circuit, the gate drive circuit comprising a plurality of stages, wherein: Each of the plurality of stages comprises: a first controller connected to the first voltage input terminal and the second voltage input terminal and configured to control a voltage of the first control node and a voltage of the second control node during a display period of one frame; a second controller connected to the first voltage input terminal and the first control node and configured to control the voltage of the first control node during a sensing period of the one frame; a first output section connected to the first clock terminal and the third voltage input terminal and configured to output a gate signal; and a second output section connected to the second clock terminal and the second voltage input terminal and configured to output a carry signal, Wherein, the first controller includes: a first transistor, configured to be turned on by a third clock signal input to a third clock terminal, and to control the voltage of the first control node using the voltage of a previous carry signal, wherein the previous carry signal is a carry signal input from a previous stage; a second transistor, configured to be turned on when the first control node is at a first level voltage, and to control the voltage of the second control node using a second voltage input to the second voltage input terminal; and a third transistor, configured to be turned on by a next carry signal, and to control the voltage of the second control node using the first voltage input to the first voltage input terminal, wherein the next carry signal is a carry signal input from a next stage.

2. The gate drive circuit according to claim 1, wherein: The second voltage is lower than a third voltage input to the third voltage input terminal, and the first voltage is higher than the second voltage and the third voltage.

3. The gate driving circuit according to claim 1, wherein: the first level voltage and the second level voltage of each of the first clock signal and the second clock signal are alternately input during the display period, the second level voltage being lower than the first level voltage, The first level voltage of the first clock signal and the first level voltage of the second clock signal are input during the sensing period.

4. The gate driving circuit according to claim 3, wherein: The third clock signal is an inverted signal of the second clock signal, wherein a period during which the second clock signal is at the first level voltage overlaps with a period during which the first clock signal is at the first level voltage, and wherein the period during which the first clock signal is at the first level voltage is shorter than the period during which the second clock signal is at the first level voltage.

5. The gate driving circuit according to claim 1, wherein: Each of the first transistor and the second transistor includes a first sub-transistor and a second sub-transistor connected in series.

6. The gate driving circuit according to claim 5, wherein: The first controller also includes a fourth transistor connected to the first voltage input terminal and an intermediate node between the first sub-transistor and the second sub-transistor of the first transistor and having a gate connected to the first control node.

7. The gate driving circuit according to claim 5, wherein: The first controller also includes a fifth transistor connected to the first voltage input terminal and an intermediate node between the first sub-transistor and the second sub-transistor of the second transistor and having a gate connected to the second control node.

8. The gate driving circuit according to claim 1, wherein: The first controller also includes a sixth transistor connected to the first voltage input terminal and the second control node and having a gate receiving a reset signal.

9. The gate driving circuit according to claim 1, wherein: The second controller comprises: a first capacitor connected to the first voltage input terminal and a sensing node; a seventh transistor connected to the sensing node and the second output portion and including a first sub-transistor and a second sub-transistor connected in series; an eighth transistor connected to the first voltage input terminal and an intermediate node between the first sub-transistor and the second sub-transistor of the seventh transistor and having a gate connected to the sensing node; and A ninth transistor is connected to the intermediate node of the seventh transistor and the first control node.

10. The gate driving circuit according to claim 9, wherein: The seventh transistor is configured to be turned on by a first control signal synchronized with a carry signal output from the second output part during the display period and to set a voltage of the sense node to a voltage of the carry signal.

11. The gate driving circuit according to claim 10, wherein: The first capacitor stores a voltage difference between a terminal connected to the first voltage input terminal and a terminal connected to the sensing node.

12. The gate driving circuit according to claim 11, wherein: The ninth transistor is configured to be turned on by the second control signal input during the sensing period, and to set the voltage of the first control node to the first voltage transmitted through the turned-on eighth transistor.

13. The gate driving circuit according to claim 1, wherein: The second output section includes a second capacitor connected between the first control node and an output terminal of the second output section.

14. The gate driving circuit according to claim 1, wherein: The first output part includes a plurality of sub-output parts, Among them, one of a plurality of first clock signals is input to a first clock terminal of each of the plurality of sub-output portions, and the plurality of first clock signals are signals having the same waveform and having phases shifted at specific intervals.

15. The gate driving circuit according to claim 14, wherein: The second output portion includes a first sub-output portion and a second sub-output portion, Among them, the first sub-output part outputs a first carry signal synchronized with the 2-1 clock signal input to the second clock terminal of the first sub-output part to the next stage, and the second sub-output part outputs a second carry signal synchronized with the 2-2 clock signal input to the second clock terminal of the second sub-output part to the previous stage.

16. The gate driving circuit according to claim 15, wherein: wherein the period during which the 2-1 clock signal is at the first level voltage overlaps with the period during which the multiple first clock signals of the multiple sub-output parts input to the first output part are at the first level voltage, wherein the period during which the 2-1 clock signal is at the first level voltage overlaps with the period during which the 2-2 clock signal is at the first level voltage, and wherein the period during which the 2-2 clock signal is at the first level voltage is shorter than the period during which the 2-1 clock signal is at the first level voltage.

17. The gate driving circuit according to claim 7, wherein: The first controller also includes a tenth transistor connected between the first transistor and the first control node and having a gate connected to the first voltage input terminal.

18. The gate driving circuit according to claim 16, wherein: The second controller comprises: an eleventh transistor connected to the first control node and the second voltage input terminal and having a gate connected to a sensing node; and The twelfth transistor is connected between the first control node and the eleventh transistor.

19. The gate driving circuit according to claim 18, wherein: The twelfth transistor is configured to be turned on by a third control signal input after the sensing period, and to set the voltage of the first control node to the second voltage transmitted through the turned-on eleventh transistor.

20. A gate drive circuit, the gate drive circuit comprising a plurality of stages, wherein: Each of the plurality of stages comprises: a first transistor connected between a first input terminal receiving a start signal and a first control node and having a gate connected to a first clock terminal; a second transistor connected to the first voltage input terminal and an intermediate node between the first sub-transistor and the second sub-transistor of the first transistor and having a gate connected to the first control node; a third transistor connected between the second control node and the second voltage input terminal and having a gate connected to the first control node; a fourth transistor connected to the first voltage input terminal and an intermediate node between the first sub-transistor and the second sub-transistor of the third transistor, and having a gate connected to the second control node; a fifth transistor connected between the first voltage input terminal and the second control node and having a gate connected to a second input terminal to which a carry signal of a next stage is input; a first pull-up transistor connected between the second clock terminal and the first output terminal and having a gate connected to the first control node; a first pull-down transistor connected between the first output terminal and a third voltage input terminal and having a gate connected to the second control node; a second pull-up transistor connected between the third clock terminal and the second output terminal and having a gate connected to the first control node; a second pull-down transistor connected between the second output terminal and the second voltage input terminal and having a gate connected to the second control node; a first capacitor connected between the first voltage input terminal and a sensing node; a sixth transistor connected between the sensing node and the second output terminal and having a gate connected to the first control signal terminal; a seventh transistor connected to the first voltage input terminal and an intermediate node between the first sub-transistor and the second sub-transistor of the sixth transistor and having a gate connected to the sensing node; and An eighth transistor is connected between the intermediate node of the sixth transistor and the first control node and has a gate connected to a second control signal terminal.

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